Storage device and method of operating the same

Abstract

A memory device and a method of operating the same are provided. The memory device includes: a plurality of memory dies corresponding to a plurality of channels and a plurality of paths; and a memory controller connected to the plurality of memory dies. The storage controller may be configured to: receive commands from a plurality of tenants; in response to the number of received commands being equal to or greater than a predetermined threshold, determining a first number of channels required to store first data of a first tenant in each of the plurality of paths based on commands received from the first tenant; and store first data in a first number of memory dies in each of the plurality of ways. First data may be stored in memory dies corresponding to the plurality of lanes in at least a portion or all of the plurality of lanes.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0123426 filed on September 15, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Example embodiments relate to a memory device and a method of operating the same. Background Art

[0003] Recently, as semiconductor technology continues to advance, the performance of computer processors has increased significantly. In addition, as multi-core processor technology develops, the amount of operations that can be performed simultaneously in a single computer server has increased significantly.

[0004] Therefore, the Internet data center provides various and reliable services (eg, web servers, mail servers, file servers, video servers, and cloud servers) to different service users by installing hundreds or thousands of computer servers in a single place.

[0005] For example, as the number of tenants requesting connections to a data center rapidly increases, the number of instances where write requests to a storage device of the data center are received from different tenants is also increasing.

[0006] However, when the data of each tenant is randomly stored (e.g., in a random access memory die of a storage device) based on write requests received from different tenants, the time required for random read operations on the stored data increases, and thus, the read performance of the stored data may be reduced. In addition, when data transmitted from tenants is concentrated and stored in a specific (one or more) channels, the time required for sequential read operations on the data may increase. Therefore, there is an increasing need for a method of storing data received from each of a plurality of tenants to improve read performance. Summary of the invention

[0007] Example embodiments provide a memory device for improving read performance and a method of operating the memory device.

[0008] According to an example embodiment, a storage device includes: a plurality of memory dies corresponding to a plurality of channels and a plurality of ways; and a storage controller connected to the plurality of memory dies. The storage controller may be configured to: receive commands from a plurality of tenants; determine a first number of channels required to store first data of a first tenant in each of the plurality of ways based on a command received from a first tenant in response to the number of commands received being equal to or greater than a predetermined threshold; and store the first data in a first number of memory dies in each of the plurality of ways. The first data may be stored in the memory dies corresponding to the plurality of channels in at least a portion or all of the plurality of ways.

[0009] According to example embodiments, a method of operating a storage device includes: receiving commands from a plurality of tenants; in response to the number of received commands being equal to or greater than a predetermined threshold, determining a first number of channels among a plurality of channels required to store first data of a first tenant in each of a plurality of ways based on the command received from a first tenant, each of the plurality of channels including a plurality of memory dies corresponding to the plurality of ways; and storing the first data in the first number of memory dies in each of the plurality of ways. The first data may be stored in the memory dies corresponding to the plurality of channels in at least a portion or all of the plurality of ways.

[0010] According to an example embodiment, a storage device includes: a nonvolatile memory device including a plurality of channels, each of the plurality of channels including a plurality of memory dies corresponding to a plurality of ways; and a storage controller. The storage controller may include: a command queue configured to store commands sent from a plurality of tenants; an input command processor configured to obtain the commands from the command queue; a channel allocator configured to determine a first number of channels required to store first data of a first tenant based on information included in a command received from a first tenant; and a placement unit configured to store the first data in a first number of memory dies in each of the plurality of ways. The first data may be stored in memory dies uniformly corresponding to the plurality of channels in at least a portion or all of the plurality of ways. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 is a block diagram of a storage system according to an example embodiment.

[0013] Figure 2 It is shown Figure 1 A block diagram of a configuration of a storage controller.

[0014] Figure 3A is a flowchart illustrating a method of operating a memory device according to example embodiments.

[0015] Figure 3B is a diagram illustrating a plurality of memory dies represented in the form of a matrix according to example embodiments.

[0016] Figure 4A is a flowchart illustrating a method in which a storage controller stores first data of a first tenant in a first way and a second way according to an example embodiment.

[0017] Figure 4B is a flowchart illustrating a method in which a storage controller stores second data of a second tenant in a first way and a second way according to an example embodiment.

[0018] Figure 5A is a diagram illustrating a configuration in which first data and second data are stored in a first way according to an example embodiment.

[0019] Figure 5B is a diagram illustrating a configuration in which first data and second data are stored in a second way according to an example embodiment.

[0020] Figure 5C is a diagram illustrating a configuration in which first data and second data are stored in a plurality of ways according to an embodiment.

[0021] Fig. 6A is a diagram illustrating a configuration in which first data and second data are stored in a first way according to an example embodiment.

[0022] Figure 6B is a diagram illustrating a configuration in which first data and second data are stored in a second way according to an example embodiment.

[0023] Figure 6C is a diagram illustrating a configuration in which first data and second data are stored in a plurality of ways according to an example embodiment.

[0024] Fig. 7A is a diagram illustrating a configuration in which first data and second data requiring different numbers of channels are stored in a first way according to example embodiments.

[0025] Figure 7B is a diagram illustrating a configuration in which first data and second data requiring different numbers of channels are stored in a second way according to example embodiments.

[0026] Figure 7C is a diagram illustrating a configuration in which first data and second data requiring different numbers of channels are stored in a plurality of ways according to example embodiments.

[0027] Figure 8 is a diagram illustrating a configuration in which a storage controller stores data of each of a plurality of tenants according to an example embodiment.

[0028] Fig. 9 is a diagram illustrating a configuration in which a storage controller stores data of each of a plurality of tenants requiring a different number of channels according to an example embodiment.

[0029] Fig. 10A is a block diagram of a storage system according to an example embodiment.

[0030] Fig. 10B It is shown Fig. 10A A block diagram of a configuration of a storage controller.

[0031] Fig.11A is a flowchart illustrating a method in which a memory controller stores first data and second data using a plurality of word lines according to example embodiments.

[0032] Fig. 11B is a diagram illustrating a configuration in which a memory controller stores first data and second data using a first word line according to example embodiments.

[0033] Fig. 11C is a diagram illustrating a configuration in which a memory controller stores first data and second data using a second word line according to example embodiments. DETAILED DESCRIPTION

[0034] Hereinafter, example embodiments will be described with reference to the accompanying drawings.

[0035] Figure 1 is a block diagram of a storage system according to an example embodiment.

[0036] Reference Figure 1 The storage system 100A may include a host 120 and a storage device 110A. The storage device 110A may include a storage controller 112A and a nonvolatile memory (or nonvolatile storage device) 111.

[0037] According to example embodiments, the storage device 110A may include a storage medium that stores data based on a request received from the host 120. For example, the storage device 110A may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory.

[0038] For example, when the storage device 110A is an SSD, the storage device 110A may be a device compliant with the Non-Volatile Memory Express (NVMe) or Compute Express Link (CXL) standards.

[0039] For example, when the storage device 110A is an embedded memory or an external memory, the storage device 110A may be a device conforming to the universal flash storage (UFS) or embedded multimedia card (eMMC) standard.

[0040] Each of the host 120 and the storage device 110A may generate a packet based on an adopted standard protocol and transmit the generated packet.

[0041] According to example embodiments, the host 120 may receive commands from a plurality of tenants Tenant 1 to Tenant n and transmit the received commands to the storage device 110A.

[0042] For example, the host 120 may receive a write command from each of the first tenant Tenant 1 and the second tenant Tenant 2 and transmit the received write command to the storage device 110A.

[0043] For example, the host 120 may receive a read command from each of the first tenant Tenant 1 and the second tenant Tenant 2 and transmit the received read command to the storage device 110A.

[0044] However, the plurality of tenants that transmit commands to the storage device 110A through the host 120 are not limited to the above-described first tenant Tenant 1 and second tenant Tenant 2 , and three or more tenants may transmit commands to the storage device 110A through 120 .

[0045] The storage device 110A may include a storage controller 112A that stores data of each tenant in the nonvolatile memory device 111 and / or reads data stored in the nonvolatile memory device 111 based on a command received through the host 120 .

[0046] The storage controller 112A may control at least one component of the storage device 110A (such as the nonvolatile memory device 111) by executing, for example, software (or a program), and may perform various data processing and / or operations. The storage controller 112A may include, for example, a central processing unit or a microprocessor, and may control the overall operation of the storage device 110A. Therefore, the following operations performed by the storage device 110A may be understood to be performed under the control of the storage controller 112A.

[0047] According to an example embodiment, the storage controller 112A may include an algorithm for storing and / or reading data sent from multiple tenants. For example, the algorithm may be a software code programmed in the storage controller 112A. For example, the algorithm may be a hard code hard-coded in the storage controller 112A, but example embodiments are not limited thereto.

[0048] For example, an algorithm may be referred to as control logic, but example embodiments are not limited thereto.

[0049] The storage controller 112A may store data transmitted from a plurality of tenants in the nonvolatile memory device 111 and / or read data stored in the nonvolatile memory device 111 based on an algorithm.

[0050] For example, the storage device 110A may store first data of the first tenant Tenant 1 in the nonvolatile memory device 111 based on a write command of the first tenant Tenant 1 received through the host 120 .

[0051] For example, the storage device 110A may read the second data of the second tenant Tenant 2 stored in the nonvolatile memory device 111 based on the read command of the second tenant Tenant 2 received through the host 120 .

[0052] The storage device 110A may obtain information about an identification ID assigned to each of the plurality of tenants from the host 120. In addition, the storage device 110A may identify data transmitted from each tenant based on the obtained information.

[0053] For example, the storage device 110A may identify first data of the first tenant Tenant 1 and second data of the second tenant Tenant 2 based on the ID information transmitted from the host 120 .

[0054] For example, the storage device 110A may also obtain information about the size of a memory area or the number of memory dies required to store data of each tenant from the host 120 .

[0055] According to example embodiments, the nonvolatile memory device 111 of the memory device 110A may include a plurality of memory dies 150 .

[0056] For example, the nonvolatile memory device 111 may include a plurality of memory dies 150 corresponding to a plurality of channels ch1 to chn.

[0057] The nonvolatile memory device 111 may include a plurality of first memory dies 151 corresponding to the first channel ch1. In addition, the nonvolatile memory device 111 may include a plurality of second memory dies 152 corresponding to the second channel ch2. In addition, the nonvolatile memory device 111 may include a plurality of third memory dies 153 corresponding to the third channel ch3.

[0058] Each of the plurality of memory dies 150 may be connected to the memory controller 112A through a corresponding channel.

[0059] Each of the plurality of memory dies 151, 152, 153 to 15n corresponding to channels ch1, ch2, ch3 to chn, respectively, may correspond to a plurality of ways w1 to wn. The memory dies may be selected in a channel unit and a way unit, and the term "way" may be used to represent a memory die at a corresponding channel that may be selected in a way unit. The memory dies connected to each channel may form a plurality of ways w1 to wn. A way may be a unit for distinguishing memory dies sharing the same channel. Each of the memory dies may be identified according to a channel number and a way number. The following will refer to Figure 3B Although an example of n number of channels (n is a positive integer) and n number of ways is described, example embodiments are not limited thereto, and the number of channels and the number of ways may be different from each other.

[0060] For example, each of the first memory dies D11, D12, D13, to D1n corresponding to the first channel ch1 may correspond to a plurality of ways w1 to wn. Also, each of the second memory dies D21, D22, D23, to D2n corresponding to the second channel ch2 may correspond to a plurality of ways w1 to wn.

[0061] Here, n may be a positive integer and may be determined variously.

[0062] When the nonvolatile memory device 111 of the storage device 110A includes a flash memory, the flash memory may include a two-dimensional (2D) NAND memory array, or a three-dimensional (3D) or vertical NAND (VNAND) memory array.

[0063] For example, the memory device 110A may include various other types of non-volatile memory. For example, the memory device 110A may be implemented as a magnetic random access memory (RAM) (MRAM), a spin transfer torque MRAM (STT-MRAM), a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), a resistive RAM (ReRAM), or various other types of memory.

[0064] According to an example embodiment, the storage controller 112A may store data of each tenant in at least a portion of the plurality of memory dies 150 based on information obtained from the host 120. The term "at least a portion" used herein may be used to include not only a portion of an element but also the entire portion of an element.

[0065] For example, the memory controller 112A may store data of each tenant in at least a portion of the plurality of memory dies 150 such that the data of each tenant corresponds to each of the plurality of channels ch1 to chn.

[0066] When the number of commands received from the plurality of tenants is greater than or equal to a predetermined threshold, the storage controller 112A may determine, based on the received commands, the number of channels required to store the first data of the first tenant Tenant 1 in each of the plurality of ways. The storage controller 112A may determine, for each of the plurality of ways, the number of channels required to store the first data of the first tenant Tenant 1.

[0067] For example, when the number of commands received from the first tenant Tenant 1 is "192" which is a predetermined threshold, each of the commands is a write command for storing 4kB of data, and each memory die stores 192kB of data, the storage controller 112A may determine that four channels are required to store the first data of the first tenant Tenant 1 in each of the multiple ways.

[0068] The memory controller 112A may store the first data in as many memory dies as the number of channels determined to be required to store the first data among the memory dies corresponding to each of the plurality of ways.

[0069] For example, the memory controller 112A may store the first data in the memory dies corresponding to the first to fourth channels ch1 to ch4 in the first way w1. In addition, the memory controller 112A may store the first data in the memory dies corresponding to the fifth to eighth channels ch5 to ch8 in the second way w2.

[0070] The first data may be stored to correspond to each of the plurality of channels ch1 to chn through at least a portion (e.g., a portion or all of the portions) of the plurality of ways w1 to wn. In other words, the first data may be stored in a memory die corresponding to each of the plurality of channels ch1 to chn in at least a portion or all of the plurality of ways w1 to wn. For example, the first data may be stored to correspond to the plurality of channels ch1 to ch8 uniformly through the first way w1 and the second way w2 (e.g., stored in the same number of memory dies corresponding to each channel).

[0071] Referring to the above configuration, the storage controller 112A according to example embodiments may store data of each tenant such that the data of each tenant corresponds to a plurality of channels ch1 to chn through at least a portion of a plurality of ways w1 to wn.

[0072] Furthermore, the memory controller 112A according to example embodiments may read data of each tenant using all of the plurality of channels ch1 to chn in response to receiving a read request from each tenant.

[0073] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each tenant. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0074] Figure 2 It is shown Figure 1 A block diagram of a configuration of a storage controller.

[0075] Reference Figure 2 , the storage controller 112A may include a command queue 130 , an input command processor 141 , a channel distributor 142 , and a placement unit 143 .

[0076] According to an example embodiment, the storage controller 112A may include a command queue 130 configured to store commands transmitted from a plurality of tenants through the host 120 .

[0077] The storage controller 112A may receive commands and / or data of a plurality of tenants transmitted from the host 120 through the command queue 130 .

[0078] In addition, the storage controller 112A may store at least a portion of commands and data of a plurality of tenants transmitted from the host 120 through the command queue 130 .

[0079] According to an example embodiment, the storage controller 112A may include an input command processor 141 configured to obtain stored commands from the command queue 130 .

[0080] For example, the input command processor 141 may sequentially extract commands stored in the command queue 130 .

[0081] In addition, the input command processor 141 may identify a tenant who has generated a command and data included in the corresponding command based on information included in the corresponding command.

[0082] For example, the input command processor 141 may identify the first tenant who has generated the first command and the first data included in the first command based on the identifier included in the first command.

[0083] Additionally, the storage controller 112A may include a channel allocator 142 configured to determine a number of channels required to store the tenant's data based on information included in the command.

[0084] For example, the channel allocator 142 may determine the number of channels required to store the first data of the first tenant Tenant 1 in each way based on information included in the first command sent from the first tenant Tenant 1.

[0085] According to example embodiments, the channel allocator 142 may determine the number of commands received from a plurality of tenants and / or the number of write requests included in the received commands.

[0086] In addition, the channel allocator 142 may determine whether the number of commands received from the plurality of tenants or the number of write requests included in the received commands is greater than or equal to a predetermined threshold.

[0087] For example, the channel allocator 142 may determine whether the number of commands received from the first tenant Tenant 1 and the second tenant Tenant 2 is greater than or equal to “384” which is a predetermined threshold.

[0088] For example, the channel allocator 142 may determine whether the number of write requests included in the commands received from the first tenant Tenant 1 and the second tenant Tenant 2 is greater than or equal to “384” which is a predetermined threshold.

[0089] Furthermore, when the number of commands received from a plurality of tenants or the number of write requests included in the received commands is greater than or equal to a predetermined threshold, the channel allocator 142 may determine the number of channels required to store data of each tenant in each way.

[0090] For example, when the number of write requests included in the commands received from the first tenant Tenant 1 and the second tenant Tenant 2 is greater than or equal to a predetermined threshold, the channel allocator 142 can determine a first number of channels required for each way to store the first data of the first tenant Tenant 1, and a second number of channels required for each way to store the second data of the second tenant Tenant 2.

[0091] The number of lanes required to store each tenant's data in each way may be determined based on the number of commands (or write requests) received from each tenant and the amount of data to be stored in a single memory die.

[0092] For example, a write request for each command may be understood as a command or signal requesting storage of 4kB of data, but example embodiments are not limited thereto. However, for ease of description, an example in which a write request for each command is a command requesting storage of 4kB of data will be provided below.

[0093] For example, when 192 write requests are received from the first tenant Tenant 1 and 192 write requests are received from the second tenant Tenant 1, the channel allocator 142 may determine whether the number of write requests included in the commands received from the first tenant Tenant 1 and the second tenant Tenant 2 is greater than or equal to "384" which is a predetermined threshold. When 192 kB of data can be stored in each memory die, the channel allocator 142 may determine that four channels are required to store the first data. In addition, the channel allocator 142 may determine that four channels are required to store the second data.

[0094] For example, when 96 write requests are received from the first tenant Tenant 1 and 288 write requests are received from the second tenant Tenant 2, the channel allocator 142 may determine whether the number of write requests included in the commands received from the first tenant Tenant 1 and the second tenant Tenant 2 is greater than or equal to "384" as a predetermined threshold. When 192 kB of data can be stored in each memory die, the channel allocator 142 may determine that two channels are required to store the first data. In addition, the channel allocator 142 may determine that six channels are required to store the second data.

[0095] However, commands received from a plurality of tenants, write requests received from a plurality of tenants, and the amount of data that may be stored in each memory die are not limited to the above examples.

[0096] Furthermore, the predetermined threshold may be set based on the number of channels ch1 to chn and the amount of data that may be stored in one of the plurality of memory dies 150 .

[0097] For example, when the memory device 110A includes eight channels and data corresponding to 48 write requests are to be stored in each memory die, a threshold of 384 may be set.

[0098] However, the size of the predetermined threshold and the method for setting the threshold are not limited to the above-mentioned examples.

[0099] The memory controller 112A may include a placement unit 143 configured to store the first data in a number of memory dies equal to the number of channels determined by the channel allocator 142 among the memory dies corresponding to each way.

[0100] For example, the placement unit 143 may store the first data in the plurality of memory dies 150 such that the first data evenly corresponds to the plurality of channels ch1 to chn through the memory dies corresponding to at least a portion of the plurality of ways w1 to wn (e.g., is stored in the same number of memory dies corresponding to each channel).

[0101] For example, when it is determined that a first number of channels are required to store the first data in each way, the placement unit 143 may store the first data in a first number of memory dies among the memory dies corresponding to the first way w1 .

[0102] Furthermore, the placement unit 143 may store the first data in a first number of memory dies corresponding to channels in which data is not stored in the first way w1 , among the memory dies corresponding to the second way w2 .

[0103] Referring to the above configuration, the storage controller 112A according to example embodiments may store data of each tenant such that the data of each tenant corresponds to each of a plurality of channels ch1 to chn through at least a portion of a plurality of ways w1 to wn.

[0104] Furthermore, the memory controller 112A according to example embodiments may read data of each tenant using a plurality of channels ch1 to chn in response to receiving a read request from each tenant.

[0105] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each tenant. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0106] Figure 3A is a flowchart illustrating a method of operating a storage device according to an example embodiment, and Figure 3B is a diagram illustrating a plurality of memory dies represented in the form of a matrix according to example embodiments.

[0107] Refer to Figure 3A and Figure 3B , the storage controller 112A according to example embodiments may store data of each tenant in at least a portion of the plurality of memory dies 150 based on commands received from the plurality of tenants.

[0108] Reference Figure 3A and Figure 3B The storage device and storage controller described herein may be understood as respectively Figure 1 Therefore, the same reference numerals may be used to denote elements that are the same or substantially the same as those described above, and redundant descriptions will be omitted.

[0109] For example, the memory controller 112A may store data of each tenant in at least a portion of the plurality of memory dies 150 based on commands received from the plurality of tenants, such that the data of each tenant is stored to correspond to the plurality of channels ch1 to chn.

[0110] Reference Figure 3A , in operation S10, the storage controller 112A may receive commands from a plurality of tenants.

[0111] For example, the storage controller 112A may receive commands including write requests for each data from multiple tenants.

[0112] For example, the storage controller 112A may receive a command including a write request for first data from the first tenant Tenant 1. In addition, the storage controller 112A may receive a command including a write request for second data from the second tenant Tenant 2.

[0113] In operation S20 , the memory controller 112A may determine whether the number of received commands is greater than or equal to a threshold value.

[0114] For example, the storage controller 112A may determine whether the number of received commands is greater than or equal to a predetermined threshold. The storage controller 112A may determine whether the number of write requests included in the received commands is greater than or equal to a predetermined threshold.

[0115] The threshold value may be set based on the number of channels ch1 to chn and the amount of data to be stored in one of the plurality of memory dies 150 .

[0116] For example, when the memory device 110A includes eight channels and data corresponding to 48 write requests are to be stored in each memory die, a threshold of 384 may be set.

[0117] In operation S30 , the storage controller 112A may determine the number of channels required to store the first data of the first tenant Tenant 1 .

[0118] Reference Figure 3B , the plurality of memory dies 150 may correspond to eight ways and eight channels, respectively. Each way may include eight memory dies corresponding to a total of eight channels ch1 to ch8, respectively.

[0119] Thus, the array of multiple memory dies 150 may be represented as an 8×8 matrix having eight ways and eight channels.

[0120] However, the number and array of channels and ways to which the plurality of memory dies 150 correspond are not limited to the above-described examples, and the plurality of memory dies 150 may be configured to correspond to various numbers and arrays of channels and ways.

[0121] According to an example embodiment, the storage controller 112A may determine the number of channels required to store first data of the first tenant Tenant 1 in each of ways w1, w2, w3, w4, w5, w6, w7, and w8.

[0122] For example, the storage controller 112A (or the channel allocator 142) may determine the number of channels required to store the first data of the first tenant Tenant 1 in each of the ways w1, w2, w3, w4, w5, w6, w7, and w8 based on the received command.

[0123] For example, when the number of commands received from the first tenant is "192", each command requests storage of 4kB of data, and each memory die stores 192KB of data, the storage controller 112A may determine that four channels are required to store the first data of the first tenant Tenant 1 in each way.

[0124] In operation S40 , the memory controller 112A may store the first data in the memory dies respectively corresponding to the ways w1 , w2 , w3 , w4 , w5 , w6 , w7 , and w8 , based on the determined number of channels.

[0125] For example, when the storage controller 112A determines that a first number of channels are required to store first data in each of ways w1, w2, w3, w4, w5, w6, w7 and w8, the storage controller 112A may store the first data in a first number of memory dies among the memory dies corresponding to ways w1, w2, w3, w4, w5, w6, w7 and w8, respectively.

[0126] When it is determined that a first number of channels are required to store the first data in each of ways w1, w2, w3, w4, w5, w6, w7 and w8, the storage controller 112A may store the first data in a first number of memory dies among the memory dies D11, D21, D31, D41, D51, D61, D71 and D81 corresponding to the first way w1.

[0127] Furthermore, the memory controller 112A may store the first data in a first number of memory dies among the memory dies D12 , D22 , D32 , D42 , D52 , D62 , D72 , and D82 corresponding to the second way w2 .

[0128] The first data may be stored to correspond to the plurality of channels ch1 to ch8 through at least a portion of the plurality of ways w1 to w8 .

[0129] For example, when the first number of channels required to store the first data is determined to be four, the storage controller 112A may store the first data in the 1-1th memory die D11, the 2-1th memory die D21, the 3-1th memory die D31, and the 4-1th memory die D41 among the memory dies D11, D21, D31, D41, D51, D61, D71, and D81 corresponding to the first way w1.

[0130] In addition, the memory controller 112A may store the first data in the 5-2nd memory die D52, the 6-2nd memory die D62, the 7-2nd memory die D72, and the 8-2nd memory die D82 among the memory dies D12, D22, D32, D42, D52, D62, D72, and D82 corresponding to the second way w2.

[0131] In this case, for example, the first data may be stored to correspond to all of the plurality of channels ch1 to ch8 through the first way w1 and the second way w2 .

[0132] Referring to the above configuration, the storage controller 112A may store data of each tenant such that the data of each tenant corresponds to a plurality of channels ch1 to ch8 through at least a portion of a plurality of ways w1 to w8 .

[0133] Furthermore, the memory controller 112A according to example embodiments may read data of each tenant using a plurality of channels ch1 to ch8 in response to receiving a read request from each tenant.

[0134] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each of a plurality of tenants. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0135] Figure 4A is a flowchart illustrating a method in which a storage controller stores first data of a first tenant in a first way and a second way according to an example embodiment, and Figure 4B is a flowchart illustrating a method in which a storage controller stores second data of a second tenant in a first way and a second way according to an example embodiment.

[0136] Figure 5A is a diagram illustrating a configuration in which first data and second data are stored in a first way according to an example embodiment, Figure 5B is a diagram showing that first data and second data are stored in a second way according to an example embodiment, and Figure 5C is a diagram illustrating a configuration in which first data and second data are stored in a plurality of ways according to an embodiment. Figure 4A and Figure 4B The operation can be understood as Figure 3A Operation S30 in or an operation performed after operation S20.

[0137] Refer to Figure 4A and Figure 4B According to an embodiment, the storage controller 112A may store data of each of the plurality of tenants in at least a portion of the plurality of memory dies 150 based on a predetermined order (or array).

[0138] For example, the memory controller 112A may store data of each of the plurality of tenants in at least a portion of the plurality of memory dies 150 based on the number of channels determined to be required to store the data of each tenant and a predetermined order in which to store the data of each tenant.

[0139] For example, the storage controller 112A may store the first data of the first tenant Tenant 1 in a first number of memory dies among the memory dies D11 to D81 corresponding to the first way w1. In addition, the storage controller 112A may store the first data in a first number of memory dies among the memory dies D12 to D82 corresponding to the second way w2.

[0140] Reference Figure 4A In operation S41 , the memory controller 112A may store the first data in a first number of memory dies in the first way w1 .

[0141] Refer to Figure 4A and Figure 5A , the storage controller 112A may store the first data of the first tenant Tenant 1 in a first number of memory dies among the memory dies D11 to D81 corresponding to the first way w1.

[0142] The first number may be understood as the number of channels determined to be required to store the first data in each way.

[0143] For example, refer to Figure 5A , when it is determined that the number of channels required to store the first data in one way is four, the memory controller 112A may store the first data in the 1-1th memory die D11, the 2-1th memory die D21, the 3-1th memory die D31, and the 4-1th memory die D41 among the memory dies D11 to D81 corresponding to the first way w1.

[0144] In operation S42 , the memory controller 112A may store the first data in a first number of memory dies corresponding to channels in which the first data is not stored in the first way w1 , among the memory dies D12 and D82 corresponding to the second way w2 .

[0145] Refer to Figure 4A and Figure 5B , the storage controller 112A may store the first data of the first tenant Tenant 1 in a first number of memory dies among the memory dies D12 to D82 corresponding to the second way w2.

[0146] For example, the memory controller 112A may store the first data in a first number of memory dies corresponding to channels in which the first data is not stored in the first way w1 , among the memory dies D12 to D82 corresponding to the second way w2 .

[0147] For example, the memory controller 112A may store the first data in the memory dies corresponding to the fifth to eighth channels ch5 to ch8 in which the first data is not stored in the first way w1 , among the memory dies D12 to D82 corresponding to the second way w2 .

[0148] For example, the memory controller 112A may store the first data in the 5-2nd memory die D52, the 6-2nd memory die D62, the 7-2nd memory die D72, and the 8-2nd memory die D82 among the memory dies D12, D22, D32, D42, D52, D62, D72, and D82 corresponding to the second way w2.

[0149] According to the above configuration, the first data of the first tenant Tenant 1 may be stored to correspond to all of the plurality of channels ch1 to ch8 through the first way w1 and the second way w2 .

[0150] Therefore, the storage device 110A according to example embodiments may improve the read performance (eg, read speed) of the first data for the first tenant Tenant 1 .

[0151] Refer to Figure 4B , Figure 5A and Figure 5B , the storage controller 112A may store the second data of the second tenant Tenant 2 in a second number of memory dies among the memory dies D11 to D81 corresponding to the first way w1. In addition, the storage controller 112A may store the second data in a second number of memory dies among the memory dies D12 to D82 corresponding to the second way w2.

[0152] The second number may be understood as the number of channels determined to be required to store the second data in each way.

[0153] In operation S31 , the storage controller 112A may determine the number of channels required to store the second data of the second tenant Tenant 2 in each way.

[0154] For example, the storage controller 112A determines the number of channels required to store the second data of the second tenant Tenant 2 in each way based on the command obtained from the second tenant Tenant 2.

[0155] For example, when the number of commands received from the second tenant Tenant 2 is "192" and each memory die can store 192 kB of data, the storage controller 112A may determine that four channels are required to store the second data in each way.

[0156] Refer to Figure 4B and Figure 5A In operation S32 , the memory controller 112A may store the second data in a second number of memory dies in the first way w1 .

[0157] For example, the memory controller 112A may store the second data in a second number of memory dies among the memory dies D11 to D81 corresponding to the first way w1 .

[0158] The memory controller 112A may store the second data in a second number of memory dies that do not store the first data among the memory dies D11 to D81 corresponding to the first way w1 .

[0159] For example, refer to Figure 5A , the memory controller 112A may store the second data in the 5-1st memory die D51 , the 6-1st memory die D61 , the 7-1st memory die D71 , and the 8-1st memory die D81 among the memory dies D11 to D81 corresponding to the first way w1 .

[0160] Refer to Figure 4B and Figure 5B In operation S33 , the memory controller 112A may store the second data in a second number of memory dies corresponding to channels not storing the second data in the first way w1 among the memory dies D12 to D82 corresponding to the second way w2 .

[0161] Furthermore, the memory controller 112A may store the second data in a second number of memory dies corresponding to channels not storing the first data, among the memory dies D12 to D82 corresponding to the second way w2 .

[0162] For example, the memory controller 112A may store the second data in a second number of memory dies corresponding to channels that do not store the first data, among the memory dies D12 to D82 corresponding to the second way w2.

[0163] For example, the memory controller 112A may store the second data in the 1-2 nd memory die D12 , the 2-2 nd memory die D22 , the 3-2 nd memory die D32 , and the 4-2 nd memory die D42 among the memory dies D12 to D82 corresponding to the second way w2 .

[0164] According to the above configuration, the second data of the second tenant Tenant 2 may be stored to correspond to all of the plurality of channels ch1 to ch8 through the first way w1 and the second way w2 .

[0165] Therefore, the storage device 110A according to example embodiments may improve the read performance (eg, read speed) of the second data for the second tenant Tenant 2 .

[0166] According to example embodiments, the storage controller 112A may determine a ratio between the number of channels to store first data and the number of channels to store second data in each way based on commands received from the first tenant Tenant 1 and the second tenant Tenant 2.

[0167] The commands received from the corresponding tenants may be understood to include a write request for storing data of each tenant.

[0168] For example, the storage controller 112A may determine a ratio between the number of channels in each way where the first data and the second data are to be stored, respectively, based on the number of commands received from the first tenant Tenant 1 and the second tenant Tenant 2 per unit time.

[0169] For example, the storage controller 112A may identify a ratio between the numbers of channels where data of the plurality of tenants are to be respectively stored based on the number of predetermined channels for storing data of each of the plurality of tenants.

[0170] However, the method in which the storage controller 112A according to example embodiments determines the ratio between the numbers of channels required to store data of a plurality of tenants in each way, respectively, is not limited to the above example.

[0171] Furthermore, the memory controller 112A may store the first data and the second data in at least a portion of the plurality of memory dies 150 based on a ratio between the determined numbers of channels.

[0172] According to an example embodiment, when it is determined that the first data and the second data are to be stored in each way at a ratio of 1:1 in terms of the number of channels used to store the first data and the second data, the storage controller 112A may store each of the first data and the second data in four memory dies among eight memory dies corresponding to each way.

[0173] According to an example embodiment, when it is determined that the first data and the second data are to be stored at a ratio of 1:3 in terms of the number of channels used to store the first data and the second data, the memory controller 112A may store the first data in two memory dies among the eight memory dies corresponding to each way, and store the second data in the remaining six memory dies.

[0174] The storage controller 112A may store the first data and the second data based on a predetermined order.

[0175] For example, the memory controller 112A may alternately store the first data and the second data in four memory dies among eight memory dies corresponding to the first way w1.

[0176] For example, the memory controller 112A may store the first data in four consecutive memory dies among eight memory dies corresponding to the first way w1 , and store the second data in the remaining four consecutive memory dies.

[0177] However, the number of tenants, the ratio between channels for storing data of a plurality of tenants, and the order in which data is stored are not limited to the above examples.

[0178] Reference Figure 5C , both the first data and the second data may be stored to correspond to the plurality of channels ch1 to ch8 through the memory die corresponding to at least a portion of the plurality of ways w1 to w8.

[0179] The first data and the second data may each be stored to uniformly correspond to the plurality of channels ch1 to ch8 through the memory dies corresponding to at least a portion of the plurality of ways w1 to w8 .

[0180] The first data and the second data may each be stored to correspond to all of the plurality of channels ch1 to ch8 through a memory die corresponding to at least a portion of the plurality of ways w1 to w8 .

[0181] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each of a plurality of tenants. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0182] Fig. 6A is a diagram illustrating a configuration in which first data and second data are stored in a first way according to an example embodiment, Figure 6B is a diagram illustrating a configuration in which first data and second data are stored in a second way according to an example embodiment, and Figure 6C is a diagram illustrating a configuration in which first data and second data are stored in a plurality of ways according to an example embodiment.

[0183] Refer to Fig. 6A , Figure 6B and Figure 6C, the storage controller 112A according to an example embodiment may store the data of each tenant in at least a portion of the plurality of memory dies 150 based on the number of channels determined to be required to store the data of each tenant and a predetermined order (or array).

[0184] Fig. 6A , Figure 6B and Figure 6C The memory controller and multiple memory dies can be understood as Figure 1 The memory controller 112A corresponds to the plurality of memory dies 150. Therefore, the same reference numerals are used to denote elements that are the same or substantially the same as those described above, and redundant descriptions will be omitted.

[0185] According to example embodiments, the memory controller 112A may store the first data in a first number of memory dies among the memory dies D11 to D81 corresponding to the first way w1. The first number may be understood as the number of channels determined to be required to store the first data in each way.

[0186] Furthermore, the memory controller 112A may store the second data in a second number of memory dies among the memory dies D11 to D81 corresponding to the first way w1. The second number may be understood as the number of channels determined to be required to store the second data in each way.

[0187] According to example embodiments, first data and second data may be alternately stored in the memory dies D11 to D81 corresponding to the first way w1 .

[0188] For example, refer to Fig. 6A , the memory controller 112A may store the first data in the 1-1th memory die D11, the 3-1th memory die D31, the 5-1th memory die D51, and the 7-1th memory die D71 among the memory dies D11 to D81 corresponding to the first way w1.

[0189] Furthermore, the memory controller 112A may store the second data in the 2-1st memory die D21 , the 4-1st memory die D41 , the 6-1st memory die D61 , and the 8-1st memory die D81 among the memory dies D11 to D81 corresponding to the first way w1 .

[0190] In addition, refer to Figure 6B , the memory controller 112A may store the first data in a first number of memory dies corresponding to channels that do not store the first data in the first way w1 among the memory dies D12 to D82 corresponding to the second way w2 .

[0191] Furthermore, the memory controller 112A may store the second data in a second number of memory dies corresponding to channels not storing the first data, among the memory dies D12 to D82 corresponding to the second way w2 .

[0192] For example, when the second data is stored in the memory dies corresponding to the fifth channel ch5 to the eighth channel ch8 in the first way w1, the memory controller 112A may store the second data in the memory dies D12 to D82 corresponding to the second way w2, which correspond to the first channel ch1 to the fourth channel ch4 in which the second data is not stored in the first way w1 (see Figure 5B ).

[0193] According to example embodiments, first data and second data may be alternately stored in the memory dies D12 to D82 corresponding to the second way w2 .

[0194] For example, the first data and the second data may be stored in the memory dies D12 to D82 corresponding to the second way in an order opposite to that in which the first data and the second data are stored in the memory dies D11 to D81 corresponding to the first way w1 (or inverse array).

[0195] For example, refer to Figure 6B , the memory controller 112A may store the first data in the 2-2 nd memory die D22 , the 4-2 nd memory die D42 , the 6-2 nd memory die D62 , and the 8-2 nd memory die D82 among the memory dies D12 to D82 corresponding to the second way w2 .

[0196] Furthermore, the memory controller 112A may store the second data in the 1-2 nd memory die D12 , the 3-2 nd memory die D32 , the 5-2 nd memory die D52 , and the 7-2 nd memory die D72 among the memory dies D12 to D82 corresponding to the second way w2 .

[0197] Reference Figure 6C , the memory controller 112A according to example embodiments may alternately store the first data and the second data in a memory die corresponding to each of the plurality of ways w1 to w8.

[0198] Furthermore, the memory controller 112A may store the first data and the second data in the memory die corresponding to each way to have an order opposite to an order in which the first data and the second data are stored in adjacent ways.

[0199] Referring to the above configuration, the storage controller 112A may store pieces of data of a plurality of tenants based on a predetermined order so that the data of each tenant corresponds to a plurality of channels ch1 to ch8 through at least a portion of a plurality of ways w1 to w8 .

[0200] Furthermore, the storage controller 112A according to example embodiments may read data of each tenant using a plurality of channels (eg, ch1 to ch8 ) in response to receiving a read request from each tenant.

[0201] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each of a plurality of tenants. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0202] Fig. 7A is a diagram illustrating a configuration in which first data and second data requiring different numbers of channels are stored in a first way according to an example embodiment, Figure 7B is a diagram illustrating a configuration in which first data and second data requiring different numbers of channels are stored in a second way according to an example embodiment, and Figure 7C is a diagram illustrating a configuration in which first data and second data requiring different numbers of channels are stored in a plurality of ways according to example embodiments.

[0203] Refer to Fig. 7A , Figure 7B and Figure 7C , the memory controller 112A according to example embodiments may store data of each of the plurality of tenants in at least a portion of the plurality of memory dies 150 based on the number of channels determined to be required to store the data of each tenant.

[0204] Fig. 7A , Figure 7B and Figure 7C The memory controller and the plurality of memory dies may be understood as being respectively Figure 1 The memory controller 112A corresponds to the plurality of memory dies 150. Therefore, the same reference numerals are used to denote elements that are the same or substantially the same as those described above, and redundant descriptions will be omitted.

[0205] For example, when a different number of channels is required to store data of each of the multiple tenants in each way, the storage controller 112A may store data of each of the multiple tenants in at least a portion of the multiple memory dies 150 based on the number of channels required for the data of each tenant.

[0206] According to an example embodiment, the storage controller 112A may determine a ratio between the number of channels (or memory dies) in each way to store first data and second data, respectively, based on commands received from the first tenant Tenant 1 and commands received from the second tenant Tenant 2.

[0207] Furthermore, the memory controller 112A may store the first data and the second data in at least a portion of the plurality of memory dies 150 based on a ratio between the determined numbers of channels.

[0208] For example, when it is determined that the first data and the second data are to be stored in each way at a channel ratio of 1:3, for each way, the storage controller 112A may store the first data in memory dies corresponding to two channels among the memory dies corresponding to eight channels, and store the second data in memory dies corresponding to six channels.

[0209] For example, refer to Fig. 7A , the memory controller 112A may store the first data in the 1-1th memory die D11 and the 5-1th memory die D51 among the memory dies D11 to D81 corresponding to the first way w1.

[0210] Furthermore, the memory controller 112A may store the second data in the 2-1st memory die D21, the 3-1st memory die D31, the 4-1st memory die D41, the 6-1st memory die D61, the 7-1st memory die D71, and the 8-1st memory die D81 among the memory dies D11 to D81 corresponding to the first way w1.

[0211] Furthermore, the memory controller 112A may store the first data in a first number of memory dies corresponding to channels in which the first data is not stored in the first way w1 , among the memory dies D12 to D82 corresponding to the second way w2 .

[0212] Furthermore, the memory controller 112A may store the second data in a second number of memory dies corresponding to channels that do not store the second data in the first way w1 among the memory dies D12 to D82 corresponding to the second way w2 .

[0213] For example, refer to Figure 7B , the memory controller 112A may store the first data in the 2-2 nd memory die D22 and the 6-2 nd memory die D62 among the memory dies D12 to D82 corresponding to the second way w2.

[0214] Furthermore, the memory controller 112A may store the second data in the 1-2 nd memory die D12, the 3-2 nd memory die D32, the 4-2 nd memory die D42, the 5-2 nd memory die D52, the 7-2 nd memory die D72, and the 8-2 nd memory die D82 among the memory dies D12 to D82 corresponding to the second way w2.

[0215] Furthermore, the memory controller 112A may store the first data in the 3-3rd memory die D33 and the 7-3rd memory die D73 among the memory dies D13 to D83 corresponding to the third way w3.

[0216] In addition, the memory controller 112A may store the second data in the 1st-3rd memory die D13, the 2nd-3rd memory die D23, the 4th-3rd memory die D43, the 5th-3rd memory die D53, the 6th-3rd memory die D63, and the 8th-3rd memory die D83 among the memory dies D13 to D83 corresponding to the third way w3.

[0217] Furthermore, the memory controller 112A may store the first data in the 4-4th memory die D44 and the 8-4th memory die D84 among the memory dies D14 to D84 corresponding to the fourth way w4.

[0218] In addition, the memory controller 112A may store the second data in the 1st-4th memory die D14, the 2nd-4th memory die D24, the 3rd-4th memory die D34, the 5th-4th memory die D54, the 6th-4th memory die D64, and the 7th-4th memory die D74 among the memory dies D13 to D83 corresponding to the third way w3.

[0219] The first data and the second data may be stored to correspond to a plurality of channels ch1 to ch8 through memory dies corresponding to the first to fourth ways w1 to w4 .

[0220] When the number of channels required to store the first data and the number of channels required to store the second data are different from each other, the memory controller 112A may first store data requiring a smaller number of channels in the memory dies D12 to D82 corresponding to the second way w2 .

[0221] For example, when a first number of channels required to store the first data (e.g., "2") is less than a second number of channels required to store the second data (e.g., "6"), the storage controller 112A may store the first data in a first number of memory dies among the memory dies D12 to D82 corresponding to the second way w2, and may then store the second data in a second number of memory dies among the memory dies D12 to D82 corresponding to the second way w2.

[0222] Reference Figure 7C , the memory controller 112A according to example embodiments may store the first data and the second data in a number of memory dies based on the determined ratio among the memory dies corresponding to each of the plurality of ways w1 to w8 .

[0223] Referring to the above configuration, the storage controller 112A may store data of each tenant requiring a different number of channels in each way so that the data of each tenant corresponds to the multiple channels ch1 to ch8 through at least a portion of the multiple ways w1 to w8 .

[0224] Furthermore, the storage controller 112A according to example embodiments may read stored data of each tenant using a plurality of channels ch1 to ch8 in response to receiving a read request from each tenant.

[0225] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each of a plurality of tenants. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0226] Figure 8 is a diagram illustrating a configuration in which a storage controller stores data for each of a plurality of tenants according to an example embodiment.

[0227] Reference Figure 8 According to an embodiment, the storage controller 112A may store data of each of the plurality of tenants in at least a portion of the plurality of memory dies 150 based on the number of channels and a predetermined order (or array) determined to be required to store the data of each tenant.

[0228] Figure 8 The memory controller and the plurality of memory dies may be understood as being respectively Figure 1 The memory controller 112A corresponds to the plurality of memory dies 150. Therefore, the same reference numerals are used to denote elements that are the same or substantially the same as those described above, and redundant descriptions will be omitted.

[0229] According to example embodiments, the storage controller 112A may obtain a command including a write request for each data from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0230] In addition, the storage controller 112A may determine the number of channels required to store data of each tenant in each way based on commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0231] For example, the storage controller 112A may determine that a first number of channels are required to store the first data of the first tenant in each way. Furthermore, the storage controller 112A may determine that a second number of channels are required to store the second data of the second tenant in each way. Furthermore, the storage controller 112A may determine that a third number of channels are required to store the third data of the third tenant in each way. Furthermore, the storage controller 112A may determine that a fourth number of channels are required to store the fourth data of the fourth tenant in each way.

[0232] For example, the storage controller 112A may determine, based on commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4, that two channels (or two memory dies corresponding to the two channels) are required to store data of each tenant in each way.

[0233] The storage controller 112A may store the data of each tenant in at least a portion of the memory die corresponding to each way based on the number of channels determined to be required to store the data of each tenant in each way.

[0234] The first data, the second data, the third data, and the fourth data may be alternately stored in the memory dies D11 , D21 , D31 , D41 , D51 , D61 , D71 , and D81 corresponding to the first way w1 .

[0235] For example, the memory controller 112A may store the first data in the 1-1th memory die D11 and the 5-1th memory die D51 among the memory dies D11 to D81 corresponding to the first way w1 .

[0236] Furthermore, the memory controller 112A may store the second data in the 2-1st memory die D21 and the 6-1st memory die D61 among the memory dies D11 to D81 corresponding to the first way w1 .

[0237] Furthermore, the memory controller 112A may store the third data in the 3-1st memory die D31 and the 7-1st memory die D71 among the memory dies D11 to D81 corresponding to the first way w1 .

[0238] Furthermore, the memory controller 112A may store the fourth data in the 4-1st memory die D41 and the 8-1st memory die D81 among the memory dies D11 to D81 corresponding to the first way w1 .

[0239] Furthermore, the memory controller 112A may store the first data in a first number of memory dies corresponding to channels in which the first data is not stored in the first way w1 , among the memory dies D12 to D82 corresponding to the second way w2 .

[0240] Furthermore, the memory controller 112A may store the second data in a second number of memory dies corresponding to channels that do not store the second data in the first way w1 among the memory dies D12 to D82 corresponding to the second way w2 .

[0241] Furthermore, the memory controller 112A may store the third data in a third number of memory dies corresponding to channels that do not store the third data in the first way w1 among the memory dies D12 to D82 corresponding to the second way w2 .

[0242] Furthermore, the memory controller 112A may store the fourth data in a fourth number of memory dies corresponding to channels that do not store the fourth data in the first way w1 among the memory dies D12 to D82 corresponding to the second way w2 .

[0243] The first data, the second data, the third data, and the fourth data may be alternately stored in the memory dies D12 to D82 corresponding to the second way w2.

[0244] Furthermore, the memory controller 112A according to the embodiment may alternately store the first data, the second data, the third data, and the fourth data to the memory die corresponding to each of the plurality of ways w1 to w8 .

[0245] According to example embodiments, the memory controller 112A may store the first data, the second data, the third data, and the fourth data in the memory die corresponding to each way based on a predetermined order.

[0246] However, the order in which the first data, the second data, the third data, and the fourth data are stored in each way is not limited to the above example.

[0247] According to example embodiments, each of the first data, the second data, the third data, and the fourth data may be stored to correspond to the plurality of channels ch1 to ch8 through at least a portion of the plurality of ways w1 to w8 .

[0248] For example, each of the first data, the second data, the third data, and the fourth data may be stored to correspond to the plurality of channels ch1 to ch8 through the first to fourth ways w1 to w4 .

[0249] Referring to the above configuration, the storage controller 112A may store data of each of the plurality of tenants such that the data of each tenant corresponds to the plurality of channels ch1 to ch8 through at least a portion of the plurality of ways w1 to w8 .

[0250] Furthermore, the memory controller 112A according to example embodiments may read data of each tenant using a plurality of channels ch1 to ch8 in response to receiving a read request from each tenant.

[0251] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each of a plurality of tenants. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0252] Fig. 9 is a diagram illustrating a configuration in which a storage controller stores data of each of a plurality of tenants requiring a different number of channels according to an example embodiment.

[0253] Reference Fig. 9 According to an example embodiment, the storage controller 112A may store data of each of the plurality of tenants in at least a portion of the plurality of memory dies 150 based on the number of channels determined to be required to store the data of each of the plurality of tenants and a predetermined order (or array).

[0254] Fig. 9 The memory controller and the plurality of memory dies may be understood as being respectively Figure 1 The memory controller 112A corresponds to the plurality of memory dies 150. Therefore, the same reference numerals are used to denote elements that are the same or substantially the same as those described above, and redundant descriptions will be omitted.

[0255] For example, when a different number of channels is required to store data of each of the multiple tenants in each way, the storage controller 112A may store data of each of the multiple tenants in at least a portion of the multiple memory dies 150 based on the number of channels required for the data of each tenant.

[0256] According to example embodiments, the storage controller 112A may obtain a command including a write request for each data from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0257] In addition, the storage controller 112A may determine the number of channels required to store data of each tenant in each way based on commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0258] For example, the storage controller 112A may determine the number of channels required to store data of each tenant in each way based on the number of commands obtained from each tenant among commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0259] For example, the storage controller 112A may determine based on commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4 that a single channel (or a single memory die) is required to store the first data of the first tenant Tenant 1 in each way.

[0260] Furthermore, the storage controller 112A may determine that a single channel (or a single memory die) is required to store the second data of the second tenant Tenant 2 in each way based on commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0261] Furthermore, the storage controller 112A may determine that a single channel (or a single memory die) is required to store third data of the third tenant Tenant 3 in each way based on commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0262] Furthermore, the storage controller 112A may determine that five channels (or five memory dies) are required to store the fourth data of the fourth tenant Tenant 4 in each way based on the commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0263] According to an example embodiment, the storage controller 112A may determine a ratio between the number of channels (or memory dies) storing data of the first tenant Tenant 1 to the fourth tenant Tenant 4 in each way, respectively, based on commands obtained from the first tenant Tenant 1 to the fourth tenant Tenant 4.

[0264] For example, the storage controller 112A may determine that data of the first tenant Tenant 1 through data of the fourth tenant Tenant 4 are to be stored in the memory die corresponding to each way at a ratio of 1:1:1:5 in terms of the number of channels used to store the data of the first tenant through the fourth tenant.

[0265] In this case, the memory controller 112A may store the first data in a single memory die among the memory dies corresponding to each way, store the second data in a single memory die, store the third data in a single memory die, and store the fourth data in five memory dies.

[0266] For example, the memory controller 112A may store the first data in the 1-1st memory die D11. Furthermore, the memory controller 112A may store the second data in the 2-1st memory die D21. Furthermore, the memory controller 112A may store the third data in the 3-1st memory die D31. Furthermore, the memory controller 112A may store the fourth data in the 4-1st memory die D41, the 5-1st memory die D51, the 6-1st memory die D61, the 7-1st memory die D71, and the 8-1st memory die D81.

[0267] For example, the memory controller 112A may store the first data in the 2-2nd memory die D22. Furthermore, the memory controller 112A may store the second data in the 3-2nd memory die D32. Furthermore, the memory controller 112A may store the third data in the 4-2nd memory die D42. Furthermore, the memory controller 112A may store the fourth data in the 1-2nd memory die D12, the 5-2nd memory die D52, the 6-2nd memory die D62, the 7-2nd memory die D72, and the 8-2nd memory die D82.

[0268] However, the array and / or order in which the first to fourth data are stored in the memory die corresponding to each way is not limited to the above example.

[0269] The memory controller 112A may store the first data, the second data, the third data, and the fourth data in the plurality of memory dies 150 based on the determined number (or ratio) of channels such that data of each tenant corresponds to the plurality of channels ch1 to ch8 .

[0270] For example, each of the first data, the second data, the third data, and the fourth data may be stored to correspond to the plurality of channels ch1 to ch8 through the first way w1 to the eighth way w8 .

[0271] Referring to the above configuration, the storage controller 112A may store data of each tenant such that the data of each tenant corresponds to a plurality of channels ch1 to ch8 through at least a portion of a plurality of ways w1 to w8 .

[0272] Furthermore, the memory controller 112A according to example embodiments may read data of each tenant using a plurality of channels ch1 to ch8 in response to receiving a read request from each tenant.

[0273] Therefore, the storage device 110A according to example embodiments may improve the read performance of data for each of a plurality of tenants. For example, the storage device 110A may improve the read speed of sequential read of data for each of a plurality of tenants.

[0274] Fig. 10A is a block diagram of a storage system according to an example embodiment, and Fig. 10B It is shown Fig. 10A A block diagram of a configuration of a storage controller. Fig.11A is a flowchart illustrating a method in which a memory controller stores first data and second data using a plurality of word lines according to example embodiments, Fig. 11B is a diagram illustrating a configuration in which a memory controller stores first data and second data using a first word line according to example embodiments, and Fig. 11Cis a diagram illustrating a configuration in which a memory controller stores first data and second data using a second word line according to example embodiments. Fig.11A The operation can be understood as Figure 3A Operations performed after operation S30 in .

[0275] Reference Fig. 10A , the storage system 100B may include a host 120 and a storage device 110B. In addition, the storage device 110B may include a storage controller 112B and a non-volatile memory device 111.

[0276] Fig. 10A The storage system 100B and the storage device 110B may be understood as respectively Figure 1 Therefore, the same reference numerals are used to denote elements that are the same or substantially the same as those described above, and redundant descriptions will be omitted.

[0277] According to example embodiments, the nonvolatile memory device 111 of the storage device 110B may include a plurality of memory dies 150 each storing data transmitted from a plurality of tenants Tenant 1 to Tenant n.

[0278] Each of the plurality of memory dies 150 may include a plurality of word lines. Data transmitted from a plurality of tenants Tenant 1 to Tenant n may be stored in memory cells connected to a selected word line among the plurality of word lines.

[0279] For example, the memory controller 112B may select the 1-1th word line WL11 of the 1-1th memory die D11 corresponding to the first channel ch1 and the first way w1. In this case, the first data transmitted from the first tenant Tenant 1 may be stored in the memory cell connected to the 1-1th word line WL11 of the 1-1th memory die D11.

[0280] In addition, the memory controller 112B may select the 1-2 word line WL12 of the 1-1th memory die D11. In this case, the second data transmitted from the second tenant Tenant 2 may be stored in the memory cell connected to the 1-2 word line WL12 of the 1-1th memory die D11.

[0281] In addition, the memory controller 112B may select the 3-1st word line WL31 of the 1-2nd memory die D12 corresponding to the first channel ch1 and the second way w2. In this case, the second data transmitted from the second tenant Tenant 2 may be stored in the memory cell connected to the 3-1st word line WL31 of the 1-2nd memory die D12.

[0282] In addition, the memory controller 112B may select the 3-2 th word line WL32 from the 1-2 th memory die D12. In this case, the first data transmitted from the first tenant Tenant 1 may be stored in the memory cell connected to the 3-2 th word line WL32.

[0283] However, the configuration in which the memory controller 112B stores data of each of the plurality of tenants using at least a portion of the plurality of word lines is not limited to the above example.

[0284] Reference Fig. 10B , the memory controller 112B may include a command queue 130 , an input command processor 141 , a channel distributor 142 , a word line distributor 149 , and a placement unit 143 .

[0285] The command queue 130, the input command processor 141, the channel distributor 142 and the placement unit 143 can be understood as having Figure 2 The command queue 130, the input command processor 141, the channel distributor 142, and the placement unit 143 have the same configuration. Therefore, a redundant description will be omitted.

[0286] According to example embodiments, the word line allocator 149 may select at least a portion of word lines in which data will be stored among a plurality of word lines based on data previously stored in each memory die.

[0287] For example, the word line allocator 149 may select at least a portion of the plurality of word lines of each of the plurality of memory dies 150 so that data of each tenant corresponds to each of the plurality of memory dies 150 .

[0288] For example, when first data of the first tenant Tenant 1 is previously stored in a memory cell of the 1-1 word line WL11 connected to the 1-1 memory die D11, the word line distributor 149 may control the 1-1 memory die D11 so that second data of the second tenant Tenant 2 is stored in a memory cell of the 1-2 word line WL12 connected to the 1-1 memory die D11.

[0289] For example, when the second data of the second tenant Tenant 2 was previously stored in the memory cell of the 3-1 word line WL31 connected to the 1-2 memory die D12, the word line distributor 149 can control the 1-2 memory die D12 so that the first data of the first tenant Tenant 1 is stored in the memory cell of the 3-2 word line WL32 connected to the 1-2 memory die D12.

[0290] First data of the first tenant Tenant 1 may be stored to correspond to each of the plurality of memory dies 150. Also, second data of the second tenant Tenant 2 may be stored to correspond to each of the plurality of memory dies 150.

[0291] Refer to FIG. 10A to FIG. 11C , the memory controller 112B according to example embodiments may store data of a plurality of tenants in cells connected to at least a portion of a plurality of word lines included in each of the plurality of memory dies 150 .

[0292] For example, the memory controller 112B may select a corresponding word line among a plurality of word lines included in each of the plurality of memory dies. The memory controller 112B may store the data of each tenant in a memory cell connected to the selected word line so that the data of each tenant corresponds to each of the plurality of memory dies 150.

[0293] Reference Fig.11A In operation S51 , the memory controller 112B may store first data in a first number of memory dies among the memory dies corresponding to each way using at least a portion of the plurality of first word lines WL1 .

[0294] The plurality of first word lines WL1 may be understood as a plurality of word lines (eg, Fig. 10A For example, the plurality of first word lines WL1 in different memory dies may correspond to each other based on the position (or order) of the first word lines among the plurality of word lines included in each of the plurality of memory dies 150.

[0295] For example, the memory controller 112B may store the first data in the memory cells connected to “at least a portion of the plurality of first word lines WL1 of a first number of memory dies among the memory dies corresponding to each way”.

[0296] Refer to Fig.11A and Fig. 11B , the memory controller 112B may store the first data in a portion of a plurality of first word lines WL1 connected to a first number of memory dies among the memory dies corresponding to the first way w1 (eg, Fig. 10A In the memory cells "WL11 and WL21)".

[0297] For example, the memory controller 112B may store the first data in a portion of the plurality of first word lines WL1 connected to the 1-1 memory die D11, the 2-1 memory die D21, the 3-1 memory die D31, and the 4-1 memory die D41 corresponding to the first way w1 (e.g., Fig. 10A In the memory cells "WL11 and WL21)".

[0298] Furthermore, the memory controller 112B may store the second data in the memory cells connected to “at least a portion of the plurality of first word lines WL1 of a second number of memory dies among the memory dies corresponding to the first way w1 ”.

[0299] For example, the memory controller 112B may store the second data in memory cells connected to “at least a portion of the plurality of first word lines WL1 of the 5-1st memory die D51 , the 6-1st memory die D61 , the 7-1st memory die D71 , and the 8-1st memory die D81 ”.

[0300] According to example embodiments, the memory controller 112B may store the first data and the second data in a memory die corresponding to the second way w2 such that each of the first data and the second data corresponds to a plurality of channels ch1 to ch8 through the first way w1 and the second way w2 .

[0301] For example, the memory controller 112B may store the first data in memory cells corresponding to at least a portion of the plurality of first word lines WL1 corresponding to the 5-2 nd memory die D52 , the 6-2 nd memory die D62 , the 7-2 nd memory die D72 , and the 8-2 nd memory die D82 of the second way w2 .

[0302] In addition, the memory controller 112B may store the second data in at least a portion (e.g., Fig. 10A In the memory cells "WL31 and WL41)".

[0303] The operation of the memory controller 112B storing the first data and the second data in the memory cells connected to the plurality of first word lines WL1 can be understood as FIG. 4A to FIG. 5C The operation of the memory controller 112A to store the first data and the second data in at least a portion of the plurality of memory dies 150 is substantially the same.

[0304] Refer to Fig.11A and Fig. 11CIn operation S52, the memory controller 112B may store the first data in a first number of memory dies among the memory dies corresponding to each way using at least a portion of the plurality of second word lines WL2.

[0305] For example, the memory controller 112B may store the first data in the memory cells connected to “at least a portion of the plurality of second word lines WL2 of a first number of memory dies among the memory dies corresponding to the first way w1 ”.

[0306] The plurality of second word lines WL2 may be understood as a plurality of word lines (eg, Fig. 10A For example, the plurality of second word lines WL2 in different memory dies may correspond to each other based on the positions (or order) of the second word lines among the plurality of word lines included in each of the plurality of memory dies 150.

[0307] For example, the memory controller 112B may store the first data in memory cells corresponding to at least a portion of the second word lines WL2 of the 5-1st memory die D51, the 6-1st memory die D61, the 7-1st memory die D71, and the 8-1st memory die D81 among the memory dies corresponding to the first way w1.

[0308] Furthermore, the memory controller 112B may store the second data in memory cells corresponding to at least a portion of the plurality of second word lines WL2 corresponding to a second number of memory dies among the memory dies of the first way w1 .

[0309] For example, the memory controller 112B may store the second data in at least a portion (e.g., Fig. 10A In the memory cells "WL12 and WL22)".

[0310] According to example embodiments, the memory controller 112B may store the first data and the second data in a memory die corresponding to the second way w2 such that each of the first data and the second data corresponds to a plurality of channels ch1 to ch8 through the first way w1 and the second way w2 .

[0311] For example, the memory controller 112B may store the first data in at least a portion of the plurality of second word lines WL2 connected to the 1-2 memory die D12, the 2-2 memory die D22, the 3-2 memory die D32, and the 4-2 memory die D42 corresponding to the second way w2 (e.g., Fig. 10A In the memory cells of "WL32 and WL42)".

[0312] Furthermore, the memory controller 112B may store the second data in the memory cells connected to at least a portion of the second word lines WL2 of the 5-2nd memory die D52, the 6-2nd memory die D62, the 7-2nd memory die D72, and the 8-2nd memory die D82 corresponding to the second way w2.

[0313] However, the order of performing operations S51 and S52 is not limited to Fig.11A According to example embodiments, operation S51 and operation S52 may be sequentially performed for each way.

[0314] The order in which the first data and the second data are stored in the memory cells connected to the plurality of second word lines WL2 may be understood as an order opposite to the order in which the first data and the second data are stored in the memory cells connected to the plurality of word lines WL1 .

[0315] The memory controller 112B may store the data of each tenant in memory cells of at least a portion of the plurality of word lines connected to each of the plurality of memory dies 150 such that the data of each tenant corresponds to each of the plurality of memory dies 150 .

[0316] Data of each of the plurality of tenants may be stored to correspond to each of the plurality of memory dies 150 through a memory cell connected to at least a portion of the plurality of word lines.

[0317] For example, the memory controller 112B may store the tenant's data “distinguished from the tenant's data stored in the memory cells connected to at least a portion of the plurality of first word lines WL1” in the memory cells of at least a portion of the plurality of second word lines WL2 connected to each of the plurality of memory dies. The memory controller 112B may store the tenant's data in the memory cells of at least a portion of the plurality of first word lines WL1 connected to each of the plurality of memory dies, and store the tenant's data in the memory cells of at least a portion of the plurality of second word lines WL2 connected to each of the plurality of memory dies.

[0318] Therefore, the number and distribution of memory dies storing each tenant's data may increase.

[0319] For example, when the storage device 110 receives a read request for data of a specific tenant, the number of memory dies used to read the data of the tenant may increase.

[0320] Therefore, the storage device 110B according to example embodiments may improve the read performance of data for each of a plurality of tenants. For example, the storage device 110 may improve the read speed of random read of data for each of a plurality of tenants.

[0321] As described above, the storage controller 112 according to example embodiments may store data of each tenant such that the data of each tenant corresponds to a plurality of channels through at least a portion of a plurality of ways.

[0322] Furthermore, the storage controller 112 according to example embodiments may read data of each tenant using a plurality of channels in response to receiving a read request from each tenant.

[0323] Therefore, the storage device 110 according to example embodiments may improve the read performance of data for each tenant. For example, the storage device 110 may improve the read speed of sequential read of data for each of a plurality of tenants.

[0324] Furthermore, the memory controller 112 according to example embodiments may store data of each tenant in memory cells of at least a portion of a plurality of word lines connected to each of the plurality of memory dies 150 , such that data of each of the plurality of tenants corresponds to each of the plurality of memory dies 150 .

[0325] Therefore, the number and distribution of memory dies storing data of each of the plurality of tenants may increase. As a result, the storage device 110 according to example embodiments may improve performance (eg, speed) of random reads for data of each of the plurality of tenants.

[0326] As described above, a memory device according to example embodiments may improve read performance.

[0327] According to example embodiments, at least one of the components, elements, modules and units described herein may be implemented as various numbers of hardware, software and / or firmware structures that perform the above-mentioned corresponding functions. For example, at least one of these components, elements and units may use a direct circuit structure (such as memory, processor, logic circuit, lookup table, etc.) that can perform the corresponding functions through the control of one or more microprocessors or other control devices. In addition, at least one of these components, elements and units may be specifically implemented by a part of a module, program or code that contains one or more executable instructions for performing a specified logical function and is performed by one or more microprocessors or other control devices. In addition, at least one of these components, elements and units may also include a processor (such as a central processing unit (CPU), microprocessor, etc. that performs the corresponding functions), or may be implemented by a processor (such as a central processing unit (CPU), microprocessor, etc. that performs the corresponding functions). Two or more of these components, elements and units may be combined into a single component, element or unit that performs all operations or functions of two or more components, elements and units combined. In addition, at least a part of the function of at least one of these components, elements and units may be performed by another of these components, elements and units. In addition, although the bus is not shown in the block diagram, the communication between components, elements or units may be performed by the bus. The functional aspects of the above exemplary embodiments may be implemented in algorithms executed on one or more processors. In addition, components, elements or units represented by blocks or processing operations may adopt any number of related technologies for electronic configuration, signal processing and / or control, data processing, etc.

[0328] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the inventive concept as defined by the appended claims and their equivalents.

Claims

1. A storage device, comprising: Multiple memory dies, corresponding to multiple channels and multiple ways; as well as a memory controller connected to the plurality of memory dies, The storage controller is configured as follows: Receive commands from multiple tenants; In response to the number of received commands being equal to or greater than a predetermined threshold, determining a first number of channels required to store first data of a first tenant among the plurality of tenants in each of the plurality of ways based on the commands received from each of the plurality of tenants; and storing first data in a first number of memory dies in each of the plurality of ways, and The first data is stored in the memory dies corresponding to the plurality of channels in at least a portion or all of the plurality of ways.

2. The storage device according to claim 1, wherein: The storage controller is also configured to: storing the first data in a first number of memory dies among the memory dies corresponding to the first way; and The first data is stored in a first number of memory dies corresponding to channels in the first way that do not store the first data, among the memory dies corresponding to the second way.

3. The storage device according to claim 2, wherein: The storage controller is also configured to: determining, based on a command received from a second tenant of the plurality of tenants, a second number of lanes required to store second data of the second tenant in each of the plurality of ways; and storing second data in a second number of memory dies in each way of the plurality of ways, and The second data is stored in the memory dies corresponding to the plurality of channels in at least a portion or all of the plurality of ways.

4. The storage device according to claim 3, wherein: The storage controller is also configured to: storing the second data in a second number of memory dies among the memory dies corresponding to the first way and not storing the first data; and The second data is stored in at least a portion of the memory dies corresponding to the channels not storing the second data in the first way among the memory dies corresponding to the second way and not storing the first data.

5. The storage device according to claim 4, wherein: The memory controller is further configured to store the first data and the second data in the memory die corresponding to the first way based on the first number, the second number, and a predetermined order in which the first data and the second data are stored.

6. The storage device according to claim 5, wherein: Based on the first number being less than the second number, the memory controller is further configured to: store the first data in a first number of memory dies in the second way, and subsequently store the second data in a second number of memory dies in the second way.

7. The storage device according to claim 1, wherein: The memory controller is further configured to, in response to receiving a read request for the first data, output the first data using the plurality of channels.

8. The storage device according to any one of claims 2 to 6, wherein: each of the plurality of memory dies comprises a plurality of word lines, The memory controller is further configured to: store the first data in memory cells connected to word lines corresponding to each other in a first number of memory dies corresponding to each of the plurality of ways, and The first data is stored to correspond to each of the plurality of memory dies.

9. The storage device according to claim 8, wherein: The storage controller is also configured to: storing first data in a first number of memory dies among the memory dies corresponding to the first way using at least a portion of a plurality of first word lines corresponding to each other in each of the plurality of memory dies; and The first data is stored in a first number of memory dies corresponding to the second way and not storing the first data in memory cells connected to the first word line of each of the memory dies corresponding to the first way, using at least a portion of the plurality of second word lines corresponding to each other in each of the plurality of memory dies.

10. The storage device according to any one of claims 1 to 7, wherein: The memory controller is further configured to determine a first number of channels based on a number of commands received from the first tenant and an amount of data to be stored in a single memory die among the plurality of memory dies.

11. A method for operating a storage device, the method comprising: Receive commands from multiple tenants; In response to the number of received commands being equal to or greater than a predetermined threshold, determining a first number of channels among a plurality of channels required to store first data of a first tenant among the plurality of tenants in each of a plurality of ways based on the commands received from each of the plurality of tenants, each of the plurality of channels including a plurality of memory dies corresponding to the plurality of ways; as well as storing first data in a first number of memory dies in each of the plurality of ways, The first data is stored in the memory dies corresponding to the plurality of channels in at least a portion or all of the plurality of ways.

12. The method of claim 11, wherein: The step of storing the first data comprises: storing first data in a first number of memory dies among the memory dies corresponding to a first way among the plurality of ways; and The first data is stored in a first number of memory dies corresponding to channels in the first way that do not store the first data, among the memory dies corresponding to a second way among the plurality of ways.

13. The method of claim 12, further comprising: determining a second number of lanes required to store second data of a second tenant of the plurality of tenants in each of the plurality of lanes; as well as storing second data in a second number of memory dies in each way of the plurality of ways, The second data is stored in the memory dies corresponding to the plurality of channels in at least a portion or all of the plurality of ways.

14. The method of claim 13, wherein: The step of storing the second data comprises: storing the second data in a second number of memory dies among the memory dies corresponding to the first way and not storing the first data; and The second data is stored in at least a portion of the memory dies corresponding to the channels not storing the second data in the first way among the memory dies corresponding to the second way and not storing the first data.

15. The method of claim 14, wherein: The first data and the second data are stored in the memory die corresponding to the first way based on the first number, the second number, and a predetermined order in which the first data and the second data are stored.

16. The method of claim 15, wherein: The first number is less than the second number, and storing the second data includes storing the second data in a second number of memory dies in the second way after storing the first data in the first number of memory dies in the second way.

17. The method of claim 11, further comprising: In response to receiving a read request for the first data, the first data is output using the plurality of channels.

18. The method of any one of claims 12 to 16, further comprising: storing first data in a first number of memory dies among the memory dies corresponding to the first way using at least a portion of a plurality of first word lines corresponding to each other in each of the plurality of memory dies; as well as storing the first data in a first number of memory dies that do not store the first data in memory cells connected to the first word line among the memory dies corresponding to the second way using at least a portion of the plurality of second word lines corresponding to each other in each of the plurality of memory dies, The first data is stored to correspond to each of the plurality of memory dies.

19. A storage device, comprising: A nonvolatile memory device comprising a plurality of channels, each of the plurality of channels comprising a plurality of memory dies corresponding to a plurality of ways; as well as Storage Controller, The storage controller includes: A command queue, configured to: store commands sent from multiple tenants; An input command processor is configured to: obtain the command from a command queue; a channel allocator configured to: determine a first number of channels required to store first data of a first tenant based on information included in the command; and a placement unit configured to: store the first data in a first number of memory dies in each way of the plurality of ways, and The first data is uniformly stored in the memory dies corresponding to the plurality of channels in at least a portion or all of the plurality of ways.

20. The storage device of claim 19, wherein: The placement unit is also configured to: storing first data in a first number of memory dies among the memory dies corresponding to the first way; as well as The first data is stored in a first number of memory dies corresponding to channels in the first way that do not store the first data, among the memory dies corresponding to the second way.

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