Heterogeneous shared dynamic cache adjustment method, device and medium

Abstract

The invention discloses a heterogeneous shared dynamic cache adjustment method, device and medium, and belongs to the field of computer technology. The invention aims to solve the technical problem of how to fully consider the characteristics of CPU application and GPGPU application, reasonably divide the cache capacity, so as to alleviate the competition for memory between CPU application and GPGPU application, and improve the cache hit rate. The technical scheme is as follows: the secondary cache receives the cache request from the primary cache, uses the LRU replacement strategy or the LFU replacement strategy, and allocates an initialization partition ratio to the secondary cache; monitors the GPGPU memory access information through the GPGPU memory access counter and the GPGPU memory access miss counter in the GPGPU source program at every custom time interval; and calculates the GPGPU memory access miss rate in the corresponding time interval according to the GPGPU memory access count information and the memory access miss information collected in the continuous time interval.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a method, device and medium for dynamically adjusting a heterogeneous shared cache. Background Art

[0002] The last level cache (LLC) is a shared storage layer between the CPU and GPGPU, which plays a vital role in accelerating data transfer between the two. However, managing the use of the shared LLC by CPU applications and GPGPU applications is a challenging key issue. During the execution of heterogeneous programs, GPGPU often dominates the limited LLC space with its faster data access speed and larger data access volume, which greatly limits the cache usage of CPU applications, resulting in a large number of CPU requests having to access the main memory after cache misses, which significantly reduces the access frequency to the LLC, not only causing additional time waste, but also increasing power consumption.

[0003] When the CPU and GPGPU share LLC, in addition to the problem of unfair occupation of cache capacity, the choice of cache replacement algorithm is also crucial. The cache replacement algorithm determines how the data in the cache is updated and replaced. The traditional LRU (Least Recently Used) replacement strategy only considers the most recently accessed information of the data block, ignoring the frequency with which the data block is accessed. When the cache capacity is smaller than the working set of the program, the cache under the LRU strategy will jitter, resulting in a decrease in computer performance. The LFU (Least Frequently Used) replacement strategy eliminates the least frequently used data blocks. However, the LFU algorithm also has shortcomings. If some data is accessed in large quantities in a short period of time, LFU will quickly increase their access frequency, but over time, the access frequency of these data has no natural decay mechanism, which may cause these data to occupy cache space for a long time, thereby affecting the cache hit rate.

[0004] Therefore, how to fully consider the characteristics of CPU applications and GPGPU applications and reasonably divide the cache capacity to alleviate the competition for memory between CPU applications and GPGPU applications while improving the cache hit rate is a technical problem that needs to be solved urgently. Summary of the invention

[0005] The technical task of the present invention is to provide a heterogeneous shared dynamically adjusted cache method, device and medium to solve the problem of how to fully consider the characteristics of CPU applications and GPGPU applications, reasonably divide the cache capacity to alleviate the competition for memory between CPU applications and GPGPU applications, and improve the cache hit rate.

[0006] The technical task of the present invention is achieved in the following manner: a method for dynamically adjusting a heterogeneous shared cache, the method being specifically as follows:

[0007] S1, L2 Cache receives cache requests from L1 Cache, uses LRU (Least Recently Used) replacement strategy or LFU (Least Frequently Used) replacement strategy, and allocates an initialization ratio to the L2 Cache;

[0008] S2. At custom time intervals, use the GPGPU memory access counter in the GPGPU source program and GPGPU memory miss counters Monitoring GPGPU memory access information; wherein the GPGPU memory access information includes memory access count information and memory access miss information;

[0009] S3, calculating the memory access miss rate of the GPGPU in the corresponding time interval according to the GPGPU memory access count information and memory access miss information collected in the continuous time interval;

[0010] S4, according to the GPGPU access count information and memory access miss information collected in the continuous time interval, obtain the number of memory accesses and the number of memory access misses in the previous stage, and calculate the memory access miss rate in the previous stage; wherein the memory access miss rate in the previous stage refers to the total miss rate in the continuous time interval of the last use of different replacement strategies;

[0011] S5. During the operation of the GPGPU source program, the cache miss rate of the GPGPU is counted according to the number of memory accesses and memory misses of the GPGPU, and compared with the set threshold range value, and the next cache partition rule is dynamically determined. In combination with the memory miss rate of the previous stage, a replacement strategy that is beneficial to the current operation state is dynamically switched, thereby reducing the miss rate and ensuring efficient operation of the system.

[0012] S6: GPGPU memory access counter when cache partitioning is completed and the next time interval begins and GPGPU memory miss counters Perform a zero reset;

[0013] S7, determine whether the GPGPU source program has finished running:

[0014] ① If not, repeat steps S2 to S7;

[0015] ②If yes, then end.

[0016] As a preferred embodiment, when the GPGPU source program is running, the GPGPU memory access counter and GPGPU memory miss counters The memory access information of monitoring GPGPU is as follows:

[0017] If a GPGPU last level cache (LLC) memory access request occurs, the GPGPU memory access counter Add 1;

[0018] If a cache request is detected to be a miss while the GPGPU makes a cache request, it means a cache miss has occurred. The GPGPU memory miss counter Add 1.

[0019] More preferably, the formula for the memory miss rate of GPGPU in the corresponding time interval is as follows:

[0020] ;

[0021] in, Indicates GPGPU memory miss rate at each time interval (gpgpu_miss_rate); =1,2,3,···,N.

[0022] Better, when the GPGPU memory miss rate When it is greater than or equal to the set GPGPU memory miss rate minimum threshold Tmin and less than or equal to the set GPGPU memory miss rate maximum threshold Tmax, it means that the current GPGPU cache miss rate is in an intermediate state. At this time, the CPU and GPGPU share the last level cache partitioning method using the intermediate state partitioning.

[0023] Better, when the GPGPU memory miss rate When it is greater than the set maximum threshold Tmax of GPGPU memory miss rate, it means that the current GPGPU cache space size limits the GPGPU performance. Increase the proportion of the last-level cache of GPGPU, restore the cache partition ratio to the initial state, improve the utilization efficiency of the last-level cache of GPGPU, and ensure that its performance no longer decreases.

[0024] As a preferred method, in the GPGPU source program, the memory access counter in the previous stage is used and the memory miss counter in the previous stage Record the GPGPU memory access information for the previous time interval, as follows:

[0025] If there is no replacement strategy in the previous time interval, the calculation formula is as follows:

[0026] ;

[0027] ;

[0028] If the strategy is replaced in the previous time interval, the calculation formula is as follows:

[0029] ;

[0030] ;

[0031] According to the GPGPU memory access miss information collected in the previous stage and the calculated GPGPU memory access information, the GPGPU memory access miss rate in the previous stage is calculated, and the corresponding initial value is set. The calculation formula is as follows:

[0032] ;

[0033] in, Indicates GPGPU memory miss rate during each phase ; ;

[0034] GPGPU memory miss rate in the previous stage It reflects the utilization efficiency of the cache space of the last level cache by the replacement strategy adopted by GPGPU in the continuous time interval of the previous stage; if the miss rate of GPGPU is higher than the miss rate of the previous stage , it means that the current replacement strategy is not suitable for the current GPGPU operation state, and a different replacement strategy needs to be used to increase the utilization efficiency of the last-level cache of GPGPU.

[0035] An electronic device comprising: a memory and at least one processor;

[0036] Wherein, the memory stores a computer program;

[0037] The at least one processor executes the computer program stored in the memory, so that the at least one processor executes the heterogeneous shared dynamic cache adjustment method as described above.

[0038] A computer-readable storage medium stores a computer program, and the computer program can be executed by a processor to implement the heterogeneous shared dynamic cache adjustment method as described above.

[0039] The heterogeneous shared dynamic cache adjustment method, device and medium of the present invention have the following advantages:

[0040] (I) The present invention can monitor the performance change of GPGPU when the program is running, and dynamically divide the shared LLC cache space according to GPGPU performance indicators, such as memory miss rate, etc., to ensure that the GPGPU can run with the same performance, while improving the CPU performance as much as possible, and reasonably change the cache replacement algorithm to increase the cache hit rate, so that the processing performance of the overall system can be optimized; for example, when the memory miss rate of the GPGPU is lower than a certain threshold, it means that its cache efficiency is high. At this time, the cache division ratio of the GPGPU can be appropriately reduced to free up more cache space for the CPU; otherwise, the cache ratio of the GPGPU can be increased to ensure its performance. This dynamic division method can flexibly adjust the cache allocation according to the actual operation situation, and ensure that the GPGPU can run with the same performance, while improving the CPU performance as much as possible;

[0041] (ii) The present invention has greater flexibility and can meet different needs in complex scenarios. Through dynamic strategies, it can adjust cache allocation in real time according to the different characteristics of CPU and GPGPU applications and the current memory access characteristics. At the same time, it avoids the problem of a large amount of cache space being occupied by GPGPU applications in traditional strategies, resulting in a shortage of CPU application cache resources. It makes more reasonable use of cache resources, improves the overall utilization of resources, and significantly improves system performance, thereby achieving higher performance of the product when processing complex computing tasks, such as faster response speed, stronger data processing capabilities, etc., thereby attracting more customers and improving the market competitiveness of the product;

[0042] (III) The present invention reasonably changes the cache replacement algorithm and increases the cache hit rate, thereby optimizing the overall system processing performance. By comparing the number of cache misses on the last-level cache, the LRU or LFU algorithm is dynamically selected to suit the current operating status. This combination of two classic algorithms not only utilizes the LRU algorithm's sensitivity to temporal locality, but also takes advantage of the LFU algorithm's advantage in frequency locality. It can more accurately predict data reuse and improve cache hit rates. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The present invention is further described below in conjunction with the accompanying drawings.

[0044] Attached Figure 1 Flowchart of the method for dynamically adjusting cache for heterogeneous sharing. DETAILED DESCRIPTION

[0045] The heterogeneous shared dynamic cache adjustment method, device and medium of the present invention are described in detail below with reference to the accompanying drawings and specific embodiments of the specification.

[0046] Embodiment 1:

[0047] This embodiment provides a method for dynamically adjusting cache for heterogeneous sharing, and the method is specifically as follows:

[0048] S1, L2 Cache receives cache requests from L1 Cache, uses LRU (Least Recently Used) replacement strategy or LFU (Least Frequently Used) replacement strategy, and allocates an initialization ratio to L2 Cache, such as 1:1;

[0049] S2. At custom time intervals, use the GPGPU memory access counter in the GPGPU source program and GPGPU memory miss counters Monitoring GPGPU memory access information; wherein the GPGPU memory access information includes memory access count information and memory access miss information;

[0050] If a GPGPU last level cache (LLC) memory access request occurs, the GPGPU memory access counter Add 1;

[0051] If a cache request is detected to be a miss while the GPGPU makes a cache request, it means a cache miss has occurred. The GPGPU memory miss counter Add 1;

[0052] S3, calculating the memory access miss rate of the GPGPU in the corresponding time interval according to the GPGPU memory access count information and memory access miss information collected in the continuous time interval;

[0053] S4, according to the GPGPU access count information and memory access miss information collected in the continuous time interval, obtain the number of memory accesses and the number of memory access misses in the previous stage, and calculate the memory access miss rate in the previous stage; wherein the memory access miss rate in the previous stage refers to the total miss rate in the continuous time interval of the last use of different replacement strategies;

[0054] S5. During the operation of the GPGPU source program, the cache miss rate of the GPGPU is counted according to the number of memory accesses and memory misses of the GPGPU, and compared with the set threshold range value, and the next cache partition rule is dynamically determined. In combination with the memory miss rate of the previous stage, a replacement strategy that is beneficial to the current operation state is dynamically switched, thereby reducing the miss rate and ensuring efficient operation of the system.

[0055] S6: GPGPU memory access counter when cache partitioning is completed and the next time interval begins and GPGPU memory miss counters Perform a zero reset;

[0056] S7, determine whether the GPGPU source program has finished running:

[0057] ① If not, repeat steps S2 to S7;

[0058] ②If yes, then end.

[0059] The formula for the memory miss rate of the GPGPU in step S3 of this embodiment within the corresponding time interval is as follows:

[0060] ;

[0061] in, Indicates GPGPU memory miss rate at each time interval (gpgpu_miss_rate); =1,2,3,···,N;

[0062] If the calculated If it is less than the threshold value Tmin, it can be judged that the current GPGPU application has high cache efficiency and causes small cache misses. On the one hand, it may be because the GPGPU access volume is relatively small during this time interval. On the other hand, it may be that the cache space is large enough, which improves the GPGPU utilization efficiency. Therefore, the division of the GPGPU shared LLC cache can be reduced at this time, for example, 1:7;

[0063] If the GPGPU memory miss rate If the value is greater than or equal to the minimum threshold value Tmin of the GPGPU memory miss rate and less than or equal to the maximum threshold value Tmax of the GPGPU memory miss rate, it means that the current GPGPU cache miss rate is in an intermediate state. At this time, the CPU and GPGPU share the last level cache partitioning method using the intermediate state partitioning;

[0064] If the GPGPU memory miss rate If it is greater than the set maximum threshold Tmax of GPGPU memory miss rate, it means that the current GPGPU cache space size limits GPGPU performance. Increase the proportion of GPGPU's last-level cache, restore the cache partition ratio to the initial state, improve GPGPU's utilization efficiency of the last-level cache, and ensure that its performance does not decrease.

[0065] In step S4 of this embodiment, in the GPGPU source program, the memory access counter in the previous stage is used. and the memory miss counter in the previous stage Record the GPGPU memory access information for the previous time interval, as follows:

[0066] If there is no replacement strategy in the previous time interval, the calculation formula is as follows:

[0067] ;

[0068] ;

[0069] If the strategy is replaced in the previous time interval, the calculation formula is as follows:

[0070] ;

[0071] ;

[0072] According to the GPGPU memory access miss information collected in the previous stage and the calculated GPGPU memory access information, the GPGPU memory access miss rate in the previous stage is calculated, and the corresponding initial value is set. The calculation formula is as follows:

[0073] ;

[0074] in, Indicates GPGPU memory miss rate during each phase ; ;

[0075] GPGPU memory miss rate in the previous stage It reflects the utilization efficiency of the cache space of the last level cache by the replacement strategy adopted by GPGPU in the continuous time interval of the previous stage; if the miss rate of GPGPU is higher than the miss rate of the previous stage , it means that the current replacement strategy is not suitable for the current GPGPU operation state, and a different replacement strategy needs to be used to increase the utilization efficiency of the last-level cache of GPGPU.

[0076] As attached Figure 1 As shown, the detailed process of this method is as follows:

[0077] (1) Accessing memory counter via GPGPU and GPGPU memory miss counters Monitor GPGPU memory access information;

[0078] (2) Determine whether the Monitoring of memory access information at time intervals:

[0079] ①If yes, then , and execute step (3);

[0080] ②If not, jump to step (1);

[0081] (3) The formula for calculating the memory miss rate of GPGPU in the corresponding time interval is as follows:

[0082] ;

[0083] (4) Judgment Relationship with the set minimum threshold Tmin of GPGPU memory miss rate and the set maximum threshold Tmax of GPGPU memory miss rate:

[0084] ① If the GPGPU memory miss rate If the GPGPU memory miss rate is less than the set minimum threshold Tmin, the GPGPU and CPU cache partition ratio is 1:1;

[0085] ② If the GPGPU memory miss rate If the value is greater than or equal to the minimum threshold value Tmin of the GPGPU memory miss rate and less than or equal to the maximum threshold value Tmax of the GPGPU memory miss rate, it means that the current GPGPU cache miss rate is in an intermediate state. At this time, the CPU and GPGPU share the last level cache partitioning method using the intermediate state partitioning method. At this time, the GPGPU and CPU cache partitioning ratio is 1:3. The next step is to execute step (5).

[0086] ③ If the GPGPU memory miss rate If it is greater than the set maximum threshold Tmax of GPGPU memory miss rate, it means that the current GPGPU cache space size limits GPGPU performance. Increase the proportion of GPGPU's last-level cache, restore the cache partition ratio to the initial state, improve GPGPU's utilization efficiency of the last-level cache, and ensure that its performance does not decrease. At this time, the GPGPU and CPU cache partition ratio is 1:7;

[0087] (5) Determine the GPGPU memory miss rate Is it greater than GPGPU memory miss rate during each phase :

[0088] ①If yes, then , and execute step (6);

[0089] ②If not, jump to step (7);

[0090] (6) Switching replacement strategy;

[0091] (7) In the GPGPU source program, the memory access counter in the previous stage is used and the memory miss counter in the previous stage Record the GPGPU memory access information of the previous time interval and calculate the GPGPU memory miss rate during each phase , the calculation formula is as follows:

[0092] ;

[0093] During the operation of the GPGPU source program, the cache miss rate of the GPGPU is counted according to the number of memory accesses and memory misses of the GPGPU, and compared with the set threshold range value, and the next cache division rule is dynamically determined. In addition, the replacement strategy that is beneficial to the current operation state is dynamically switched in combination with the memory miss rate of the previous stage, thereby reducing the miss rate and ensuring the efficient operation of the system.

[0094] (8) GPGPU memory access counter when cache partitioning is completed and the next time interval begins and GPGPU memory miss counters Perform a zero reset;

[0095] (9) Determine whether the GPGPU source program has finished running:

[0096] ① If not, repeat steps S1 to S9;

[0097] ②If yes, then end.

[0098] Embodiment 2:

[0099] This embodiment also provides an electronic device, including: a memory and a processor;

[0100] Wherein, the memory stores computer-executable instructions;

[0101] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the heterogeneous shared dynamic cache adjustment method in any embodiment of the present invention.

[0102] The processor may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor may be a microprocessor or any conventional processor, etc.

[0103] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and calling the data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application required for a function, etc.; the data storage area can store data created according to the use of the terminal, etc. In addition, the memory can also include a high-speed random access memory, and can also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart memory card (SMC), a secure digital (SD) card, a flash memory card, at least one disk storage period, a flash memory device, or other volatile solid-state storage devices.

[0104] Embodiment 3:

[0105] This embodiment also provides a computer-readable storage medium, in which a plurality of instructions are stored, and the instructions are loaded by a processor, so that the processor executes the heterogeneous shared dynamic adjustment cache method in any embodiment of the present invention. Specifically, a system or device equipped with a storage medium can be provided, on which a software program code that implements the functions of any of the above embodiments is stored, and a computer (or CPU or MPU) of the system or device reads and executes the program code stored in the storage medium.

[0106] In this case, the program code itself read from the storage medium can realize the function of any one of the above-mentioned embodiments, and thus the program code and the storage medium storing the program code constitute a part of the present invention.

[0107] Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RYM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROMs. Alternatively, program code may be downloaded from a server computer via a communication network.

[0108] In addition, it should be clear that the functions of any of the above embodiments can be implemented not only by executing the program code read by the computer, but also by enabling an operating system operating on the computer to complete part or all of the actual operations based on instructions from the program code.

[0109] In addition, it can be understood that the program code read from the storage medium is written to a memory provided in an expansion board inserted into the computer or written to a memory provided in an expansion unit connected to the computer, and then based on the instructions of the program code, a CPU installed on the expansion board or the expansion unit is enabled to perform part or all of the actual operations, thereby realizing the functions of any of the above-mentioned embodiments.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for dynamically adjusting heterogeneous shared cache, characterized in that: The method is as follows: S1. The L2 cache receives a cache request from the L1 cache, uses an LRU replacement strategy or an LFU replacement strategy, and allocates an initialization fraction to the L2 cache; S2. At custom time intervals, use the GPGPU memory access counter in the GPGPU source program and GPGPU memory miss counters Monitor GPGPU memory access information; S3, calculating the memory access miss rate of the GPGPU in the corresponding time interval according to the GPGPU memory access count information and memory access miss information collected in the continuous time interval; S4, according to the GPGPU access count information and memory access miss information collected in the continuous time interval, obtain the number of memory accesses and the number of memory access misses in the previous stage, and calculate the memory access miss rate in the previous stage; S5. When the GPGPU source program is running, the cache miss rate of the GPGPU is counted according to the number of memory accesses and memory misses of the GPGPU, and compared with the set threshold range value, so as to dynamically determine the partitioning rule of the next cache, and dynamically switch the replacement strategy that is beneficial to the current running state in combination with the memory miss rate of the previous stage; S6: GPGPU memory access counter when cache partitioning is completed and the next time interval begins and GPGPU memory miss counters Perform a zero reset; S7, determine whether the GPGPU source program has finished running: ① If not, repeat steps S2 to S7; ②If yes, then end.

2. The heterogeneous shared dynamic cache adjustment method according to claim 1, characterized in that: When the GPGPU source program is running, the GPGPU memory access counter and GPGPU memory miss counters The memory access information of monitoring GPGPU is as follows: If a GPGPU last-level cache memory access request occurs, the GPGPU memory access counter Add 1; If a cache request is detected to be a miss while the GPGPU makes a cache request, it means a cache miss has occurred. The GPGPU memory miss counter Add 1.

3. The heterogeneous shared dynamic cache adjustment method according to claim 1 or 2, characterized in that: The formula for the memory miss rate of GPGPU in the corresponding time interval is as follows: ； in, Indicates GPGPU memory miss rate at time intervals; = 1, 2, 3, ···, N.

4. The heterogeneous shared dynamic cache adjustment method according to claim 3, characterized in that: When the GPGPU memory miss rate When it is greater than or equal to the set GPGPU memory miss rate minimum threshold Tmin and less than or equal to the set GPGPU memory miss rate maximum threshold Tmax, it means that the current GPGPU cache miss rate is in an intermediate state. At this time, the CPU and GPGPU share the last level cache partitioning method using the intermediate state partitioning.

5. The heterogeneous shared dynamic cache adjustment method according to claim 3, characterized in that: When the GPGPU memory miss rate When it is greater than the set maximum threshold Tmax of the GPGPU memory miss rate, it means that the current GPGPU cache space size limits the GPGPU performance. Increase the proportion of the last-level cache of the GPGPU and restore the cache partition ratio to the initial state.

6. The heterogeneous shared dynamic cache adjustment method according to claim 1, characterized in that: In the GPGPU source program, the memory access counter in the previous stage is used and the memory miss counter in the previous stage Record the GPGPU memory access information for the previous time interval, as follows: If there is no replacement strategy in the previous time interval, the calculation formula is as follows: ； ； If the strategy is replaced in the previous time interval, the calculation formula is as follows: ； ； According to the GPGPU memory access miss information collected in the previous stage and the calculated GPGPU memory access information, the GPGPU memory access miss rate in the previous stage is calculated, and the corresponding initial value is set. The calculation formula is as follows: ； in, Indicates GPGPU memory miss rate during each phase ; ; GPGPU memory miss rate in the previous stage It reflects the efficiency of the replacement strategy used by GPGPU in the last level cache space utilization during the continuous time interval of the previous stage; if the miss rate of GPGPU is higher than the miss rate of the previous stage , it means that the current replacement strategy is not suitable for the current GPGPU operation state, and a different replacement strategy needs to be used to increase the utilization efficiency of the last-level cache of GPGPU.

7. An electronic device, characterized in that: include: memory and at least one processor; Wherein, the memory stores a computer program; The at least one processor executes the computer program stored in the memory, so that the at least one processor executes the heterogeneous shared dynamic adjustment cache method according to any one of claims 1 to 6.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which can be executed by a processor to implement the heterogeneous shared dynamic cache adjustment method according to any one of claims 1 to 6.

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