Data processing method, device, equipment and storage medium of CPU card chip

Abstract

The invention relates to the technical field of data processing, and discloses a data processing method, device, equipment and storage medium for a CPU card chip. The method comprises: constructing a data verification matrix for a ROM area and a RAM area of ​​a CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix; performing format verification on an input data stream to obtain a standard format data block and a non-standard format data item; performing format conversion on the non-standard format data item to obtain a converted format data block and a format conversion record; performing compression processing on an input CPU core to obtain a compressed data stream and a compression identifier; performing group encryption on the compressed data stream based on the compression identifier to obtain an encrypted data group and a MAC check value; performing consistency verification to obtain a data integrity identifier and a processing status record. The invention realizes efficient data compression and transmission under limited RAM resource conditions, reduces storage space occupancy, and ensures the continuity and stability of data processing.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing, and in particular to a data processing method, device, equipment and storage medium for a CPU card chip. Background Art

[0002] Due to the limited storage resources of CPU card chips, there are dual challenges of efficiency and security when processing large amounts of data. Especially when processing non-standard format data, the traditional single storage structure is difficult to meet the needs of data processing.

[0003] At present, the data processing method of CPU card chips mainly relies on a single RAM cache or EEPROM storage, which not only increases hardware costs but also reduces data processing efficiency. Especially when processing data in multiple formats, the lack of a unified data verification and conversion mechanism can easily lead to data processing errors and security risks. In addition, existing data processing methods often ignore the potential of ROM-RAM hybrid storage structure in reducing costs and improving efficiency. Summary of the invention

[0004] The present invention provides a data processing method, device, equipment and storage medium for a CPU card chip. The present invention realizes efficient data compression and transmission under limited RAM resource conditions, reduces storage space occupancy, and ensures the continuity and stability of data processing.

[0005] In a first aspect, the present invention provides a data processing method for a CPU card chip, the data processing method for a CPU card chip comprising:

[0006] Construct data verification matrix for the ROM area and RAM area of ​​the CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix;

[0007] Performing format verification on the input data stream according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items;

[0008] Performing format conversion on the non-standard format data item to obtain a converted format data block and a format conversion record;

[0009] Input the standard format data block and the converted format data block into the CPU core for compression processing to obtain a compressed data stream and a compression identifier;

[0010] Encrypt the compressed data stream in groups based on the compression identifier to obtain an encrypted data group and a MAC check value;

[0011] The encrypted data group is verified for consistency according to the MAC check value to obtain a data integrity identifier and a processing status record.

[0012] In a second aspect, the present invention provides a data processing device for a CPU card chip, the data processing device for the CPU card chip comprising:

[0013] A construction module is used to construct a data verification matrix for the ROM area and RAM area of ​​the CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix;

[0014] A format verification module, used for performing format verification on the input data stream according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items;

[0015] A format conversion module, used for performing format conversion on the non-standard format data item to obtain a converted format data block and a format conversion record;

[0016] A compression processing module, used for inputting the standard format data block and the converted format data block into the CPU core for compression processing to obtain a compressed data stream and a compression identifier;

[0017] A packet encryption module, used for performing packet encryption on the compressed data stream based on the compression identifier to obtain an encrypted data group and a MAC check value;

[0018] The consistency verification module is used to perform consistency verification on the encrypted data group according to the MAC check value to obtain a data integrity identifier and a processing status record.

[0019] The third aspect of the present invention provides a computer device, comprising: a memory and at least one processor, wherein the memory stores instructions; the at least one processor calls the instructions in the memory so that the computer device executes the data processing method of the CPU card chip mentioned above.

[0020] A fourth aspect of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the data processing method of the CPU card chip described above.

[0021] In the technical solution provided by the present invention, by constructing a data verification matrix of a ROM-RAM hybrid storage structure, the data processing efficiency is improved while the hardware cost is reduced, so that the CPU card chip can process data in standard format and non-standard format at the same time; by adopting a data format verification mechanism based on a ROM verification matrix template, automatic recognition and conversion of data formats are realized, data processing errors are reduced, and the accuracy of data processing is improved; by combining the hardware acceleration characteristics of the CPU core and the group compression algorithm, efficient data compression and transmission are realized under the condition of limited RAM resources, and the storage space occupancy is reduced; by introducing a multi-level security protection mechanism, including data format verification, compression identifier verification, MAC value verification, etc., a complete data security protection system is constructed, which effectively prevents data tampering and theft attacks; based on an asynchronous processing mechanism triggered by an event, the parallel processing capability of the CPU card chip is improved, the data processing delay is reduced, and the system response performance is enhanced; by establishing a data integrity verification and automatic recovery mechanism, the reliability and fault tolerance of the system are improved, and the continuity and stability of data processing are ensured. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0023] Figure 1 A schematic diagram of the steps of the data processing method of the CPU card chip in an embodiment of the present invention;

[0024] Figure 2 It is a structural schematic diagram of a data processing device of a CPU card chip in an embodiment of the present invention;

[0025] Figure 3 It is a schematic block diagram of the structure of a computer device in an embodiment of the present invention. DETAILED DESCRIPTION

[0026] The embodiment of the present invention provides a data processing method, device, equipment and storage medium for a CPU card chip. The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments described here can be implemented in an order other than that illustrated or described here. In addition, the terms "including" or "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] For ease of understanding, the specific process of the embodiment of the present invention is described below. Figure 1 , an embodiment of the data processing method of the CPU card chip in the embodiment of the present invention includes:

[0028] Step S1, constructing a data verification matrix for the ROM area and RAM area of ​​the CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix;

[0029] It is understandable that the execution subject of the present invention may be a data processing device of a CPU card chip, or a terminal or a server, which is not limited here. The embodiment of the present invention is described by taking a server as the execution subject as an example.

[0030] Specifically, the ROM area of ​​the CPU card chip is divided into an N×M dimensional matrix, where N represents the number of data types and M represents the number of features. This division method effectively organizes the storage structure so that different types of data show regularity in the storage space, which is convenient for subsequent data verification and format checking. The preset data verification matrix constructed by this step classifies the storage space according to different data categories. The preset data verification matrix is ​​filled with feature rules to generate a ROM verification matrix template. The core goal of feature rule filling is to set valid value ranges, format requirements and verification rules for different data types. In this process, for different data types, their legal value ranges are defined to ensure the compliance of data storage. For example, for numerical data, a minimum and maximum value range is set, and for string type data, its length constraint or character set restriction is defined. In order to improve the verifiability of data, corresponding verification rules are defined, such as parity check, cyclic redundancy check or hash value check, so as to quickly find potential errors when storing or reading data. Through the feature rule filling process, the ROM verification matrix template formed has data constraint capabilities, so that the CPU card chip can automatically identify data that does not conform to the rules when data is input or stored, and perform corresponding processing, thereby improving the reliability and security of the overall data. At the same time, N×M dimensional cache space is allocated in the RAM area to form a RAM cache matrix, thereby providing efficient storage and temporary cache capabilities in data processing. Unlike the ROM area, the storage space in the RAM area is mainly used for short-term data storage and processing. When constructing the RAM cache matrix, attention is paid to its data access efficiency. Each matrix element of the RAM cache matrix contains 16 bytes of data cache space, which means that a single matrix element stores data of a certain length, thereby adapting to various types of data storage requirements. In order to achieve the management of data storage status, each matrix element contains an additional 4-byte status identification bit, which is used to record the storage status of the data, such as whether the data is valid, whether it has been read, whether the verification has been completed, etc. Through this design, during the data processing process, the data status is monitored in real time to ensure the integrity of the data and improve the efficiency of data storage and processing.

[0031] Step S2, performing format verification on the input data stream according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items;

[0032] Specifically, the input data stream is parsed for delimiters to split the data stream into multiple independent data item sequences. Since the input data stream is organized in a structured or semi-structured manner, predefined delimiters, such as fixed-length delimiters, punctuation marks, or specific byte marks, are used to perform effective data cutting to ensure that each independent data item can be correctly identified and extracted. Type identification is extracted for each independent data item sequence to form a data type identification set. This process involves pattern recognition, field matching, or rule-based classification methods to ensure that each data item is accurately classified into a corresponding data category. Based on the data type identification set, feature matching is performed from a pre-built ROM verification matrix template to obtain a corresponding data format requirement set. Through index query or hash mapping, the format requirements corresponding to each data type are quickly located to ensure that the data can be compared with the standard format before processing. In this process, a variety of format rule matching methods are considered, such as regular expression-based format verification, data length-based format checking, or validity judgment based on numerical ranges to ensure that the data format meets established standards. If some data types involve specific encoding formats (such as Base64 encoding, hexadecimal encoding, or compressed formats), additional decoding operations are performed to facilitate subsequent format matching. Multiple independent data item sequences are format matched against a set of data format requirements to obtain format matching results. The specific content of each independent data item sequence is analyzed and compared with the corresponding data format requirements to determine whether the data item conforms to the standard format. For example, if the length of a data item does not match the provisions in the set of format requirements, or the data value exceeds the predefined valid range, the data item will be judged as a format error. Similarly, if the encoding of a data item is different from that expected, such as a field that should be an ASCII-encoded string but the actual data is in binary format, it will also be considered as a format non-compliant situation. Through this step, a format matching result is generated to distinguish between qualified and unqualified data items. Based on the format matching results, multiple independent data item sequences are classified and marked to obtain standard format data blocks and non-standard format data items. Standard format data blocks refer to data items that fully comply with the rules defined by the ROM verification matrix template, and these data items are directly used in subsequent processing steps, such as data compression, encryption, or storage. Non-standard format data items refer to data items that fail to pass verification during the format matching process. These data items require further processing, such as format conversion, error correction, or direct discarding, to prevent non-compliant data from affecting the normal operation of the system.

[0033] Step S3, performing format conversion on the non-standard format data item to obtain a converted format data block and a format conversion record;

[0034] Specifically, the data position information in the non-standard format data item is read to obtain the specific position record of the data item in the input data stream. Since the non-standard format data items are distributed in different areas of the input data stream, the storage location of the data is accurately located by using index technology or pointer offset calculation. Through these position information, it is ensured that the data to be processed is accurately extracted during the subsequent format conversion, and data omission or incorrect mapping is avoided. At the same time, based on the parsed position information, the corresponding format conversion rules are extracted from the pre-built ROM verification matrix template. These rules include data length adjustment, character encoding conversion, data zero padding, numerical format conversion, etc. By querying the ROM verification matrix template, a data format conversion mapping table is obtained to define how each non-standard format data item should be adjusted to meet the requirements of the standard format. The non-standard format data item is input into the hardware accelerator of the CPU core for format normalization processing. Since the CPU card chip has a built-in dedicated hardware acceleration module, such as a customized DSP (digital signal processor) or a programmable logic unit (such as FPGA), these hardware units are used to perform efficient format conversion operations, thereby reducing the computing burden of the CPU core. The process of format normalization mainly involves format standardization, such as adjusting variable-length data to fixed-length format, converting big-endian byte order to little-endian byte order, or converting data encoding formats (such as EBCDIC, UTF-16) to target formats (such as UTF-8 or ASCII). In some cases, data masking operations are performed to ensure that the data meets specific security requirements, such as desensitizing some sensitive data or reorganizing data fields in blocks. The result of format normalization is an initial conversion data block, which basically meets the standard format requirements. Data completion operations are performed on the initial conversion data block. The data completion process depends on the field definition and default fill value in the format conversion rule. For those fields missing in the original data items, the default value is filled according to the rules, such as setting the missing numeric field to zero or filling the string field with spaces. If the data alignment method is specified in the format conversion rule, the byte alignment adjustment is performed according to the regulations to ensure that the data can be parsed correctly. After the data completion is completed, a data block that meets the standard format is formed and written into the data area and status area of ​​the RAM cache matrix. The data area stores the converted format data blocks, while the status area records the data conversion status, such as whether the data has been converted and verified, so that the subsequent data processing flow can correctly identify the processing status of these data. The entire format conversion process is logged, and the data format before conversion, the data format after conversion, the conversion rule number used, and the timestamp of the conversion are stored in the log system. The data format before conversion records the structure of the original data item so that it can be traced back when an exception occurs, and the data format after conversion reflects the final structure of the data after adjustment.The conversion rule number is used to identify the specific rule used for this conversion so that it can be audited or analyzed when necessary, while the timestamp provides the time information of the conversion operation, allowing the system to perform timing analysis on the data processing flow.

[0035] Step S4, inputting the standard format data block and the converted format data block into the CPU core for compression processing to obtain a compressed data stream and a compression identifier;

[0036] Specifically, entropy values ​​are calculated for the standard format data block and the converted format data block respectively to obtain the data entropy value. The data entropy value is an important indicator to measure the randomness of data. Its calculation is based on the Shannon entropy formula, that is, the redundancy of data is evaluated by calculating the probability of occurrence of different byte values ​​in the data block and calculating its information entropy. If the data entropy value is low, it means that the data has high repetitiveness and is suitable for lossless compression. If the data entropy value is high, it means that the data has strong randomness and needs to adopt a special compression strategy or direct storage to avoid poor compression effect and waste of computing resources. The compression mode is selected according to the relationship between the data entropy value and the preset thresholds T1 and T2, so as to determine the optimal compression processing mode. When the data entropy value is lower than T1, it indicates that the data has a large redundancy. At this time, a lossless compression algorithm with a high compression rate is selected, such as Huffman coding, run-length encoding (RLE) or LZ77, etc., to minimize storage occupancy. When the data entropy value is higher than T2, it means that the data is close to random distribution, and the conventional lossless compression algorithm cannot significantly reduce the amount of data. Therefore, direct storage or low-overhead compression algorithms are selected, such as simple block repetition compression or dictionary compression. If the data entropy value is between T1 and T2, a general fast compression algorithm, such as DEFLATE or LZ4, is selected to strike a balance between compression rate and processing speed. After determining the specific compression mode, the standard format data block and the converted format data block are aligned by 8 bytes to obtain the padded data block. Since the compression instruction set of the CPU core is optimized for data blocks with fixed word length, the memory access overhead is reduced by 8-byte alignment, and the throughput of compression calculation is improved. The data alignment method uses zero padding or pattern padding to ensure that the data block size meets the alignment requirements of the CPU, while not affecting the restoration of the decompressed data. The padded data block is input into the hardware compression instruction set of the CPU core for parallel compression operation to obtain a compressed data stream. Since modern CPU card chips integrate specialized compression instruction sets, such as vectorized compression units that support SIMD (single instruction multiple data) operations, these hardware acceleration units are used to quickly compress data blocks in parallel, thereby greatly improving compression efficiency. During the parallel compression process, the CPU calls the corresponding instruction set to perform encoding conversion of data blocks according to the previously selected compression mode, and distributes computing tasks among multiple computing units to achieve efficient data compression. After the compression calculation is completed, the generated compressed data stream is still in the form of raw data, and the storage format is reorganized to ensure that the data can be correctly parsed during subsequent storage and transmission. The core of the storage format reorganization is to construct a standardized compressed data packet, which contains multiple key fields, including a 4-byte data length field, a 4-byte checksum field, a 2-byte compression mode field, and the actual compressed data field.Among them, the data length field is used to record the total size of the compressed data so that the storage space can be correctly allocated during decompression; the checksum field is used for data integrity verification, which is calculated using algorithms such as CRC-32 or MD5 to ensure that no errors occur in the compressed data during storage and transmission; the compression mode field is used to identify the specific algorithm used for this compression so that the correct decoding method can be selected during decompression, and the compressed data field stores the specific compressed data stream. Through the structured data encapsulation method, the stability of data storage and transmission is improved, and the manageability and compatibility of data are enhanced. The compressed data packet is written to the EEPROM data storage area to ensure long-term storage of data. Due to the long write cycle of the EEPROM memory, a batch write strategy or a write cache optimization strategy is adopted to reduce storage delay and improve the efficiency of data storage. At the same time, after the data is written, the processing status flag is updated in the RAM cache matrix to obtain the final compression flag. The compression flag is used to mark whether the current data has completed the compression process, and contains additional metadata, such as compression timestamp, compression rate, and storage address, for subsequent data reading and management.

[0037] Step S5: Encrypt the compressed data stream in groups based on the compression identifier to obtain an encrypted data group and a MAC check value;

[0038] Specifically, the encryption parameters are read from the ROM and integrity check is performed to obtain the encryption mode parameters and key length parameters. When reading the ROM data, a predefined check mechanism, such as CRC-32, SHA hash verification or digital signature check, is used to ensure that the encryption parameters have not been tampered with or damaged. After the integrity check, the encryption mode parameters are obtained, which determine the encryption algorithm used, such as AES-128, AES-256 or other symmetric encryption methods. At the same time, the key length parameter is used to specify the length of the key to ensure that the encryption process meets the established security standards. The random number generator based on the CPU core is used to generate keys to obtain session keys and initialization vectors. Since the security of the key is directly related to the anti-attack ability of the encrypted data, a high-quality random number generation algorithm is used, such as a true random number generator based on a hardware entropy source or a deterministic random bit generator based on a pseudo-random number algorithm, to generate a high-strength encryption key. The session key is used to symmetric encrypt the compressed data stream, and the initialization vector is used to ensure that the same plaintext data generates different ciphertexts after encryption, thereby enhancing the security of the data. After generating the key and initialization vector, the compressed data stream is grouped into 64 bytes to obtain a fixed-length data group to be encrypted. The 64-byte grouping method is adopted to ensure the efficiency of encryption calculation, and at the same time, it is optimized to match the encryption instruction set of the CPU core, thereby improving the overall encryption processing speed. After completing the data grouping, the data group to be encrypted is input into the encryption instruction set of the CPU core, and the group chaining encryption operation is performed to obtain the encrypted data group. The encryption instruction set includes AES-NI or a dedicated hardware acceleration module. These instruction sets perform efficient block encryption operations and support different encryption modes, such as ECB (electronic codebook mode), CBC (cipher block chaining mode) or GCM (Galois / Counter mode). The CBC mode is more common and can use the ciphertext of the previous data block to encrypt the current data block to enhance security, while the GCM mode combines encryption and authentication functions and is suitable for scenarios with high data integrity requirements. During the encryption process, each data group uses the session key and initialization vector for encryption operation, and performs parallel processing through the encryption instruction set to improve encryption efficiency. When all data groups are encrypted, the final encrypted data group is obtained. The HMAC-SHA256 algorithm is executed on the encrypted data group to calculate the MAC check value to ensure the integrity and tamper resistance of the data. HMAC (Hash Message Authentication Code) is a message authentication method based on hash functions and keys, which can effectively prevent data from being tampered or forged. As a hash algorithm, SHA-256 provides a 256-bit hash value for data and has high collision resistance. In the process of calculating the MAC check value, the pre-generated session key is used as the key of HMAC, and the encrypted data group is hashed to obtain the final MAC check value.This checksum is verified after data transmission or storage to ensure that the data has not been tampered with or damaged, thereby improving the security and reliability of the system.

[0039] Step S6: Perform consistency verification on the encrypted data group according to the MAC check value to obtain a data integrity identifier and a processing status record.

[0040] Specifically, the state information of the data to be verified is read from the RAM cache matrix and parsed to obtain the encryption identifier and storage location information. Since the RAM cache matrix is ​​used to temporarily store the data state, the encryption identifier therein indicates whether the data has been encrypted, and the storage location information is used to determine the specific storage address of the encrypted data group in the EEPROM data storage area. By parsing these state information, it is determined how the subsequent verification process should be carried out, and it is ensured that the data is read from the correct storage location to avoid data misjudgment or loss. After obtaining the storage location information, the corresponding encrypted data group is read from the EEPROM data storage area, and the data is reconstructed to obtain the data block to be verified. Since the EEPROM memory adopts a block-level storage structure, when reading data, data is extracted according to a predefined block size, and the complete data block is restored by data format parsing. During the data reading process, the storage integrity of the data is checked, for example, by storing a checksum or an error correction code to detect potential errors in the storage process to ensure that the acquired data block to be verified is complete and undamaged. When the data block to be verified is successfully extracted, the MAC is recalculated according to the key material in the EEPROM key storage area to obtain a verification MAC value. During the calculation process, the session key corresponding to the data is extracted from the EEPROM key storage area to ensure that the MAC calculation process is consistent with the key used when the data is encrypted. The MAC calculation of the data block to be verified is performed using an authentication algorithm such as HMAC-SHA256 to generate a new verification MAC value. The calculation process follows the MAC generation method when the original data is encrypted to ensure the accuracy and consistency of the calculation result. After the MAC recalculation is completed, the calculated verification MAC value is compared with the original stored MAC verification value to obtain the data integrity identifier. If the two match, it means that the data has not been tampered with or damaged during storage and transmission, so a data integrity identifier of the "complete" state is generated; otherwise, it means that the data has been tampered with, miswritten or lost, and further analysis of the abnormal source of the data is required to take corresponding recovery or alarm measures. Based on the data integrity identifier, the data operation record is read from the EEPROM log storage area and the time point is located to obtain the latest correct operation time record. The log storage area contains the historical records of all data operations, including data writing time, encryption time, MAC calculation time, etc. By querying the log, the latest valid state of the data is found and the last correct operation time of the data is determined. This process helps identify data anomalies, such as whether data has failed to be partially written due to a system crash or power outage, or whether the MAC value does not match due to an incorrect update, etc. After determining the latest correct operation time record, the encrypted data group is backed up and restored based on the time record to ultimately obtain a processing status record.The backup data recovery process relies on the data redundancy storage mechanism in the EEPROM, such as the dual storage area design or log rollback mechanism to restore the correct data version. During the recovery process, the latest correct operation time is used as a reference to find the corresponding historical data version and overwrite the current erroneous data to ensure data consistency and availability. After the recovery is completed, the processing status record is updated in the RAM cache matrix to mark that the data has successfully passed the consistency verification and ensure that subsequent system operations can be processed based on the correct data.

[0041] In the embodiment of the present invention, by constructing a data verification matrix of a ROM-RAM hybrid storage structure, the data processing efficiency is improved while reducing the hardware cost, so that the CPU card chip can process data in standard format and non-standard format at the same time; by adopting a data format verification mechanism based on a ROM verification matrix template, automatic recognition and conversion of data formats are realized, data processing errors are reduced, and the accuracy of data processing is improved; by combining the hardware acceleration characteristics of the CPU core and the packet compression algorithm, efficient data compression and transmission are realized under limited RAM resource conditions, and storage space occupancy is reduced; by introducing a multi-level security protection mechanism, including data format verification, compression identifier verification, MAC value verification, etc., a complete data security protection system is constructed, which effectively prevents data tampering and theft attacks; based on an asynchronous processing mechanism triggered by an event, the parallel processing capability of the CPU card chip is improved, data processing delay is reduced, and system response performance is enhanced; by establishing a data integrity verification and automatic recovery mechanism, the reliability and fault tolerance of the system are improved, and the continuity and stability of data processing are ensured.

[0042] In a specific embodiment, the process of executing step S1 may specifically include the following steps:

[0043] The storage space of the ROM area in the CPU card chip is divided into an N×M dimensional matrix to obtain a preset data verification matrix, where N represents the number of data types and M represents the number of features;

[0044] Fill the preset data verification matrix with characteristic rules to obtain a ROM verification matrix template including data valid value range, format requirements and verification rules;

[0045] An N×M-dimensional cache space is allocated to the RAM area to obtain a RAM cache matrix, in which each matrix element includes a 16-byte data cache space and a 4-byte status flag.

[0046] Specifically, in the ROM area, the storage structure is as follows The form of division, in which Represents different data categories, while Represents the number of features contained in each category. The matrix size of the entire ROM storage area is expressed as:

[0047]

[0048] in, Indicates the total storage size of the preset data verification matrix in the ROM area, in bytes or storage cells. After the storage matrix is ​​established in the ROM area, fill in the feature rules to form a ROM verification matrix template. Set a single storage cell in the matrix to ,in The index representing the data category, Represents the feature index, then the ROM verification matrix is ​​expressed as:

[0049]

[0050] in, Indicates the valid value range of the data; Represents format constraints on data, such as length limits, alignment requirements, or encoding methods; Indicates the verification rules, such as parity check, hash check or CRC check. After completing the construction of the ROM verification matrix, allocate the corresponding Dimensional cache matrix, each matrix unit contains data storage space and status flags. The storage requirement of a single matrix element is expressed as:

[0051]

[0052] in, Indicates the size of a single storage unit in the RAM matrix; Indicates the size of the data stored in this unit; Indicates the size of the unit storage status identifier. From this, the storage requirement of the entire RAM cache matrix can be obtained:

[0053]

[0054] in, Indicates the total storage space requirement of the RAM cache matrix. In the design of the status flag, the status flag uses binary encoding to record the processing status of the data. For example, 0001 means that the data has been written but not verified; 0010 means that the data has passed the format check; 0100 means that the data has been processed; 1000 means that the data needs to be rechecked.

[0055] In this embodiment, before constructing the data verification matrix for the ROM area and RAM area of ​​the CPU card chip, it also includes: performing feature decomposition processing on the historical data set to obtain an N×K dimensional data feature matrix, where N represents the number of data types and K represents the number of feature components; inputting the data feature matrix into a sparse coding network for feature mapping to obtain a sparse representation dictionary; performing regularization optimization on the sparse representation dictionary to obtain an optimized dictionary containing data feature weights; constructing a semi-quadratic iterative verification network based on the optimized dictionary to obtain a verification matrix generation model; inputting the verification matrix generation model into the ROM area of ​​the CPU card chip for storage division to obtain a preset verification space; caching the RAM area according to the preset verification space to obtain a corresponding cache verification space; cross-validating the preset verification space and the cache verification space to obtain verification matrix parameters; generating a ROM verification matrix template and an initial structure of the RAM cache matrix based on the verification matrix parameters.

[0056] In a specific embodiment, the process of executing step S2 may specifically include the following steps:

[0057] Parsing the input data stream for delimiters to obtain multiple independent data item sequences, and extracting type identifiers from the multiple independent data item sequences to obtain a data type identifier set;

[0058] Perform feature matching from the ROM verification matrix template according to the data type identification set to obtain a corresponding data format requirement set;

[0059] Performing format matching on multiple independent data item sequences and data format requirement sets to obtain format matching results;

[0060] According to the format matching results, multiple independent data item sequences are classified and marked to obtain standard format data blocks and non-standard format data items.

[0061] Specifically, define the basic structure of the input data stream and set the delimiter rules between data items so that the data stream can be parsed into independent data items according to the established format. Assume that the input data stream is , which consists of multiple data items, expressed as:

[0062]

[0063] in, Indicates the first data items, and Indicates the total number of data items. Each data item is separated by a separator To separate, define the data stream parsing function , used to extract a sequence of independent data items from a data stream:

[0064]

[0065] in, represents a sequence of parsed data items, and Indicates the parsed After obtaining the data item sequence set, extract the type identifier of each data item to form a data type identifier set. Suppose the data type identifier set is:

[0066]

[0067] in, Represents a data item The type of data. The type identifier is extracted based on the data content, length, encoding format or a specific pattern matching algorithm, for example:

[0068]

[0069] in, is a type recognition function that determines the data type through regular matching, value range detection, or machine learning classification models. After obtaining the data type identification set, Perform feature matching in the ROM verification matrix template to obtain the data format requirement set. Suppose the ROM verification matrix template is:

[0070]

[0071] in, Indicates data category Corresponding features During the matching process, the set is identified by type. , find the format requirement set that meets the criteria in the ROM verification matrix template:

[0072]

[0073] in, Represents a data item The corresponding format requirements include data length requirements, value range, character encoding, alignment, etc. After completing the format matching, the data item sequence and the data format requirement set are format verified to generate the format matching result. Suppose the format matching function is , which is used to check the data item Does it meet the format requirements?

[0074]

[0075] By performing format matching checks on all data items, a format matching result set is obtained:

[0076]

[0077] in, Represents a data item Based on the format matching results, the data items are classified and marked to distinguish between standard format data blocks and non-standard format data items. Suppose the set of standard format data blocks is:

[0078]

[0079] The set of non-standard format data items is:

[0080]

[0081] in, The data items in the ROM verification matrix template meet the format requirements and are directly used for subsequent data processing. The data items in the data set need further conversion or correction to ensure that they conform to the standard format.

[0082] In a specific embodiment, the process of executing step S3 may specifically include the following steps:

[0083] Reading data position information in a non-standard format data item to obtain a position record of the data item in an input data stream, and extracting a format conversion rule from a ROM verification matrix template according to the position record to obtain a data format conversion mapping table;

[0084] Inputting non-standard format data items into the hardware accelerator of the CPU core for format normalization processing to obtain an initial conversion data block;

[0085] The initial conversion data block is completed to obtain a format data block that meets the requirements of the ROM verification matrix template, and the format data block is written into the data area and the status area of ​​the RAM cache matrix to obtain a converted format data block;

[0086] The format conversion process is logged to obtain a format conversion record including the data format before conversion, the data format after conversion, the conversion rule number and the timestamp.

[0087] Specifically, in the input data stream In the data analysis function Scan the data stream and combine it with the index mechanism to determine the specific location of non-standard format data items. Include Data items:

[0088]

[0089] in, Indicates the first data items, and the set of non-standard format data items is:

[0090]

[0091] in, Represents a data item Format requirements The matching function of , whose value is 0, indicates that the format requirement is not met. Extract the position information of the data item in the input data stream from the ROM verification matrix template. Suppose the data position information set is:

[0092]

[0093] in, Represents a non-standard format data item In the data flow After obtaining the location information, the matrix template is verified according to the ROM Extract format conversion rules. Suppose the set of format conversion rules is:

[0094]

[0095] in, Represents a data item The conversion rules include data length adjustment, encoding conversion, alignment change, etc. On this basis, a data format conversion mapping table is constructed:

[0096]

[0097] The mapping table is used to store the location of non-standard format data items, the corresponding format conversion rules, and guide the CPU to perform data format conversion. The non-standard format data items are input into the hardware accelerator of the CPU core for format normalization processing to obtain the initial conversion data block. Suppose the format conversion function of the CPU accelerator is , then the initial conversion data block set is:

[0098]

[0099] in, It indicates that the initial data block after format conversion has a data structure that meets some format requirements, and the initial data block is completed. In the data completion process, the data completion function is set to , used to fill in missing fields, align data, and ensure compliance with the format requirements of the ROM verification matrix template. The final set of data blocks that conform to the standard format is:

[0100]

[0101] in, The completed data block meets the format requirements of the ROM verification matrix template. The format data block is written into the data area and status area of ​​the RAM cache matrix for subsequent data processing. Assume that the RAM cache matrix storage function is , then the data storage process is expressed as:

[0102]

[0103] in, Indicates the result of the storage operation, including the update status of the data area and the status area. In order to ensure the traceability of the format conversion process, log records are recorded so that backtracking can be performed when data anomalies occur. Suppose the log record set is:

[0104]

[0105] in, Indicates the timestamp of data conversion. This log set records the format of the data before conversion, the format after conversion, the conversion rule number used, and the time when the conversion occurred to ensure the transparency and traceability of data processing.

[0106] Among them, before format verification is performed on the input data stream according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items, and before format conversion is performed on the non-standard format data items, the method also includes: performing data quality assessment on the non-standard format data items to obtain an initial quality assessment matrix, wherein the initial quality assessment matrix includes a data coverage index and a data specificity index; performing weighted calculation according to the data coverage index and the data specificity index to obtain a comprehensive quality score, wherein the weight of the data coverage index is α, and the weight of the data specificity index is 1-α, wherein 0<α<1; performing grouping and clustering processing on the non-standard format data items according to the comprehensive quality score to obtain multiple data subsets, wherein each data subset contains data items with similar quality characteristics; and performing grouping and clustering processing on the multiple data subsets. Local features are extracted for each data subset to obtain a subset feature vector, which includes data distribution features and quality features. A quality optimization model is constructed based on the subset feature vector, and anomaly detection is performed on non-standard format data items to obtain normal data sets and abnormal data sets. Format mapping rules are matched on the normal data sets to obtain a standardized processing rule set, which includes data conversion rules and quality constraints. Special rule processing is performed on the abnormal data sets to obtain a supplementary processing rule set, which includes abnormal data processing rules and quality compensation mechanisms. The standardized processing rule set and the supplementary processing rule set are integrated to generate a final processing rule base to obtain a data quality optimization strategy, which is then written into the ROM verification matrix template.

[0107] In a specific embodiment, the process of executing step S4 may specifically include the following steps:

[0108] Calculate the entropy value of the standard format data block and the converted format data block to obtain the data entropy value;

[0109] A compression mode is selected according to the relationship between the data entropy value and the preset thresholds T1 and T2 to obtain a compression processing mode, and 8-byte alignment is performed on the standard format data block and the converted format data block to obtain a padded data block;

[0110] The padded data block is input into the hardware compression instruction set of the CPU core for parallel compression operation to obtain a compressed data stream;

[0111] Reorganizing the storage format of the compressed data stream to obtain a compressed data packet including a 4-byte data length field, a 4-byte checksum field, a 2-byte compression mode field and a compressed data field;

[0112] The compressed data packet is written into the EEPROM data storage area, and the processing status flag is updated in the RAM cache matrix to obtain the compression flag.

[0113] Specifically, entropy values ​​of standard format data blocks and converted format data blocks are calculated to measure the redundancy and randomness of the data, thereby determining a suitable compression strategy. Assume that the standard format data blocks and the converted format data blocks are respectively recorded as sets:

[0114]

[0115] in, Indicates data blocks, and Indicates the total number of data blocks. The entropy value is calculated based on the Shannon entropy formula, which is defined as:

[0116]

[0117] in, Represents a collection of data blocks The entropy value of Represents a set of different byte values ​​in a data block, while Representation value The probability of appearing in a data block. The higher the entropy value, the more random the data is and the worse the compression effect may be; the lower the entropy value, the higher the redundancy of the data and the stronger the compressibility. and The size relationship between the two sets of compression modes is used to select the appropriate compression mode. Set the compression mode selection function as follows:

[0118]

[0119] Among them, the high compression mode is suitable for low entropy data, using Huffman coding or LZ77 compression; the standard compression mode is suitable for medium entropy data, using LZ4 or DEFLATE algorithm; the low compression or no compression mode is suitable for high entropy data, at this time, choose to store the original data or perform lightweight compression to reduce computing overhead. After determining the compression mode, the data block is aligned to 8 bytes to ensure that the data can be efficiently processed in the hardware compression instruction set of the CPU core. Let the padding operation function be , which ensures that the size of each data block is an integer multiple of 8:

[0120]

[0121] in, Indicates the padding value, which can be filled with zero or a specific pattern value to ensure that the data block size is aligned to an integer multiple of 8. The aligned data block set is represented as:

[0122]

[0123] When the data block is aligned, it is input into the hardware compression instruction set of the CPU core for parallel compression operation. Suppose the compression operation function is , which is used to compress the data block set according to the selected compression mode To perform parallel compression:

[0124]

[0125] in, Represents the compressed data stream set. The CPU hardware compression instruction set uses SIMD parallel computing capabilities to speed up data compression and improve system throughput. After compression, the compressed data stream is reorganized in storage format to form a structured compressed data packet. Assume that the data packet format is

[0126]

[0127] in, It is a 4-byte data length field, recording the total size of the data packet; It is a 4-byte checksum field, which is calculated using CRC32 or MD5 to verify data integrity. It is a 2-byte compression mode field, indicating the compression mode of the current data; is the actual compressed data field, which stores the compressed data stream generated by the CPU core. The compressed data packet is written to the EEPROM data storage area, and the processing status flag is updated in the RAM cache matrix for subsequent data reading and management. Suppose the EEPROM storage operation function is , which is used to compress data packets Store in EEPROM and update the status information in RAM:

[0128]

[0129] in, Indicates the storage operation result, including the EEPROM address information and the status flag update. Through the above steps, the compression processing of the standard format data block and the converted format data block is realized, and finally a compressed data packet in the EEPROM storage format is generated. At the same time, the processing status flag of the RAM cache matrix is ​​updated to ensure the efficiency, security and traceability of data processing.

[0130] In a specific embodiment, the process of executing step S5 may specifically include the following steps:

[0131] Read the encryption parameters from the ROM for integrity check to obtain the encryption mode parameters and key length parameters;

[0132] The random number generator based on the CPU core generates keys to obtain session keys and initialization vectors, and groups the compressed data stream into 64-byte groups to obtain fixed-length data groups to be encrypted;

[0133] The data group to be encrypted is input into the encryption instruction set of the CPU core for group chaining encryption operation to obtain an encrypted data group, and the HMAC-SHA256 algorithm is executed on the encrypted data group to obtain a MAC check value.

[0134] Specifically, before data encryption, the encryption parameters are read from the ROM and integrity check is performed to ensure that the obtained parameters have not been tampered with. Assume that the encryption parameter set stored in the ROM is:

[0135]

[0136] in, Indicates the encryption mode parameter, which defines the encryption algorithm (such as AES-128, AES-256 or other encryption methods); Indicates the key length parameter, which can be 128 bits, 192 bits, or 256 bits; Indicates the key derivation rule or IV (initialization vector) generation method. After reading these parameters, their integrity is verified. Let the verification function be:

[0137]

[0138] in, Represents a set of parameters The checksum after hash calculation, Represents the expected checksum value stored in ROM. If the two are equal, it indicates that the parameters are complete; otherwise, the error handling mechanism needs to be triggered to prevent incorrect parameters from causing encryption failure or security vulnerabilities. After confirming that the encryption parameters are complete, the random number generator (RNG) of the CPU core is used to generate session keys and initialization vectors (IV) to ensure the security and unpredictability of each encryption process. Assume that the random number generator of the CPU core is , which is used to generate a length of The session key is a random sequence of and initialization vector The generation of is represented as:

[0139]

[0140] in, The key length is defined, such as 128 bits or 256 bits, and the IV is usually 16 bytes to adapt to the block encryption mode (such as AES-CBC or AES-GCM). After the key and IV are generated, the compressed data stream is grouped into 64 bytes to form a fixed-length data group to be encrypted. Suppose the compressed data stream is:

[0141]

[0142] in, Indicates In order to ensure the alignment of data blocks during encryption, the data stream is grouped into 64 bytes. The data grouping function is:

[0143]

[0144] in, Indicates a 64-byte encrypted data group. is the number of data sets, which is calculated as:

[0145]

[0146] If the data block is less than 64 bytes, it needs to be filled. Let the filling function be , then the filling rule is defined as:

[0147]

[0148] The padding method uses PKCS#7 padding or zero padding to ensure that the data length meets the grouping requirements of the encryption algorithm. After obtaining the data group to be encrypted, it is input into the encryption instruction set of the CPU core to perform the group chaining encryption operation. Suppose the encryption function is , which uses the key and initialization vector For data set Perform encryption operations:

[0149]

[0150] in, Represents an encrypted data group, that is, a component of an encrypted data group. After all data groups are encrypted, a complete encrypted data stream is formed:

[0151]

[0152] After the data is encrypted, in order to ensure the integrity of the data, the HMAC-SHA256 operation is performed on the encrypted data group to generate a MAC check value. Suppose the HMAC calculation function is:

[0153]

[0154] in, Represents an encrypted data group, that is, a component of an encrypted data group. After all data groups are encrypted, a complete encrypted data stream is formed:

[0155]

[0156] After the data is encrypted, in order to ensure the integrity of the data, the HMAC-SHA256 operation is performed on the encrypted data group to generate a MAC check value. Suppose the HMAC calculation function is:

[0157]

[0158] in, Indicates the use of a key Encrypted data stream Perform SHA-256 hash operation to generate the final MAC check value. The calculation method of the HMAC algorithm is as follows:

[0159]

[0160] in, is the SHA-256 hash function. opad and ipad are padding constants used to enhance security.

[0161] In a specific embodiment, the process of executing step S6 may specifically include the following steps:

[0162] Read the state information of the data to be verified from the RAM cache matrix and parse it to obtain the encryption identifier and storage location information;

[0163] Read the encrypted data group from the EEPROM data storage area for reconstruction to obtain the data block to be verified;

[0164] Recalculate the MAC of the data block to be verified based on the key material in the EEPROM key storage area to obtain a verification MAC value;

[0165] Compare the verification MAC value and the MAC check value to obtain the data integrity identifier;

[0166] Based on the data integrity identifier, the data operation record is read from the EEPROM log storage area to locate the time point and obtain the latest correct operation time record;

[0167] The encrypted data group is backed up and restored according to the latest correct operation time record to obtain a processing status record.

[0168] Specifically, the state information of the data to be verified is read from the RAM cache matrix to obtain the encryption identification and storage location information of the data. Assume that the RAM cache matrix is:

[0169]

[0170] in, Indicates The structure of each storage unit contains data storage status information. The status information of each storage unit is expressed as:

[0171]

[0172] in, Indicates the encryption flag of the data, indicating whether the data is encrypted. Indicates the storage location information of the data, pointing to the specific storage address in the EEPROM. After obtaining the storage location information, read the corresponding encrypted data group from the EEPROM data storage area, and reconstruct the data to obtain the data block to be verified. Suppose the encrypted data set in the EEPROM storage area is:

[0173]

[0174] in, Indicates the first encrypted data groups, and their storage locations are determined by OK, so the data block to be verified is represented as:

[0175]

[0176] in, It is the data block to be verified read from the EEPROM, which contains additional storage metadata, so its structure needs to be parsed to extract the real encrypted data content. According to the key material in the EEPROM key storage area, the MAC of the data block to be verified is recalculated to obtain the verification MAC value. Assume that the key set in the EEPROM key storage area is:

[0177]

[0178] in, Indicates key material, and the key index is identified by the encryption Therefore, the key used for MAC calculation is expressed as:

[0179]

[0180] Use the key to calculate the HMAC-SHA256 checksum, assuming the HMAC calculation function is:

[0181]

[0182] in, is the calculated verification MAC value. Compare with the stored MAC check value to determine data integrity. Suppose the stored MAC check value is , then the integrity verification function is defined as:

[0183]

[0184] in, Represents the data integrity flag. When its value is 1, it indicates that the data is complete, otherwise it indicates that the data has been damaged or tampered with. Based on the data integrity flag, read the data operation record from the EEPROM log storage area to locate the time point and obtain the latest correct operation time record. Assume that the data operation record set in the EEPROM log storage area is:

[0185]

[0186] in, Indicates The timestamp of the operation, and Indicates the details of the operation. By finding the most recent correct operation record, determine the latest correct operation time:

[0187] Recording status normal

[0188] Based on the latest correct operation time record, the encrypted data group is backed up and restored to ensure data availability. The historical data set in the device data storage area is:

[0189]

[0190] in, Indicates the first Historical data versions, and the data recovery operation is expressed as:

[0191]

[0192] in, Indicates the data content recovered from the backup data corresponding to the latest correct operation time. The recovered data needs to be written back to the EEPROM to ensure data consistency, and at the same time update the processing status record in the RAM cache matrix so that the system can correctly identify the repaired data blocks.

[0193] The data processing method of the CPU card chip in the embodiment of the present invention is described above. The data processing device of the CPU card chip in the embodiment of the present invention is described below. Figure 2 , an embodiment of the data processing device of the CPU card chip in the embodiment of the present invention includes:

[0194] A construction module is used to construct a data verification matrix for the ROM area and RAM area of ​​the CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix;

[0195] A format verification module is used to perform format verification on the input data stream according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items;

[0196] A format conversion module, used for performing format conversion on non-standard format data items to obtain converted format data blocks and format conversion records;

[0197] A compression processing module, used for inputting the standard format data block and the converted format data block into the CPU core for compression processing to obtain a compressed data stream and a compression identifier;

[0198] The packet encryption module is used to perform packet encryption on the compressed data stream based on the compression identifier to obtain an encrypted data group and a MAC check value;

[0199] The consistency verification module is used to perform consistency verification on the encrypted data group according to the MAC check value to obtain the data integrity identification and processing status record.

[0200] Through the coordinated cooperation of the above-mentioned components and by constructing a data verification matrix of a ROM-RAM hybrid storage structure, the data processing efficiency is improved while reducing hardware costs, so that the CPU card chip can process data in both standard and non-standard formats at the same time; a data format verification mechanism based on a ROM verification matrix template is adopted to realize automatic identification and conversion of data formats, reduce data processing errors, and improve the accuracy of data processing; combined with the hardware acceleration characteristics of the CPU core and the packet compression algorithm, efficient data compression and transmission are achieved under limited RAM resources, reducing storage space occupancy; by introducing a multi-level security protection mechanism, including data format verification, compression identifier verification, MAC value verification, etc., a complete data security protection system is constructed to effectively prevent data tampering and theft attacks; based on an asynchronous processing mechanism triggered by events, the parallel processing capability of the CPU card chip is improved, data processing delay is reduced, and system response performance is enhanced; by establishing a data integrity verification and automatic recovery mechanism, the reliability and fault tolerance of the system are improved, ensuring the continuity and stability of data processing.

[0201] Reference Figure 3In an embodiment of the present invention, a computer device is also provided. The computer device may be a server, and its internal structure may be as follows: Figure 3 As shown. The computer device includes a processor, a memory, a display screen, an input device, a network interface and a database connected through a system bus. Among them, the processor designed by the computer is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store the corresponding data in this embodiment. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above method is implemented.

[0202] Those skilled in the art will understand that Figure 3 The structure shown in the figure is merely a block diagram of a portion of the structure related to the solution of the present invention, and does not constitute a limitation on the computer device to which the solution of the present invention is applied.

[0203] An embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, the above method is implemented. It can be understood that the computer-readable storage medium in this embodiment can be a volatile readable storage medium or a non-volatile readable storage medium.

[0204] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media provided by the present invention and used in the embodiments may include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double-speed data rate SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM.

[0205] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, systems and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0206] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art or the whole or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program code.

[0207] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features thereof may be replaced by equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A data processing method for a CPU card chip, characterized in that: The method comprises: Construct data verification matrix for the ROM area and RAM area of ​​the CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix; Performing format verification on the input data stream according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items; Performing format conversion on the non-standard format data item to obtain a converted format data block and a format conversion record; Input the standard format data block and the converted format data block into the CPU core for compression processing to obtain a compressed data stream and a compression identifier; Encrypt the compressed data stream in groups based on the compression identifier to obtain an encrypted data group and a MAC check value; The encrypted data group is verified for consistency according to the MAC check value to obtain a data integrity identifier and a processing status record.

2. The data processing method of the CPU card chip according to claim 1, characterized in that: The data verification matrix is ​​constructed for the ROM area and the RAM area of ​​the CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix, including: The storage space of the ROM area in the CPU card chip is divided into an N×M dimensional matrix to obtain a preset data verification matrix, where N represents the number of data types and M represents the number of features; Filling the preset data verification matrix with characteristic rules to obtain a ROM verification matrix template including a data valid value range, format requirements and verification rules; An N×M-dimensional cache space is allocated to the RAM area to obtain a RAM cache matrix, wherein each matrix element of the RAM cache matrix includes a 16-byte data cache space and a 4-byte status flag.

3. The data processing method of the CPU card chip according to claim 1, characterized in that: The format verification of the input data stream is performed according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items, including: Performing separator parsing on the input data stream to obtain multiple independent data item sequences, and extracting type identifiers from the multiple independent data item sequences respectively to obtain a data type identifier set; Perform feature matching from the ROM verification matrix template according to the data type identification set to obtain a corresponding data format requirement set; Performing format matching on the plurality of independent data item sequences and the data format requirement set to obtain a format matching result; The plurality of independent data item sequences are classified and marked according to the format matching results to obtain standard format data blocks and non-standard format data items.

4. The data processing method of the CPU card chip according to claim 1, characterized in that: The step of performing format conversion on the non-standard format data item to obtain a converted format data block and a format conversion record includes: Reading data position information in the non-standard format data item to obtain a position record of the data item in the input data stream, and extracting a format conversion rule from the ROM verification matrix template according to the position record to obtain a data format conversion mapping table; Inputting the non-standard format data item into the hardware accelerator of the CPU core for format normalization processing to obtain an initial conversion data block; Completing the initial conversion data block to obtain a format data block that meets the requirements of the ROM verification matrix template, and writing the format data block into the data area and the status area of ​​the RAM cache matrix to obtain a converted format data block; The format conversion process is recorded in a log to obtain a format conversion record including the data format before conversion, the data format after conversion, the conversion rule number and the timestamp.

5. The data processing method of the CPU card chip according to claim 1, characterized in that: The step of inputting the standard format data block and the converted format data block into a CPU core for compression processing to obtain a compressed data stream and a compression identifier includes: Calculating entropy values ​​of the standard format data block and the converted format data block to obtain data entropy values; A compression mode is selected according to a size relationship between the data entropy value and preset thresholds T1 and T2 to obtain a compression processing mode, and 8-byte alignment is performed on the standard format data block and the converted format data block to obtain a padded data block; Inputting the padded data block into the hardware compression instruction set of the CPU core to perform parallel compression operation to obtain a compressed data stream; Reorganizing the compressed data stream into a storage format to obtain a compressed data packet including a 4-byte data length field, a 4-byte checksum field, a 2-byte compression mode field and a compressed data field; The compressed data packet is written into the EEPROM data storage area, and the processing state identifier is updated in the RAM cache matrix to obtain a compression identifier.

6. The data processing method of the CPU card chip according to claim 1, characterized in that: The step of grouping and encrypting the compressed data stream based on the compression identifier to obtain an encrypted data group and a MAC check value includes: Read the encryption parameters from the ROM for integrity check to obtain the encryption mode parameters and key length parameters; A random number generator based on the CPU core is used to generate a key to obtain a session key and an initialization vector, and the compressed data stream is grouped into 64 bytes to obtain a fixed-length data group to be encrypted; The data group to be encrypted is input into the encryption instruction set of the CPU core to perform group chaining encryption operation to obtain an encrypted data group, and the HMAC-SHA256 algorithm is executed on the encrypted data group to obtain a MAC check value.

7. The data processing method of the CPU card chip according to claim 1, characterized in that: The performing consistency verification on the encrypted data group according to the MAC check value to obtain a data integrity identifier and a processing status record includes: Read the state information of the data to be verified from the RAM cache matrix and parse it to obtain the encryption identifier and storage location information; Read the encrypted data group from the EEPROM data storage area for reconstruction to obtain a data block to be verified; Recalculate the MAC of the data block to be verified according to the key material in the EEPROM key storage area to obtain a verification MAC value; Comparing the verification MAC value with the MAC verification value to obtain a data integrity identifier; Based on the data integrity identifier, the data operation record is read from the EEPROM log storage area to perform time point positioning, and the latest correct operation time record is obtained; The encrypted data group is backed up and restored according to the latest correct operation time record to obtain a processing status record.

8. A data processing device for a CPU card chip, characterized in that: Used to execute the data processing method of the CPU card chip according to any one of claims 1 to 7, the data processing device of the CPU card chip comprises: A construction module is used to construct a data verification matrix for the ROM area and RAM area of ​​the CPU card chip to obtain a ROM verification matrix template and a RAM cache matrix; A format verification module, used for performing format verification on the input data stream according to the ROM verification matrix template to obtain standard format data blocks and non-standard format data items; A format conversion module, used for performing format conversion on the non-standard format data item to obtain a converted format data block and a format conversion record; A compression processing module, used for inputting the standard format data block and the converted format data block into the CPU core for compression processing to obtain a compressed data stream and a compression identifier; A packet encryption module, used for performing packet encryption on the compressed data stream based on the compression identifier to obtain an encrypted data group and a MAC check value; The consistency verification module is used to perform consistency verification on the encrypted data group according to the MAC check value to obtain a data integrity identifier and a processing status record.

9. A computer device, characterized in that: The method comprises a memory and a processor, wherein the memory stores a computer program that can be run on the processor, and is characterized in that when the processor executes the computer program, the data processing method of the CPU card chip described in any one of claims 1 to 7 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the processor executes the data processing method for a CPU card chip according to any one of claims 1 to 7.

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