Integrated circuit division method and device, equipment and medium

Abstract

The embodiment of the invention discloses an integrated circuit division method and device, equipment and a medium, and the method comprises the steps: determining a circuit tree diagram of an integrated circuit according to each logic element of a preset integrated circuit, the types of the logic elements comprise a combination logic element and a time sequence logic element, the combinational logic element is used for regulating and controlling a clock signal of the sequential logic element associated with the combinational logic element, and the circuit tree diagram is used for representing the connection relation of the logic elements; for any sequential logic element in the integrated circuit, determining a target combinational logic element associated with the sequential logic element based on the circuit tree diagram; and obtaining a partition block corresponding to the integrated circuit, and updating the partition block according to the sequential logic element and the target combinational logic element associated with the sequential logic element. According to the technical scheme provided by the invention, errors of clock signals of the integrated circuit can be reduced, and the synchronization capability of the integrated circuit is improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to an integrated circuit partitioning method, device, equipment and medium. Background Art

[0002] RTL (Register Transfer Level) logic segmentation is a key stage in integrated circuit design. It refers to the decomposition of complex digital systems into smaller, more manageable and verifiable parts. At this stage, designers will divide the system's functions into a series of register transfer operations, each of which involves the transfer of data from one register to another. This segmentation helps to simplify the design process and improve the testability and maintainability of the design. RTL-level logic segmentation can facilitate the subsequent logic synthesis and verification of integrated circuits. It is also an important step to achieve parallel design and optimize resource utilization, laying the foundation for subsequent physical design and layout and routing.

[0003] However, the current integrated circuit segmentation method will cause the originally unified gated clock of the segmented blocks to be cut, resulting in low clock synchronization capability of the segmented blocks and large clock errors. Summary of the invention

[0004] The present invention provides a method, device, equipment and medium for partitioning an integrated circuit. Through the technical solution provided by the embodiments of the present invention, the clock synchronization capability of the partitioned blocks of the integrated circuit can be improved and the clock error can be reduced.

[0005] In a first aspect, an embodiment of the present invention provides a method for partitioning an integrated circuit, comprising:

[0006] Determine a circuit tree diagram of the integrated circuit according to each logic element of the preset integrated circuit, wherein the types of the logic elements include combinational logic elements and sequential logic elements, the combinational logic elements are used to regulate the clock signal of the sequential logic elements associated therewith, and the circuit tree diagram is used to represent the connection relationship between the logic elements;

[0007] For any sequential logic element in the integrated circuit, determining a target combinational logic element associated with the sequential logic element based on the circuit tree diagram;

[0008] A partition block corresponding to the integrated circuit is obtained, and the partition block is updated according to the sequential logic element and a target combinational logic element associated with the sequential logic element.

[0009] In a second aspect, an embodiment of the present invention provides a device for dividing an integrated circuit, including:

[0010] A generating module, configured to determine a circuit tree diagram of the integrated circuit according to various logic elements of the preset integrated circuit, wherein the types of the logic elements include combinational logic elements and sequential logic elements, the combinational logic elements are used to regulate the clock signal of the sequential logic elements associated therewith, and the circuit tree diagram is used to characterize the connection relationship between the various logic elements;

[0011] a target combinational logic element determination module, configured to determine, for any sequential logic element in the integrated circuit, a target combinational logic element associated with the sequential logic element based on the circuit tree diagram;

[0012] The updating module is used to obtain the partition block corresponding to the integrated circuit, and update the partition block according to the sequential logic element and the target combinational logic element associated with the sequential logic element.

[0013] In a third aspect, an embodiment of the present invention provides an electronic device, the electronic device comprising:

[0014] at least one processor; and,

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform any one of the integrated circuit partitioning methods described in the embodiments of the present invention.

[0017] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, characterized in that the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the integrated circuit partitioning method described in any one of the embodiments of the present invention when executed.

[0018] The embodiment of the present invention provides a partitioning method, device, equipment and medium for an integrated circuit, the method comprising: determining a circuit tree diagram of the integrated circuit according to each logic element of a preset integrated circuit, wherein the type of the logic element includes a combinational logic element and a sequential logic element, the combinational logic element is used to regulate the clock signal of the sequential logic element associated therewith, and the circuit tree diagram is used to characterize the connection relationship of the logic elements; for any sequential logic element in the integrated circuit, determining a target combinational logic element associated with the sequential logic element based on the circuit tree diagram; obtaining a partition block corresponding to the integrated circuit, and updating the partition block according to the sequential logic element and the target combinational logic element associated with the sequential logic element. Specifically, the partition block can be updated by the sequential logic element and the target combinational logic element associated with the sequential logic element, thereby ensuring that the sequential logic element and the target combinational logic element associated with the sequential logic element are contained in the same partition block, thereby avoiding the transmission of the clock signal across the partition block when transmitting the clock signal, improving the clock synchronization capability of the partition block of the integrated circuit, and reducing the clock error. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0020] Figure 1 A flowchart of a method for dividing an integrated circuit provided in Embodiment 1 of the present invention;

[0021] Figure 2 A schematic diagram of a circuit tree diagram provided by an embodiment of the present invention;

[0022] Figure 3 A flowchart of a method for dividing an integrated circuit provided in Embodiment 2 of the present invention;

[0023] Figure 4 A schematic diagram of a partition block provided by an embodiment of the present invention;

[0024] Figure 5 A schematic diagram of the structure of a device for dividing an integrated circuit provided in Embodiment 3 of the present invention;

[0025] Figure 6 A schematic diagram of the structure of an electronic device provided in Embodiment 4 of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] It should be noted that the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved in the technical solution of the present disclosure are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0029] Embodiment 1

[0030] Figure 1 A flowchart of an integrated circuit partitioning method provided in Embodiment 1 of the present invention is provided. The method can be applicable to the case of performing logical partitioning on the integrated circuit at the RTL level. The method can be executed by an integrated circuit partitioning device, which can be made of software and / or hardware and configured in various computers or servers.

[0031] like Figure 1 As shown, including:

[0032] Step 110: Determine a circuit tree diagram of the integrated circuit according to the various logic elements of the preset integrated circuit, wherein the types of the logic elements include combinational logic elements and sequential logic elements, the combinational logic elements are used to regulate the clock signals of the sequential logic elements associated therewith, and the circuit tree diagram is used to characterize the connection relationship between the various logic elements.

[0033] The preset integrated circuit is composed of a plurality of logic elements, and the logic elements include combinational logic elements and sequential logic elements. Furthermore, in the integrated circuit, different combinational logic elements and sequential path elements can be combined to realize specific functions, wherein the synchronization of timing has an important influence on energy consumption and clock error, and the combinational logic element is designed to regulate the clock signal of the sequential logic element associated with it, such as realizing the on-off of the clock signal by the on-off of one or more combinational logic elements, thereby regulating the clock signal of the sequential logic element associated with it, wherein the relevance of the logic elements can be determined by the association of the transmission path or the association of the connection mode.

[0034] Specifically, for integrated circuits that protect specific functions, they can be abstractly represented through corresponding circuit tree diagrams, the nodes in the circuit tree diagram can represent different logic elements, and the node paths in the circuit tree diagram can represent the connection relationship or signal transmission relationship of the logic elements.

[0035] Optionally, a sequential logic element is connected to an output end of the integrated circuit, and the logic element includes an element identifier and an input interface identifier, and the input interface identifier is an element identifier of a logic element to which an input interface of the logic element is connected.

[0036] The integrated circuit described in the embodiment of the present invention may be a subcircuit or submodule of a large integrated circuit, having fixed input and output terminals, wherein the sequential logic element is connected to the output terminal of the integrated circuit; the element identifier is preset in the logic element, and is used to determine whether the logic element is a sequential logic element or a combinational logic element, and the input interface identifier is used to determine the logic element corresponding to the input terminal of the logic element. Exemplarily, if the input interface identifier of the logic element A is B, the input interface of the logic element is connected to the output interface of the logic element B.

[0037] Optionally, step 110 includes:

[0038] Determining a sequential logic element among the logic elements according to the element identification of the logic element;

[0039] Determine the sequential logic element as a leaf node of the circuit tree diagram;

[0040] The circuit tree diagram is generated according to the leaf nodes and the input interface identifiers of the logic elements.

[0041] Specifically, the sequential logic element in the logic element can be determined according to the element identifier of the logic element. The embodiment of the present invention presets the last layer of logic elements of the sequential logic element circuit, that is, the sequential logic element is located at the leaf node of the circuit tree diagram. Furthermore, according to the leaf node of the circuit tree diagram and the input interface identifier of the logic element, a reverse traversal can be performed to generate a circuit tree diagram.

[0042] Specifically, generating the circuit tree diagram according to the leaf node and the input interface identifier of the logic element includes:

[0043] Determine, according to the input interface identifier of the leaf node, a logical element corresponding to the parent node of the leaf node;

[0044] If the input interface of the parent node is an input terminal of the integrated circuit, determining the parent node as a root node;

[0045] Otherwise, the parent node of the logic element corresponding to the parent node is determined according to the input interface identifier of the logic element corresponding to the parent node.

[0046] Specifically, starting from a leaf node, the parent node of the logic element can be determined according to the input interface identifier of the logic element, and then the parent node of the parent node can be determined according to the input interface identifier of the parent node, until the root node is reached. Specifically, since the root node is the first-level node of the circuit logic tree and is connected to the input end of the integrated circuit, when determining the parent node, if the input interface of the parent node is the input end of the integrated circuit, the parent node is determined as the root node.

[0047] For example, Figure 2 A schematic diagram of a circuit tree diagram provided for an embodiment of the present invention, wherein logic1, logic2, logic6 and logic7 are sequential logic elements and are leaf nodes of the circuit tree diagram, logic3, logic4, logic5, logic8 and logic9 are combinational logic elements, the direction of the arrow is the direction of signal transmission or data transmission, and logic5 and logic8 are root nodes.

[0048] Step 120 : For any sequential logic element in the integrated circuit, based on the circuit tree diagram, determine a target combinational logic element associated with the sequential logic element.

[0049] Specifically, in actual clock signal transmission, the signal will be input into the root node, and then transmitted from the root node along the path of the circuit tree diagram, and finally reach the leaf node (time domain logic element). Therefore, in the process of logic element division, it is necessary to ensure that each logic element on the same path is located in the same division block, so that the clock signal will not be transmitted across the division block during the transmission process, so as to ensure the continuity of clock signal transmission and reduce clock error. Therefore, it is necessary to determine all logic elements contained in the same path during the transmission of the clock signal in the circuit tree diagram, and their mutually related logic elements. Furthermore, the target combinational logic elements associated with the sequential logic element are all combinational logic elements on the transmission path from the root node to the sequential logic element in the circuit tree diagram.

[0050] Optionally, step 120 includes:

[0051] For any leaf node of the circuit tree diagram, determining a logic path corresponding to the leaf node according to a path between a root node of the circuit tree diagram and the leaf node;

[0052] The combinational logic element corresponding to the logic path is determined as the target combinational logic element associated with the sequential logic element represented by the leaf node.

[0053] Specifically, the path between the root node and the leaf node can be determined as the logical path of the leaf node, and then the combinational logic element on the logic path can be determined as the target combinational logic element associated with the sequential logic element represented by the leaf node. It should be noted that since the clock signal is input from the root node and output from the leaf node, one of the purposes of the embodiment of the present invention is to ensure that the divided blocks, during the clock signal transmission process, the sequential logic element and the target logic element associated therewith are located in the same partition block, so as to ensure that there is no cross-partition block transmission during the signal transmission process, thereby reducing the clock error and improving the synchronization capability of the partition block.

[0054] Step 130: Acquire a partition block corresponding to the integrated circuit, and update the partition block according to the sequential logic element and a target combinational logic element associated with the sequential logic element.

[0055] Specifically, since the integrated circuit is designed to implement multiple functions, the implementation of different functions requires specific logic elements in the integrated circuit. Therefore, the partition block can be a partition block divided based on a specific requirement or function. For example, the integrated circuit can be divided according to the purpose of minimizing the resource consumption of each function, and partition blocks corresponding to multiple functions can be generated. It should be noted that the method of obtaining and generating the partition block is not limited here.

[0056] Furthermore, since the partition blocks are generated based on specific goals, the logic elements inside the partition blocks are not fixed. Therefore, when the clock signal is transmitted along the path of the circuit tree diagram, cross-partition block transmission may occur, which will increase the clock error and reduce the synchronization capability. Therefore, it is necessary to update the partition blocks according to the sequential logic elements and the target combination logic elements associated with the sequential logic elements, so that when the logic elements in the updated partition blocks transmit the clock signal, cross-partition block transmission will not occur. The specific method is as follows.

[0057] Specifically, the clock signal here may be a signal related to a gated clock, that is, through the method of the embodiment of the present invention, it can be ensured that the signal related to the gated clock is complete and undivided before and after the integrated circuit is divided.

[0058] The embodiment of the present invention provides a partitioning method for an integrated circuit, the method comprising: determining a circuit tree diagram of the integrated circuit according to each logic element of a preset integrated circuit, wherein the type of the logic element comprises a combinational logic element and a sequential logic element, the combinational logic element is used to regulate the clock signal of the sequential logic element associated therewith, and the circuit tree diagram is used to characterize the connection relationship of the logic elements; for any sequential logic element in the integrated circuit, determining a target combinational logic element associated with the sequential logic element based on the circuit tree diagram; obtaining a partitioning block corresponding to the integrated circuit, and updating the partitioning block according to the sequential logic element and the target combinational logic element associated with the sequential logic element. Specifically, the partitioning block can be updated by the sequential logic element and the target combinational logic element associated with the sequential logic element, thereby ensuring that the sequential logic element and the target combinational logic element associated with the sequential logic element are contained in the same partitioning block, thereby avoiding the transmission of the clock signal across the partitioning block when transmitting the clock signal, improving the clock synchronization capability of the partitioning block of the integrated circuit, and reducing the clock error.

[0059] Embodiment 2

[0060] Figure 3 A flowchart of a partitioning method for an integrated circuit provided by an embodiment of the present invention is provided. The method is based on the above embodiment and further defines a method for updating the partitioning block according to the sequential logic element and the target combinational logic element associated with the sequential logic element.

[0061] like Figure 3 As shown, including:

[0062] Step 210: Determine a circuit tree diagram of the integrated circuit according to the various logic elements of the preset integrated circuit, wherein the types of the logic elements include combinational logic elements and sequential logic elements, the combinational logic elements are used to regulate the clock signals of the sequential logic elements associated therewith, and the circuit tree diagram is used to characterize the connection relationship between the various logic elements.

[0063] Step 220: Determine the combinational logic element corresponding to the logic path as the target combinational logic element associated with the sequential logic element represented by the leaf node.

[0064] Step 230: Divide the integrated circuit into blocks according to preset circuit requirements.

[0065] Among them, the integrated circuit is used to complete multiple functions, and each function needs to meet different requirements when implemented, such as energy consumption requirements and timing requirements. Therefore, the partition block is generated by dividing the integrated circuit accordingly according to the required requirements.

[0066] Step 240: Determine at least one sequential logic element in the partitioned block.

[0067] Step 250: If at least one target combinational logic element associated with the sequential logic element is missing in the partition block, copy the missing target combinational logic element into the partition block.

[0068] Specifically, it is necessary to determine each sequential logic element contained in the partition block, and then determine whether the partition block includes the target combinational logic element associated with the sequential logic element. If not, it means that the missing target combinational logic element may be located in other partition blocks. Therefore, in the clock signal transmission, the problem of cross-block transmission may occur, resulting in large clock error and poor synchronization effect. Therefore, it is necessary to copy the missing target combinational logic element into the partition block to ensure that the partition block contains all the target combinational logic elements associated with the sequential logic element.

[0069] Optionally, the missing target combinational logic element is obtained from a preset component library, and the missing target combinational logic element is added to the partition block, wherein the preset component library includes all logic elements of the integrated circuit.

[0070] Specifically, the preset component library includes various logic components of the integrated circuit. If a partition block needs to add a logic component, the component identifier of the required logic component can be obtained from the preset component library, and the target combination logic component can be added to the partition block.

[0071] For example, Figure 4 A schematic diagram of a partition block provided in an embodiment of the present invention. Specifically, Figure 4 The logical elements of the divided blocks correspond to Figure 2 The partition block may be a block generated according to a specific algorithm to meet specific requirements. For example, the partition block meets the preset minimum energy consumption requirement. The partition block before the update includes sequential logic blocks logic1 and logic2. Figure 2 From the content, we can see that the combinational logic blocks associated with logic1 are logic3 and logic5, and the combinational logic blocks associated with logic2 are logic4 and logic5. However, the partition block before the update lacks logic3 associated with logic1, so logic3 needs to be copied into the partition block through the update operation.

[0072] Optionally, after updating the partition block, the method further includes:

[0073] Inputting a clock signal into an input end of the partition block, performing a preset error test on the partition block, and determining a clock delay;

[0074] A clock error is determined according to the clock delay; if the clock error does not meet a test error threshold, the integrated circuit and / or partition block is adjusted.

[0075] Specifically, since logic elements are added to the partitioning blocks, other unpredictable problems may occur in the updated partitioning blocks, such as the clock error is still too large, or there is an obvious logical deviation from the function of the partitioning blocks before the update. Therefore, it is necessary to perform a preset error test on the updated partitioning blocks, and then determine the clock error based on the clock delay; if the clock error does not meet the test error threshold, the integrated circuit and / or partitioning block is adjusted.

[0076] Optionally, the test content also includes consistency testing of actual logic functions before and after the partition block is updated. If the test results are inconsistent, it means that the update of the partition block has changed the original logic function and the composition of the partition block needs to be re-partitioned or adjusted.

[0077] Furthermore, the updated testing method can improve the completeness of the partition block function.

[0078] It should be noted that the embodiment of the present invention is a simulation process before the actual application of the integrated circuit. The purpose is to determine the relatively optimal partition block through different forms of partitioning as much as possible to meet the needs of the integrated circuit operation. The partition block has no necessary connection with the physical wiring and composition of the final integrated circuit. The partition result can be used for subsequent partition block testing. If the test is not satisfactory, it may need to be re-partitioned.

[0079] An embodiment of the present invention provides a partitioning method for an integrated circuit. The method copies target combinational logic elements missing in a partition block into the partition block, thereby ensuring that the same partition block contains a sequential logic element and a target combinational logic element associated with the sequential logic element. Therefore, when transmitting a clock signal, the transmission of the clock signal across the partition blocks can be avoided, thereby improving the clock synchronization capability of the partition blocks of the integrated circuit and reducing clock errors.

[0080] Embodiment 3

[0081] Figure 5 This is a schematic diagram of the structure of a device for dividing an integrated circuit provided in Embodiment 3 of the present invention. Figure 5 As shown, the device comprises:

[0082] A generating module 310 is used to determine a circuit tree diagram of the integrated circuit according to various logic elements of the preset integrated circuit, wherein the types of the logic elements include combinational logic elements and sequential logic elements, the combinational logic elements are used to regulate the clock signal of the sequential logic elements associated therewith, and the circuit tree diagram is used to represent the connection relationship between the various logic elements;

[0083] A target combinational logic element determination module 320 is used to determine, for any sequential logic element in the integrated circuit, a target combinational logic element associated with the sequential logic element based on the circuit tree diagram;

[0084] The updating module 330 is configured to obtain a partition block corresponding to the integrated circuit, and update the partition block according to the sequential logic element and a target combinational logic element associated with the sequential logic element.

[0085] An embodiment of the present invention provides a partitioning device for an integrated circuit. The device copies target combinational logic elements missing in a partition block into the partition block, thereby ensuring that the same partition block contains a sequential logic element and a target combinational logic element associated with the sequential logic element. Therefore, when transmitting a clock signal, the transmission of the clock signal across the partition blocks can be avoided, thereby improving the clock synchronization capability of the partition blocks of the integrated circuit and reducing clock errors.

[0086] Optionally, the sequential logic element is connected to an output terminal of the integrated circuit, and the logic element includes an element identifier and an input interface identifier;

[0087] The generation module 310 includes:

[0088] A sequential logic element determination unit, configured to determine a sequential logic element among the logic elements according to an element identifier of the logic element;

[0089] A leaf node determination unit, used for determining the sequential logic element as a leaf node of the circuit tree diagram;

[0090] A generating unit is used to generate the circuit tree diagram according to the leaf nodes and the input interface identifiers of the logic elements.

[0091] The generation unit specifically includes:

[0092] A determination subunit, used to determine the logic element corresponding to the parent node of the leaf node according to the input interface identifier of the leaf node;

[0093] The judgment subunit is used to determine the parent node as a root node if the input interface of the parent node is an input terminal of the integrated circuit; otherwise, determine the parent node of the logic element corresponding to the parent node according to the input interface identifier of the logic element corresponding to the parent node.

[0094] Optionally, the target combinational logic element determination module 320 includes:

[0095] A logic path determination unit, configured to determine, for any leaf node of the circuit tree diagram, a logic path corresponding to the leaf node according to a path between a root node of the circuit tree diagram and the leaf node;

[0096] The target combinational logic element determination unit is used to determine the combinational logic element corresponding to the logic path as the target combinational logic element associated with the sequential logic element represented by the leaf node.

[0097] Optionally, the updating module 330 includes:

[0098] A partitioning unit, used to partition the integrated circuit according to preset circuit requirements and determine partition blocks;

[0099] A determination unit, configured to determine at least one sequential logic element in the partition block;

[0100] The updating unit is configured to copy the missing target combinational logic element into the partition block if at least one target combinational logic element associated with the sequential logic element is missing in the partition block.

[0101] The updating unit is specifically used for: acquiring the missing target combinational logic element from a preset component library, and adding the missing target combinational logic element to the partition block, wherein the preset component library includes all logic elements of the integrated circuit.

[0102] Optionally, the integrated circuit partitioning device also includes a testing module, which is used to input a clock signal into the input end of the partitioning block, perform a preset error test on the partitioning block, and determine the clock delay; determine the clock error based on the clock delay; if the clock error does not meet the test error threshold, adjust the integrated circuit and / or partitioning block.

[0103] The integrated circuit partitioning device provided in the embodiment of the present invention can execute the integrated circuit partitioning method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0104] Embodiment 4

[0105] Figure 6A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0106] like Figure 6 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0107] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0108] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as a partitioning method of an integrated circuit.

[0109] In some embodiments, the partitioning method of the integrated circuit may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the partitioning method of the integrated circuit described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the partitioning method of the integrated circuit in any other appropriate manner (e.g., by means of firmware).

[0110] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0111] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0112] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0113] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0114] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0115] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0116] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0117] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for partitioning an integrated circuit, characterized in that: include: Determine a circuit tree diagram of the integrated circuit according to each logic element of the preset integrated circuit, wherein the types of the logic elements include combinational logic elements and sequential logic elements, the combinational logic elements are used to regulate the clock signal of the sequential logic elements associated therewith, and the circuit tree diagram is used to characterize the connection relationship between the logic elements; For any sequential logic element in the integrated circuit, determining a target combinational logic element associated with the sequential logic element based on the circuit tree diagram; A partition block corresponding to the integrated circuit is obtained, and the partition block is updated according to the sequential logic element and a target combinational logic element associated with the sequential logic element.

2. The method according to claim 1, characterized in that The sequential logic element is connected to the output end of the integrated circuit, the logic element includes an element identifier and an input interface identifier, and the input interface identifier is an element identifier of a logic element to which the input interface of the logic element is connected; The step of determining a circuit tree diagram of the integrated circuit according to each logic element of the preset integrated circuit comprises: Determining a sequential logic element among the logic elements according to the element identification of the logic element; Determine the sequential logic element as a leaf node of the circuit tree diagram; The circuit tree diagram is generated according to the leaf nodes and the input interface identifiers of the logic elements.

3. The method according to claim 2, characterized in that: The step of generating the circuit tree diagram according to the leaf node and the input interface identifier of the logic element includes: Determine, according to the input interface identifier of the leaf node, a logical element corresponding to the parent node of the leaf node; If the input interface of the parent node is an input terminal of the integrated circuit, determining the parent node as a root node; Otherwise, the parent node of the logic element corresponding to the parent node is determined according to the input interface identifier of the logic element corresponding to the parent node.

4. The method according to claim 3, characterized in that: The step of determining, for any sequential logic element in the integrated circuit, a target combinational logic element associated with the sequential logic element based on the circuit tree diagram comprises: For any leaf node of the circuit tree diagram, determining a logic path corresponding to the leaf node according to a path between a root node of the circuit tree diagram and the leaf node; The combinational logic element corresponding to the logic path is determined as the target combinational logic element associated with the sequential logic element represented by the leaf node.

5. The method according to claim 1, characterized in that The obtaining of the partition block corresponding to the integrated circuit, and updating the partition block according to the sequential logic element and the target combinational logic element associated with the sequential logic element, comprises: According to preset circuit requirements, the integrated circuit is divided to determine the division blocks; determining at least one sequential logic element in the partition block; If at least one target combinational logic element associated with the sequential logic element is missing in the partition block, the missing target combinational logic element is copied into the partition block.

6. The method according to claim 5, characterized in that The step of copying the missing target combinational logic element into the partition block comprises: The missing target combinational logic element is obtained from a preset component library, and the missing target combinational logic element is added to the partition block, wherein the preset component library includes all logic elements of the integrated circuit.

7. The method according to claim 1, characterized in that: After the updating of the partition blocks, the method further includes: Inputting a clock signal into an input end of the partition block, performing a preset error test on the partition block, and determining a clock delay; A clock error is determined according to the clock delay; if the clock error does not meet a test error threshold, the integrated circuit and / or partition block is adjusted.

8. An integrated circuit partitioning device, characterized in that: include: A generating module, configured to determine a circuit tree diagram of the integrated circuit according to various logic elements of the preset integrated circuit, wherein the types of the logic elements include combinational logic elements and sequential logic elements, the combinational logic elements are used to regulate the clock signal of the sequential logic elements associated therewith, and the circuit tree diagram is used to characterize the connection relationship between the various logic elements; a target combinational logic element determination module, configured to determine, for any sequential logic element in the integrated circuit, a target combinational logic element associated with the sequential logic element based on the circuit tree diagram; The updating module is used to obtain the partition block corresponding to the integrated circuit, and update the partition block according to the sequential logic element and the target combinational logic element associated with the sequential logic element.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the integrated circuit partitioning method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the integrated circuit partitioning method according to any one of claims 1 to 7 when executed.

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