Internal clock monitoring using external clock provided by communication interface

Abstract

The invention relates to internal clock monitoring using an external clock provided by a communication interface. An integrated circuit (IC) includes: an internal clock source configured to generate an internal clock signal; a communication interface configured to receive an external clock signal from an external clock source and to receive a communication frame signal indicating a communication frame during which data communication between the IC and the external clock source is enabled, in which the external clock signal and the communication frame signal are received in parallel; and a clock monitoring circuit configured to monitor the internal clock signal based on the external clock signal. The clock monitoring circuit is configured to compare an internal clock signal and an external clock signal during a communication frame, and generate a timing error signal if a frequency of the internal clock signal does not satisfy a predetermined threshold relative to a frequency of the external clock signal.

Description

Background Art

[0001] When using digital sensors, clock monitoring is a necessary safety measure to ensure that common cause failures are detected. However, monitoring the clock signal generated internally by the digital sensor can usually only be implemented with low precision and limited diagnostic coverage (only marginal benefits), or with high precision and considerable workload. When performed internally by the digital sensor, clock monitoring also requires redundant clock sources, which need to be tested before the redundant clocks can be reliably used for clock monitoring. For high precision, the clock source also needs to be adjusted. The adjustment and testing of the redundant clocks increase the chip area of ​​the digital sensor and increase the test time, both of which lead to higher costs. The adjustment of the redundant clocks is inherently dependent on the digital core of the digital sensor, which reduces the diagnostic coverage of the safety mechanism. Especially because the safety mechanism is usually implemented to protect the digital core from the common cause failure of the faulty clock signal. Summary of the invention

[0002] In some implementations, a communication system includes a first integrated circuit (IC) comprising: a first clock source configured to generate a first clock signal; a counter configured to receive the first clock signal and increment or decrement a counter value based on the first clock signal; and a first communication interface configured to receive a counter value from the counter and transmit the counter value from the first IC; and a second IC comprising: a second clock source configured to generate a second clock signal; a sampling circuit configured to obtain a first sample of the counter value at a first sampling time, obtain a second sample of the counter value at a second sampling time, and calculate a difference value as a difference between the second sample and the first sample; and a clock monitoring circuit configured to monitor the first clock signal based on the second clock signal, wherein the clock monitoring circuit is configured to compare the difference value with the second clock signal and generate a timing error signal if the difference value deviates from a clock value derived from the second clock signal by more than a predetermined threshold.

[0003] In some implementations, an integrated circuit (IC) includes: an internal clock source configured to generate an internal clock signal; a communication interface configured to receive an external clock signal from an external clock source and a communication frame signal indicating a communication frame, during which data communication between the IC and the external clock source is enabled, wherein the external clock signal and the communication frame signal are received in parallel; and a clock monitoring circuit configured to monitor the internal clock signal based on the external clock signal, wherein the clock monitoring circuit is configured to compare the internal clock signal and the external clock signal during the communication frame, and generate a timing error signal if the frequency of the internal clock signal does not meet a predetermined threshold relative to the frequency of the external clock signal.

[0004] In some implementations, a method for monitoring an internal clock source of an integrated circuit (IC) using an external clock signal includes: generating an internal clock signal by an internal clock source; receiving an external clock signal from the external clock source by a communication interface of the IC; receiving a communication frame signal from the external clock source by the communication interface of the IC, wherein the communication frame signal indicates a plurality of communication frames, during which data communication between the IC and the external clock source is enabled, and wherein the external clock signal and the communication frame signal are received in parallel; and monitoring the internal clock signal based on the external clock signal by a clock monitoring circuit of the IC, the monitoring including: comparing the internal clock signal and the external clock signal during a plurality of communication frames; and generating a timing error signal if the frequency of the internal clock signal does not meet a predetermined threshold relative to the frequency of the external clock signal, wherein monitoring of the internal clock signal is disabled outside of a plurality of communication frames.

[0005] In some implementation methods, a communication system includes a first integrated circuit (IC), which includes: a first clock source, which is configured to generate a first clock signal; and a communication interface, which is configured to generate a communication signal having a signal period and transmit the communication signal, the signal period being proportional to the first clock period of the first clock signal; a second IC, which includes: a second clock source, which is configured to generate a second clock signal having a second clock period; a sampling circuit, which is configured to detect a transition edge of the communication signal to determine the signal period of the communication signal; a scaler, which is configured to scale the signal period by a first scaling factor to derive a first clock value, which represents the first clock period of the first clock signal; and a clock monitoring circuit, which is configured to monitor the first clock signal based on the second clock signal, wherein the clock monitoring circuit is configured to receive the first clock value from the scaler, and generate a timing error signal if the first clock value deviates from the second clock value derived from the second clock signal by more than a predetermined threshold. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Implementation methods are described herein with reference to the accompanying drawings.

[0007] Figure 1 is a schematic block diagram of a communication system according to one or more implementation methods.

[0008] Figure 2 A communication system according to one or more implementations is shown.

[0009] Figure 3 A communication system according to one or more implementations is shown.

[0010] Figure 4A A signal diagram illustrating a single external clock cycle of an external clock signal according to one or more implementations.

[0011] Figure 4BA signal diagram of a single communication frame of a communication frame signal according to one or more implementations is shown.

[0012] Figure 5 is a diagram illustrating an example algorithm that may be used to monitor an internal clock source in accordance with one or more implementations.

[0013] Figure 6 A communication system according to one or more implementations is shown.

[0014] Figure 7 A communication system according to one or more implementations is shown. DETAILED DESCRIPTION

[0015] In the following, details are set forth to provide a more comprehensive explanation of exemplary implementations. However, it will be apparent to those skilled in the art that these implementations may be practiced without these specific details. In other examples, known structures and devices are shown in block diagram form or in schematic diagrams rather than in detail to avoid obscuring the implementations. In addition, unless otherwise specifically noted, the features of the different implementations described below may be combined with each other.

[0016] Further, equivalent or similar elements or elements having equivalent or similar functions are indicated by equivalent or similar reference numerals in the following description. Since identical or functionally equivalent elements are assigned the same reference numerals in the figures, repeated descriptions of elements provided with the same reference numerals may be omitted. Therefore, the descriptions provided for elements having the same or similar reference numerals are mutually interchangeable.

[0017] It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements. Other words used to describe relationships between elements (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," etc.) should be interpreted in a similar manner.

[0018] In the implementations described herein or shown in the accompanying drawings, any direct electrical connection or electrical coupling (e.g., any connection or coupling without additional intermediate elements) may also be implemented by an indirect connection or coupling (e.g., a connection or coupling with one or more additional intermediate elements, or vice versa), as long as the general purpose of the connection or coupling is essentially maintained (e.g., to transmit a certain signal or to transmit a certain information). Features from different implementations may be combined to form additional implementations. For example, unless otherwise noted, variations or modifications described with respect to one of the implementations may also apply to other implementations.

[0019] As used herein, the terms "substantially" and "approximately" mean "within reasonable tolerances of manufacturing and measurement." For example, without exceeding the scope of the embodiments described herein, the terms "substantially" and "approximately" may be used herein to explain small manufacturing tolerances or other factors (e.g., within 5%) that are considered acceptable in the industry. For example, a resistor having an approximate resistance value may actually have a resistance within 5% of the approximate resistance value. As another example, a signal having an approximate signal value may actually have a signal value within 5% of the approximate signal value.

[0020] In the present disclosure, expressions including ordinal numbers (such as "first", "second" and / or similar expressions) can modify various elements. However, such elements are not limited by such expressions. For example, such expressions do not limit the order and / or importance of elements. In addition, such expressions are only used for the purpose of distinguishing elements from other elements. For example, the first box and the second box indicate different boxes, although both are boxes. For example, without departing from the scope of the present disclosure, the first element can be called the second element, and similarly, the second element can be called the first element.

[0021] "Sensor" may refer to a component that converts a characteristic to be measured into an electrical sensor signal (e.g., a current signal or a voltage signal). The characteristic to be measured may, for example, include, but is not limited to, a magnetic field, an electric field, an electromagnetic wave (e.g., a radio wave), a pressure, a temperature, a force, a current, or a voltage. The sensor device and the controller (e.g., a microcontroller) may be integrated on a separate integrated circuit (IC) (e.g., a separate semiconductor chip). Therefore, the sensor device may communicate with the controller via a communication bus (e.g., a serial peripheral interface (SPI)). Therefore, the sensor device may communicate with the controller via a communication interface (e.g., a pulse width modulation (PWM) interface, an incremental interface (e.g., an ABZ interface), or an interface emulation Hall switch (e.g., a UVW interface)).

[0022] Components of a sensor device may operate based on an internal clock used as a master clock. When using digital sensors, clock monitoring of the master clock is a necessary safety measure to ensure that each component of the digital sensor operates correctly. Clock monitoring can also be used to detect common cause failures of sensor devices. Clock monitoring can be implemented by comparing the master clock with a redundant safety clock generated by the sensor device that is independent of the master clock. If the comparison of the master clock and the safety clock falls outside the specified safety limits, a clock failure is detected. However, redundant safety clocks require testing and potential adjustments, which increases chip area and test time, and therefore increases cost.

[0023] Therefore, some implementations disclosed herein are directed to performing clock monitoring of a master clock of a sensor device (e.g., performing a safety check on a master clock of a sensor device) using an external clock source. The external clock source can be much more accurate than a redundant safety clock generated by the sensor device, does not require dedicated adjustments, and is independent of the sensor device structure (e.g., independent of any limitations of a digital core of the sensor device). The digital communication interface can be used to provide internal clock information to an external device that performs clock monitoring, or can be used to receive an external reference clock signal from an external device, which the sensor device uses to perform clock monitoring.

[0024] Figure 1 1 is a schematic block diagram of a communication system 100 according to one or more implementation methods. The communication system 100 includes a master device 101 (such as a microcontroller) and a slave device (such as a sensor device or other peripheral device). The slave device 102 can be any integrated circuit (such as a chip) that includes a data register and can perform data operations (such as read and write operations) from / to the data register under the control of the master device 101. Here, a read operation is a data transmission originating from the slave device 102 and terminating at the master device 101, and a write operation is a data transmission originating from the master device 101 and terminating at the slave device 102. The master device and the slave device each include at least one processor for performing corresponding data operations.

[0025] In some implementations, the communication system 100 may be a serial peripheral interface (SPI) communication system. In an SPI communication configuration, both the master device 101 and the slave device 102 include an SPI clock terminal connected by a clock signal line that transmits a clock signal SCK (e.g., a communication clock signal, such as an SPI clock signal). The device that generates the clock signal SCK is referred to as a host. The data transmitted between the host and the slave is synchronized with the clock generated by the host. During SPI communication, data is synchronously transmitted (serially shifted out to the MOSI / SDI signal line) and received (data on the MISO / SDO line is sampled or read in). The serial clock edge synchronizes the shifting and sampling of data. The SPI interface provides the user with the flexibility of selecting the rising edge or falling edge of the clock to sample and / or shift data. Each clock cycle represents one bit.

[0026] For example, data present at the serial data input (SDI) can be latched on the rising edge of the clock signal SCK, and data at the serial data output (SDO) can be shifted out at the falling edge of the clock signal SCK. SDI is a data input terminal of the slave device 102, and is connected to the master output slave input (MOSI) terminal of the master device 101 via a data line. The master device 101 transmits information including control information and data to the slave device 102 via its MOSI terminal. The SDI terminal is used to transfer data serially to the slave device. The SDI terminal receives data to be written. SDO is a data output terminal of the slave device 102, and is connected to the master input slave output (MISO) terminal of the master device 101 via a data line. The master device 101 receives (reads) information from the slave device 102 via its MISO terminal. The SDO terminal is used to transfer data serially out of the slave device. The SDO terminal transmits data to be read.

[0027] The chip select non (CSN) signal indicates the time when the slave device 102 is selected for communication and defines a communication frame during which the communication between the master device 101 and the slave device 102 is enabled. The communication between the master device 101 and the slave device 102 can be enabled on a frame-by-frame basis. Therefore, the CSN signal can be referred to as a communication frame signal indicating a communication frame. For example, when the CSN signal is a high level, the slave device 102 is not selected and SDO is set to high impedance. Alternatively, when the CSN signal is a low level, the slave device 102 is selected for communication. Communication starts and ends at the low potential of the clock signal SCK.

[0028] Both the master device and the slave device include a chip select terminal connected by a selection signal line. Here, the chip select terminal is a CSN terminal, that is, the chip select signal is a low-level effective signal. The chip select signal is emitted from the master device 101 and is used to select and / or enable the slave device 102 for SPI communication. When enabling communication with the slave device 102, the chip select signal is a low level, and it is pulled high to disconnect the slave device 102 from the SPI bus, thereby disabling communication with the slave device 102. More specifically, when the chip select signal is pulled high, the SDO terminal is placed in high impedance. The CSN signal is driven at a low level to enable communication. Therefore, the master device 101 must send a logic 0 on the CSN signal to select the slave device 102. SPI is a full-duplex interface, so that the master device 101 and the slave device 102 can send data simultaneously via the MOSI data line and the MISO data line, respectively.

[0029] A communication frame (i.e., a CSN frame) is defined by the time interval between two consecutive high-level (logic 1) signal bits, during which the CSN signal is low (logic 0). Therefore, the falling edge of the CSN signal from high level to low level identifies the beginning of the CSN frame, and the next edge (e.g., rising edge) from low level to high level identifies the end of the CSN frame. Each CSN frame is a predetermined number of clock cycles, and the frame length corresponds to the number of bits or bytes of the SPI buffer. For example, for an x-byte SPI buffer, the length of each CSN frame is x bytes, where x is an integer greater than 1. Two consecutive CSN frames are separated by an idle period, during which the CSN signal is high (logic 1) and communication from the slave device 102 is disabled.

[0030] The master device 101 includes at least one processor 103 and / or processing circuit device, which performs the functions of the master device 101 for performing SPI communication described herein, including: generating signals (such as CSN, SCK and MOSI signals) (including synchronizing and controlling the slave device 102), receiving signals (such as MISO signal) and processing signals, sampling data from the MISO data line, shifting data out to the MOSI signal line, incrementing and tracking register addresses, evaluating register addresses, and automatic register address incrementing across SPI data (communication) frames, including enabling and disabling thereof.

[0031] Similarly, the slave device 102 includes at least one processor 104 and / or processing circuit device that performs the functions of the slave device 102 for performing SPI communication described herein, including: generating signals (e.g., MISO signal), receiving signals (e.g., CSN, SCK, and MOSI signals), and processing signals, sampling data from the MOSI data line, shifting data out to the MISO data line, incrementing and tracking register addresses, evaluating register addresses, and automatically incrementing register addresses across SPI data (communication) frames based on whether the slave device 102 is enabled by the master device 101.

[0032] Although SPI communication is described with respect to one or more implementations, other types of data communication protocols may be used for communication between the master device 101 and the slave device 102. Communication between the master device 101 and the slave device 102 may be enabled based on a communication frame signal provided by the master device 101 to the slave device 102.

[0033] As indicated above, provide Figure 1 As an example. Other examples can be related to Figure 1 Different than described. Figure 1 The number and arrangement of components shown in FIG. are provided as examples. In practice, Figure 1 The communication system 100 may include additional components, fewer components, different components, or components arranged differently than those shown.

[0034] Figure 2 2 shows a communication system 200 according to one or more implementation methods. The communication system 200 includes a first IC 201 and a second IC 202. The first IC 201 may be a host device (such as a microcontroller) and may be combined with a Figure 1 The second IC 202 may be a slave device (such as a digital sensor) and may be combined with Figure 1 The description corresponds to the slave device 102 .

[0035] The second IC 202 may include a first clock source 204, a counter 206, and a first communication interface 208. The first clock source 204 may generate a first clock signal CLK1 to be monitored by the first IC 201. The counter 206 may receive the first clock signal CLK1 and increment or decrement a counter value (counter_val) stored in a counter register based on the first clock signal CLK1. The first communication interface 208 may be configured to receive the counter value (counter_val) from the counter 206 and transmit the counter value (counter_val) from the second IC 202 to the first IC 201 via a communication bus (e.g., an SPI bus).

[0036] The first IC 201 may include a second communication interface 210, a second clock source 212, a sampling circuit 214, and a clock monitoring circuit 216. The second communication interface 210 may be configured to receive a counter value from the second IC 202 via a communication bus. The second clock source 212 may generate a second clock signal CLK2 to be used for monitoring the first clock signal CLK1. The sampling circuit 214 may read (e.g., sample) two consecutive counter values ​​val[n-1] and val[n] within a timing time interval relevant to safety. In other words, the sampling circuit 214 may obtain a first sample val[n-1] of the counter value at a first sampling time, and obtain a second sample val[n] of the counter value at a second sampling time. In addition, the sampling circuit 214 may calculate a difference value t clksenor As the difference between the second sample val[n] and the first sample val[n-1]. The difference t clksenor is proportional to the period of the first clock signal CLK1 , or is proportional to the frequency of the first clock signal CLK1 .

[0037] The clock monitoring circuit 216 can monitor the first clock signal CLK1 based on the second clock signal CLK2. For example, the clock monitoring circuit 216 can monitor the difference t clksenor with the second clock signal CLK2 (eg, with the clock value t derived from the second clock signal CLK2). clkμc ) and if the difference t clksenor Deviation clock value t clkμc If a predetermined threshold safety_limit (eg a safety limit) is exceeded, a timing error signal ε is generated.

[0038] In some implementations, the first IC 201 may derive the clock value t using a fixed firmware schedule. clkμc For example, the clock monitoring circuit 216 may have information of a counter value (counter_val) read from the second IC 202 every N clock ticks of the second clock signal CLK2. Therefore, N or one value derived therefrom may be used for the clock value t clkμc The first IC 201 may include a timer module 218 (eg, a register) that stores a clock value t clkμc And the clock value t clkμc Provided to the clock monitoring circuit 216.

[0039] In some implementations, the timer module 218 may include a counter that counts the number of clock ticks of the second clock signal CLK2 that occur between two comparison events. The timer module 218 may provide the number of clock ticks of the second clock signal CLK2 that occur between two comparison events as the clock value t clkμ.

[0040] In some implementations, the timer module 218 may include a real-time clock driven by the second clock signal CLK2, and the real-time clock is used as the clock value t in each comparison event. clkμc is read out.

[0041] The clock monitoring circuit 216 may be configured to calculate another difference value (eg, t clksenor -t clkμc ) as the difference t clksenor and the clock value t derived from the second clock signal CLK2 clkμc The clock monitoring circuit 216 may be configured to: if the difference t clksenor does not deviate from the second clock signal CLK2 by more than a predetermined threshold safety_limit (for example, when the difference t clksenor There is no deviation from the clock value t clkμc When the predetermined threshold safety_limit is exceeded, it is determined that the first clock source 204 operates normally.

[0042] As indicated above, provide Figure 2 As an example. Other examples can be related to Figure 2 Different than described. Figure 2 The number and arrangement of components shown in FIG. are provided as examples. In practice, Figure 2 The communication system 200 may include additional components, fewer components, different components, or components arranged differently than those shown in FIG. Figure 2 Two or more components shown in may be implemented in a single component, or Figure 2 A single component shown in may be implemented as multiple distributed components.

[0043] Figure 3 1 shows a communication system 300 according to one or more implementation methods. The communication system 300 includes a first IC 301 and a second IC 302. The first IC 301 may be a host device (such as a microcontroller) and may be combined with a Figure 1 The second IC 302 may be a slave device (such as a digital sensor) and may be combined with Figure 1 The slave device 102 described corresponds.

[0044] The first IC 301 may include a communication interface module 304 for communicating with the second IC 302. For example, the communication interface module 304 may be an SPI communication interface module. The communication interface module 304 may include a communication clock generator 306 configured to generate a communication clock signal (e.g., an external clock signal SCK). Therefore, the communication clock generator 306 may be used as an external clock source for the second IC 302. The communication interface module 304 may also generate a communication frame signal (e.g., a CSN signal) indicating a communication frame, during which data communication between the IC and the first IC 301 and the second IC 302 is enabled. The communication interface module 304 may transmit the communication clock signal and the communication frame signal in parallel to the second IC 302. During an effective communication period, the first IC 301 may provide the external clock signal SCK to the second IC 302 to shift and sample data on the transmission line of the communication bus.

[0045] The fixed number of clock cycles of the external signal SCK per communication frame depends on the communication frame length (eg 32 clock cycles for a 32-bit communication frame). For example, each CSN frame is a predetermined number of SCK clock cycles, the frame length corresponding to the number of bytes of the SPI buffer.

[0046] The second IC 302 includes an internal clock source 308, a communication interface module 310, and a clock monitoring circuit 312. The internal clock source 308 is configured to generate an internal clock signal CLK. The internal clock signal CLK can be designed to be faster than the external clock signal SCK to support the communication transfer rate (e.g., SPI transfer rate). For example, the internal clock signal CLK can be designed to have multiple clock cycles (e.g., a target number n) for each clock cycle of the external clock signal SCK. targetclk The clock cycle, where n targetclk is an integer greater than 1). In other words, when the internal clock signal CLK operates normally, the frequency of the internal clock signal CLK can be n higher than the frequency of the external clock signal SCK. targetclk times. Therefore, the frequency ratio of the two frequencies may be intended to be fixed. In addition, the internal clock signal CLK may have a target number n per communication frame of the communication frame signal CSN. targetframe The target number n is a number of clock cycles (for example, because the external clock signal SCK has a fixed number of external clock cycles per communication frame). targetframe It can be n targetclk The external clock signal SCK can be used as an external clock source to generate the number n of internal clock pulses of the internal clock signal CLK per external clock cycle of the external clock signal SCK. clkCounting and / or calculating the number of internal clock pulses n of the internal clock signal CLK per communication frame of the communication frame signal CSN frame The internal clock signal CLK is monitored by counting.

[0047] The communication interface module 310 may receive the external clock signal SCK and the communication frame signal CSN in parallel from the first IC 301. The clock monitoring circuit 312 may monitor the internal clock signal CLK based on the external clock signal SCK and / or based on the communication frame signal CSN, thereby evaluating the functionality of the internal clock signal CLK. For example, the clock monitoring circuit 312 may include a processing circuit 314, which may be configured to compare the internal clock signal CLK and the external clock signal SCK during a communication frame, and generate a timing error signal if the frequency of the internal clock signal CLK does not meet a predetermined threshold (e.g., a safety limit) relative to the frequency of the external clock signal SCK.

[0048] In some implementations, the clock monitoring circuit 312 may include a first counter 316, a second counter 318, and a processing circuit 314. The first counter 316 may be configured to receive the internal clock signal CLK and generate a first counter value representing a first number of internal clock cycles of the internal clock signal CLK occurring during a first time interval. The second counter may be configured to receive the external clock signal SCK from the communication interface module 310 and generate a second counter value n SCK1 , which represents a first number of external clock cycles of the external clock signal SCK occurring during the first time interval.

[0049] In some implementations, the first counter value may be n clk The first time interval may be one external clock cycle (eg, a single external clock cycle) of the external clock signal SCK, and the second counter value n SCK1 can be 1. In some implementations, the first counter value can be n frame The first time interval may be a communication frame (eg, a single communication frame) of the communication frame signal CSN, and the second counter value n SCK1 It can be a predetermined number of SCK clock cycles in a communication frame. In some implementations, the two time intervals include an external clock cycle of the external clock signal SCK and a communication frame, and both can be used to monitor the internal clock signal CLK. Therefore, the first counter value can be n clk The first time interval may be an external clock cycle of the external clock signal SCK, and the second counter value n SCK1 can be 1, and the third counter value can be n frameThe second time interval may be a communication frame of the communication frame signal CSN, and the fourth counter value n SCK2 It may be a predetermined number of SCK clock cycles in one communication frame.

[0050] The clock monitoring circuit 312 may include a register storing a target count value including a target number n of clock cycles per external clock cycle. targetclk and the target number of clock cycles per communication frame n targetframe The processing circuit 314 may use the target count value to determine whether the frequency of the internal clock signal SCK satisfies a predetermined threshold relative to the frequency of the external clock signal SCK.

[0051] The processing circuit 314 may include at least one processor and / or other processing circuit device, which is used to determine whether the frequency of the internal clock signal SCK meets a predetermined threshold relative to the frequency of the external clock signal SCK. For example, the processing circuit 314 compares the first counter value n clk (or n frame ) and the second counter value n SCK1 The first comparison is performed by comparing the derived first measurement value with a first predetermined threshold. The first comparison can be sufficient to quantify the deviation of the frequency ratio of the frequency of the internal clock signal CLK to the frequency of the external clock signal SCK from a nominal ratio (e.g., from a desired ratio). If the first comparison indicates that the first measurement value exceeds the first predetermined threshold, the processing circuit 314 can generate a first timing error signal.

[0052] In some implementations, the processing circuit 314 may calculate the first counter value n clk (or n frame ) and the second counter value n SCK1 The processing circuit 314 may generate a first timing error signal if the first difference is equal to or greater than the first predetermined threshold.

[0053] In some implementations, the second counter 318 may generate a trigger signal at the end of the first time interval (e.g., at the end of each external clock cycle of the external clock signal SCK). The first counter 316 may be configured to receive the trigger signal and increase the first counter value n based on the trigger signal (e.g., in response to the trigger signal). clk (or n frame ) is output to the processing circuit 314.

[0054] In some implementations, the second counter 318 may generate a first trigger signal at the beginning of the first time interval and a second trigger signal at the end of the first time interval. Thus, the first counter 316 may receive a first trigger signal to start counting a first number of internal clock cycles of the internal clock signal CLK and receive a second trigger signal to stop counting the first number of internal clock cycles of the internal clock signal CLK. The first counter 316 may be configured to increment the first counter value n based on a second trigger signal (e.g., in response to receiving the second trigger signal). clk (or n frame ) is output to the processing circuit 314. In some implementations, the second counter 318 may be configured to receive the communication frame signal CSN, and when n frame When used as a first counter value, the second counter 318 may generate a first trigger signal at the beginning of a communication frame indicated by the communication frame signal CSN, and may generate a second trigger signal at the end of a communication frame indicated by the communication frame signal CSN.

[0055] In some implementations, the first counter 316 may be configured to receive an internal clock signal CLK and generate n clk as a first counter value representing a first number of internal clock cycles of the internal clock signal occurring during the first time interval, and generating n frame As a third counter value, it represents a second number of internal clock cycles of the internal clock signal occurring during the second time interval. Since the first time interval can be defined by a single external clock cycle of the external clock signal SCK, and the second time interval can be defined by a single communication frame of the communication frame signal CSN, the first time interval and the second time interval can have different durations. In addition, the second counter 318 can be configured to receive the external clock signal SCK, generate a second counter value n SCK1 , which represents a first number of external clock cycles of the external clock signal occurring during the first time interval, and generates a fourth counter value n SCK2 , which represents a second number of external clock cycles of the external clock signal SCK occurring during the second time interval.

[0056] The processing circuit 314 may be configured to process the frame and the fourth counter value n SCK2The derived second measurement value is compared with a second predetermined threshold value to perform a second comparison. The second comparison may be sufficient to quantify the deviation of the frequency ratio of the frequency of the internal clock signal CLK to the frequency of the external clock signal SCK from the nominal ratio. If the second comparison indicates that the second measurement value exceeds the second predetermined threshold value, the processing circuit 314 may generate a second timing error signal. In some implementations, the first predetermined threshold value may be less than the second predetermined threshold value. For example, in this example, since the first time interval is less than the second time interval, the error tolerance corresponding to the first predetermined threshold value may be less than the error tolerance corresponding to the second predetermined threshold value.

[0057] In some implementations, the first counter 316 may be configured to receive an internal clock signal CLK and generate a first counter value n. clk (or n frame ), which represents the number of internal clock cycles of the internal clock signal occurring during the time interval. The second counter 318 may be configured to receive the external clock signal SCK and generate a second counter value n SCK1 (or n SCK2 ), which represents the number of external clock cycles of the external clock signal SCK occurring during the time interval. The processing circuit 314 may be configured to convert the second counter value and the target counter value n targetclk (or n targetframe ) are multiplied to determine the product value, and the first counter value n is calculated. clk (or n frame ) and the product value, and if the ratio does not meet a first predetermined threshold, a timing error signal is generated.

[0058] In some implementations, the first counter 316 may be configured to receive an internal clock signal CLK and generate a counter value n. clk , which represents the number of internal clock cycles of the internal clock signal that occur during a single external clock cycle of the external clock signal SCK. The second counter 318 may be configured as a communication clock detector configured to determine the frequency of the external clock signal SCK. The processing circuit 314 may be configured to determine a ratio of the frequency of the external clock signal to the frequency of the internal clock source 308 and compare the ratio to the counter value n. clk The processing circuit 314 may generate a timing error signal if the product value does not meet a predetermined threshold. For example, if the product value is equal to or greater than a predetermined threshold, the processing circuit 314 may generate a timing error signal.

[0059] In some implementations, the first counter 316 may be configured to receive an internal clock signal CLK and generate a first counter value n. clk (or n frame), which represents the number of internal clock cycles of the internal clock signal occurring during the time interval. The second counter 318 may be configured to receive the external clock signal SCK and generate a second counter value n. SCK1 (or n SCK2 ), which represents the number of external clock cycles of the external clock signal occurring during the time interval. The communication interface module 310 may include a communication clock detector configured to determine the frequency of the external clock signal SCK. The processing circuit 314 may be configured to calculate the first counter value n clk (or n frame ) and the second counter value n SCK1 (or n SCK2 ), calculating a first ratio of the frequency of the external clock signal SCK and the frequency of the internal clock source 308, multiplying the first ratio by the second ratio to determine a product value, and generating a timing error signal if the product value does not meet a predetermined threshold. For example, if the product value is equal to or greater than the predetermined threshold, the processing circuit 314 may generate a timing error signal.

[0060] As indicated above, Figure 3 Other examples can be found in the Figure 3 Different than described. Figure 3 The number and arrangement of components shown in FIG. are provided as examples. In practice, Figure 3 The communication system 300 may include additional components, fewer components, different components, or differently arranged components compared to the components shown in FIG. Figure 3 Two or more components shown in FIG. 1 may be implemented in a single component, or in Figure 3 A single component shown in FIG. 1 may be implemented as multiple distributed components.

[0061] Figure 4A A signal diagram 400A shows a single external clock cycle of an external clock signal SCK according to one or more implementations. The internal clock signal CLK includes a first predefined number (eg, n) of external clock cycles of the external clock signal SCK. targetclk ) of the internal clock cycle. In this example, when the internal clock source (eg, internal clock source 308) operates as expected, in one external clock cycle T SCK The first predefined number of internal clock cycles is 7.

[0062] As indicated above, Figure 4A Other examples can be found in the Figure 4A Different than described.

[0063] Figure 4BA signal diagram 400B of a single communication frame of a communication frame signal CSN according to one or more implementations is shown. The external clock signal SCK includes a predefined number of external clock cycles N_SCK per communication frame of the communication frame signal CSN. The internal clock signal CLK includes a second predefined number (e.g., n_SCK) of cycles per communication frame of the communication frame signal CSN. targetframe ) internal clock cycles. In this example, when the internal clock source (eg, internal clock source 302) operates as expected, assuming a 32-bit communication frame and 7 internal clock cycles per external clock cycle, the first predefined number of internal clock cycles is 224 (ie, 7×32).

[0064] As indicated above, Figure 4B Other examples can be found in the Figure 4B Different than described.

[0065] Figure 5 5 is a diagram 500 illustrating example algorithms that may be used to monitor the internal clock source 308 according to one or more implementations. As described above, the processing circuit 314 may use one of the algorithms to monitor the internal clock signal CLK.

[0066] As indicated above, Figure 5 Other examples can be found in the Figure 5 Different than described.

[0067] Figure 6 6 shows a communication system 600 according to one or more implementation methods. The communication system 600 includes a first IC 601 and a second IC 602. The first IC 601 can be a host device (such as a microcontroller) and can be combined with Figure 1 The second IC 602 may be a slave device (such as a digital sensor) and may be combined with Figure 1 The description corresponds to the slave device 102 .

[0068] The second IC 602 may include a first clock source 604 and a first communication interface 606. The first clock source 604 may generate a first clock signal CLK1 to be monitored by the first IC 601. The first communication interface 606 may be a PWM communication interface configured to generate a PWM signal (e.g., a communication signal) encoded with sensor information or other data. For example, a pulse width or duty cycle of the PWM signal may be modulated based on sensor information to be transmitted to the first IC 601 by the first communication interface 606. For example, the second IC 602 may be an angle sensor, and the sensor information may be angle information measured by the angle sensor. The duty cycle of the PWM signal may be adjusted based on the measured angle so that the duty cycle of the PWM signal represents the measured angle.

[0069] In addition, the PWM period T of the PWM signal PWM In other words, for each PWM cycle, the PWM period T is defined PWM The time interval between two consecutive falling transition edges or two consecutive rising transition edges is fixed. PWM It can be proportional to the clock period of the first clock signal CLK1. For example, the PWM period T PWM The PWM period T may be a scaled version of the clock period of the first clock signal CLK1. For example, the first communication interface 606 may receive the first clock signal CLK1 and derive the PWM period T from the clock period of the first clock signal CLK1 by applying the scaling factor to the first clock signal CLK1 or to the clock period of the first clock signal CLK1. PWM In some implementations, the scaling factor may be an amplified scaling factor (eg, a scaling factor greater than 1) such that the PWM period T PWM is a multiple factor greater than the clock period of the first clock signal CLK1. Therefore, the PWM frequency of the PWM signal generated using the first clock signal CLK1 is a direct measurement of the clock frequency of the first clock signal CLK1. The first communication interface 606 can transmit the PWM signal to the first IC 610 via a communication bus (eg, a PWM bus).

[0070] The first IC 601 may include a second communication interface 608, a second clock source 610, a sampling circuit 612, a scaler 614, a clock monitoring circuit 616, and a timer module 618. The second communication interface 608 may be configured to receive a PWM signal from the second IC 602 via a communication bus. In some implementations, the sampling circuit 612 may be part of the second communication interface 608. The second clock source 610 may generate a second clock signal CLK2 for monitoring CLK1 of the first clock signal. The sampling circuit 612 (e.g., a PWM timer module) may read (e.g., sample) two consecutive falling edges of the PWM signal to determine a PWM period T of the PWM signal. PWM Alternatively, if the PWM period T PWM The sampling circuit 612 can read (eg, sample) two consecutive rising edges of the PWM signal to determine the PWM period T of the PWM signal. PWM Whether to use two consecutive falling edges or two consecutive rising edges to define the PWM period T PWM It could be a matter of design choice.

[0071] The scaler 614 (eg, a clock divider) may be configured to scale the PWM period T by a scaling factor PWM To derive the first clock value tclksenor , which represents the clock period of the first clock signal CLK. The scaling factor used by the scaler 614 may be the opposite value of the scaling factor used by the first communication interface 606. Therefore, the scaling factor used by the scaler 614 may be a reduction scaling factor (e.g., a scaling factor less than 1), which is inversely proportional to the magnification scaling factor of the first communication interface 606.

[0072] The clock monitoring circuit 616 may be configured to receive the first clock value t from the scaler 614. clksenor , and receiving a second clock value t derived from the second clock signal CLK clkμc , and perform the evaluation. For example, if the first clock value t clksenor Deviation from the second clock value t clkμc If the predetermined threshold safety_limit_1 is exceeded, the clock monitoring circuit 616 may generate a timing error signal ε1. For example, the clock monitoring circuit 616 may be configured to calculate the first clock value t clksenor With the second clock value t clkμc If the difference is greater than a predetermined threshold (i.e., ε1 = t clksenor -t clkμc >safety_limit_1), then the timing error signal ε1 is generated. Alternatively, the clock monitoring circuit 616 may be configured to: if the first clock value t clksenor There is no deviation from the second clock value t clkμc exceeds a predetermined threshold (ie, ε = t clksenor -t clkμc ≤safety_limit_1), the first clock source 604 is determined to be operating normally. Based on the determination that the first clock source 604 is operating normally, the clock monitoring circuit 616 may indicate that the first clock source 604 is operating normally (eg, by not generating the timing error signal ε1).

[0073] In some implementations, the first IC 601 may derive the second clock value t using a fixed firmware schedule. clkμc The first IC 601 may include a timer module 618 (eg, a register) that stores a second clock value t clkμc And the second clock value t clkμc Provided to the clock monitoring circuit 616. In some implementations, the timer module 618 may include a counter that counts the number of clock ticks of the second clock signal CLK2 that occur between the predetermined time intervals. The timer module 618 may provide the number of clock ticks of the second clock signal CLK2 that occur in the predetermined time interval as the second clock value t clkμcIn some implementations, the timer module 618 may include a real-time clock that is driven by the second clock signal CLK2 and that is read out as a clock value t at each sampling event of the sampling circuit 612. clkμc .

[0074] Clock monitoring inside the second IC 602 can be implemented only with low accuracy and limited diagnostic coverage (e.g., low results with high effort). Using the first IC 601 to perform external clock monitoring of the PWM frequency avoids complex implementation methods with reduced silicon area, reduced verification (processing) effort, and reduced test time. In addition, using the first IC 601 to perform external clock monitoring of the PWM frequency enables more accurate clock monitoring without adjusting or using redundant safety clocks by using the accurate quartz oscillator of the first IC 601 (e.g., the second clock source 610). Clock monitoring can be used as a safety measure to ensure detection of common cause failures.

[0075] As indicated above, Figure 6 Other examples can be found in the Figure 6 Different than described. Figure 6 The number and arrangement of components shown in FIG. are provided as examples. In practice, Figure 6 The communication system 600 may include additional components, fewer components, different components, or differently arranged components than those shown in FIG. Figure 6 Two or more components shown in may be implemented in a single component, or Figure 6 A single component shown in FIG. 1 may be implemented as multiple distributed components.

[0076] Figure 7 A communication system 700 is shown according to one or more implementation methods. The communication system 700 is similar to the one incorporating Figure 6 The communication system 600 described differs in that the communication system 700 comprises an additional interface for value monitoring and an additional monitoring circuit arrangement.

[0077] The second IC 702 may include a sensor module 703, a first clock source 704, and a first communication interface 706 and a second communication interface 720. The first clock source 704 may generate a first clock signal CLK1 to be monitored by the first IC 701, such as in combination with Figure 7As described. The sensor module 703 may generate sensor data X based on a sensed or measured property, such as a magnetic field or pressure. The first communication interface 706 may be a PWM communication interface configured to generate a first communication signal (e.g., a PWM signal) encoded with the sensor data X or other sensor information. For example, the pulse width or duty cycle of the first communication signal may be modulated based on the sensor data X to be transmitted to the first IC 701 by the first communication interface 706. The second communication interface 720 may be a second PWM communication interface, an incremental interface (ABZ), a Hall switch mode simulation interface (UVW), or any other analog or digital communication interface configured to generate a second communication signal encoded with the sensor data X or other sensor information. For example, the pulse transmitted on the ABZ interface may be modulated based on the sensor data X to be transmitted to the first IC 701 by the second communication interface 720.

[0078] The first communication signal may have a signal period based on the first clock signal CLK1. The first communication signal and the second communication signal may encode the same, redundant, or multiple sensor data. For example, the duty cycle of the first communication signal may encode the first sensor data X1, and the second communication signal may encode the same sensor data, redundant sensor data, or multiple sensor data X2 (e.g., second sensor data X2).

[0079] The first IC 701 may include a third communication interface 708, a second clock source 710, a sampling circuit 712, a scaler 714, a clock monitoring circuit 716, and a timer module 718, a fourth communication interface 711 (e.g., an interface module), and a value monitoring circuit 724. The third communication interface 708 may be configured to receive a first communication signal from the second IC 702 via a first communication bus (e.g., a PWM bus), and the fourth communication interface 722 may be configured to receive a second communication signal from the second IC 702 via a second communication bus. In some implementations, the sampling circuit 712 may be part of the third communication interface 708.

[0080] The second clock source 710, the sampling circuit 712, the scaler 714, the clock monitoring circuit 716, and the timer module 718 can operate in a manner similar to the second clock source 610, the sampling circuit 612, the scaler 614, the clock monitoring circuit 616, and the timer module 618 of the communication system 600, respectively. clksenor Deviation from the second clock value t clkμc If the first predetermined threshold safety_limit_1 is exceeded, the clock monitoring circuit 716 may generate a timing error signal ε1.

[0081] The sampling circuit 712 (eg, a PWM timer module) may read (eg, sample) two consecutive falling edges or two consecutive rising edges of the first PWM signal to determine the PWM period T of the first communication signal. PWM Alternatively, the sampling circuit 712 may determine a first pulse width of the first communication signal. Thus, the first communication signal represents a first value (eg, PWM period T PWM or pulse width), and the sampling circuit 712 can decode the first communication signal to determine the first value.

[0082] The fourth communication interface 722 (e.g., ABZ interface module) can read (e.g., sample) the second communication signal to determine a second value corresponding to the sensor data X2. The second value can be represented by the number of pulses, the relationship between pulses transmitted on different signal lines via the second communication signal, the serial binary code transmitted on the second communication signal, or the parallel binary code transmitted on the second communication signal.

[0083] The value monitoring circuit 724 may be configured to receive a first value corresponding to the first sensor data X1 and a second value corresponding to the second sensor data X2, compare the first value X1 and the second value X2, and generate a communication error signal ε2 if the first value X1 deviates from the second value X2 by more than a second predetermined threshold. For example, the value monitoring circuit 724 may be configured to calculate the difference between the first sensor reference X1 and the second sensor reference X2, and generate a communication error signal ε2 if the difference is greater than a second predetermined threshold safety_limit_2 (i.e., ε2=X1-X2>safety_limit_2).

[0084] Therefore, the first IC 701 can be used to perform both clock monitoring of the second IC 702 and value monitoring of the second IC 702 .

[0085] As indicated above, Figure 7 Other examples can be found in the Figure 7 Different than described. Figure 7 The number and arrangement of components shown in FIG. are provided as examples. In practice, Figure 7 The communication system 700 may include additional components, fewer components, different components, or differently arranged components than those shown in FIG. Figure 7 Two or more of the components shown in the figure may be implemented in a single component, or Figure 7 A single component shown in FIG. 1 may be implemented as multiple distributed components.

[0086] The following provides an overview of some aspects of the disclosure:

[0087] Aspect 1: A communication system, comprising: a first integrated circuit (IC), comprising: a first clock source, configured to generate a first clock signal; a counter, configured to receive the first clock signal and increment or decrement a counter value based on the first clock signal; and a first communication interface, configured to receive a counter value from the counter and transmit the counter value from the first IC; and a second IC, comprising: a second clock source, configured to generate a second clock signal; a sampling circuit, configured to obtain a first sample of the counter value at a first sampling time, obtain a second sample of the counter value at a second sampling time, and calculate a difference as the difference between the second sample and the first sample; and a clock monitoring circuit, configured to monitor the first clock signal based on the second clock signal, wherein the clock monitoring circuit is configured to compare the difference with the second clock signal, and generate a timing error signal if the difference deviates from the clock value derived from the second clock signal by more than a predetermined threshold.

[0088] Aspect 2: The communication system of Aspect 1, wherein the difference is proportional to the period of the first clock signal, or proportional to the frequency of the first clock signal.

[0089] Aspect 3: The communication system of any one of Aspects 1 to 2, wherein the clock monitoring circuit is configured to calculate another difference value as the difference between the difference value and a clock value derived from the second clock signal, and to generate a timing error signal if the another difference value does not meet a predetermined threshold.

[0090] Aspect 4: The communication system of any one of Aspects 1 to 3, wherein the clock monitoring circuit is configured to: determine that the first clock source is operating normally if the difference does not deviate from the clock value by more than a predetermined threshold.

[0091] Aspect 5: The communication system of any one of Aspects 1 to 4, wherein the first IC is integrated on a first semiconductor chip and the second IC is integrated on a second semiconductor chip.

[0092] Aspect 6: An integrated circuit (IC), comprising: an internal clock source, configured to generate an internal clock signal; a communication interface, configured to receive an external clock signal from an external clock source and a communication frame signal indicating a communication frame, during which data communication between the IC and the external clock source is enabled, wherein the external clock signal and the communication frame are received in parallel; and a clock monitoring circuit, configured to monitor the internal clock signal based on the external clock signal, wherein the clock monitoring circuit is configured to compare the internal clock signal and the external clock signal during the communication frame, and generate a timing error signal if the frequency of the internal clock signal does not meet a predetermined threshold relative to the frequency of the external clock signal.

[0093] Aspect 7: An IC of Aspect 6, wherein the predetermined threshold is a first predetermined threshold, and wherein the clock monitoring circuit comprises: a first counter configured to receive an internal clock signal and generate a first counter value representing a first number of internal clock cycles of the internal clock signal occurring during a first time interval; a second counter configured to receive an external clock signal and generate a second counter value representing a first number of external clock cycles of the external clock signal occurring during the first time interval; and a processing unit configured to perform a first comparison by comparing a first measurement value derived from the first counter value and the second counter value with a first predetermined threshold, wherein the first comparison is sufficient to quantify a deviation of a frequency ratio of the frequency of the internal clock signal to the frequency of the external clock signal from a nominal ratio, and wherein the processing unit is configured to: generate a first timing error signal if the first comparison indicates that the first measurement value exceeds the first predetermined threshold.

[0094] Aspect 8: The IC of Aspect 7, wherein the first time interval is defined by a single external clock cycle of the external clock signal.

[0095] Aspect 9: The IC of Aspect 7, wherein the first time interval is defined by a single communication frame of the communication frame signal.

[0096] Aspect 10: The IC of aspect 7, wherein the second counter is configured to generate a trigger signal at the end of the first time interval, and wherein the first counter is configured to receive the trigger signal and output the first counter value to the processing unit based on the trigger signal.

[0097] Aspect 11: An IC of Aspect 7, wherein the second counter is configured to generate a first trigger signal at the beginning of a first time interval and to generate a second trigger signal at the end of the first time interval, wherein the first counter is configured to receive the first trigger signal to start counting a first number of internal clock cycles of the internal clock signal and to receive the second trigger signal to stop counting the first number of internal clock cycles of the internal clock signal, and wherein the first counter is configured to output the first counter value to the processing unit based on the second trigger signal.

[0098] Aspect 12: The IC of Aspect 11, wherein the second counter is configured to receive a communication frame signal and generate a first trigger signal at the beginning of a communication frame indicated by the communication frame signal, and to generate a second trigger signal at the end of a communication frame indicated by the communication frame signal.

[0099] Aspect 13: An IC of Aspect 7, wherein the first counter is configured to receive an internal clock signal and generate a third counter value representing a second number of internal clock cycles of the internal clock signal occurring during a second time interval, wherein the first time interval and the second time interval have different durations, wherein the second counter is configured to receive an external clock signal and generate a fourth counter value representing a second number of external clock cycles of the external clock signal occurring during the second time interval, and the processing unit is configured to perform a second comparison by comparing a second measurement value derived from the third counter value and the fourth counter value with a second predetermined threshold, wherein the second comparison is sufficient to quantify a deviation of a frequency ratio of the frequency of the internal clock signal to the frequency of the external clock signal from a nominal ratio, and wherein the processing unit is configured to: generate a second timing error signal if the second comparison indicates that the second measurement value exceeds the second predetermined threshold.

[0100] Aspect 14: The IC of Aspect 13, wherein the first time interval is defined by a single external clock cycle of the external clock signal, and wherein the second time interval is defined by a single communication frame of the communication frame signal.

[0101] Aspect 15: The IC of Aspect 14, wherein the first predetermined threshold is less than the second predetermined threshold.

[0102] Aspect 16: An IC of Aspect 13, wherein the external clock signal includes a predefined number of external clock cycles per communication frame of the communication frame signal, and wherein, during normal operation of the internal clock source, the internal clock signal includes a first predefined number of internal clock cycles per external clock cycle of the external clock signal, and a second predefined number of internal clock cycles per communication frame of the communication frame signal.

[0103] Aspect 17: An IC of any one of Aspects 6 to 16, wherein the clock monitoring circuit includes: a first counter configured to receive an internal clock signal and generate a first counter value, which represents the number of internal clock cycles of the internal clock signal occurring during a time interval; a second counter configured to receive an external clock signal and generate a second counter value, which represents the number of external clock cycles of the external clock signal occurring during the time interval; and a processing circuit configured to multiply the second counter value with a target counter value to determine a product value, calculate a ratio of the first counter value to the product value, and generate a timing error signal if the ratio does not meet a predetermined threshold.

[0104] Aspect 18: An IC of any one of Aspects 6 to 17, wherein the clock monitoring circuit includes: a counter configured to receive an internal clock signal and to generate a counter value representing the number of internal clock cycles of the internal clock signal that occur during a single external clock cycle of the external clock signal; a communication clock detector configured to determine the frequency of the external clock signal; and a processing circuit configured to determine a ratio of the frequency of the external clock signal to a frequency of an internal clock source, multiply the ratio by the counter value to determine a product value, and generate a timing error signal if the product value does not meet a predetermined threshold.

[0105] Aspect 19: An IC of any one of Aspects 6 to 18, wherein the clock monitoring circuit includes: a first counter configured to receive an internal clock signal and generate a first counter value, which represents the number of internal clock cycles of the internal clock signal occurring during a time interval; a second counter configured to receive an external clock signal and generate a second counter value, which represents the number of external clock cycles of the external clock signal occurring during the time interval; a communication clock detector configured to determine the frequency of the external clock signal; and a processing circuit configured to calculate a first ratio of the first counter value and the second counter value, calculate a second ratio of the frequency of the external clock signal and the frequency of the internal clock source, multiply the first ratio by the second ratio to determine a product value, and generate a timing error signal if the product value does not meet a predetermined threshold.

[0106] Aspect 20: The IC of any one of Aspects 6 to 19, wherein the communication interface is a serial peripheral interface (SPI), the external clock signal is a SPI clock signal, and the communication frame signal is a chip select signal.

[0107] Aspect 21: The IC of any one of Aspects 6 to 20, wherein the external clock source is a microcontroller having an oscillator configured to generate the external clock signal.

[0108] Aspect 22: A method for monitoring an internal clock source of an integrated circuit (IC) using an external clock signal, the method comprising: generating an internal clock signal by an internal clock source; receiving an external clock signal from the external clock source by a communication interface of the IC; receiving a communication frame signal from the external clock source by the communication interface of the IC, wherein the communication frame signal indicates multiple communication frames, during which data communication between the IC and the external clock source is enabled, and wherein the external clock signal and the communication frame signal are received in parallel; and monitoring the internal clock signal based on the external clock signal by a clock monitoring circuit of the IC, comprising: comparing the internal clock signal and the external clock signal during multiple communication frames; and generating a timing error signal if the frequency of the internal clock signal does not meet a predetermined threshold relative to the frequency of the external clock signal, wherein monitoring of the internal clock signal is disabled outside multiple communication frames.

[0109] Aspect 23: A communication system, comprising: a first integrated circuit (IC), comprising: a first clock source, configured to generate a first clock signal; and a communication interface, configured to generate a communication signal and transmit the communication signal, the communication signal having a signal period proportional to a first clock period of the first clock signal; a second IC, comprising: a second clock source, configured to generate a second clock signal having a second clock period; a sampling circuit, configured to detect a transition edge of the communication signal to determine the signal period of the communication signal; a scaler, configured to scale the signal period using a first scaling factor to derive a first clock value, which represents the first clock period of the first clock signal; and a clock monitoring circuit, configured to monitor the first clock signal based on the second clock signal, wherein the clock monitoring circuit is configured to receive the first clock value from the scaler, and to generate a timing error signal if the first clock value deviates from the second clock value derived from the second clock signal by more than a predetermined threshold.

[0110] Aspect 24: The communication system of Aspect 23, wherein the communication interface is a pulse width modulation (PWM) interface, and the communication signal is a PWM signal.

[0111] Aspect 25: The communication system of any one of Aspects 23 to 24, wherein the second clock value represents a second clock period, and wherein the clock monitoring circuit is configured to calculate a difference between the first clock value and the second clock value, and to generate a timing error signal if the difference is greater than a predetermined threshold.

[0112] Aspect 26: The communication system of Aspect 25, wherein the second IC comprises a timer module configured to receive the second clock signal and derive a second clock value representing a second clock cycle from the second clock signal.

[0113] Aspect 27: The communication system of any one of Aspects 23 to 25, wherein the PWM communication interface is configured to scale the first clock period of the first clock signal using a second scaling factor to derive the PWM period, and wherein the second scaling factor is an inverse factor of the first scaling factor.

[0114] Aspect 28: The communication system of any one of Aspects 23 to 27, wherein the clock monitoring circuit is configured to: determine that the first clock source is operating normally if the first clock value does not deviate from the second clock value by more than a predetermined threshold.

[0115] Aspect 29: The communication system of any one of Aspects 23 to 28, wherein the first IC is integrated on a first semiconductor chip and the second IC is integrated on a second semiconductor chip.

[0116] Aspect 30: The communication system of Aspects 23 to 29, wherein the first communication signal represents a first value to be transmitted to the second IC, wherein the first IC includes a second communication interface configured to generate a second communication signal, the second communication signal represents a second value to be transmitted to the second IC, wherein the second IC includes a third communication interface and a fourth communication interface, the third communication interface is configured to receive the first communication signal and decode the first communication signal to obtain the first value, the fourth communication interface is configured to receive the second communication signal and decode the second communication signal to obtain the second value, and wherein the second IC includes a value monitoring circuit configured to compare the first value with the second value, and generate a communication error signal if the first value deviates from the second value by more than a second predetermined threshold.

[0117] Aspect 31: A communication system of Aspect 30, wherein the first value is represented by a first pulse width, duty cycle or signal period of the first communication signal, and the second value is represented by the number of pulses and the relationship between pulses transmitted on different signal lines via the second communication signal, a serial binary encoding on the second communication signal, or a parallel binary encoding on the second communication signal.

[0118] Aspect 32: A system configured to perform one or more operations recited in one or more of Aspects 1 to 31.

[0119] Aspect 33: An apparatus comprising means for performing one or more operations recited in one or more of Aspects 1 to 31.

[0120] Aspect 34: A non-transitory computer-readable medium for storing an instruction set, the instruction set comprising one or more instructions, which, when executed by a device, causes the device to perform one or more operations listed in one or more of aspects 1 to 31.

[0121] Aspect 35: A computer program product comprising instructions or codes for performing one or more operations recited in one or more of Aspects 1 to 31.

[0122] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation methods to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the implementation methods.

[0123] Some implementation methods may be described herein in conjunction with threshold values. As used herein, "satisfying" a threshold value may refer to being greater than a threshold value, more than a threshold value, higher than a threshold value, greater than or equal to a threshold value, less than a threshold value, less than a threshold value, lower than a threshold value, less than or equal to a threshold value, equal to a threshold value, etc.

[0124] As used herein, the term "component" is intended to be broadly interpreted as hardware, firmware, or a combination of hardware and software. The systems and / or methods described herein can be implemented in different forms of hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not limited by the implementation method. Therefore, the operation and behavior of the system and / or method are described herein without reference to specific software codes-it should be understood that software and hardware can be designed to implement the system and / or method based on the description of this article.

[0125] Any of the processing components may be implemented as a central processing unit (CPU) or other processors that read and execute software programs from a non-transient computer-readable recording medium (such as a hard disk or a semiconductor memory device). For example, instructions may be executed by one or more processors, such as one or more CPUs, digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field programmable logic arrays (FPLAs), programmable logic controllers (PLCs), or other equivalent integrated or discrete logic circuit devices. Therefore, the term "processor" used herein refers to any other structure of the aforementioned structure or an implementation method suitable for the technology described herein. The software may be stored on a non-transient computer-readable medium, so that the non-transient computer-readable medium includes a program code or a program algorithm stored thereon, and when the program code or program algorithm is executed, the processor is caused to perform the steps of the method via a computer program.

[0126] A controller including hardware may also perform one or more techniques of the present disclosure. A controller including one or more processors may use electrical signals and digital algorithms to perform its reception, analysis, and control functions, and may further include correction functions. The hardware, software, and firmware may be implemented in the same device or in separate devices to support the various techniques described in the present disclosure.

[0127] Signal processing circuitry and / or signal conditioning circuitry may receive one or more signals (e.g., measurement signals) in the form of raw measurement data from one or more components, and may derive further information from the measurement signals. As used herein, "signal conditioning" refers to manipulating an analog signal in some manner so that the signal meets the requirements of the next stage for further processing. Signal conditioning may include conversion from analog to digital (e.g., via an analog-to-digital converter), amplification, filtering, conversion, biasing, range matching, isolation, and any other process required to make the signal suitable for processing after conditioning.

[0128] Although specific combinations of features are listed in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of the implementation methods described herein. Many of these features can be combined in a manner that is not clearly listed in the claims and / or not disclosed in the specification. For example, the present disclosure includes a combination of each dependent claim in the claim set with each other independent claim in the claim set, and each combination of multiple claims in the claim set. As used herein, the phrase "at least one" in the list of items refers to any combination of these items, including a single member. For example, "at least one of a, b or c" is intended to cover a, b, c, a and b, a and c, b and c, and a, b and c, and any combination of multiple identical elements (e.g., a+a, a+a+a, a+a+b, a+a+c, a+b+b, a+c+c, b+b, b+b+b, b+b+c, c+c, and c+c+c, or any other order of a, b and c).

[0129] In addition, it should be understood that the disclosure of multiple behaviors or functions disclosed in the specification or in the claims may not be interpreted as being in a specific order. Therefore, the disclosure of multiple behaviors or functions will not limit them to a specific order unless the behaviors and functions are not interchangeable for technical reasons. In addition, in some implementations, a single behavior may include or may be decomposed into multiple sub-behaviors. Unless explicitly excluded, these sub-behaviors may be included and become part of the disclosure of a single behavior.

[0130] When a "component" or "one or more components" (or another element, such as a "controller" or "one or more controllers") is described or claimed (either within a single claim or across multiple claims) as performing or being configured to perform multiple operations, the language is intended to broadly cover a variety of structures and environments. For example, unless otherwise expressly claimed (e.g., via the use of "first component" and "second component" or other language that distinguishes components in the claims), the language is intended to cover a single component that performs or is configured to perform all operations, a group of components that collectively perform or are configured to perform all operations, a first component that performs or is configured to perform a first operation and a second component that performs or is configured to perform a second operation, or any combination of components that perform or are configured to perform operations. For example, when a claim has the form "one or more components configured to: perform X; perform Y; and perform Z," the claim should be interpreted as "one or more components configured to perform X; one or more (possibly different) components configured to perform Y; and one or more (possibly different) components configured to perform Z."

[0131] Elements, behaviors or instructions used herein should not be interpreted as key or necessary, unless so clearly described. In addition, as used herein, the articles "a" and "an" are intended to include one or more items and can be used interchangeably with "one or more". In addition, as used herein, the article "the" is intended to include one or more items quoted in conjunction with the article "the", and can be used interchangeably with "the one or more (the one or more)". When only referring to an item, the phrase "only one (only one)", "single (single)" or similar language is used. In addition, as used herein, the term "has", "have", "having (having)" or other similar expressions are intended to be open terms, and the elements modified by them are not limited (for example, "having" A elements can also have B). In addition, the phrase "based on" is intended to mean "based on at least in part", unless otherwise explicitly stated. As used herein, the term "multiple (multiple)" can be replaced by "a plurality of (a plurality of)" and vice versa. Furthermore, as used herein, the term "or" when used in a series is intended to be inclusive, and it can be used interchangeably with "and / or" unless expressly stated otherwise (e.g., if used in combination with "either" or "only one of").

Claims

1. A communication system, comprising: The first integrated circuit IC comprises: A first clock source is configured to generate a first clock signal; a counter configured to receive the first clock signal and to increment or decrement a counter value based on the first clock signal; and a first communication interface configured to receive the counter value from the counter and transmit the counter value from the first IC; and The second IC includes: A second clock source is configured to generate a second clock signal; a sampling circuit configured to obtain a first sample of the counter value at a first sampling time, obtain a second sample of the counter value at a second sampling time, and calculate a difference value as a difference between the second sample and the first sample; and A clock monitoring circuit is configured to monitor the first clock signal based on the second clock signal, wherein the clock monitoring circuit is configured to compare the difference with the second clock signal and generate a timing error signal if the difference deviates from a clock value derived from the second clock signal by more than a predetermined threshold. 2 . The communication system according to claim 1 , wherein the difference is proportional to a period of the first clock signal or proportional to a frequency of the first clock signal.

3. A communication system according to claim 1, wherein the clock monitoring circuit is configured to calculate another difference value as the difference between the difference value and the clock value derived from the second clock signal, and to generate the timing error signal if the another difference value does not meet the predetermined threshold. 4 . The communication system of claim 1 , wherein the clock monitoring circuit is configured to determine that the first clock source is operating normally if the difference value does not deviate from the clock value by more than the predetermined threshold. 5 . The communication system according to claim 1 , wherein the first IC is integrated on a first semiconductor chip and the second IC is integrated on a second semiconductor chip.

6. An integrated circuit IC, comprising: an internal clock source configured to generate an internal clock signal; a communication interface configured to receive an external clock signal from an external clock source and a communication frame signal indicating a communication frame, and enable data communication between the IC and the external clock source during the communication frame, wherein the external clock signal and the communication frame signal are received in parallel; as well as A clock monitoring circuit is configured to monitor the internal clock signal based on the external clock signal, wherein the clock monitoring circuit is configured to compare the internal clock signal and the external clock signal during the communication frame and generate a timing error signal if the frequency of the internal clock signal does not meet a predetermined threshold relative to the frequency of the external clock signal.

7. The IC of claim 6, wherein the predetermined threshold is a first predetermined threshold, and The clock monitoring circuit comprises: a first counter configured to receive the internal clock signal and generate a first counter value representing a first number of internal clock cycles of the internal clock signal occurring during a first time interval; a second counter configured to receive the external clock signal and generate a second counter value representing a first number of external clock cycles of the external clock signal that occurred during the first time interval; as well as a processing unit configured to perform a first comparison by comparing a first measurement value derived from the first counter value and the second counter value with the first predetermined threshold, wherein the first comparison is sufficient to quantify a deviation of a frequency ratio of the frequency of the internal clock signal to the frequency of the external clock signal from a nominal ratio, and wherein the processing unit is configured to generate a first timing error signal if the first comparison indicates that the first measurement value exceeds the first predetermined threshold.

8. The IC of claim 7, wherein the first time interval is defined by a single external clock cycle of the external clock signal.

9. The IC of claim 7, wherein the first time interval is defined by a single communication frame of the communication frame signal.

10. The IC of claim 7, wherein the second counter is configured to generate a trigger signal at the end of the first time interval, and The first counter is configured to receive the trigger signal and output the first counter value to the processing unit based on the trigger signal.

11. The IC of claim 7, wherein the second counter is configured to generate a first trigger signal at the beginning of the first time interval and to generate a second trigger signal at the end of the first time interval, wherein the first counter is configured to receive the first trigger signal to start counting the first number of internal clock cycles of the internal clock signal, and to receive the second trigger signal to stop counting the first number of internal clock cycles of the internal clock signal, and The first counter is configured to output the first counter value to the processing unit based on the second trigger signal.

12. The IC of claim 11 , wherein the second counter is configured to receive the communication frame signal, and to generate the first trigger signal at the beginning of the communication frame indicated by the communication frame signal, and to generate the second trigger signal at the end of the communication frame indicated by the communication frame signal.

13. The IC of claim 7 , wherein the first counter is configured to receive the internal clock signal and generate a third counter value, the third counter value representing a second number of internal clock cycles of the internal clock signal occurring during a second time interval, wherein the first time interval and the second time interval have different durations, wherein the second counter is configured to receive the external clock signal and generate a fourth counter value, the fourth counter value representing a second number of external clock cycles of the external clock signal occurring during the second time interval, and The processing unit is configured to perform a second comparison by comparing a second measurement value derived from the third counter value and the fourth counter value with a second predetermined threshold, wherein the second comparison is sufficient to quantify the deviation of the frequency ratio of the frequency of the internal clock signal to the frequency of the external clock signal from the nominal ratio, and wherein the processing unit is configured to: generate a second timing error signal if the second comparison indicates that the second measurement value exceeds the second predetermined threshold.

14. The IC of claim 13, wherein the first time interval is defined by a single external clock cycle of the external clock signal, and The second time interval is defined by a single communication frame of the communication frame signal. The IC of claim 14 , wherein the first predetermined threshold is less than the second predetermined threshold.

16. The IC of claim 13, wherein the external clock signal comprises a predefined number of external clock cycles per communication frame of the communication frame signal, and in, During normal operation of the internal clock source, the internal clock signal includes a first predefined number of internal clock cycles per external clock cycle of the external clock signal and a second predefined number of internal clock cycles per communication frame of the communication frame signal.

17. The IC of claim 6, wherein the clock monitoring circuit comprises: a first counter configured to receive the internal clock signal and generate a first counter value representing a number of internal clock cycles of the internal clock signal that occurred during a time interval; a second counter configured to receive the external clock signal and generate a second counter value representing a number of external clock cycles of the external clock signal that occurred during the time interval; as well as A processing unit is configured to multiply the second counter value and a target counter value to determine a product value, calculate a ratio of the first counter value to the product value, and generate the timing error signal if the ratio does not meet the predetermined threshold.

18. The IC of claim 6, wherein the clock monitoring circuit comprises: a counter configured to receive the internal clock signal and to generate a counter value representing a number of internal clock cycles of the internal clock signal that occur during a single external clock cycle of the external clock signal; a communication clock detector configured to determine a frequency of the external clock signal; as well as Processing circuitry is configured to determine a ratio of the frequency of the external clock signal to a frequency of the internal clock source, multiply the ratio by the counter value to determine a product value, and generate the timing error signal if the product value does not meet the predetermined threshold.

19. The IC of claim 6, wherein the clock monitoring circuit comprises: a first counter configured to receive the internal clock signal and generate a first counter value representing a number of internal clock cycles of the internal clock signal that occurred during a time interval; a second counter configured to receive the external clock signal and generate a second counter value representing a number of external clock cycles of the external clock signal that occurred during the time interval; a communication clock detector configured to determine a frequency of the external clock signal; as well as a processing circuit configured to calculate a first ratio of the first counter value to the second counter value, calculate a second ratio of the frequency of the external clock signal to the frequency of the internal clock source, multiply the first ratio by the second ratio to determine a product value, and generate the timing error signal if the product value does not meet the predetermined threshold.

20. The IC of claim 6, wherein the communication interface is a serial peripheral interface (SPI), the external clock signal is a SPI clock signal, and the communication frame signal is a chip select signal.

21. The IC of claim 6, wherein the external clock source is a microcontroller having an oscillator configured to generate the external clock signal.

22. A method for monitoring an internal clock source of an integrated circuit IC using an external clock signal, the method comprising: generating an internal clock signal from the internal clock source; Receiving the external clock signal from an external clock source by the communication interface of the IC; receiving, by the communication interface of the IC, a communication frame signal from the external clock source, wherein the communication frame signal indicates a plurality of communication frames during which data communication between the IC and the external clock source is enabled, and wherein the external clock signal and the communication frame signal are received in parallel; as well as Monitoring the internal clock signal based on the external clock signal by a clock monitoring circuit of the IC, comprising: comparing the internal clock signal and the external clock signal during the plurality of communication frames; as well as generating a timing error signal if the frequency of the internal clock signal does not meet a predetermined threshold relative to the frequency of the external clock signal, Wherein monitoring of the internal clock signal is disabled outside of the plurality of communication frames.

23. A communication system comprising: The first integrated circuit IC comprises: A first clock source configured to generate a first clock signal; and A first communication interface configured to generate a first communication signal and transmit the first communication signal, the first communication signal having a signal period proportional to a first clock period of the first clock signal; The second IC includes: A second clock source is configured to generate a second clock signal having a second clock period; a sampling circuit, configured to detect a switching edge of the first communication signal, thereby determining the signal period of the first communication signal; a scaler configured to scale the signal period by a first scaling factor to derive a first clock value, the first clock value representing the first clock period of the first clock signal; and A clock monitoring circuit is configured to monitor the first clock signal based on the second clock signal, wherein the clock monitoring circuit is configured to receive the first clock value from the scaler and generate a timing error signal if the first clock value deviates from a second clock value derived from the second clock signal by more than a first predetermined threshold.

24. The communication system of claim 23, wherein the communication interface is a pulse width modulation (PWM) interface, and the first communication signal is a PWM signal.

25. The communication system of claim 23, wherein the second clock value represents the second clock period, and The clock monitoring circuit is configured to calculate a difference between the first clock value and the second clock value and generate the timing error signal if the difference is greater than the first predetermined threshold. 26 . The communication system of claim 25 , wherein the second IC comprises a timer module configured to receive the second clock signal and derive the second clock value representing the second clock period from the second clock signal.

27. The communication system of claim 23, wherein the clock monitoring circuit is configured to determine that the first clock source is operating normally if the first clock value does not deviate from the second clock value by more than the first predetermined threshold.

28. The communication system of claim 23, wherein the first IC is integrated on a first semiconductor chip, and the second IC is integrated on a second semiconductor chip.

29. The communication system of claim 23, wherein the first communication signal represents a first value to be transmitted to the second IC, wherein the first IC includes a second communication interface, the second communication interface is configured to generate a second communication signal, the second communication signal representing a second value to be transmitted to the second IC, wherein the second IC comprises a third communication interface and a fourth communication interface, the third communication interface being configured to receive the first communication signal and decode the first communication signal to obtain the first value, the fourth communication interface being configured to receive the second communication signal and decode the second communication signal to obtain the second value, and Wherein the second IC includes a value monitoring circuit configured to compare the first value and the second value and generate a communication error signal if the first value deviates from the second value by more than a second predetermined threshold.

30. The communication system according to claim 29, wherein the first value is represented by a first pulse width, a duty cycle or the signal period of the first communication signal, and The second value is represented by a number of pulses and a relationship between pulses transmitted on different signal lines via the second communication signal, a serial binary encoding on the second communication signal, or a parallel binary encoding on the second communication signal.

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