Static time sequence statistical analysis system and method, computer equipment and storage medium

Abstract

The invention relates to the technical field of chips, and discloses a static time sequence statistical analysis system and method, computer equipment and a storage medium, and the system comprises a first processing module which is configured to obtain input data; determining a screening condition according to a condition threshold value in the input data, and determining a target time sequence path according to the screening condition; the second processing module is configured to perform target feature extraction on the target time sequence path to obtain a target extraction result, and write the target extraction result into a time sequence path feature source file; the third processing module is configured to determine feature data of a target time sequence path according to the time sequence path feature source file; the fourth processing module is configured to determine a violation time sequence path, generate a violation diagnosis report and determine a time sequence path optimization strategy; the fifth processing module is configured to generate a statistical distribution table and a statistical distribution map. According to the method, the logic features and the physical features of the time sequence paths can be automatically extracted on a large scale, the time sequence path optimization strategy is automatically generated, and a designer does not need to analyze the time sequence paths one by one.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a static timing statistical analysis system, method, computer equipment and storage medium. Background Art

[0002] In the field of chip design, timing analysis is an extremely critical technical link. Timing analysis ensures that the chip can work normally at the specified clock frequency. Timing analysis exists in various design processes including the front-end, mid-end, DFT and back-end. Conventional timing analysis methods require designers to analyze the causes of timing violations one by one according to the detailed report of the timing path, which is very inefficient. In addition, when the number of timing violations is large, designers can often only analyze a small number of paths with larger timing violations, and use the violation causes of this small number of paths as the violation causes of the entire timing path group. This analysis method cannot achieve batch analysis, and the analysis results are not comprehensive and accurate.

[0003] Therefore, there is an urgent need for a time series statistics method that can realize batch analysis and improve the comprehensiveness and accuracy of the analysis results. Summary of the invention

[0004] In view of this, the present invention provides a static timing statistical analysis system, method, computer device and storage medium to solve the problems of low efficiency, lack of comprehensiveness and low accuracy of timing statistical analysis in related technologies.

[0005] In a first aspect, the present invention provides a static timing statistics analysis system, the static timing statistics analysis system comprising:

[0006] A feature extraction subsystem and a statistical analysis subsystem; the feature extraction subsystem includes a first processing module and a second processing module; the statistical analysis subsystem includes a third processing module, a fourth processing module and a fifth processing module;

[0007] The first processing module is configured to obtain input data; the input data includes a target database and a condition threshold, the target database includes timing path information and physical location information stored in a corresponding relationship, the timing path information includes a timing path group and related information of the timing path group, and a timing path group includes multiple timing paths; when the input data is obtained, a screening condition is determined according to the condition threshold, and a target timing path is determined according to the screening condition, and the target timing path includes: a timing path in the target database that meets the screening condition;

[0008] The second processing module is configured to, when determining to obtain a target timing path according to the screening condition, perform target feature extraction on the target timing path to obtain a target extraction result, and when obtaining the target extraction result, write the target extraction result into a timing path feature source file; the target extraction result includes: a target logical feature, or a target logical feature and a target physical feature; the timing path feature source file includes a feature value of the target timing path;

[0009] The third processing module is configured to determine characteristic data of a target timing path according to the timing path characteristic source file;

[0010] The fourth processing module is configured to determine a violation timing path according to the characteristic data of the target timing path, generate a violation diagnosis report, and determine a timing path optimization strategy according to the violation diagnosis report;

[0011] The fifth processing module is configured to generate a statistical distribution table and a statistical distribution graph according to the characteristic data of the target timing path and the violation diagnosis report.

[0012] In an optional embodiment, when the conditional threshold includes a first quantity, a first threshold, a second threshold and a preset depth, the first processing module is specifically configured to determine a first condition based on the first quantity, determine a second condition based on the first threshold, and determine a third condition based on the second threshold; the first condition is that the total number of target timing paths is less than or equal to the first quantity, the second condition is that the maximum margin in the target timing path is less than or equal to the first threshold; the third condition is that the minimum margin in the target timing path is greater than or equal to the second threshold; the preset depth is used to divide the modules to which the starting point and end point of the target timing path belong.

[0013] In an optional embodiment, the second processing module includes a feature extraction unit; the feature extraction unit is configured to perform logical feature extraction on the target timing path to obtain a target logical feature, and perform physical feature extraction on the target timing path to obtain a target physical feature.

[0014] In an optional embodiment, the feature extraction unit is specifically configured to perform logical feature extraction on the target timing path to obtain a target logical feature, determine whether to perform physical feature extraction on the target timing path, and when determining to perform physical feature extraction on the target timing path, perform physical feature extraction on the target timing path to obtain a target physical feature.

[0015] In an optional embodiment, the fourth processing module includes a diagnostic report determination unit, which is configured to generate a violation diagnostic report based on the name of the target feature in the violation timing path, the feature data of the violation timing path, and the violation cause determined based on the feature data of the violation timing path.

[0016] In an optional embodiment, the fourth processing module also includes an optimization strategy determination unit, which is configured to read the violation diagnosis report, traverse the violation timing path, group the violation timing path according to the starting module and the end module, and obtain at least one violation timing path group, and for each violation timing path group, determine the violation cause corresponding to a single violation timing path group, and determine whether a preset condition is met according to the violation cause corresponding to the single violation timing path group, and when the violation cause corresponding to the single violation timing path group is determined to meet the preset condition, determine the timing path optimization strategy.

[0017] In an optional implementation, the statistical distribution table includes: a timing margin distribution table, a clock domain timing margin distribution table, a module timing margin distribution table, a path starting point timing margin distribution table, a level distribution table, a combinational logic level distribution table, a unit level delay distribution table, a unit distance delay distribution table, a path length distribution table, a path redundancy ratio distribution table, and a crosstalk delay distribution table;

[0018] The statistical distribution diagrams include: a timing margin distribution diagram, a timing margin cumulative distribution diagram, a level distribution diagram, a combinational logic level distribution diagram, a path group unit level delay distribution diagram, a path group unit distance delay distribution diagram, a unit level delay distribution diagram, a unit distance delay distribution diagram, a path length distribution diagram, a path redundancy ratio distribution diagram, a path group path redundancy ratio distribution diagram, a crosstalk delay distribution diagram, a path group crosstalk delay distribution diagram, a violation diagnosis distribution diagram, and a path group violation diagnosis distribution diagram.

[0019] In a second aspect, the present invention provides a static timing statistical analysis method, which is applied to the static timing statistical analysis system of the first aspect or any corresponding embodiment thereof, and the static timing statistical analysis method includes:

[0020] Acquire input data; the input data includes a target database and a condition threshold, the target database includes timing path information and physical location information stored in a corresponding relationship, the timing path information includes a timing path group and related information of the timing path group, and a timing path group includes multiple timing paths; when the input data is acquired, determine a screening condition according to the condition threshold, determine a target timing path according to the screening condition, and the target timing path includes: a timing path in the target database that meets the screening condition;

[0021] When the target timing path is determined according to the screening condition, target feature extraction is performed on the target timing path to obtain a target extraction result. When the target extraction result is obtained, the target extraction result is written into a timing path feature source file; the target extraction result includes: target logical features, or target logical features and target physical features; the timing path feature source file includes feature values ​​of the target timing path;

[0022] Determine characteristic data of a target timing path according to the timing path characteristic source file;

[0023] Determine the violation timing path according to the characteristic data of the target timing path, generate a violation diagnosis report, and determine the timing path optimization strategy according to the violation diagnosis report;

[0024] Generate statistical distribution tables and statistical distribution graphs based on the characteristic data of the target timing path and the violation diagnosis report.

[0025] In a third aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the static timing statistical analysis system of the above-mentioned second aspect or any corresponding embodiment thereof by executing the computer instructions.

[0026] In a fourth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the static timing statistical analysis system of the second aspect or any corresponding embodiment thereof.

[0027] In a fifth aspect, the present invention provides a computer program product, including computer instructions, which are used to enable a computer to execute the static timing statistical analysis system of the first aspect or any corresponding embodiment thereof.

[0028] The technical solution provided by the present invention has the following technical effects:

[0029] Based on the technical solution of the present invention, it is possible to realize the automated batch extraction of the logical features and physical features of the timing paths, which can greatly improve the efficiency of timing analysis, and provide a comprehensive data basis for the overall timing analysis of the entire design and the overall timing analysis of the timing path group. The present invention can automatically diagnose the causes of violations of a large number of timing paths. Compared with the conventional timing analysis method, the present invention does not require the designer to analyze the timing paths one by one. The automated diagnostic capability greatly improves the efficiency of timing analysis, and the analysis results are more comprehensive and reliable, thereby reducing the number of additional timing optimization iterations caused by the incomplete single analysis. The present invention can automatically generate a timing path optimization strategy for the designer's reference based on the violation causes of the timing path, which can improve the iteration speed of synthesis and physical design. The present invention can perform statistical analysis on a large number of specified timing paths from different dimensions through the automatically generated statistical distribution tables and statistical distribution graphs of a series of timing paths, which can comprehensively and quantitatively reflect the statistical distribution characteristics of the logical features and physical features of a large number of timing paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0031] Figure 1 It is a flowchart of the conventional timing analysis method;

[0032] Figure 2 is a structural block diagram of a static time series statistical analysis system according to an embodiment of the present invention;

[0033] Figure 3 is a structural block diagram of another static time series statistical analysis system according to an embodiment of the present invention;

[0034] Figure 4 is a schematic diagram of a timing path optimization process according to an embodiment of the present invention;

[0035] Figure 5 is a flow chart of a feature extraction subsystem of an embodiment of the present invention;

[0036] Figure 6 is a flow chart of a statistical analysis subsystem of an embodiment of the present invention;

[0037] Figure 7 is a flow chart of a static timing statistics analysis method according to an embodiment of the present invention;

[0038] Figure 8It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0040] like Figure 1 As shown in the figure, the conventional timing analysis method is usually divided into the following steps:

[0041] (1) Generate a timing violation summary report and a detailed report. The timing violation summary report usually contains information about the worst negative timing margin, the total negative timing margin, and the number of timing violation timing paths for the entire design, as well as information about the worst negative timing margin, the total negative timing margin, and the number of timing violation timing paths for each timing path group. Among them, grouping the timing paths for analysis is a common method in timing analysis, which means grouping the timing paths in the entire design according to the designer's preset rules, and analyzing each group of timing paths separately, thereby achieving the effect of refining the granularity of the timing analysis and making it easier for designers to find the timing bottlenecks in the entire design. The timing violation detailed report contains the specific path information of each timing path group.

[0042] (2) By analyzing the timing violation summary report, find the timing path group with the worst timing violation.

[0043] (3) Analyze the detailed report of the timing path group with the worst timing violations. When the number of timing path violations is large, the detailed report often contains thousands of timing path information. Designers often only analyze a small number of paths with large timing violations to find out the causes of their timing violations.

[0044] (4) Adjust the timing optimization strategy based on the timing violation causes analyzed in step 3.

[0045] Conventional timing analysis methods require designers to analyze the causes of timing violations one by one based on the detailed reports of the timing paths, which is very inefficient. Moreover, when there are many timing violations, designers can only analyze a small number of paths with large timing violations, and use the violation causes of this small number of paths as the violation causes of the entire timing path group. This analysis method cannot achieve batch analysis, and the analysis results are not comprehensive and accurate.

[0046] The main disadvantages of conventional timing analysis methods are as follows:

[0047] 1) Conventional timing analysis methods require designers to analyze the causes of timing violations one by one based on the detailed report of the timing path, which is very inefficient. Moreover, when there are many timing violations, designers can only analyze a small number of paths with large timing violations, and use the violation causes of this small number of paths as the violation causes of the entire timing path group. This analysis method cannot achieve batch analysis, and the analysis results are not comprehensive and accurate.

[0048] 2) Although the timing path detailed report contains detailed information about each timing path violation, the timing path detailed report cannot intuitively reflect the distribution characteristics of the timing violations. Therefore, it is difficult for designers to grasp the overall timing distribution of the entire module or path group through the timing path detailed report.

[0049] 3) Timing violation summary reports and detailed reports usually only contain information about the timing paths that violated the rules. However, the distribution of timing paths with positive timing margins is also worth paying attention to. Designers can find opportunities to further optimize the design frequency, area, and power consumption through the distribution of timing paths with positive timing margins.

[0050] Therefore, the embodiments of the present invention provide a static timing statistics analysis system, method, computer device and storage medium to solve the above problems.

[0051] In the present invention, a static timing statistics analysis system is provided, which is used to implement the following embodiments and optional implementation methods. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the system described in the following embodiments is preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0052] Figure 2 It is a structural block diagram of a static timing statistics analysis system according to an embodiment of the present invention.

[0053] like Figure 2 As shown, an embodiment of the present invention provides a static timing statistics analysis system, and the static timing statistics analysis system includes:

[0054] Feature extraction subsystem 1111 and statistical analysis subsystem 1212. Feature extraction subsystem 1111 includes a first processing module 111111 and a second processing module 112112. Statistical analysis subsystem 1212 includes a third processing module 121121, a fourth processing module 122122 and a fifth processing module 123123.

[0055] The first processing module 111 is configured to obtain input data. The input data includes a target database and a condition threshold, the target database includes timing path information and physical location information stored in a corresponding relationship, the timing path information includes a timing path group and related information of the timing path group, and a timing path group includes multiple timing paths. When the input data is obtained, a screening condition is determined according to the condition threshold, and a target timing path is determined according to the screening condition. The target timing path includes: a timing path in the target database that meets the screening condition.

[0056] The second processing module 112 is configured to extract target features from the target timing path to obtain a target extraction result when the target timing path is determined to be obtained according to the screening condition, and write the target extraction result into the timing path feature source file when the target extraction result is obtained. The target extraction result includes: target logical features, or target logical features and target physical features. The timing path feature source file includes feature values ​​of the target timing path.

[0057] The third processing module 121 is configured to determine characteristic data of a target timing path according to the timing path characteristic source file.

[0058] The fourth processing module 122 is configured to determine a violation timing path according to the characteristic data of the target timing path, generate a violation diagnosis report, and determine a timing path optimization strategy according to the violation diagnosis report.

[0059] The fifth processing module 123 is configured to generate a statistical distribution table and a statistical distribution graph according to the characteristic data of the target timing path and the violation diagnosis report.

[0060] For the first processing module 111:

[0061] The first processing module 111 is configured to obtain input data. The input data includes a target database and a condition threshold. The target database includes timing path information and physical location information stored in a corresponding relationship. The timing path information includes a timing path group and related information of the timing path group. A timing path group includes multiple timing paths. When the input data is obtained, the screening condition is determined according to the condition threshold, and the target timing path is determined according to the screening condition. The target timing path includes: the timing path in the target database that meets the screening condition. The related information of the timing path group includes necessary information for timing analysis such as parasitic resistance and capacitance values ​​and timing constraints.

[0062] In this embodiment, the target database is the input of the static timing statistical analysis system of the present invention. The static timing statistical analysis system can be applied to each stage in the middle and back-end design process, supports the database of each stage as input, and can use the database of each stage in the middle and back-end design process as the target database. The middle and back-end design process includes a synthesis stage, a physical design stage, and a timing analysis stage. In the synthesis stage, the database of the comprehensive EDA tool can be used as input, and commonly used comprehensive EDA tools include GENUS, DC, etc. In the physical design stage, the database of the physical design EDA tool can be used as input, and commonly used physical design tools include INNOVUS, ICC2, etc. In the timing analysis stage, the database of the timing analysis EDA tool can be used as input, and commonly used timing analysis tools include PrimeTime, Tempus, etc.

[0063] In this embodiment, when the conditional threshold includes a first quantity, a first threshold, a second threshold, and a preset depth, the first processing module 111 is specifically configured to determine the first condition according to the first quantity, determine the second condition according to the first threshold, and determine the third condition according to the second threshold. The first condition is that the sum of the number of target timing paths is less than or equal to the first quantity, and the second condition is that the maximum margin in the target timing path is less than or equal to the first threshold. The third condition is that the minimum margin in the target timing path is greater than or equal to the second threshold. The preset depth is used to divide the modules to which the starting point and end point of the target timing path belong.

[0064] In this embodiment, the first number: the maximum number of timing paths. The designer can set and modify the upper limit of the number of timing paths according to actual needs to perform feature extraction of the timing paths. As an example, the default upper limit value is 1000000. The sum of the number of corresponding target timing paths is less than or equal to 1000000, indicating that feature extraction is performed on a maximum of 1000000 timing paths. The first threshold: the maximum margin of the timing path. The designer can set and modify the maximum margin of the timing path according to actual needs to limit the timing paths involved in feature extraction. The default value is 0. The second threshold: the minimum margin of the timing path. The designer can set and modify the minimum margin of the timing path according to actual needs to limit the timing paths involved in feature extraction. The first threshold and the second threshold refer to slack values. Preset depth: logic module depth. The preset depth is used to divide the modules to which the starting point and end point of the timing path belong, and determine the granularity of the module division. The larger the preset depth, the finer the granularity of the module division.

[0065] In this embodiment, the user or designer can set different condition thresholds according to actual needs, and input the condition thresholds into the static timing statistical analysis system. The first processing module 111 can obtain input data according to the input of the user or designer. Specifically, data input can be implemented through a visual interface, and input can be implemented by importing a table or filling in the condition threshold in the visual interface.

[0066] In this embodiment, the first processing module 111 can perform timing path screening. When the input data is obtained, it automatically traverses the target database according to the screening conditions (the first condition corresponding to the first quantity, the second condition corresponding to the first threshold, the third condition corresponding to the second threshold, and the preset depth) to screen out the target timing paths in the target database that meet the screening conditions.

[0067] For the second processing module 112:

[0068] The second processing module 112 is configured to extract target features from the target timing path to obtain a target extraction result when the target timing path is determined to be obtained according to the screening condition, and write the target extraction result into the timing path feature source file when the target extraction result is obtained. The target extraction result includes: target logical features, or target logical features and target physical features. The timing path feature source file includes feature values ​​of the target timing path.

[0069] like Figure 3 As shown, in the present invention, the second processing module 112 includes a feature extraction unit 1121. The feature extraction unit 1121 is configured to extract logical features from the target timing path to obtain target logical features, and to extract physical features from the target timing path to obtain target physical features.

[0070] The feature extraction unit 1121 is specifically configured to perform logical feature extraction on the target timing path to obtain the target logical feature, determine whether to perform physical feature extraction on the target timing path, and when it is determined to perform physical feature extraction on the target timing path, perform physical feature extraction on the target timing path to obtain the target physical feature.

[0071] If the static timing statistical analysis system does not need to perform physical feature extraction, the target database only includes timing path information but not physical location information. The corresponding feature extraction unit 1121 does not need to determine whether to perform physical feature extraction on the target timing path, and does not need to perform physical feature extraction on the target timing path to obtain the target physical feature.

[0072] In this embodiment, the target extraction result specifically includes the target logical feature, or the target logical feature and the target physical feature. The feature extraction unit 1121 includes a logical feature extraction subunit (specifically a logical feature extractor) and a physical feature extraction subunit (specifically a physical feature extractor). The logical feature extraction subunit can be specifically a logical feature extractor. The logical feature extractor automatically extracts the logical features of the target timing path screened by the first processing module 111 to obtain the target logical feature. The extracted target logic features include the timing margin corresponding to each target timing path, the previous stage timing margin, the next stage timing margin, the number of data path levels, the number of data path combinational logic levels, the data path delay, the data path crosstalk delay, the data path unit delay, the data path line delay, the data path unit level delay, the starting clock, the end clock, the clock skew, the starting clock delay, the end clock delay, the clock path pessimism removal value, the timing path starting point, the timing path end point, the timing path starting point module, the timing path end point module, the timing path group to which the timing path belongs, the mode and process corner to which the timing path belongs, the timing path check synchronization and asynchronous type, the timing path end point setup time / hold time and additional constraints on the timing path, etc.

[0073] In this embodiment, the designer can control whether the feature extraction subsystem 11 performs physical feature extraction on the target timing path as needed. When it is determined that the physical feature extraction is performed on the target timing path, the physical feature extraction subunit is started, and the physical feature extraction subunit is configured to perform physical feature extraction on the target timing path to obtain the target physical feature after the physical feature extraction subunit is started. The extracted target physical features include the Manhattan distance between the start point and the end point of the target timing path, the cumulative Manhattan distance of the target timing path, etc.

[0074] In the present invention, the second processing module 112 further includes a source file generating unit 1122, which is configured to write the target extraction result into the timing path feature source file when the target extraction result is obtained, thereby realizing the automatic generation of the timing path feature source file. As an example, the timing path feature source file adopts the CSV format, and the timing path feature source file contains the feature values ​​of each feature of all analyzed timing paths.

[0075] For the third processing module 121:

[0076] The third processing module 121 is configured to determine characteristic data of a target timing path according to the timing path characteristic source file.

[0077] In this embodiment, the third processing module 121 is specifically configured to read the timing path feature source file, read the timing path feature source file into the memory, and generate a two-dimensional data structure. As an example, the two-dimensional data structure is a matrix. Other characteristic values ​​are calculated based on the characteristic values ​​of each target timing path in the timing path feature source file, including the number of driver units of the data path, the data path redundancy ratio, the average delay per unit level, the average delay per unit distance, etc. The characteristic data of the complete target timing path are summarized in the memory based on the characteristic values ​​of the target timing path and the other characteristic values ​​inferred.

[0078] The fourth processing module 122 is configured to determine a violation timing path according to the characteristic data of the target timing path, generate a violation diagnosis report, and determine a timing path optimization strategy according to the violation diagnosis report.

[0079] like Figure 3 As shown, in the present invention, the fourth processing module 122 includes a diagnostic report determination unit 1221, which is configured to generate a violation diagnostic report based on the name of the target feature in the violation timing path, the feature data of the violation timing path, and the violation cause determined based on the feature data of the violation timing path.

[0080] The diagnostic report determination unit 1221 automatically writes the violation timing path in the memory into the violation diagnostic report. The present invention can use an Excel file as the violation diagnostic report format. The first line of the violation diagnostic report is the name of each feature, including the features in the feature source file, the inferred features, and the cause of the violation. Starting from the second line, the violation diagnostic report is the feature values ​​corresponding to each violation timing path. The feature name row automatically has a filtering function, which supports filtering and viewing of one or more columns of features, making it convenient for designers to perform more detailed timing analysis.

[0081] In this embodiment, the diagnostic report determination unit 1221 is further configured to perform violation diagnosis in batches according to the characteristic data of the target timing path based on the automatic diagnosis rule to determine the violation timing path. Specifically, a timing path violation diagnostic device can be developed according to the automatic diagnosis rule. The timing path violation diagnostic device is used to perform diagnosis and determine the violation timing path.

[0082] Considering that static timing analysis is to analyze all possible timing paths in the circuit, calculate signal propagation delays, and check whether they meet the timing constraints. Among various timing constraints, setup time and hold time are usually the most concerned by chip designers. As an example, the "virtual optimization weighted algorithm" can be used to diagnose violations of setup time and hold time. The rules for automatic diagnosis of setup time and hold time are as follows:

[0083] For setup time violation diagnosis, first calculate the virtual optimization condition trigger value based on the characteristic data of each target timing path, and use the virtual optimization condition trigger value to determine whether the characteristic is a potential violation cause. Finally, calculate the virtual optimization timing margin for each potential violation cause. The specific calculation method is as follows:

[0084] For combinational logic level diagnosis:

[0085] Virtual optimization condition trigger value calculation formula: k1 = L combo -Lth combo .

[0086] Among them, k1 represents the virtual optimization condition trigger value during the diagnosis of the combinational logic level, L combo Indicates the combinational logic level, Lth combo Indicates the preset combinational logic level threshold. When k1>0, virtual optimization calculation is triggered.

[0087] Virtual optimization timing margin calculation formula: Δ 1slack =D avg *k1*ε1.

[0088] Among them, Δ 1slack Denotes the virtual optimized timing margin, D avg It represents the average delay per level of the current timing path, and ε1 represents the virtual optimization weight coefficient of the combinational logic level.

[0089] For drive unit level diagnosis:

[0090] Virtual optimization condition trigger value calculation formula: k2 = L repeater -Lth repeater .

[0091] Where k2 represents the trigger value of the virtual optimization condition during the diagnosis of the drive unit level, L repeater Indicates the number of drive units, Lth repeater Indicates the preset drive unit level threshold. When k2>0, virtual optimization calculation is triggered.

[0092] Virtual optimization timing margin calculation formula: Δ 2slack =D avg *k2*ε2.

[0093] Among them, Δ 2slack Denotes the virtual optimized timing margin, D avg It represents the average per-stage delay of the current timing path, and ε2 represents the virtual optimization weight coefficient of the number of driving units.

[0094] For unit level delay diagnosis:

[0095] Virtual optimization condition trigger value calculation formula: k3 = Davg -Dth avg .

[0096] Among them, k3 represents the virtual optimization condition trigger value when the unit level delay diagnosis is performed, and D avg Indicates the average delay per stage of the current timing path, Dth avg Indicates the preset unit level delay threshold. When k3>0, virtual optimization calculation is triggered.

[0097] Virtual optimization timing margin calculation formula: Δ 3slack =k3*L*ε3.

[0098] Among them, Δ 3slack represents the virtual optimization timing margin, L represents the number of levels of the current data path, and ε3 represents the virtual optimization weight coefficient of unit level delay.

[0099] For crosstalk delay diagnosis:

[0100] Virtual optimization condition trigger value calculation formula: k4 = D si -D path *α th .

[0101] Among them, k4 represents the virtual optimization condition trigger value during crosstalk delay diagnosis, D si Denotes the total crosstalk delay of the current data path, D path represents the total delay of the current data path, α th Indicates the preset crosstalk threshold ratio. When k4>0, the virtual optimization calculation is triggered.

[0102] Virtual optimization timing margin calculation formula: Δ 4slack =k4*ε4.

[0103] Among them, Δ 4slack represents the virtual optimization timing margin, and ε4 represents the virtual optimization weight coefficient of the crosstalk delay.

[0104] For data path verbosity diagnostics:

[0105] Virtual optimization condition trigger value calculation formula: k5 = P ac -P se *β th .

[0106] Among them, k5 represents the virtual optimization condition trigger value during data path lengthy diagnosis, P ac Indicates the current data path cumulative Manhattan distance, P se Indicates the Manhattan distance between the starting point and the end point of the current time series path, β th Indicates the preset path length threshold ratio. When k5>0, virtual optimization calculation is triggered.

[0107] Virtual optimization timing margin calculation formula: Δ 5slack =k5*D avgd *ε5.

[0108] Among them, Δ 5slack Denotes the virtual optimized timing margin, D avgd It represents the delay per unit distance of the current data path, and ε5 represents the virtual optimization weight coefficient of the lengthy data path.

[0109] For setup time diagnostics:

[0110] Virtual optimization condition trigger value calculation formula: k6 = T setup -T th .

[0111] Where k6 represents the trigger value of the virtual optimization condition when establishing time diagnosis, T setup Indicates the setup time of the current timing path endpoint, T th Indicates the preset establishment time threshold. When k6>0, virtual optimization calculation is triggered.

[0112] Virtual optimization timing margin calculation formula: Δ 6slack =k6*ε6.

[0113] Among them, Δ 6slack represents the virtual optimization timing margin, and ε6 represents the virtual optimization weight coefficient of the setup time.

[0114] For additional constraint diagnostics:

[0115] Virtual optimization condition trigger value calculation formula: k7 = CC th .

[0116] Among them, k7 represents the virtual optimization condition trigger value during additional constraint diagnosis, C represents the additional constraint value of the current timing path, and C th Indicates the preset additional constraint threshold. When k7>0, the virtual optimization calculation is triggered.

[0117] Virtual optimization timing margin calculation formula: Δ 7slack =k7*ε7.

[0118] Among them, Δ 7slack represents the virtual optimization timing margin, and ε7 represents the virtual optimization weight coefficient of the additional constraints.

[0119] For clock skew diagnosis:

[0120] Virtual optimization condition trigger value calculation formula: k8 = SS th .

[0121] Where k8 represents the virtual optimization condition trigger value during clock skew diagnosis, S represents the clock skew value of the current timing path, and S th Indicates the preset clock skew threshold. When k8>0, virtual optimization calculation is triggered.

[0122] Virtual optimization timing margin calculation formula: Δ 8slack =min(k8,(M+N)*τ)*ε8.

[0123] Among them, Δ 8slack represents the virtual optimized timing margin, M represents the positive timing margin of the next-level timing path of the current timing path, N represents the positive timing margin of the previous-level timing path of the current timing path, τ represents the system's built-in timing margin coefficient, and ε8 represents the virtual optimization weight coefficient of clock skew.

[0124] According to the type of input database and the type of diagnosed features, the system automatically adapts the appropriate virtual optimization weight coefficient for each feature, as shown in Table 1.

[0125] Table 1 Virtual optimization weight coefficient ε value

[0126] comprehensive Physical Design Timing Analysis Combinational Logic Levels 0.9 0.8 0.4 Drive unit level 0.6 0.9 0.6 Unit level delay 0.7 0.8 0.8 Crosstalk Delay N / A 0.7 0.8 Long data path 0.5 0.9 0.6 Build Time 0.7 0.6 0.8 Additional constraints 0.3 0.3 0.7 Clock skew N / A 0.8 0.8

[0127] After calculating the virtual optimization timing margin of each feature that triggers virtual optimization, the system automatically finds the timing violation cause corresponding to the largest virtual optimization timing margin as the main violation cause of the violating timing path. At the same time, the system automatically adds a "violation cause" feature to the violating timing path and uses the specific cause of the violation as the feature value of the feature.

[0128] For the fourth processing module 122:

[0129] The fourth processing module 122 also includes an optimization strategy determination unit 1222, which is configured to read the violation diagnosis report, traverse the violation timing path, group the violation timing path according to the starting module and the end module, obtain at least one violation timing path group, determine the violation cause corresponding to the single violation timing path group for each violation timing path group, determine whether the preset condition is met according to the violation cause corresponding to the single violation timing path group, and determine the timing path optimization strategy when the violation cause corresponding to the single violation timing path group is determined to meet the preset condition. The timing path optimization strategy is used for further comprehensive optimization or physical design optimization.

[0130] The optimization strategy determination unit 1222 can be configured to automatically traverse all violation timing paths. The preset conditions include: querying the violation cause of the violation timing path group through the timing path optimization solution comparison table shown in Table 2 to trigger the preset optimization strategy, and the absolute value of the worst negative timing margin of the violation timing path group is less than the clock cycle (timing constraint) involved in the violation. If the violation cause corresponding to the violation timing path group is determined to meet the preset conditions, a timing path optimization strategy is generated, including setting a high optimization intensity and an appropriate optimization weight for the violation timing path group. The calculation formula of the optimization weight is as follows: ω=10-[T worst / 0.015].

[0131] Among them, T worst is the worst negative slack of the group of violating timing paths.

[0132] If the absolute value of the worst negative timing margin of the violation timing path group is not less than the clock cycle involved in the violation, the system will list the violation timing paths and prompt the designer that the negative timing margin of the violation timing path is too large, and the designer needs to pay attention to whether there are unreasonable timing constraints and other reasons.

[0133] After generating a timing path optimization strategy corresponding to a timing path group that violates the rule, the optimization strategy determination unit 1222 can also generate timing path optimization strategies corresponding to other timing path groups that violate the rule according to Table 2 for each timing path that violates the rule in the group. The specific scheme is as follows:

[0134] Reduce timing over-limit: Based on the current additional constraints of the timing violation path, the system automatically calculates the optimized additional constraint value. The additional constraint reduction calculation formula is as follows: Δ c =CC th .

[0135] Among them, C and C th They are the additional constraint value of the current timing path and the preset additional constraint threshold.

[0136] Optimize clock skew: Based on the current negative timing margin of the violating timing path and the timing margins of its predecessor and successor stages, the system automatically calculates the optimization amount of the path start and end clock paths. The optimization calculation formula for the end clock path is as follows: Φ e =min(|T slack |, M*τ).

[0137] Wherein, M is the positive timing margin of the next-level timing path of the current timing path, and τ is the timing margin coefficient built into the system.

[0138] When |T slack When |>M*τ, the system continues to calculate the optimization amount of the starting point clock path. The calculation formula is as follows:

[0139] Φ s =min(|T slack |-M*τ, N*τ).

[0140] Wherein, N is the positive timing margin of the previous-level timing path of the current timing path.

[0141] Optimize conversion time: When the violation reason is unit-order delay, crosstalk delay or setup time, the system prompts the designer to focus on the optimization of conversion time and summarizes the violation timing paths that need conversion time optimization.

[0142] Timing path overrun: This optimization solution is usually used to solve the timing consistency problem between different design stages and different tools. The system automatically generates a timing path overrun script based on the negative timing margin of the current timing path. The calculation formula for the overrun value is as follows: δ = T r -T slack .

[0143] Among them, T r represents the timing margin of the current path in the implementation tool, T slack Indicates the timing margin of the current path.

[0144] Table 2 Timing Path Optimization Scheme Comparison Table

[0145]

[0146] As shown in Table 2, the system's built-in preset optimization strategies are mainly divided into five categories: optimizing timing path groups, timing path over-limit, reducing timing over-limit, optimizing clock skew, and optimizing conversion time. Among them, when the violation cause is one of the combinational logic level, the driver unit level, the unit level delay, the crosstalk delay, and the data path redundancy, the generation of the scheme for optimizing the timing path group and the timing path over-limit will be triggered. When the violation cause is additional constraints, the generation of the scheme for reducing timing over-limit will be triggered. When the violation cause is clock skew, the generation of the scheme for optimizing clock skew will be triggered. When the violation cause is one of the unit level delay, crosstalk delay, and setup time, the generation of the scheme for optimizing conversion time will be triggered.

[0147] like Figure 4As shown, the optimization strategy determination unit first reads the violation diagnosis report, automatically traverses all violation timing paths and groups the violation timing paths according to the starting module and the end module, and then takes the union of the violation causes in each violation timing path group to obtain the violation causes involved in the group of violation timing paths. Then, the optimization strategy determination unit calculates whether the violation timing path group meets the preset conditions. Meeting the preset conditions means that the preset optimization strategy is triggered, and the absolute value of the worst negative timing margin of the violation timing path group is less than the clock cycle involved in the violation. When the preset conditions are met, the timing path optimization strategy corresponding to the violation timing path group and the timing path optimization strategy corresponding to other violation timing path groups are generated. When the preset conditions are not met, it is determined whether the timing constraint setting is reasonable. When it is determined that the timing constraint setting is unreasonable, the timing constraint is adjusted (for example, the clock cycle involved in the violation is adjusted) or the design is optimized (for example, the circuit structure), and it is re-determined whether the adjusted preset conditions are met.

[0148] For the fifth processing module 123:

[0149] The fifth processing module 123 is configured to generate a statistical distribution table and a statistical distribution graph according to the characteristic data of the target timing path and the violation diagnosis report.

[0150] In this embodiment, the statistical distribution tables include: timing margin distribution table, clock domain timing margin distribution table, module timing margin distribution table, path starting point timing margin distribution table, level distribution table, combinational logic level distribution table, unit level delay distribution table, unit distance delay distribution table, path length distribution table, path redundancy ratio distribution table and crosstalk delay distribution table.

[0151] In this embodiment, the fifth processing module 123 includes a distribution table generating unit 1231 and a distribution graph generating unit 1232. The distribution table generating unit 1231 can be a system-built-in statistical distribution table generator, which can automatically generate a series of statistical distribution tables. The distribution graph generating unit 1232 can be a system-built-in statistical distribution graph generator that can automatically generate a series of statistical distribution graphs, including a timing margin distribution graph, a timing margin cumulative distribution graph, a series distribution graph, a combinational logic series distribution graph, a path group unit series delay distribution graph, a path group unit distance delay distribution graph, a unit series delay distribution graph, a unit distance delay distribution graph, a path length distribution graph, a path redundancy ratio distribution graph, a path group path redundancy ratio distribution graph, a crosstalk delay distribution graph, a path group crosstalk delay distribution graph, a violation diagnosis distribution graph, and a path group violation diagnosis distribution graph. The statistical distribution graph generated by the present invention can be displayed in the form of a histogram, a stacked histogram, and a pie chart, which can more intuitively reflect the overall distribution characteristics of the timing path and the distribution characteristics of the timing path group.

[0152] The functions of the statistical distribution table generator and the statistical distribution graph generator are implemented by script programs. It should be noted that the script program is written by the developer according to the system requirements, which can be an automatically executed code segment and stored in the system in advance. It can be set based on actual conditions, and this embodiment does not specifically limit this. The statistical distribution graph generator can set different drawing algorithms for display modes such as histograms, stacked histograms, and pie charts.

[0153] Drawing algorithm corresponding to the histogram: The statistical distribution graph generator generates a feature data list based on the feature data of the read target timing path and the path features that need to be drawn, and uses the binning algorithm to calculate the appropriate distribution interval through the data in the feature data list. Then, for each distribution interval, the number of values ​​in the feature data list that fall into the distribution interval is calculated to form a distribution value list. Finally, the distribution value list is used to draw the histogram and mark the coordinate axis.

[0154] Drawing algorithm corresponding to the stacked histogram: The statistical distribution graph generator generates a feature data list and a group feature data dictionary based on the feature data of the read target timing path and the path features to be drawn. The key of the dictionary is the group name, and the value is the feature data list corresponding to the group. Next, the generator uses the binning algorithm to calculate the appropriate distribution interval through the data in the feature data list, and then calculates the number of values ​​of each group feature data list that fall into the distribution interval for each distribution interval to form a distribution value dictionary. The key of the dictionary is the group name, and the value is the number of distribution values ​​of the group in the interval. Then the generator randomly assigns colors to each group, and finally uses the distribution value dictionary to draw the stacked histogram and mark the coordinate axis.

[0155] The drawing algorithm corresponding to the fan chart: The statistical distribution chart generator generates a feature data list based on the feature data of the target timing path read and the path features to be drawn, and then calculates the frequency of occurrence of the same data in the list through the data in the feature data list to generate a data frequency dictionary. The key of the dictionary is the data and the value is the frequency of the data. Then the generator calculates the optimal arrangement between the fan chart blocks based on the frequency of each data and randomly assigns a color to each data. Finally, the data frequency dictionary is used to draw the fan chart and add marks.

[0156] The flow chart of the feature extraction subsystem 11 is as follows: Figure 5 As shown, the flow chart of the statistical analysis subsystem 12 is as follows Figure 6 As shown. Figure 5 As shown, when the input data includes one or more specified timing path groups, target features of the one or more specified timing path groups in the input data are extracted. If not specified, the present invention will analyze all timing path groups in the target database.

[0157] The static timing statistics analysis system in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0158] The present invention provides an automated static timing statistical analysis system. Compared with conventional timing analysis methods, the present invention mainly has the following features:

[0159] 1) The present invention can automatically extract logical features and physical features of timing paths in large quantities through the built-in feature extraction subsystem 11, and calculate other features, such as logical features and physical features, through an automatic timing path feature inference method, which can greatly improve the efficiency of timing analysis and provide a comprehensive data basis for the overall timing analysis of the entire design and the overall timing analysis of the timing path group.

[0160] 2) The present invention can automatically diagnose the violation causes of a large number of timing paths through the built-in timing path violation diagnostic device. Compared with the conventional timing analysis method, the present invention does not require the designer to analyze the timing paths one by one. The automated diagnostic capability greatly improves the efficiency of timing analysis, and the analysis results are more comprehensive and reliable, thereby reducing the number of additional timing optimization iterations caused by incomplete single analysis.

[0161] 3) The present invention can automatically generate timing path optimization strategies based on the violation diagnosis report, and the designer can directly use or refer to these timing path optimization strategies for further optimization.

[0162] 4) The present invention automatically generates a series of statistical distribution tables through a built-in statistical distribution table generator, performs statistical analysis on a large number of timing paths from different dimensions, and comprehensively and quantitatively reflects the statistical distribution characteristics of the logical characteristics and physical characteristics of a large number of timing paths.

[0163] 5) The present invention automatically generates a series of statistical distribution graphs through a built-in statistical distribution graph generator, performs statistical analysis on a large number of specified timing paths from different dimensions, and can more intuitively and detailedly reflect the statistical distribution characteristics of the logical characteristics and physical characteristics of the timing paths of the entire design and each timing path group.

[0164] 6) The static timing statistical analysis system of the present invention can perform feature extraction on the databases of various EDA tools in the middle and back-end, and can be applied to timing analysis work at various stages in the middle and back-end processes.

[0165] 7) The static timing statistical analysis system of the present invention is not limited to analyzing timing paths with violations, but can perform batch statistical analysis on timing paths within any timing margin range according to the needs of designers. It can not only help designers to quickly converge timing, but also provide an important data basis for further improving the key chip indicator PPA (Performance, Power, Area, performance, power consumption, size).

[0166] It should be noted that the extracted logical features and physical features mentioned in the above embodiments of the present invention are only some examples listed, and extracting other features for statistical analysis should also be within the protection scope of the present invention.

[0167] The various statistical distribution tables and statistical distribution graphs generated in the above embodiments of the present invention are only some examples listed, and statistical distribution tables and statistical distribution graphs with other contents or other formats should also be within the protection scope of the present invention.

[0168] The timing path feature source file generated by the present invention uses the CSV format, and the use of other file formats that can achieve the same purpose is also within the protection scope of the present invention.

[0169] The violation diagnosis report generated by the present invention uses the Excel format, and other file formats that can achieve the same purpose are also within the protection scope of the present invention.

[0170] In the above embodiment, the description of the timing path automatic diagnosis part is illustrated by taking the setup time violation as an example. The present invention can also be applied to the analysis of the hold time violation and the asynchronous timing violation, which should also belong to the protection scope of the present invention.

[0171] The diagnostic rules of the timing path automatic diagnostic device mentioned in the present invention are only some examples, and the use of other standards or rules for diagnosis should also fall within the protection scope of the present invention.

[0172] The key technical points of the technical solution of the present invention are:

[0173] The present invention provides an automated static timing statistical analysis system. Different from conventional timing analysis methods, the present invention uses a method combining statistical analysis and data visualization to achieve more comprehensive and intuitive analysis of large batches of timing paths.

[0174] The present invention can automatically extract the logical features and physical features of timing paths in large quantities, and calculate other logical features and physical features through an automatic timing path feature inference method, which can greatly improve the efficiency of timing analysis.

[0175] The present invention can automatically diagnose the causes of violations of a large number of timing paths without requiring designers to analyze the timing paths one by one, thereby greatly improving the efficiency of timing analysis.

[0176] The present invention automatically generates statistical distribution tables and statistical distribution graphs, and performs statistical analysis on a large number of timing paths from multiple dimensions through the statistical tables and statistical graphs, quantitatively and intuitively characterizing the overall statistical distribution characteristics of the timing paths and the statistical distribution characteristics of the timing path groups.

[0177] The present invention can be applied to the timing analysis work at each stage in the middle and back-end processes, and the feature extraction subsystem 11 and the statistical analysis subsystem 12 have extremely strong scalability. The built-in feature extraction subsystem 11 of the present invention takes the database of each stage as input, automatically extracts the logical features and physical features of the timing path, and then generates the timing path feature source file and passes it to the statistical analysis subsystem 12. The statistical analysis subsystem 12 takes the timing path feature source file as input, automatically performs batch diagnosis and statistical analysis on the timing path, and generates violation diagnosis reports, timing path optimization strategies, and a series of multi-dimensional statistical distribution tables and statistical distribution graphs.

[0178] The present invention is not limited to analyzing paths with timing violations, but can analyze the timing of any specified timing margin range and timing path group as needed.

[0179] It should be noted that the contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

[0180] An embodiment of the present invention provides an embodiment of a static timing statistical analysis method. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0181] Figure 7 It is a flowchart of a static timing statistics analysis method according to an embodiment of the present invention.

[0182] like Figure 7 As shown, an embodiment of the present invention provides a static timing statistics analysis method, which includes:

[0183] S101: Obtain input data.

[0184] In this embodiment, the input data includes a target database and a condition threshold, the target database includes timing path information and physical location information stored in a corresponding relationship, the timing path information includes a timing path group and related information of the timing path group, and a timing path group includes multiple timing paths.

[0185] S102: When the input data is acquired, a screening condition is determined according to a condition threshold, and a target timing path is determined according to the screening condition.

[0186] In this embodiment, the target timing path includes: a timing path in the target database that meets the screening condition.

[0187] S103: When the target timing path is determined to be obtained according to the screening conditions, target feature extraction is performed on the target timing path to obtain a target extraction result. When the target extraction result is obtained, the target extraction result is written into the timing path feature source file.

[0188] In this embodiment, the target extraction result includes: target logical features, or target logical features and target physical features. The timing path feature source file includes feature values ​​of the target timing path.

[0189] S104: Determine characteristic data of the target timing path according to the timing path characteristic source file.

[0190] S105: Determine a violation timing path according to the characteristic data of the target timing path, generate a violation diagnosis report, and determine a timing path optimization strategy according to the violation diagnosis report.

[0191] S106: Generate a statistical distribution table and a statistical distribution graph according to the characteristic data of the target timing path and the violation diagnosis report.

[0192] In an optional implementation, when the condition threshold includes the first quantity, the first threshold, the second threshold, and the preset depth, determining the screening condition according to the condition threshold in S102 specifically includes:

[0193] The first condition is determined according to the first quantity, the second condition is determined according to the first threshold, and the third condition is determined according to the second threshold. The first condition is that the sum of the number of target timing paths is less than or equal to the first quantity, and the second condition is that the maximum margin in the target timing path is less than or equal to the first threshold. The third condition is that the minimum margin in the target timing path is greater than or equal to the second threshold. The preset depth is used to divide the modules to which the starting point and the end point of the target timing path belong.

[0194] In an optional implementation, the step of extracting target features from the target timing path to obtain a target extraction result in S103 specifically includes:

[0195] Logical features are extracted from the target timing path to obtain target logical features, and physical features are extracted from the target timing path to obtain target physical features.

[0196] In an optional implementation, the step of extracting target features from the target timing path to obtain a target extraction result in S103 further includes:

[0197] Logical features are extracted from the target timing path to obtain target logical features, and it is determined whether to perform physical features extraction on the target timing path. When it is determined that physical features are extracted on the target timing path, physical features are extracted from the target timing path to obtain target physical features.

[0198] In an optional implementation manner, generating a violation diagnosis report in S105 specifically includes:

[0199] A violation diagnosis report is generated according to the name of the target feature in the violation timing path, the feature data of the violation timing path, and the violation cause determined according to the feature data of the violation timing path.

[0200] In an optional implementation manner, determining the timing path optimization strategy according to the violation diagnosis report in S105 specifically includes:

[0201] Read the violation diagnosis report, traverse the violation timing path, group the violation timing path according to the starting module and the end module, obtain at least one violation timing path group, and for each violation timing path group, determine the violation cause corresponding to the single violation timing path group, and determine whether the preset condition is met according to the violation cause corresponding to the single violation timing path group; when the violation cause corresponding to the single violation timing path group is determined to meet the preset condition, determine the timing path optimization strategy.

[0202] In an optional embodiment, the statistical distribution table includes: a timing margin distribution table, a clock domain timing margin distribution table, a module timing margin distribution table, a path starting point timing margin distribution table, a level distribution table, a combinational logic level distribution table, a unit level delay distribution table, a unit distance delay distribution table, a path length distribution table, a path redundancy ratio distribution table and a crosstalk delay distribution table.

[0203] In an optional embodiment, the statistical distribution graph includes: a timing margin distribution graph, a timing margin cumulative distribution graph, a level distribution graph, a combinational logic level distribution graph, a path group unit level delay distribution graph, a path group unit distance delay distribution graph, a unit level delay distribution graph, a unit distance delay distribution graph, a path length distribution graph, a path redundancy ratio distribution graph, a path group path redundancy ratio distribution graph, a crosstalk delay distribution graph, a path group crosstalk delay distribution graph, a violation diagnosis distribution graph, and a path group violation diagnosis distribution graph.

[0204] The embodiment of the present invention also provides a computer device having the above Figure 2 The static timing statistics analysis system shown.

[0205] See also Figure 8 , Figure 8 Schematic diagram of the hardware structure of the computer device according to the embodiment of the present invention. Figure 8As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as a display device coupled to the interface). In an optional embodiment, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 8 A processor 10 is taken as an example.

[0206] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0207] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0208] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function. The data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage devices. In an optional embodiment, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0209] The memory 20 may include a volatile memory, such as a random access memory. The memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive. The memory 20 may also include a combination of the above-mentioned types of memory.

[0210] The computer device further comprises a communication interface 30 for the computer device to communicate with other devices or a communication network.

[0211] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0212] A part of the present invention may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present invention through the operation of the computer. Those skilled in the art should understand that the existence of the computer program instruction in a computer-readable medium includes, but is not limited to, a source file, an executable file, an installation package file, etc., and accordingly, the way in which the computer program instruction is executed by the computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium may be any available computer-readable storage medium or communication medium accessible to the computer.

[0213] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A static time series statistical analysis system, characterized in that: include: A feature extraction subsystem and a statistical analysis subsystem; the feature extraction subsystem includes a first processing module and a second processing module; The statistical analysis subsystem includes a third processing module, a fourth processing module and a fifth processing module; The first processing module is configured to obtain input data; the input data includes a target database and a condition threshold, the target database includes timing path information and physical location information stored in a corresponding relationship, the timing path information includes a timing path group and related information of the timing path group, and a timing path group includes multiple timing paths; when the input data is obtained, a screening condition is determined according to the condition threshold, and a target timing path is determined according to the screening condition, and the target timing path includes: a timing path in the target database that meets the screening condition; The second processing module is configured to, when determining to obtain a target timing path according to the screening condition, perform target feature extraction on the target timing path to obtain a target extraction result, and when obtaining the target extraction result, write the target extraction result into a timing path feature source file; the target extraction result includes: a target logical feature, or a target logical feature and a target physical feature; the timing path feature source file includes a feature value of the target timing path; The third processing module is configured to determine characteristic data of a target timing path according to the timing path characteristic source file; The fourth processing module is configured to determine a violation timing path according to the characteristic data of the target timing path, generate a violation diagnosis report, and determine a timing path optimization strategy according to the violation diagnosis report; The fifth processing module is configured to generate a statistical distribution table and a statistical distribution graph according to the characteristic data of the target timing path and the violation diagnosis report.

2. The system according to claim 1, characterized in that When the condition threshold includes a first quantity, a first threshold, a second threshold and a preset depth, the first processing module is specifically configured to determine a first condition according to the first quantity, determine a second condition according to the first threshold, and determine a third condition according to the second threshold; the first condition is that the sum of the number of target timing paths is less than or equal to the first quantity, and the second condition is that the maximum margin in the target timing path is less than or equal to the first threshold; The third condition is that the minimum margin in the target timing path is greater than or equal to the second threshold; the preset depth is used to divide the modules to which the starting point and the end point of the target timing path belong.

3. The system according to claim 1, characterized in that The second processing module includes a feature extraction unit; The feature extraction unit is configured to perform logic feature extraction on the target timing path to obtain a target logical feature, and perform physical feature extraction on the target timing path to obtain a target physical feature.

4. The system according to claim 3, characterized in that The feature extraction unit is specifically configured to perform logical feature extraction on the target timing path to obtain a target logical feature, determine whether to perform physical feature extraction on the target timing path, and when it is determined to perform physical feature extraction on the target timing path, perform physical feature extraction on the target timing path to obtain a target physical feature.

5. The system according to claim 1, characterized in that The fourth processing module includes a diagnostic report determination unit, which is configured to generate a violation diagnostic report according to the name of the target feature in the violation timing path, the feature data of the violation timing path, and the violation cause determined according to the feature data of the violation timing path.

6. The system according to claim 1, characterized in that The fourth processing module also includes an optimization strategy determination unit, which is configured to read the violation diagnosis report, traverse the violation timing path, group the violation timing path according to the starting module and the end module, and obtain at least one violation timing path group; for each violation timing path group, determine the violation cause corresponding to a single violation timing path group; determine whether a preset condition is met according to the violation cause corresponding to the single violation timing path group; and when the violation cause corresponding to the single violation timing path group is determined to meet the preset condition, determine the timing path optimization strategy.

7. The system according to claim 1, characterized in that The statistical distribution table includes: a timing margin distribution table, a clock domain timing margin distribution table, a module timing margin distribution table, a path starting point timing margin distribution table, a level distribution table, a combinational logic level distribution table, a unit level delay distribution table, a unit distance delay distribution table, a path length distribution table, a path redundancy ratio distribution table and a crosstalk delay distribution table; The statistical distribution diagrams include: a timing margin distribution diagram, a timing margin cumulative distribution diagram, a level distribution diagram, a combinational logic level distribution diagram, a path group unit level delay distribution diagram, a path group unit distance delay distribution diagram, a unit level delay distribution diagram, a unit distance delay distribution diagram, a path length distribution diagram, a path redundancy ratio distribution diagram, a path group path redundancy ratio distribution diagram, a crosstalk delay distribution diagram, a path group crosstalk delay distribution diagram, a violation diagnosis distribution diagram, and a path group violation diagnosis distribution diagram.

8. A static timing statistical analysis method, characterized in that: Applied to the system according to any one of claims 1 to 7, the static timing statistical analysis method comprises: Acquire input data; the input data includes a target database and a condition threshold, the target database includes timing path information and physical location information stored in a corresponding relationship, the timing path information includes a timing path group and related information of the timing path group, and a timing path group includes multiple timing paths; when the input data is acquired, determine a screening condition according to the condition threshold, determine a target timing path according to the screening condition, and the target timing path includes: a timing path in the target database that meets the screening condition; When the target timing path is determined according to the screening condition, target feature extraction is performed on the target timing path to obtain a target extraction result. When the target extraction result is obtained, the target extraction result is written into a timing path feature source file; the target extraction result includes: target logical features, or target logical features and target physical features; the timing path feature source file includes feature values ​​of the target timing path; Determine characteristic data of a target timing path according to the timing path characteristic source file; Determine the violation timing path according to the characteristic data of the target timing path, generate a violation diagnosis report, and determine the timing path optimization strategy according to the violation diagnosis report; Generate statistical distribution tables and statistical distribution graphs based on the characteristic data of the target timing path and the violation diagnosis report.

9. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the steps of the static timing statistical analysis method according to claim 8 by executing the computer instructions.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the steps of the static timing statistical analysis method according to claim 8.

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