Chip id layout determination method and device, equipment and storage medium

Abstract

The application discloses a kind of chip ID layout determination method, device, equipment and storage medium, method includes: from chip arrangement layout multiple non-testing chips located in wafer boundary line are selected as target chip, and the first position coordinate of multiple target chips is determined;From multiple target chips, reference chip is selected, and the offset of reference chip relative to coordinate system origin is determined;Based on offset, the position coordinate of multiple target chips is corrected;Based on the size of each chip and the position coordinate after correction, the chip ID coordinate encoding of each chip is determined;Based on the first position coordinate and the preset encoding movement, the third position coordinate of the chip ID coordinate encoding of each chip is determined;Based on the chip ID coordinate encoding corresponding to each chip and the third position coordinate of each chip, chip ID layout is generated.The method can realize the efficient, accurate, automatic determination of chip ID layout.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of micro-electro-mechanical system manufacturing, and in particular, to a chip ID layout determination method and device, equipment and a storage medium. BACKGROUND

[0002] With the rapid development of micro-electro-mechanical system (MEMS) technology, the industry scale continues to expand, and the market demand for MEMS products also shows a trend of increasing year by year. In the wafer manufacturing process, MEMS products often need to be managed in the form of identity identification (chip ID) to meet the needs of tracking and failure analysis of each independent chip. In the IC field, the chip ID is usually recorded in the internal circuit of the chip, while the MEMS product often needs to directly manufacture the chip ID on the surface of the chip in a physical form through 1X times of contact photolithography and etching process due to its special application scenario. This not only facilitates quick identification in the subsequent packaging and cutting process, but also quickly locates the specific chip position and arrangement on the wafer during failure analysis.

[0003] In related technologies, the chip ID code is usually generated according to the chip arrangement layout and the arrangement order of the chip, and the chip ID code position is determined according to the fixed pitch of the chip size, so as to generate a wafer-level chip ID layout that records the position of each chip in the wafer and the corresponding ID code information of the chip. Finally, a corresponding photomask is manufactured according to the generated chip ID layout, and the photomask is used for photolithography and etching of the chip to form the corresponding chip ID on the surface of the chip. Since the chip arrangement layout is usually designed based on the chip size, it means that it cannot fully reflect the arrangement mode of the chips that need to generate ID on the actually manufactured wafer. When the arrangement mode of the chips that need to generate ID on the actually manufactured wafer is different from that in the chip arrangement layout, the chip ID layout generated by the above method will be inaccurate. If the generated chip ID layout is adjusted according to the arrangement mode of the chips on the actually manufactured wafer, the manufacturing cost and time cost will be increased. Therefore, it is difficult to automatically and accurately generate the chip ID layout according to the arrangement of the chips that need to generate ID on the actually manufactured wafer by using the above method.

[0004] In view of the above problems, there is an urgent need for a method for accurately, automatically and efficiently generating a chip ID layout to adapt to the increasing flexibility and diversity requirements in the MEMS product manufacturing process. SUMMARY

[0005] In view of the above problems, the present application is proposed to provide a chip ID layout determination method, device, equipment and storage medium which overcomes the above problems or at least partially solves the above problems. The chip ID layout determination method, device, equipment and storage medium select non-test chips located within a wafer boundary line from a chip arrangement layout as target chips, and determine a chip ID layout matched with the arrangement of the target chips. The arrangement of the target chips is closer to the arrangement of the chips in the wafer which need to generate an ID, thereby realizing efficient, accurate and automatic determination of the chip ID layout.

[0006] In a first aspect, a chip ID layout determination method is provided, applied to an electronic device, and the method comprises:

[0007] Selecting a plurality of non-test chips located within a wafer boundary line from a chip arrangement layout as target chips, wherein the wafer boundary line is an outer edge contour line of a wafer with a center point of the chip arrangement layout as a midpoint;

[0008] Determining first position coordinates of the plurality of target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system with the center point of the chip arrangement layout as an origin of the coordinate system;

[0009] Selecting one target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip, and determining an offset of the reference chip relative to the origin of the coordinate system;

[0010] Based on the offset, correcting the first position coordinates of the plurality of target chips to obtain second position coordinates after correction;

[0011] Determining a chip ID coordinate code of each target chip based on the size of each target chip and the corresponding second position coordinates;

[0012] Determining a third position coordinate of the chip ID coordinate code of each target chip based on the first position coordinates of each target chip and a preset encoding movement amount;

[0013] Generating a chip ID layout based on the chip ID coordinate code of each target chip and the corresponding third position coordinates.

[0014] Optionally, the first position coordinates of the target chip include first position sub-coordinates of a first vertex and a second vertex of a target chip bounding box, and the first vertex and the second vertex are two opposite vertices of the target chip bounding box.

[0015] Optionally, the selecting one target chip closest to the origin of the coordinate system from the plurality of target chips as a reference chip comprises:

[0016] determining a minimum distance of each of the target chips to the origin of the coordinate system based on the first position coordinates of each of the target chips;

[0017] selecting one of the target chips with the minimum distance to the origin of the coordinate system as the reference chip.

[0018] Optionally, the determining the offset of the reference chip relative to the origin of the coordinate system comprises:

[0019] selecting the first vertex or the second vertex of the reference chip bounding box as a reference point, and determining a distance of the reference point to the origin of the coordinate system as the offset.

[0020] Optionally, the second position coordinates comprise second position sub-coordinates of the first vertex or the second vertex, and the correcting the first position coordinates of the plurality of target chips based on the offset to obtain corrected second position coordinates comprises:

[0021] when the reference point is the first vertex, adding the first position sub-coordinate of the first vertex by the offset to obtain a second position sub-coordinate of the corrected first vertex;

[0022] when the reference point is the second vertex, adding the first position sub-coordinate of the second vertex by the offset to obtain a second position sub-coordinate of the corrected second vertex.

[0023] Optionally, the determining the chip ID coordinate encoding of each chip based on the size of each chip and the corresponding second position coordinates comprises:

[0024] determining the chip ID coordinate encoding of each chip according to the following formula:

[0025] ID nX = Die nX0 / width(nX);

[0026] ID nY = Die nY0 / height(nY);

[0027] wherein the ID coordinate encoding of the nth chip is (ID nX, ID nY), the second position coordinates corresponding to the nth chip are (Die nX0, Die nY0), width(nX) represents the length of the nth chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

[0028] Optionally, the selecting a plurality of chips located within the wafer boundary line from the chip arrangement layout as target chips comprises:

[0029] extracting a bounding box layout of all effective chips from a preset chip layout, to obtain an effective chip layout, wherein the chip layout includes the layout of the bounding boxes of the effective chips for exposure and the ineffective chips for testing;

[0030] selecting, from the effective chip layout, an effective chip whose four vertices of the chip bounding box are located within the wafer boundary line as the target chip.

[0031] In a second aspect, a device for determining a chip ID layout is provided, comprising:

[0032] a chip selecting module configured to select a plurality of non-testing chips located within a wafer boundary line from a chip layout as target chips, wherein the wafer boundary line is an outer edge contour line of a wafer with a center point of the chip layout as a midpoint;

[0033] a coordinate determining module configured to determine first position coordinates of the plurality of target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system with the center point of the chip layout as an origin point of the coordinate system;

[0034] an offset determining module configured to select one target chip closest to the origin point of the coordinate system from the plurality of target chips as a reference chip, and determine an offset of the reference chip relative to the origin point of the coordinate system;

[0035] a coordinate correcting module configured to correct the first position coordinates of the plurality of target chips based on the offset, to obtain second position coordinates after correction;

[0036] an ID encoding determining module configured to determine a chip ID coordinate encoding of each of the target chips based on a size of each of the target chips and the corresponding second position coordinates;

[0037] an encoding coordinate determining module configured to determine third position coordinates of the chip ID coordinate encoding of each of the target chips based on the first position coordinates of each of the target chips and a preset encoding movement amount;

[0038] an ID layout determining module configured to generate a chip ID layout based on the chip ID coordinate encoding of each of the target chips and the corresponding third position coordinates.

[0039] In a third aspect, an electronic device is provided, comprising a memory and a processor, which are communicatively connected with each other, and the memory stores computer instructions, and the processor executes the computer instructions to perform the method for determining a chip ID layout according to the first aspect.

[0040] In a fourth aspect, a computer readable storage medium is provided, which stores computer instructions for causing a computer to perform the chip ID layout determining method according to the first aspect.

[0041] The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0042] The chip ID layout determining method, device, equipment and storage medium provided by the embodiments of the present application can select non-test chips located in the wafer boundary line from the chip arrangement layout as target chips in the chip arrangement layout which need to form chip IDs, and the arrangement manner of the target chips is closer to the arrangement manner of the chips which need to generate IDs in the actually manufactured wafer, so that the problem of inaccurate chip ID layout caused by the inconsistency between the chip arrangement layout and the arrangement manner of the chips which need to form IDs on the actually manufactured wafer in the traditional method is effectively avoided.

[0043] Meanwhile, the position coordinates of each target chip are corrected according to the offset of the reference chip relative to the origin of the coordinate system, so that the accuracy of the position coordinates of each chip is ensured, and the accuracy of the chip ID layout is improved. Moreover, the method can automatically generate the corresponding chip ID layout according to the arrangement manner of the chips which need to generate IDs in the actually manufactured wafer, and there is no need to manually adjust the generated chip ID layout according to the arrangement manner of the chips on the actually manufactured wafer, so that the manufacturing cost and time cost are significantly reduced, the production efficiency is improved, the chips of different sizes and different arrangement manners can be well adapted, the method itself does not need to be greatly modified or adjusted, the accurate generation of chip ID layouts of various MEMS product chips can be efficiently realized, and high flexibility and applicability are exhibited.

[0044] The above description is only a summary of the technical solutions of the present application. In order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described below. BRIEF DESCRIPTION OF DRAWINGS

[0045] Various other advantages and benefits will become apparent to those of ordinary skill in the art, upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of preferred embodiments, and are not meant to limit the present application. Furthermore, the same reference numerals are used throughout the several drawings to refer to same or like parts. In the drawings:

[0046] Figure 1 is a chip ID layout determining method flowchart provided by the embodiments of the present application;

[0047] Figure 2 is a schematic diagram of an effective chip layout provided by an embodiment of the present application;

[0048] Figure 3 is a schematic diagram of another effective chip layout provided by an embodiment of the present application;

[0049] Figure 4 is a schematic diagram of a target chip layout provided by an embodiment of the present application;

[0050] Figure 5 is a schematic diagram of a chip ID coordinate encoding provided by an embodiment of the present application;

[0051] Figure 6 is a schematic diagram of a chip ID encoding font layout file provided by an embodiment of the present application;

[0052] Figure 7 is a structure block diagram of a chip ID layout determining device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0053] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical solutions of the present application, rather than limitations of the technical solutions of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0054] Many MEMS products need to directly make chip ID on the chip through 1X times contact photolithography and etching process, so as to facilitate the tracking of the position and arrangement of the failed chip on the wafer after cutting and packaging. For this method, a wafer-level chip ID layout needs to be made to make a corresponding mask according to the chip ID layout, and the mask is used for photolithography and etching of the chip to form a corresponding chip ID on the surface of the chip.

[0055] In the related art, a chip ID code is generated according to a chip arrangement layout and a chip arrangement sequence, and a chip ID layout is generated according to a chip size and a fixed interval, so that the chip ID layout records the position of each chip in a wafer and corresponding ID code information. However, the chip arrangement layout is an arrangement layout of chip boundary boxes designed in advance based on chip size, and the chip arrangement layout includes arrangement of boundary boxes of effective chips for exposure and invalid chips for testing. The effective chip is a chip that needs to form a chip ID, and the testing chip is a chip used for PCM (process control monitoring) testing in the wafer manufacturing process. The testing chip in the testing area does not need to form a chip ID. Since the chip arrangement layout includes testing chips, and the size and position of the testing area where the testing chips are located are not fixed. If the above method is used to generate a chip ID layout based on the chip arrangement layout and a fixed interval according to the chip size, the testing chip located in the wafer boundary line will also generate a corresponding chip ID in the chip ID layout, resulting in an error in the finally generated chip ID layout. If the above method is used to generate a chip ID layout based on the chip arrangement layout and a fixed interval according to the chip size, the testing chip located in the wafer boundary line will also generate a corresponding chip ID in the chip ID layout, resulting in an error in the finally generated chip ID layout. If the above method is used to generate a chip ID layout based on the chip arrangement layout and a fixed interval according to the chip size, the testing chip located in the wafer boundary line will also generate a corresponding chip ID in the chip ID layout, resulting in an error in the finally generated chip ID layout. Therefore, it is difficult to automatically and accurately generate a chip ID layout according to the arrangement of chips that need to generate an ID in the actual manufactured wafer by using the above method.

[0056] Therefore, in order to solve the technical problems in the related art, the embodiments of the present application provide a method, device and equipment for determining a chip ID layout and a storage medium, and the inventive concept is to select non-testing chips located in a wafer boundary line from a chip arrangement layout as target chips, and determine a chip ID layout matched with the arrangement of the target chips. The arrangement of the target chips is closer to the arrangement of chips that need to generate an ID in the actually manufactured wafer, so that the chip ID layout is efficiently, accurately and automatically determined.

[0057] Figure 1 A flowchart of a method for determining a chip ID layout provided by the embodiments of the present application is shown in FIG. 1. Figure 1 The method comprises the following steps.

[0058] In step S110, a plurality of non-testing chips located in a wafer boundary line are selected from a chip arrangement layout as target chips, wherein the wafer boundary line is a wafer outer edge contour line with a center point of the chip arrangement layout as a midpoint.

[0059] In a specific implementation, the staff can draw a chip arrangement layout on the terminal device according to the chip size and the chip type (including chips for exposure and chips for testing), or can import a pre-drawn chip arrangement layout into the terminal device. After the chip arrangement layout is prepared, the chip ID layout can be generated by clicking the chip ID layout generation button on the terminal device. After clicking the generation button, the terminal device transmits a start instruction carrying the chip arrangement layout to an electronic device (such as a server), and the server starts to execute S110 in response to the start instruction.

[0060] Optionally, step S110 comprises:

[0061] extracting a boundary box arrangement of all effective chips from the preset chip arrangement layout to obtain an effective chip arrangement layout, wherein the chip arrangement layout comprises an arrangement of boundary boxes of the effective chips for exposure and the ineffective chips for testing which are pre-designed;

[0062] selecting, from the effective chip arrangement layout, an effective chip whose four vertices of the chip boundary box are located within the wafer boundary line as a target chip.

[0063] Figure 2 is a schematic diagram of an effective chip arrangement layout provided by an embodiment of the present application, as shown in Figure 2 each red small square in the figure represents an effective chip a, the blue rectangular box represents a main exposure area S1, the main exposure area S1 includes a plurality of effective chips a which need to form chip IDs, the blank area is a test area S2 formed by test chips for PCM (process control monitoring) testing, and the black circle represents a wafer boundary line. Since the test chips have been selected when the chip arrangement layout is made, the arrangement of the test chips and the effective chips can be determined according to the chip function when the chip arrangement layout is made. In step S110, after the effective chip arrangement layout as shown in Figure 2 is extracted, the chip whose four vertices of the chip boundary box are located within the wafer boundary line needs to be selected as a target chip, that is, a more close-to-actual arrangement of the chips which need to generate IDs in the wafer manufactured can be obtained. It should be noted that the wafer boundary line in the embodiment is a wafer outer edge contour line with the center point of the effective chip arrangement layout as the midpoint, and the circular radius of the wafer boundary line can be set by the designer according to the actual effective chip area radius of the wafer.

[0064] In the embodiment, the chip whose four vertices of the chip boundary box are located within the wafer boundary line is selected as the target chip from the effective chip arrangement layout, which can specifically comprise:

[0065] Based on the pre-established layout coordinate system, the position coordinates of each effective chip in the effective chip arrangement layout are determined, and the position coordinates at least include two opposite vertex position coordinates of the effective chip boundary box; based on the position coordinates of each effective chip, the distances of four vertexes of each effective chip boundary box to the coordinate system origin are determined; and the effective chip with the distances of four vertexes of the boundary box to the coordinate system origin all less than or equal to the wafer radius is selected as the target chip.

[0066] In order to better understand this step, the following is combined with Figure 3 The selection of the target chip is specifically described as follows: Figure 3 Another schematic diagram of the effective chip arrangement layout provided by the embodiment of the present application is shown in FIG. 2. Figure 3 As shown in the figure, NO. 1-NO. 13, NO. 16, NO. 18-NO. 21, NO. 23-NO. 25 represent effective chips, the layout coordinate system is a two-dimensional coordinate system established with the center point O of the effective chip arrangement layout as the coordinate system origin, the horizontal coordinate of the layout coordinate system is the X axis, and the vertical coordinate is the Y axis. Based on the coordinate system, the position coordinates of each effective chip can be determined, and the position coordinates of each effective chip can include the position coordinates of two opposite vertexes of the boundary box. For example, the position coordinates of the left lower and right upper two opposite vertexes can be selected to represent the position coordinates of the effective chip, that is, the position coordinates of the nth effective chip are (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY), and the position coordinates of the coordinate system origin are (0, 0).

[0067] In the specific implementation, the specific GDS NO in the GDS file can be used as the chip identification layer to represent the position and size of each chip. In this embodiment, GDS: 101 / 1 can be used as the chip identification layer, and it should be noted that GDS: 101 / 1 only draws the chip position that needs to be encoded with the chip ID, and is not used for drawing other graphics. Further, the.shape function in the klayout library can be used to extract the actual position coordinates of two opposite vertexes of each effective chip in the chip identification layer, and then Python is used to count the coordinate data into table data columns (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY) for facilitating subsequent calculation and conversion.

[0068] When the position coordinates of each chip are obtained, the distances of four vertexes of each chip boundary box to the coordinate system origin can be determined according to the following formula:

[0069] The distance of the left lower vertex to the coordinate system origin is ((DieLeft nX)2+(DieLeft nY)2) 0.5 ;

[0070] Distance from top-left vertex to origin of coordinate system: ((DieLeft nX)2+(DieRight nY)2) 0.5 ;

[0071] Distance from top-right vertex to origin of coordinate system: ((DieRight nX)2+(DieRight nY)2) 0.5 ;

[0072] Distance from bottom-right vertex to origin of coordinate system: ((DieRight nX)2+(DieLeft nY)2) 0.5 ;

[0073] The distances from the four vertices to the origin of the coordinate system are calculated one by one, if the distances from the four vertices of the chip bounding box to the origin of the coordinate system are all less than or equal to the wafer radius, the target chip of the chip is selected; if the distance from any one of the four vertices to the origin of the coordinate system is greater than the wafer radius, the chip is not selected as the target chip, and the position coordinates corresponding to the chip are deleted from the table data column.

[0074] Figure 4 is a schematic diagram of the arrangement of a target chip provided by an embodiment of the present application, as shown in Figure 4 According to the above method, effective chips NO. 7, NO. 8, NO. 9, NO. 12, NO. 13, NO. 18 and NO. 19 can be selected from Figure 3 as target chips, and the arrangement of each target chip is as shown in Figure 4 .

[0075] It should be noted that Figure 3 and Figure 4 The arrangement and size of the chips in and are only examples, and the arrangement and size of the actual chips can be set according to the chips on the wafer actually manufactured, and the present application does not limit this.

[0076] Step S120, based on a pre-established layout coordinate system, determine the first position coordinates of a plurality of target chips, the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip arrangement layout as the origin of the coordinate system.

[0077] In the embodiment, the first position coordinates of the target chip include first position sub-coordinates of a first vertex of the target chip bounding box (DieLeft nX, DieLeft nY) and first position sub-coordinates of a second vertex (DieRight nX, DieRight nY), the first vertex and the second vertex being two opposite vertices (for example, the lower left and the upper right, or the lower right and the upper left) of the target chip bounding box, and the corresponding first position coordinates of the target chip can be represented as (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY). As shown in FIG. 18, taking the target chip NO. 7 as an example, the lower left vertex P7a of the target chip NO. 7 can be selected as the first vertex, and the upper right vertex P7b can be selected as the second vertex, and the first position coordinates of the target chip NO. 7 are (DieLeft 7X, DieLeft 7Y, DieRight 7X, DieRight 7Y). Figure 4

[0078] In step S130, one target chip closest to the origin of the coordinate system is selected from the plurality of target chips as a reference chip, and an offset of the reference chip relative to the origin of the coordinate system is determined.

[0079] Optionally, step S130 includes:

[0080] Based on the first position coordinates of each target chip, a minimum distance of each target chip to the origin of the coordinate system is determined, and one target chip with the minimum minimum distance to the origin of the coordinate system is selected as the reference chip.

[0081] In one implementation manner of the embodiment, the distance of each vertex of the bounding box of each target chip to the origin of the coordinate system can be calculated according to the calculation formula in step S110, and then the minimum value is selected from the four distances as the minimum distance of each target chip to the origin of the coordinate system. When the minimum distances corresponding to all target chips are calculated, the target chip with the minimum minimum distance can be further selected as the reference chip.

[0082] In another implementation manner of the embodiment, based on the first position coordinates of each target chip, the bounding box line of each target chip can be extracted, and then one target chip with the bounding box line closest to the origin of the coordinate system is selected as the reference chip.

[0083] Optionally, the offset of the reference chip relative to the origin of the coordinate system in step S130 includes:

[0084] The first vertex or the second vertex of the bounding box of the reference chip is selected as a reference point, and the distance of the reference point to the origin of the coordinate system is determined as the offset.

[0085] Specifically, as shown in FIG. 19, the first vertex of the bounding box of the reference chip is selected as the reference point, and the distance of the reference point to the origin of the coordinate system is determined as the offset.​Figure 4 As shown, when the target chip NO. 13 is selected as the reference chip, the lower left vertex P13a of the target chip NO. 13 can be selected as the reference point, and the distance from the reference point P13a to the origin of the coordinate system is determined as the offset. At this time, the offset includes an offset DieShiftX in the X-axis direction and two partial offsets DieShiftY in the Y-axis direction, and the offset can be expressed as (DieShiftX, DieShiftY).

[0086] In other implementations of the present embodiment, the upper right, upper left, and lower right vertices of the reference chip can also be selected as the reference point, and the present application does not limit this.

[0087] Step S140, based on the offset, correcting the first position coordinates of the plurality of target chips to obtain the corrected second position coordinates.

[0088] In the present embodiment, the second position coordinates include the second position sub-coordinates (DieLeft nX', DieLeft nY') of the first vertex or the second position sub-coordinates (DieRight nX', DieRight nY') of the second vertex, and the second position coordinates can be uniformly expressed as (Die nX0, Die nY0), wherein Die nX0 = DieLeft nX' or Die nX0 = DieRight nX'; Die nY0 = DieLeft nY' or Die nY0 = DieRight nY'.

[0089] Optionally, when the reference point selected in step S130 is the first vertex, the corresponding step S140 can include:

[0090] Adding the first position sub-coordinates of the first vertex to the offset to obtain the second position sub-coordinates of the corrected first vertex.

[0091] Specifically, when the first position sub-coordinates of the first vertex are (DieLeft nX, DieLeft nY), the X-axis coordinate DieLeft nX in the first position sub-coordinates of the first vertex can be added to the X-axis partial offset DieShiftX, and the Y-axis coordinate DieLeft nY in the first position sub-coordinates of the first vertex can be added to the Y-axis partial offset DieShiftY, so as to obtain the second position sub-coordinates (DieLeft nX', DieLeft nY') of the corrected first vertex, wherein DieLeft nX' = DieLeft nX + DieShiftX + DieLeft nY' = DieLeft nY + DieShiftY.

[0092] Optionally, when the reference point selected in step S130 is the second vertex, the corresponding step S140 can include:

[0093] The first position sub-coordinate of the second vertex is added with the offset to obtain the second position sub-coordinate of the corrected second vertex.

[0094] Specifically, when the first position sub-coordinate of the second vertex is (DieRight nX, DieRight nY), the X-axis coordinate DieRight nX in the first position sub-coordinate of the second vertex is added with the X-axis part offset DieShiftX, and the Y-axis coordinate DieRight nY in the first position sub-coordinate of the second vertex is added with the Y-axis part offset DieShiftY, so as to obtain the second position sub-coordinate (DieRight nX', DieRight nY') of the corrected second vertex, wherein DieRight nX' = DieRight nX + DieShiftX; DieRight nY' = DieRight nY + DieShiftY. At this time, the corresponding corrected second position coordinate of the reference chip NO. 13 is (0, 0).

[0095] Step S150, based on the size of each target chip and the corresponding second position coordinate, determines the chip ID coordinate code of each target chip.

[0096] Optionally, step S150 includes:

[0097] The chip ID coordinate code of each target chip is determined according to the following formula:

[0098] ID nX = Die nX0 / width(nX);

[0099] ID nY = Die nY0 / height(nY);

[0100] Wherein, the ID coordinate code of the nth target chip is (ID nX, ID nY), the second position coordinate corresponding to the nth target chip is (Die nX0, Die nY0), width(nX) represents the length of the nth target chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

[0101] Since the center point of the layout coordinate system may not be at a vertex of the chip when determining the first position coordinates of the target chips, the X-axis coordinate of the first position coordinates may be a non-integer multiple of the length of the chip, and the Y-axis coordinate of the first position coordinates may be a non-integer multiple of the width of the chip. If the chip ID coordinate code is determined according to the first position coordinates and the chip size, the chip ID coordinate code determined may be a non-integer. Therefore, the embodiment of the present application adds an offset to the first position coordinates of each target chip to obtain second position coordinates, which is equivalent to taking a vertex of one of the target chips (i.e., a reference chip) as the center point. In this way, the X-axis coordinate of the second position coordinates of each target chip can be an integer multiple of the length of the chip, and the Y-axis coordinate of the second position coordinates of each target chip can be an integer multiple of the width of the chip. The X-axis coordinate Die nX0 of the second position coordinates divided by the length of the chip width (nX) and the Y-axis coordinate Die nY0 of the second position coordinates divided by the width of the chip height (nY) can both obtain an integer, so that the chip ID coordinate code of each target chip obtained finally can be an integer.

[0102] Figure 5 is a chip ID coordinate code diagram provided by the embodiment of the present application, as shown in Figure 5 the chip ID coordinate code corresponding to the target chip NO. 7 is (1, -1); the chip ID coordinate code corresponding to the target chip NO. 8 is (1, 0); the chip ID coordinate code corresponding to the target chip NO. 9 is (1, 1); the chip ID coordinate code corresponding to the target chip NO. 12 is (-1, 0); the chip ID coordinate code corresponding to the target chip NO. 13 is (0, 0); the chip ID coordinate code corresponding to the target chip NO. 18 is (-1, 0); and the chip ID coordinate code corresponding to the target chip NO. 19 is (-1, 1).

[0103] In step S160, the third position coordinates of the chip ID coordinate code of each target chip are determined based on the first position coordinates of each target chip and the preset encoding movement amount.

[0104] Specifically, the encoding movement can be set by a designer, including the encoding movement in the X-axis direction and the encoding movement in the Y-axis direction, and the encoding movement can be represented as (DieID nX, DieID nY). In the embodiment, the first position coordinates of each target chip include two position sub-coordinates of opposite vertices of the target chip boundary box, and when calculating the third position coordinates of the chip ID coordinate encoding, only one position sub-coordinate of the vertex needs to be selected. For example, when the first position sub-coordinate (DieLeft nX, DieLeft nY) of the first vertex is selected to calculate the third position coordinates, if the third position coordinates (Die nX1, Die nY1) of the chip ID coordinate encoding, then Die nX1 = DieLeft nX + DieID nX; Die nY1 = DieLeft nY + Die nY0); when the first position sub-coordinate (DieRight nX, DieRight nY) of the second vertex is selected to calculate the third position coordinates, if the third position coordinates (Die nX1, Die nY1) of the chip ID coordinate encoding, then Die nX1 = DieRight nX + DieID nX; Die nY1 = DieRight nY + Die nY0). The etching position of the chip ID coordinate encoding of each chip on the chip can be determined according to the determined third position coordinates.

[0105] In step S170, the chip ID layout is generated based on the chip ID coordinate encoding of each target chip and the corresponding third position coordinates.

[0106] In the embodiment, after determining the chip ID coordinate encoding of each target chip and the corresponding third position coordinates of the chip ID coordinate encoding, the related encoding information of the chip ID coordinate encoding can also be set and customized. The encoding information at least includes the encoding display bit number, the encoding base, the encoding font size, the encoding font type and the encoding font spacing. The encoding display bit number can be set to 3 bits, 4 bits, etc. as needed, and the front of the insufficient bit number is automatically filled with zero, for example, (0001, -0001), etc. The encoding base can be set to decimal, hexadecimal, and binary, etc. The encoding font size and the encoding font spacing will affect the position of the encoding display, and therefore, when setting, it is necessary to ensure that the chip ID encoding formed on the chip can be correctly displayed; and the encoding font type can be designed arbitrarily, which is not limited in the embodiment.

[0107] It should be noted that the chip ID layout generation in the prior art is usually realized by relying on EDA (Electronic Design Automation) paid software, for example, Virtuoso software can be realized by programming language, and the Label mapping arrangement function is built in the Tanner software, but this makes the layout designers limited to the EDA software, and the use cost of the software is increased. By using the above method provided by the embodiment of the application, the chip coordinates can be converted into a database by using open-source Python and Klayout software, and the chip ID layout data can be automatically generated by using the method combining database statistical processing and layout text conversion. The design requirements of the chip ID can be realized by editing and converting the text, and finally the text content can be converted into GDS layout data, which reduces the dependence of the designers on the EDA software, avoids the limitations of some EDA software on the chip ID design, reduces the demand cost of the EDA software, realizes the automatic generation of the chip ID layout with customization and low cost.

[0108] The following briefly describes how to use open-source Python and Klayout software to realize the above chip ID layout determination provided by the embodiment:

[0109] Step S201: An effective chip arrangement layout for which a chip ID needs to be made is prepared, and a specific GDS NO is used as a chip identification layer to represent the position and size of each chip.

[0110] Step S202: The.shape function in the klayout library is used to extract the actual coordinate positions of the two opposite corners of each effective chip in the chip identification layer, and Python is used to statistically convert the coordinate data into table data columns (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY) for easy calculation and conversion later.

[0111] Step S203: Based on the position coordinates (DieLeft nX, DieLeft nY, DieRight nX, DieRight nY) of each effective chip obtained in S202, the distances from the four corners of the effective chip to the center of the wafer (i.e., the origin of the coordinate system) are calculated, and the distances from the four corners to the origin of the coordinate system are calculated one by one. If the distances from the four corners of the chip boundary box to the origin of the coordinate system are all less than or equal to the radius of the wafer, the target chip of the effective chip is selected; if the distance from any one of the four corners to the origin of the coordinate system is greater than the radius of the wafer, the chip is not selected as the target chip, and the position coordinates corresponding to the chip are deleted from the table data column.

[0112] Step S204: Find the target chip closest to the wafer center in the layout as the reference chip, and obtain the actual coordinate value of the lower left corner of the reference chip, and set it as the offset amount (DieShiftX, DieShiftY) of the lower left corner of the reference chip relative to the wafer center.

[0113] Step S205: Add the offset amount (DieShiftX, DieShiftY) obtained in step S204 to the data table in step S202 using Python language respectively, to obtain the corrected chip position coordinates (Die nX0, Die nY0). That is, Die nX0 = DieLeft nX + DieShiftX; Die nY0 = DieLeft nY + DieShiftY.

[0114] Step S206: Divide the corrected chip position coordinates (Die nX0, Die nY0) by the length: X and the width: Y of the chip, that is, the width (nX) and the height (nY) of GDS: 101, and take the integer to obtain the decimal chip ID coordinate encoding (ID nX, ID nY) in sequence. At this time, the encoding (0, 0) is at the wafer center position.

[0115] Step S207: Set the display bit number of ID nX and ID nY to two digits, three digits, etc. by Python.zfill() function. Automatically fill zeros in front of insufficient bits.

[0116] Step S208: Adjust the starting position of the chip ID on the wafer by adding or subtracting the maximum or minimum value of ID nX and ID nY to the chip ID generated in step S206, that is, ID nX + / - min / max (ID nX), ID nY + / - min / max (ID nY).

[0117] Step S209: The ID nX and ID nY generated in step S207 or step S208 can be converted to decimal, hexadecimal, and any other base by using Python functions, such as example (AF, FF). Converting the base can reduce the number of bits of the chip ID. For example, the decimal 255 of three digits can be represented by the hexadecimal FF of two digits, which reduces the size of the chip ID occupying the position on the chip by one bit.

[0118] Step S210: prepare the chip encoding layout font, generate a DIE_ID_Label GDS file. The file name is not limited, and each cell in the file has a font pattern corresponding to the cell name. The cell has two layers, GDS: 1 / 0 is used to draw the font pattern, and the form of the font pattern is not required. Layer GDS: 2 / 0 is used to draw the spacing of a single chip ID font. Figure 6 is a schematic diagram of a chip ID encoding font layout file provided by an embodiment of the present application, as Figure 3 shown, the example GDS file has a total of 17 cells (unit cells), top cell: all contains all ID fonts, this embodiment takes 16 as an example, so there are 0-F 16 characters, such as Figure 3 -①. There are two layers as Figure 3 -②, Figure 3 -③ and 3-④ are font examples, cell 0 (cell 0) is the layout of using GDS: 1 / 0 to draw the number 0, and GDS: 2 / 0 is used as the boundary of the font spacing. Cell F (cell F) is the layout of using GDS: 1 / 0 to draw the number F, and GDS: 2 / 0 is used as the boundary of the font spacing. All character cells need to be embedded into topcell: all, and arranged in order, as Figure 3 -⑤, the spacing of each font is GDS: 2 / 0 boundary, so the spacing between the chip ID fonts can be adjusted according to the size of the GDS: 2 / 0 rectangular box. The specific number or letter layout pattern under the cell name is not limited, and can be designed according to the needs, and is not limited to any font format in any EDA software.

[0119] Step S211: The final required ID nX and ID nY values formed before step S210 are called by the load_from_file function in the Klayout library to call the DIE_ID_Label GDS file prepared in step S210. The gen.TextGenerator() function of the Klayout library is used to create a text generator, and the text generator gen is used to create the text area of ID nX and ID nY region=gen.text(Die_ID, ly.dbu, mag).moved(xy), wherein Die_ID is used to obtain the position coordinates of the corrected chip, ly.dbu represents the design unit, mag represents the magnification of the font, which affects the size of the generated text, and move moves the text generated by region to the appropriate position according to the given offset, to ensure the correct display of the chip ID on the chip, so as to realize the position setting of the chip ID layout in the chip as required.

[0120] Step S212: Using the klayout library's `.Shape().insert(region)` function, insert the moved text object `region` into the specified layer. Then, use `Python.apply()` to apply the text generator function to each row of the data frame created before step S211, thus adding a chip ID to each chip.

[0121] Step S213: Use the Python.write() function to write the modified layout object to the GDS file, ultimately forming the DIE ID layout data for all chips on the entire wafer, in the universal .gds format. GDS format files can be readily applied to any EDA software. The Pythonpd.pivot_table function converts the final set ID nX and ID nY into a chip ID mapping Excel file with rows of Die_ID nX and columns of Die_ID nY, facilitating the location and arrangement of valid chips during product testing.

[0122] Based on the same inventive concept, embodiments of the present invention also provide a chip ID layout determination device for determining the chip ID layout. Figure 7 This is a structural block diagram of a chip ID layout determination device provided in an embodiment of the present invention, as shown below. Figure 7 As shown, the device includes a chip selection module 710, a coordinate determination module 720, an offset determination module 730, a coordinate correction module 740, an ID encoding determination module 750, an encoding coordinate determination module 760, and an ID layout determination module 770.

[0123] The chip selection module 710 is used to select multiple non-test chips located within the wafer boundary line from the chip layout as target chips, wherein the wafer boundary line is the outer edge contour line of the wafer with the center point of the chip layout as the midpoint;

[0124] The coordinate determination module 720 is used to determine the first position coordinates of multiple target chips based on a pre-established layout coordinate system. The layout coordinate system is a two-dimensional coordinate system established with the center point of the chip layout as the origin.

[0125] The offset determination module 730 is used to select the target chip closest to the origin of the coordinate system from multiple target chips as the reference chip, and to determine the offset of the reference chip relative to the origin of the coordinate system.

[0126] The coordinate correction module 740 is used to correct the first position coordinates of multiple target chips based on the offset to obtain the corrected second position coordinates.

[0127] The ID code determination module 750 is configured to determine a chip ID coordinate code of each target chip based on the size of each target chip and the corresponding second position coordinate.

[0128] The encoded coordinate determination module 760 is configured to determine a third position coordinate of the chip ID coordinate code of each target chip based on the first position coordinate of each target chip and a preset encoding movement amount.

[0129] The ID layout determination module 770 is configured to generate a chip ID layout based on the chip ID coordinate code of each target chip and the corresponding third position coordinate.

[0130] Optionally, the chip selection module 710 is further configured to:

[0131] provide a chip arrangement layout, the chip arrangement layout being an arrangement layout of chip boundary boxes that are designed in advance based on chip sizes, and the chip arrangement layout including arrangement of boundary boxes of effective chips for exposure and invalid chips for testing;

[0132] extract an arrangement layout of boundary boxes of all effective chips from the chip arrangement layout to obtain an effective chip arrangement layout;

[0133] select, from the effective chip arrangement layout, a chip whose four vertices of the chip boundary box are located within the wafer boundary line as a target chip.

[0134] Optionally, the first position coordinate of the target chip includes first position sub-coordinates of a first vertex and a second vertex of the target chip boundary box, and the first vertex and the second vertex are two opposite vertices of the target chip boundary box.

[0135] Optionally, the offset determination module 730 is further configured to:

[0136] determine a minimum distance from each target chip to the origin of the coordinate system based on the first position coordinate of each target chip;

[0137] select a target chip with the minimum distance to the origin of the coordinate system as a reference chip.

[0138] Optionally, the offset determination module 730 is further configured to:

[0139] select the first vertex or the second vertex of the boundary box of the reference chip as a reference point, and determine a distance from the reference point to the origin of the coordinate system as the offset.

[0140] Optionally, the second position coordinate includes a second position sub-coordinate of the first vertex or the second vertex, and the coordinate correction module 740 is further configured to:

[0141] When the reference point is the first vertex, the first position sub-coordinate of the first vertex is added with the offset to obtain a second position sub-coordinate of the corrected first vertex;

[0142] When the reference point is the second vertex, the first position sub-coordinate of the second vertex is added with the offset to obtain a second position sub-coordinate of the corrected second vertex.

[0143] Optionally, the ID code determination module 750 is further configured to:

[0144] The chip ID coordinate code of each chip is determined according to the following formula:

[0145] ID nX = Die nX0 / width(nX);

[0146] ID nY = Die nY0 / height(nY);

[0147] wherein the ID coordinate code of the nth chip is (ID nX, ID nY), the second position coordinate corresponding to the nth chip is (Die nX0, Die nY0), width(nX) represents the length of the nth chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

[0148] The specific details of the chip ID layout determination method used in the above determination device can be understood as corresponding to the relevant description and effects in the above-mentioned chip ID layout determination method embodiment, which will not be repeated here.

[0149] Based on the same inventive concept as the chip ID layout determination method described above, the present application also provides an electronic device, which can include a processor and a memory, wherein the processor and the memory can be connected to each other in communication through a bus or other means. The processor can be a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, or combinations thereof. The memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs and modules, such as program instructions / modules corresponding to the chip ID layout determination method in the embodiments of the present application. The processor executes various functions and data processing of the processor by running the non-transitory software programs, instructions and modules stored in the memory, that is, implements the chip ID layout determination method in the above method embodiments.

[0150] The memory can include a program storage area and a data storage area, wherein the program storage area can store an operating system and at least one application required by a function; the data storage area can store data created by the processor, etc. In addition, the memory can include a high-speed random access memory, and can also include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. The one or more modules are stored in the memory, and when executed by the processor, perform the chip ID layout determination method in the embodiments shown. Figure 1 The chip ID layout determination method in the embodiments shown.

[0151] The above electronic device can correspond to the specific details of the embodiments shown Figure 1 The corresponding related descriptions and effects can be understood, and will not be repeated here.

[0152] Based on the same inventive concept as the chip ID layout determination method, the present application also provides a computer-readable storage medium, which stores computer instructions, and the computer program instructions are used to make a computer execute the chip ID layout determination method in the above embodiments.

[0153] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiment methods. The storage medium can be a read-only memory (ROM), a random access memory (RAM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD), etc. The storage medium can also include a combination of the above-mentioned types of memories.

[0154] The technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages: The chip ID layout determination method, device, equipment and storage medium provided by the embodiments of the present application select non-test chips located in the wafer boundary line from the chip arrangement layout as target chips in the chip arrangement layout that need to form chip IDs. The arrangement manner of the target chips is closer to the arrangement manner of the chips that need to generate IDs in the actually manufactured wafer, which effectively avoids the problem of inaccurate chip ID layout caused by the inconsistency between the chip arrangement layout and the arrangement manner of the chips that need to form IDs on the actually manufactured wafer in the traditional method. At the same time, the position coordinates of each target chip are corrected according to the offset of the reference chip relative to the origin of the coordinate system, which ensures the accuracy of the position coordinates of each chip, thereby improving the accuracy of the chip ID layout. Moreover, the method can automatically generate the corresponding chip ID layout according to the arrangement manner of the chips that need to generate IDs in the actually manufactured wafer, without the need to manually adjust the generated chip ID layout according to the arrangement manner of the chips on the actually manufactured wafer, which significantly reduces the manufacturing cost and time cost, improves the production efficiency, and can well adapt to chips of different sizes and different arrangement manners, without the need to substantially modify or adjust the method itself, so as to efficiently realize the accurate generation of chip ID layouts of various MEMS product chips, and exhibit high flexibility and applicability.

[0155] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the present specification.

[0156] Similarly, it should be understood that, in order to simplify this disclosure and aid in understanding one or more of the various aspects of the invention, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof. However, this method of disclosure should not be construed as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the following claims, inventive aspects lie in fewer than all features of a single foregoing disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into this detailed description, wherein each claim itself is a separate embodiment of the invention.

[0157] It should be noted that the above embodiments are illustrative of the invention and not restrictive of the invention, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method for determining a chip ID layout, characterized in that, Applied to electronic devices, the method includes: Multiple non-test chips located within the wafer boundary line are selected as target chips from the chip layout diagram, wherein the wafer boundary line is the outer edge contour line of the wafer with the center point of the chip layout diagram as the midpoint; Based on a pre-established layout coordinate system, the first position coordinates of multiple target chips are determined. The layout coordinate system is a two-dimensional coordinate system established with the center point of the chip layout as the origin. Select the target chip closest to the origin of the coordinate system from among the multiple target chips, and use it as the reference chip; and determine the offset of the reference chip relative to the origin of the coordinate system. Based on the offset, the first position coordinates of the multiple target chips are corrected to obtain the corrected second position coordinates; Based on the size of each target chip and the corresponding second position coordinates, the chip ID coordinate code of each target chip is determined; Based on the first position coordinates of each target chip and the preset coded movement amount, the third position coordinates of the chip ID coordinate code of each target chip are determined; A chip ID layout is generated based on the chip ID coordinate encoding of each target chip and the corresponding third position coordinates; The step of determining the chip ID coordinate encoding for each chip based on its size and the corresponding second position coordinates includes: The chip ID coordinate code for each chip is determined using the following formula: ID nX=Die nX0 / width(nX); ID nY=Die nY0 / height(nY); The ID coordinates of the nth chip are encoded as (ID nX, ID nY), and the second position coordinates corresponding to the nth chip are (Die nX0, Die nY0). width(nX) represents the length of the nth chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

2. The determination method according to claim 1, characterized in that, The first position coordinates of the target chip include the first position sub-coordinates of the first vertex and the second vertex of the target chip bounding box, wherein the first vertex and the second vertex are two diagonal vertices of the target chip bounding box.

3. The determination method according to claim 2, characterized in that, Selecting the target chip closest to the origin of the coordinate system from among the multiple target chips as the reference chip includes: Based on the first position coordinates of each target chip, determine the minimum distance from each target chip to the origin of the coordinate system; The target chip with the smallest minimum distance to the origin of the coordinate system is selected as the reference chip.

4. The determination method according to claim 3, characterized in that, Determining the offset of the reference chip relative to the origin of the coordinate system includes: Select the first vertex or the second vertex of the bounding box of the reference chip as the reference point, and determine the distance from the reference point to the origin of the coordinate system as the offset.

5. The determination method according to claim 4, characterized in that, The second position coordinates include the second position sub-coordinates of the first vertex or the second vertex. The step of correcting the first position coordinates of the multiple target chips based on the offset to obtain the corrected second position coordinates includes: When the reference point is the first vertex, the first position sub-coordinate of the first vertex is added to the offset to obtain the corrected second position sub-coordinate of the first vertex; When the reference point is the second vertex, the first position sub-coordinate of the second vertex is added to the offset to obtain the corrected second position sub-coordinate of the second vertex.

6. The determination method according to claim 1, characterized in that, The selection of multiple non-test chips located within the wafer boundary line from the chip layout diagram as target chips includes: Extract the bounding box layout of all valid chips from the preset chip layout to obtain the valid chip layout, wherein the chip layout includes the arrangement of the bounding boxes of the valid chips for exposure and the invalid chips for testing. From the effective chip layout diagram, the effective chip whose four vertices are all located within the wafer boundary line is selected as the target chip.

7. A device for determining a chip ID layout, characterized in that, include: The chip selection module is used to select multiple non-test chips located within the wafer boundary line as target chips from the chip layout diagram, wherein the wafer boundary line is the outer edge contour line of the wafer with the center point of the chip layout diagram as the midpoint; The coordinate determination module is used to determine the first position coordinates of multiple target chips based on a pre-established layout coordinate system, wherein the layout coordinate system is a two-dimensional coordinate system established with the center point of the chip layout as the origin. The offset determination module is used to select the target chip closest to the origin of the coordinate system from among the multiple target chips as the reference chip, and to determine the offset of the reference chip relative to the origin of the coordinate system. A coordinate correction module is used to correct the first position coordinates of the multiple target chips based on the offset to obtain the corrected second position coordinates. The ID encoding determination module is used to determine the chip ID coordinate encoding of each target chip based on the size of each target chip and the corresponding second position coordinates; The encoding coordinate determination module is used to determine the third position coordinate of the chip ID coordinate encoding of each target chip based on the first position coordinate of each target chip and a preset encoding movement amount; The ID layout determination module is used to generate a chip ID layout based on the chip ID coordinate encoding of each target chip and the corresponding third position coordinate; The ID encoding determination module is used for: The chip ID coordinate code for each chip is determined using the following formula: ID nX=Die nX0 / width(nX); ID nY=Die nY0 / height(nY); The ID coordinates of the nth chip are encoded as (ID nX, ID nY), and the second position coordinates corresponding to the nth chip are (Die nX0, Die nY0). width(nX) represents the length of the nth chip along the X direction of the layout coordinate system, and height(nY) represents the width of the nth chip along the Y direction of the layout coordinate system.

8. An electronic device, characterized in that, include: A memory and a processor are communicatively connected, the memory stores computer instructions, and the processor executes the computer instructions to perform the chip ID layout determination method as described in any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions for causing the computer to execute the chip ID layout determination method according to any one of claims 1 to 6.

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