Display panel and display device

Abstract

The invention discloses a display panel and a display device.The display panel comprises a plurality of low-potential lines, a plurality of high-potential lines, a gate drive circuit and a first test circuit, the first test circuit is connected with the gate drive circuit through at least two of the low-potential lines, at least two paths of low-potential signals can be provided for the gate drive circuit, and the gate drive circuit is connected with the high-potential lines. Compared with a gate drive circuit which needs one path of low-potential signal, the gate drive circuit which needs two paths of low-potential signals can be met, so that the problem of voltage matching between the first test circuit and the gate drive circuit is relieved, and normal testing is facilitated.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In order to ensure the quality of the display panel, it is usually necessary to configure a corresponding test circuit to check various technical indicators of the display panel.

[0003] However, with the development of display technology, existing test circuits can no longer meet test requirements. Summary of the invention

[0004] The present application provides a display panel and a display device to alleviate the technical problem of voltage matching between a test circuit and a gate drive circuit.

[0005] In a first aspect, the present application provides a display panel, which includes a plurality of low potential lines, a plurality of high potential lines, a gate drive circuit, and a first test circuit, each gate drive circuit being connected to at least two of the plurality of low potential lines and one of the plurality of high potential lines; the first test circuit being connected to the plurality of low potential lines and the plurality of high potential lines.

[0006] In a second aspect, the present application provides a display device, which includes the above-mentioned display panel.

[0007] In the display panel and display device provided by the present application, the first test circuit is connected to the gate driving circuit through at least two of the multiple low-potential lines, and can provide at least two low-potential signals for the gate driving circuit. Compared with the gate driving circuit that requires one low-potential signal, this can meet the gate driving circuit that requires two low-potential signals, thereby alleviating the voltage matching problem between the first test circuit and the gate driving circuit, which is conducive to the normal progress of the test. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0009] Figure 1 A schematic diagram of the first structure of a display panel provided in an embodiment of the present application.

[0010] Figure 2 A second structural schematic diagram of a display panel provided in an embodiment of the present application.

[0011] Figure 3 A schematic diagram of the structure of a gate drive circuit provided in an embodiment of the present application.

[0012] Figure 4 A circuit schematic diagram of the stage transmission module provided in an embodiment of the present application.

[0013] Figure 5 A circuit schematic diagram of the output module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0014] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0015] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of technical features indicated. Therefore, the features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0016] After completing the array process, OLED evaporation (EL) and encapsulation (TFE), or before entering the module process, the panel in the cell state needs to be tested online (CT). CT includes aging test and functional test, the purpose of which is to improve various functional defects such as bright spots caused by thin film transistor (TFT) leakage, and to identify and intercept defects in the front-end process.

[0017] In addition, after the module manufacturing process is completed, final (FT) testing is required to further clarify the module and product yield.

[0018] In the related art, each gate drive circuit (GOA) only needs one high potential signal and one low potential signal, and the CT and FT designs in the related art can meet the needs of the gate drive circuit. However, with the development of display technology, each gate drive circuit needs one high potential signal and at least two low potential signals, which makes the CT and FT designs in the related art unable to meet the needs.

[0019] Based on the above premise, according to the different working characteristics (IGZO, LTPS) of the driving tube (DTFT), conversion tube (STFT) and indium gallium zinc oxide transistor (GTFT) in the LTPO Pixel circuit, the voltage output mode of the IC end, and on the basis of satisfying the work of GOA at the same time, the voltage connection mode in the pad (Pad) in the CT is designed to ensure the voltage supply compatibility of CT, FT and GOA.

[0020] This embodiment provides a display panel. Figures 1 to 5 ,like Figure 1 As shown, the display panel includes a plurality of low potential lines, a plurality of high potential lines, a gate drive circuit 100 and a first test circuit 200, each gate drive circuit 100 is connected to at least two of the plurality of low potential lines and one of the plurality of high potential lines; the first test circuit 200 is connected to the plurality of low potential lines and the plurality of high potential lines.

[0021] It can be understood that, in the display panel provided in this embodiment, the first test circuit 200 is connected to the gate driving circuit 100 through at least two of the multiple low-potential lines, and can provide at least two low-potential signals for the gate driving circuit 100. Compared with the gate driving circuit 100 which requires one low-potential signal, this can meet the gate driving circuit 100 that requires two low-potential signals, thereby alleviating the voltage matching problem between the first test circuit 200 and the gate driving circuit 100, which is conducive to the normal progress of the test.

[0022] It should be noted that, a plurality of low potential lines, such as the first low potential line NVGL1, the second low potential line PVGL1, the third low potential line NVGL2, and the fourth low potential line PVGL2, each low potential line is used to transmit a low potential signal, and the low potential signal can turn on the transistor of the P channel or turn off the transistor of the N channel. A plurality of high potential lines, such as the first high potential line PVGH and the second high potential line NVGH, each high potential line is used to transmit a high potential signal, and the high potential signal can turn off the transistor of the P channel or turn on the transistor of the N channel. The first test circuit 200 is used to implement the aging test and functional test of the CELL state panel.

[0023] In some embodiments, such as Figure 1 As shown, the gate drive circuit 100 includes at least one of a first gate drive circuit 103, a second gate drive circuit 102 and a third gate drive circuit 101, the first gate drive circuit 103 is connected to the first high potential line PVGH, the second low potential line PVGL1 and the fourth low potential line PVGL2; the second gate drive circuit 102 is connected to the second high potential line NVGH, the first low potential line NVGL1 and the third low potential line NVGL2; the third gate drive circuit 101 is connected to the first high potential line PVGH, the second low potential line PVGL1 and the fourth low potential line PVGL2.

[0024] It should be noted that this embodiment can provide one high potential signal and two different low potential signals for each of the first gate driving circuit 103, the second gate driving circuit 102 and the third gate driving circuit 101 to meet the testing requirements of each gate driving circuit 100.

[0025] Among them, Figure 2 As shown, the first gate driving circuit 103 is used to output a first gate driving signal with a negative pulse, namely Pscan, and the first gate driving signal is used to drive a P-channel transistor in a pixel circuit. The second gate driving circuit 102 is used to output a second gate driving signal with a positive pulse, namely Nscan, and the second gate driving signal is used to drive an N-channel transistor in a pixel circuit. The third gate driving circuit 101 is used to output a light emitting control signal, namely EM, and the light emitting control signal is used to drive a light emitting control transistor in a pixel circuit.

[0026] In some embodiments, such as Figure 1 and Figure 2 As shown, the first test circuit 200 includes a first test terminal D1, a second test terminal D2, a third test terminal D3, a fourth test terminal D4, a fifth test terminal D5 and a sixth test terminal D6. The first test terminal D1 is connected to the first high potential line PVGH; the second test terminal D2 is connected to the second high potential line NVGH; the third test terminal D3 is connected to the first low potential line NVGL1; the fourth test terminal D4 is connected to the second low potential line PVGL1; the fifth test terminal D5 is connected to the third low potential line NVGL2; and the sixth test terminal D6 is connected to the fourth low potential line PVGL2.

[0027] It should be noted that, in this embodiment, each test end may be a pad for testing.

[0028] In some embodiments, such as Figure 1 and Figure 2 As shown, the first test terminal D1 to the sixth test terminal D6 are arranged in sequence, and the first test circuit 200 further includes a seventh test terminal D7, which is located between the second test terminal D2 and the third test terminal D3.

[0029] It should be noted that the seventh test terminal D7 is provided between the second test terminal D2 and the third test terminal D3, so that the second test terminal D2 and the third test terminal D3 are electrically isolated to avoid mutual interference or short circuit. The seventh test terminal D7 can be an idle pad.

[0030] In some embodiments, such as Figure 1 and Figure 2 As shown, the first test circuit 200 also includes some other pads, such as two pads for transmitting clock signals, namely PCK, and an idle pad, namely D15.

[0031] In some embodiments, such as Figure 1 and Figure 2As shown, the display panel also includes a first connection line PVGH1, a second connection line NVGH1, a third connection line VGL2, a fourth connection line VGL1 and a second test circuit 300. The second test circuit 300 is connected to the first test terminal D1 through the first connection line PVGH1, is connected to the second test terminal D2 through the second connection line NVGH1, is connected to the fifth test terminal D5 and the sixth test terminal D6 through the third connection line VGL2, and is connected to the third test terminal D3 and the fourth test terminal D4 through the fourth connection line VGL1.

[0032] It should be noted that the second test circuit 300 is not only used for performing the final test, but also can be used to provide corresponding low potential signals and high potential signals for the first test circuit 200 .

[0033] In some embodiments, such as Figure 1 and Figure 2 As shown, the second test circuit 300 includes an eighth test terminal D8, a ninth test terminal D9, a tenth test terminal D10 and an eleventh test terminal D11, the eighth test terminal D8 is connected to the first connection line PVGH1; the ninth test terminal D9 is connected to the second connection line NVGH1; the tenth test terminal D10 is connected to the third connection line VGL2; and the eleventh test terminal D11 is connected to the fourth connection line VGL1.

[0034] It should be noted that each test terminal in the present embodiment can be a pad for testing. The tenth test terminal D10 can provide two low potential signals for the fifth test terminal D5 and the sixth test terminal D6 through the third connection line VGL2, and the eleventh test terminal D11 can provide two low potential signals for the third test terminal D3 and the fourth test terminal D4 through the fourth connection line VGL1, so that the number of pads used in the second test circuit 300 does not increase.

[0035] In some embodiments, such as Figure 1 and Figure 2 As shown, the eighth test terminal D8 to the eleventh test terminal D11 are arranged in sequence, and the second test circuit 300 further includes a twelfth test terminal D12, which is located between the ninth test terminal D9 and the tenth test terminal D10.

[0036] It should be noted that the twelfth test terminal D12 is provided between the ninth test terminal D9 and the tenth test terminal D10, so that the ninth test terminal D9 and the tenth test terminal D10 are electrically isolated to avoid mutual interference or short circuit. The twelfth test terminal D12 can be an idle pad.

[0037] In some embodiments, such as Figure 1 and Figure 2As shown, the second test circuit 300 also includes some other pads, such as four pads for transmitting clock signals, namely PCK, and an idle pad, namely D16.

[0038] In some embodiments, such as Figure 3 As shown, each gate drive circuit 100 includes a level transmission module 10 and an output module 20, the level transmission module 10 is connected to a high potential line and one of a plurality of low potential lines; the output module 20 is connected to the high potential line and another of a plurality of low potential lines; wherein the signal voltage transmitted by one of the plurality of low potential lines is different from the signal voltage transmitted by another of the plurality of low potential lines.

[0039] It should be noted that the high potential line is used to transmit a high potential signal, namely VGH, which can be transmitted through the first high potential line PVGH or the second high potential line NVGH. One of the multiple low potential lines is used to transmit a low potential signal, namely VGL11, and another of the multiple low potential lines is used to transmit a low potential signal, namely VGL12, and VGL11 is different from VGL12. VGL11 and VGL12 can be transmitted through two of the multiple low potential lines.

[0040] In some embodiments, such as Figure 3 and Figure 4 As shown, the stage transmission module 10 includes a first transistor T1 and a second transistor T2, wherein the first electrode of the first transistor T1 is connected to the high potential line, and the gate of the first transistor T1 is connected to the first control line; the first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1, the gate of the second transistor T2 is connected to the gate of the first transistor T1, and the second electrode of the second transistor T2 is connected to one of the multiple low potential lines.

[0041] It should be noted that the channel type of the first transistor T1 is different from the channel type of the second transistor T2. For example, the first transistor T1 is a P-channel transistor and the second transistor T2 is an N-channel transistor. The first control line is used to transmit the first control signal S1. The stage transmission module 10 is used to output a corresponding cascade signal COUT according to the first control signal S1. The cascade signal COUT can be transmitted to the shift registers of other stages, such as the shift register of the next stage, to realize the cascade between different shift registers.

[0042] In some embodiments, such as Figure 3 and Figure 5As shown, the output module 20 includes a third transistor T3 and a fourth transistor T4, the first electrode of the third transistor T3 is connected to the high potential line, and the gate of the third transistor T3 is connected to the second control line; the first electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the gate of the fourth transistor T4 is connected to the gate of the third transistor T3, and the second electrode of the fourth transistor T4 is connected to another one of the multiple low potential lines.

[0043] It should be noted that the channel type of the third transistor T3 is different from the channel type of the fourth transistor T4. For example, the third transistor T3 is a P-channel transistor and the fourth transistor T4 is an N-channel transistor. The second control line is used to transmit the second control signal S2. The output module 20 is used to output a corresponding gate drive signal GOUT according to the second control signal S2, and the gate drive signal GOUT is configured to be transmitted to the display area to drive the corresponding device.

[0044] In some of the embodiments, the present embodiment provides a display device, which includes the above-mentioned display panel.

[0045] It can be understood that, since the display device provided in this embodiment includes the above-mentioned display panel, the display device can also obtain the technical effect of the display panel, that is, the first test circuit 200 is connected to the gate drive circuit 100 through at least two of the multiple low-potential lines, and can provide at least two low-potential signals for the gate drive circuit 100. Compared with the gate drive circuit 100 that requires one low-potential signal, this can meet the gate drive circuit 100 that requires two low-potential signals, thereby alleviating the voltage matching problem between the first test circuit 200 and the gate drive circuit 100, which is conducive to the normal progress of the test.

[0046] It should be noted that the display panel may be, but is not limited to, an organic light emitting diode panel, and may also be an applicable micro light emitting diode panel or a mini light emitting diode panel.

[0047] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0048] The display panel and the display device provided in the embodiments of the present application are introduced in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: The display panel comprises: Multiple low potential lines and multiple high potential lines; a gate driving circuit, each of the gate driving circuits being connected to at least two of the plurality of low potential lines and one of the plurality of high potential lines; A first test circuit is connected to the plurality of low potential lines and the plurality of high potential lines.

2. The display panel according to claim 1, characterized in that: The plurality of low potential lines include a first low potential line, a second low potential line, a third low potential line and a fourth low potential line, and the plurality of high potential lines include a first high potential line and a second high potential line; the gate drive circuit includes: a first gate driving circuit, wherein the first gate driving circuit is connected to the first high potential line, the second low potential line, and the fourth low potential line; a second gate driving circuit, the second gate driving circuit being connected to the second high potential line, the first low potential line and the third low potential line; A third gate driving circuit is connected to the first high potential line, the second low potential line, and the fourth low potential line.

3. The display panel according to claim 2, characterized in that: The first test circuit comprises: A first test end, wherein the first test end is connected to the first high potential line; A second test terminal, the second test terminal being connected to the second high potential line; a third test terminal connected to the first low potential line; a fourth test terminal connected to the second low potential line; a fifth test terminal connected to the third low potential line; A sixth test terminal is connected to the fourth low potential line.

4. The display panel according to claim 3, characterized in that: The first test terminal to the sixth test terminal are arranged in sequence, and the first test circuit further includes a seventh test terminal, and the seventh test terminal is located between the second test terminal and the third test terminal.

5. The display panel according to claim 3, characterized in that: The display panel further includes: A first connecting line, a second connecting line, a third connecting line and a fourth connecting line; A second test circuit, wherein the second test circuit is connected to the first test terminal through the first connecting line, is connected to the second test terminal through the second connecting line, is connected to the fifth test terminal and the sixth test terminal through the third connecting line, and is connected to the third test terminal and the fourth test terminal through the fourth connecting line.

6. The display panel according to claim 5, characterized in that: The second test circuit comprises: an eighth test end, the eighth test end being connected to the first connecting line; a ninth test end connected to the second connecting line; a tenth test end connected to the third connecting line; An eleventh testing end, the eleventh testing end is connected to the fourth connecting line.

7. The display panel according to claim 6, characterized in that: The eighth test terminal to the eleventh test terminal are arranged in sequence, and the second test circuit further includes a twelfth test terminal, and the twelfth test terminal is located between the ninth test terminal and the tenth test terminal.

8. The display panel according to any one of claims 1 to 7, characterized in that: Each of the gate drive circuits comprises: A level transmission module, the level transmission module is connected to one of the high potential lines and one of the plurality of low potential lines; an output module, the output module being connected to the high potential line and another one of the plurality of low potential lines; The signal voltage transmitted by one of the plurality of low-potential lines is different from the signal voltage transmitted by another of the plurality of low-potential lines.

9. The display panel according to claim 8, characterized in that: The level transmission module comprises: a first transistor, wherein a first electrode of the first transistor is connected to the high potential line, and a gate of the first transistor is connected to a first control line; a second transistor, wherein a first electrode of the second transistor is connected to a second electrode of the first transistor, a gate of the second transistor is connected to a gate of the first transistor, and a second electrode of the second transistor is connected to one of the plurality of low potential lines; The output module comprises: a third transistor, wherein a first electrode of the third transistor is connected to the high potential line, and a gate of the third transistor is connected to the second control line; A fourth transistor, wherein a first electrode of the fourth transistor is connected to a second electrode of the third transistor, a gate of the fourth transistor is connected to a gate of the third transistor, and a second electrode of the fourth transistor is connected to another one of the plurality of low potential lines.

10. A display device, characterized in that: The display device comprises the display panel according to any one of claims 1 to 9.

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