Display device

Abstract

A display device according to an exemplary embodiment of the present disclosure includes: a substrate including a non-display area and a display area, the non-display area including a bending area and a pad area; a gate driver disposed in the non-display area; a driving integrated circuit disposed in the pad region; a plurality of signal lines disposed in the bending region and connecting the driving integrated circuit and the gate driver to each other; and at least one protection line provided at an end portion of the bending region in the width direction. In a display device according to an exemplary embodiment of the present disclosure, one end of at least one protection line may be connected to a driving integrated circuit.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0123509 filed in the Korean Intellectual Property Office on September 15, 2023, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device. Background Art

[0004] With the advent of the information age, the field of display devices that visually express electrical information signals has been rapidly developed, and research continues to improve the performance of various display devices, such as thin thickness, light weight, and low power consumption.

[0005] Among various display devices, the light-emitting display device is a self-luminous display device, so that a separate light source is not required. Therefore, the light-emitting display device can be manufactured to have a light weight and a small thickness. Since the light-emitting display device is driven at a low voltage, the light-emitting display device is advantageous not only in terms of power consumption, but also in terms of color realization, response speed, viewing angle, and contrast ratio (CR). Therefore, the light-emitting display device is expected to be applied to various fields. Summary of the invention

[0006] An object to be achieved by the present disclosure is to provide a display device that suppresses cracks generated in a wiring provided in a bent region.

[0007] Another object to be achieved by the present disclosure is to provide a display device that senses a crack generated in a wiring disposed in a bending region.

[0008] The objects of the exemplary embodiments of the present disclosure are not limited to the above objects, and other objects not mentioned above may be clearly understood by those skilled in the art through the following description.

[0009] A display device according to an exemplary embodiment of the present disclosure includes: a substrate including a non-display area and a display area, the non-display area including a bending area and a pad area; a gate driver arranged in the non-display area; a driving integrated circuit arranged in the pad area; a plurality of signal lines arranged in the bending area and connecting the driving integrated circuit and the gate driver to each other; and at least one protection line arranged at an end portion in a width direction of the bending area.

[0010] In the display device according to the exemplary embodiment of the present disclosure, one end of at least one protection line may be connected to the driving integrated circuit.

[0011] Additional details of example embodiments are included in the detailed description and accompanying drawings.

[0012] According to an exemplary embodiment of the present disclosure, a crack suppression circuit is applied to a display device to provide a low-power display device with improved reliability.

[0013] According to an exemplary embodiment of the present disclosure, a crack detection wiring is applied to a non-display area of ​​a display device to sense defects in advance, so that a display device robust to reliability can be provided.

[0014] The effects of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned above will be apparently understood by those of ordinary skill in the art through the following description.

[0015] The above-mentioned objects to be achieved by the present disclosure, means for achieving the objects, and effects of the present disclosure do not indicate essential features of the claims, and therefore, the scope of the claims is not limited to the disclosed contents of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a diagram of a display device according to an exemplary embodiment of the present disclosure;

[0018] Figure 2 is a circuit diagram of a display device according to an exemplary embodiment of the present disclosure;

[0019] Figure 3 is a plan view of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 4 is a cross-sectional view of one pixel provided in a display area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 5 yes Figure 3 A graph of region A;

[0022] Figure 6 It is along Figure 3 A cross-sectional view taken along line BB';

[0023] Figure 7 According to another exemplary embodiment of the present disclosure Figure 3 A cross-sectional view taken along line BB';

[0024] Figure 8 According to an exemplary embodiment of the present disclosure, Figure 3 A cross-sectional view taken along line CC';

[0025] Fig. 9According to another exemplary embodiment of the present disclosure Figure 3 A cross-sectional view taken along line C-C';

[0026] Fig.10 According to an exemplary embodiment of the present disclosure Fig. 9 A plan view of area D;

[0027] Fig.11 is a plan view of a plurality of signal lines according to an exemplary embodiment of the present disclosure; and

[0028] Fig.12 yes Fig.11 Cross-sectional view along line EE'. DETAILED DESCRIPTION

[0029] By referring to the exemplary embodiments described in detail below together with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are only provided by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0030] The shapes, sizes, proportions, angles, quantities, etc. shown in the drawings describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, the same reference numerals generally represent the same elements. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "comprising" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0031] Even if not explicitly stated, parts are interpreted as including ordinary error ranges.

[0032] When terms such as “on,” “above,” “below,” and “beside” are used to describe a positional relationship between two parts, one or more parts may be located between the two parts unless these terms are used together with the terms “immediately” or “directly.”

[0033] When terms such as "after," "continuing to," "next," and "before" are used to describe a time series order relationship, the order may not be sequential unless these terms are used with the terms "immediately" or "directly."

[0034] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0035] When describing the components of the exemplary embodiments of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are used to distinguish one component from another component, but the nature, order or number of the components are not limited by the terms. When a component is "engaged", "coupled" or "connected" to another component, the component may be directly engaged or connected to the other component. However, unless otherwise specifically stated, it should be understood that a third component may be interposed between components that may be indirectly engaged or connected.

[0036] It should be understood that “at least one” includes all combinations of one or more associated components. For example, “at least one of a first component, a second component, and a third component” means not only including the first component, the second component, or the third component, but also including all combinations of two or more of the first component, the second component, and the third component.

[0037] In this specification, "display device" may include narrow display devices such as liquid crystal modules (LCM), organic light emitting diode modules (OLED modules) and quantum dot modules (including display panels and drivers for driving display panels). In addition, "display device" may also include: a complete set of electronic devices or complete sets of equipment (or complete sets of devices) as complete products or final products such as notebook computers, televisions or computer displays including LCM, OLED modules, QD modules, etc., including automotive display devices or equipment display devices of another type of vehicle, and mobile electronic devices including smart phones or electronic tablets.

[0038] Accordingly, the display device disclosed herein may include not only the display device itself in a narrow sense, such as LCM, OLED module, QD module, etc., but also application products or complete sets of equipment having LCM, OLED module, QD module, etc. as final consumer devices.

[0039] In addition, in some cases, an LCM, an OLED module, or a QD module consisting of a display panel and a driver can be expressed as a "display device" in a narrow sense, and an electronic device as a complete product including an LCM, an OLED module, and a QD module can be expressed as a "set of equipment". For example, a display device in a narrow sense includes a liquid crystal (LCD) display panel, an OLED display panel, or a quantum dot display panel and a source PCB as a controller for driving the display panel. In contrast, a set of equipment can be a concept that further includes a set of PCBs, which are set controllers electrically connected to the source PCB to control the entire set of equipment.

[0040] As the display panel used in the exemplary embodiment of the present disclosure, any type of display panel, such as a liquid crystal display panel, an organic light emitting diode (OLED) display panel, a quantum dot (QD) display panel, and an electroluminescent display panel, can be used. The display panel of the exemplary embodiment is not limited to a specific display panel, wherein the frame is bent together with the flexible substrate for the organic light emitting diode (OLED) display panel and the backplane support structure thereunder. In addition, the display panel used for the display device according to the exemplary embodiment of the present disclosure is not limited to the shape or size of the display panel.

[0041] For example, when the display panel is an OLED display panel, the display panel may include a plurality of gate lines, a plurality of data lines, and pixels formed at the intersection of the gate lines and / or the data lines. In addition, the display panel may be configured to include: an array including thin film transistors as elements for selectively applying voltage to individual pixels; a light emitting diode layer on the array; and an encapsulation substrate or encapsulation layer disposed on the array to cover the light emitting diode layer. The encapsulation layer may protect the thin film transistor and the light emitting diode layer from external impacts, and may inhibit moisture or oxygen from penetrating into the light emitting diode layer. In addition, the layer formed on the array may include an inorganic light emitting layer, for example, a nano-sized material layer, quantum dots, and the like.

[0042] The features of various exemplary embodiments of the present disclosure may be coupled or combined with each other in part or as a whole and may be technically associated and operated in various ways, and the exemplary embodiments may be performed independently or in association with each other.

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the following drawings and exemplary embodiments. For the purpose of description, the scale of components shown in the drawings is different from the real scale, and thus the scale is not limited to the scale shown in the drawings.

[0044] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0045] Figure 1is a block diagram of a display device according to an exemplary embodiment of the present disclosure.

[0046] Reference Figure 1 , the display device 100 according to an exemplary embodiment of the present disclosure may include an image processor 151, a timing controller 152, a data driver 153, a gate driver 154, and a display panel DP.

[0047] At this time, the image processor 151 may output a data signal DATA supplied from the outside, a data enable signal DE, etc. The image processor 151 may output one or more of a vertical synchronization signal, a horizontal synchronization signal, and a clock signal in addition to the data enable signal DE.

[0048] The timing controller 152 is supplied with a data signal DATA from the image processor 151 and a driving signal including a data enable signal DE or a vertical synchronization signal, a horizontal synchronization signal, a clock signal, etc. The timing controller 152 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 154 and a data timing control signal DDC for controlling the operation timing of the data driver 153 based on the driving signal.

[0049] For example, the data driver 153 samples and latches the data signal DATA supplied from the timing controller 152 to convert the data signal into a gamma reference voltage and output the converted gamma reference voltage in response to the data timing control signal DDC supplied from the timing controller 152. The data driver 153 may output the data signal DATA through the data lines DL1 to DLn.

[0050] For example, the gate driver 154 may output a gate signal while shifting a level of a gate voltage in response to the gate timing control signal GDC supplied from the timing controller 152. The gate driver 154 may output the gate signal through the gate lines GL1 to GLm.

[0051] When the sub-pixel SP emits light in response to the data signal DATA supplied from the data driver 153 and the gate signal supplied from the gate driver 154, the display panel DP may display an image. Figure 2 and Figure 4 The detailed structure of the sub-pixel SP is described in detail.

[0052] Figure 2 is a circuit diagram of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure.

[0053] Reference Figure 2 , a sub-pixel of the display device 100 according to an exemplary embodiment of the present invention may include a switching transistor ST, a driving transistor DT, a compensation circuit 135 and a light emitting diode 120 .

[0054] The light emitting diode 120 may operate to emit light according to a driving current formed by the driving transistor DT.

[0055] The switching transistor ST may perform a switching operation so that a data signal supplied through the data line DL is stored in the capacitor Cst as a data voltage in response to a gate signal supplied through the gate line GL.

[0056] The driving transistor DT may operate in response to the data voltage stored in the capacitor Cst to allow a constant driving current to flow between the high potential power line VDD and the low potential power line GND.

[0057] The compensation circuit 135 is a circuit for compensating for a threshold voltage of the driving transistor DT, etc., and may include one or more thin film transistors and capacitors. The configuration of the compensation circuit 135 may vary according to a compensation method.

[0058] Figure 2 The sub-pixel shown in FIG. 1 is composed of a 2T (transistor) 1C (capacitor) structure including a switching transistor ST, a driving transistor DT, a capacitor Cst, and a light emitting diode 120. When a compensation circuit 135 is added, the sub-pixel can be configured in various forms such as 3T1C, 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, and 7T2C.

[0059] Figure 3 is a plan view of a display device according to an exemplary embodiment of the present disclosure.

[0060] Figure 3 A state in which the substrate 110 of the display device 100 according to an exemplary embodiment of the present disclosure is not bent is shown as an example.

[0061] exist Figure 3 In the figure, for convenience of description, among the components of the display device 100, only the substrate 110, the gate driver 154, the circuit element 161, and the plurality of wirings 130 are shown.

[0062] The substrate 110 is a component for supporting various components included in the display device 100, and may be formed of an insulating material. The substrate 110 may be formed of a bendable flexible material. The substrate 110 may be formed of a transparent insulating material. For example, the substrate 110 may be formed of a plastic material such as polyimide (PI).

[0063] A plurality of gate lines GL and a plurality of data lines DL are disposed to cross each other on the substrate 110. A plurality of sub-pixels SP may be defined at intersections of the plurality of gate lines GL and the plurality of data lines DL. A region where a plurality of sub-pixels SP realizing an image are disposed may be referred to as a display region AA, and a region disposed outside the display region AA where a plurality of sub-pixels SP are not disposed may be referred to as a non-display region NA.

[0064] Each sub-pixel SP includes sub-pixels with different colors to realize color. The sub-pixels include red sub-pixels, green sub-pixels, and blue sub-pixels. Each sub-pixel SP may also include a white sub-pixel. Hereinafter, when a pixel is not defined separately, the pixel may be interpreted as a sub-pixel. Each sub-pixel may include a pixel circuit.

[0065] In the display area, a display unit for displaying an image and a circuit unit for driving the display unit may be provided. For example, when the display device 100 is an organic light-emitting display device, the display unit may include a light-emitting diode. That is, the display unit may include an anode, an organic light-emitting layer on the anode, and a cathode on the organic light-emitting layer. For example, the organic light-emitting layer may be composed of a hole transport layer, a hole injection layer, an organic light-emitting layer, an electron injection layer, and an electron transport layer. However, when the display device 100 is a liquid crystal display device, the display unit may be configured to include a liquid crystal layer. In the following, for ease of description, it is assumed that the display device 100 is an organic light-emitting display device, but is not limited thereto.

[0066] The circuit unit may include various transistors, capacitors, and wirings for driving the light emitting diode. For example, the circuit unit may be composed of various components such as a driving transistor, a switching transistor, a storage capacitor, a gate line, and a data line, but is not limited thereto.

[0067] The non-display area NA is an area where an image is not displayed, and a circuit (for example, a gate driver 154 and various wirings for driving a display unit provided in the display area AA) may be provided in the non-display area.

[0068] The non-display area NA can be defined as Figure 3 The area shown surrounds the display area AA, but is not limited thereto, and the non-display area NA may be defined as an area extending from the display area AA. In addition, the non-display area NA may be defined as extending from a plurality of sides of the display area AA.

[0069] The non-display area NA may include a pad area PA.

[0070] The pad area PA may be formed to receive a data driving signal from an external power source, or to transmit a touch signal to the external power source and receive a touch signal from the external power source.

[0071] The driving integrated circuit DIC 150 may be disposed in the pad region.

[0072] For example, in the pad area PA, the circuit element 161 disposed in a direction of a more outer area of ​​the substrate 110 than the driving integrated circuit 150 may be bonded.

[0073] For example, the circuit element 161 may be a flexible printed circuit, but is not limited thereto.

[0074] The driving integrated circuit 150 disposed in the pad area PA may be connected to the plurality of signal lines SL, and may be connected to the plurality of data lines DL or the plurality of gate lines GL disposed in the display area AA through the plurality of signal lines SL via the gate driver 154. Therefore, a driving signal from the driving integrated circuit 150 disposed in the pad area PA may be applied to each of the plurality of sub-pixels SP.

[0075] Meanwhile, in the curved area BA of the non-display area NA, a plurality of protection lines ML disposed outside the curved area BA may be included along the width direction of the curved area BA. The plurality of protection lines ML may be disposed closer to the end of the width of the curved area BA than the plurality of signal lines SL. For example, one end of at least one protection line ML is connected to the driving integrated circuit 150 to be applied with a signal relatively equal to or lower than the lowest voltage of the signal line SL. For example, a signal of a low voltage or a negative (-) voltage relatively equal to or lower than the low voltage line VGL may be applied to at least one protection line ML.

[0076] The following will refer to Figure 5 A plurality of wirings 130 including a plurality of signal lines SL and a plurality of guard lines ML are described.

[0077] For example, the bent area BA formed by bending a portion of the non-display area NA in one direction may be located between the display area AA and the pad area PA in the non-display area NA.

[0078] The non-display area NA is not an area displaying an image, and thus may not be visible from the top surface of the substrate 110. For example, a portion of the non-display area NA of the substrate 110 is bent to reduce the non-display area NA while ensuring an area for wiring and driving circuits.

[0079] For example, the display device 100 according to an exemplary embodiment of the present disclosure may be bent in a rearward direction such that a lower edge of the substrate 110 has a predetermined curvature.

[0080] The lower edge of the substrate 110 may correspond to the outside of the display area AA and may correspond to the area where the driver integrated circuit 150 and the pad area PA are arranged. When the substrate 110 is bent, the driver integrated circuit 150 and the pad area PA may be arranged to overlap the display area AA in the rearward direction of the display area AA. Therefore, the frame area perceived from the front of the display device 100 may be minimized. Therefore, the frame width is reduced, so that the aesthetics may be improved.

[0081] In the following, we will refer to Figure 4 The cross-sectional structure of the display device 100 is described in more detail.

[0082] Figure 4 is a cross-sectional view of one sub-pixel SP provided in a display area of ​​a display device according to an exemplary embodiment of the present disclosure.

[0083] Reference Figure 4 According to an exemplary embodiment of the present disclosure, a display device 100 may include a substrate 110, a first buffer layer 111, a first thin film transistor T1, a second thin film transistor T2, a first gate insulating layer 112a, a first insulating layer 113a, a second buffer layer 114, a second gate insulating layer 112b, a second insulating layer 113b, a first connection electrode CE1, a first planarization layer 115a, a second planarization layer 115b, a second connection electrode CE2, a dam 116a, a spacer 116b, a first electrode 121, a light emitting layer 122, a second electrode 123, an encapsulation layer 117, and a touch sensing unit.

[0084] The substrate 110 is used to support and protect components of the flexible display device disposed above the substrate.

[0085] The substrate 110 may be formed of glass or a plastic material having flexibility. When the substrate 110 is formed of a plastic material, for example, the substrate may be formed of polyimide (PI). When the substrate 110 is formed of polyimide (PI), the manufacturing process of the display device 100 is performed with a support substrate formed of glass disposed below the substrate 110, and the support substrate may be released after the manufacturing process of the display device 100 is completed. In addition, after the support substrate is released, a backplane of the support substrate 110 may be disposed below the substrate 110.

[0086] For example, when a back plate is further disposed under the substrate 110 , the back plate may not be disposed in a portion overlapping the bending area BA of the substrate 110 , but is not limited thereto.

[0087] When the substrate 110 is formed of polyimide (PI), moisture passes through the substrate 110 formed of polyimide (PI) to penetrate into the first thin film transistor 120 or the light emitting structure, so that the performance of the display device 100 may be deteriorated. The display device 100 according to an exemplary embodiment of the present disclosure may be composed of a double-layer polyimide (PI) to suppress the performance degradation of the display device 100 due to moisture penetration. In addition, an inorganic layer is formed between the double-layer polyimide (PI) to block moisture components from penetrating the lower polyimide (PI), thereby improving the reliability of product performance.

[0088] In addition, in the display device 100 according to the exemplary embodiment of the present disclosure, an inorganic layer is formed between the double-layer polyimide (PI), so that the charges charged in the lower polyimide (PI) are blocked, thereby improving the reliability of the product. In addition, the process of forming a metal layer to block the charges charged in the polyimide (PI) can be omitted, so that the process can be simplified and the production cost can be reduced.

[0089] For the display device 100 using polyimide (PI) as the substrate 110, it is very important to ensure environmental reliability and performance reliability of the panel.

[0090] Therefore, the display device 100 according to the exemplary embodiment of the present disclosure uses a double-layer polyimide (PI) as the substrate 110, so that a structure for ensuring the environmental reliability of the product can be realized. For example, the substrate 110 of the display device 100 may include a first polyimide layer 110a and a second polyimide layer 110b formed of polyimide (PI), and an inorganic insulating layer 110c formed between the first polyimide layer 110a and the second polyimide layer 110b, but is not limited thereto. When the charge is charged in the first polyimide layer 110a, the inorganic insulating layer 110c can be used to block the charge from passing through the second polyimide layer 110b to affect the first thin film transistor T1. In addition, the inorganic insulating layer 110c can also be used to block the moisture component from penetrating into the upper part through the second polyimide layer 110b.

[0091] It can be made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a multilayer thereof to form the inorganic insulating layer 110c. In the display device 100 according to an exemplary embodiment of the present disclosure, the inorganic insulating layer 110c may be made of silicon oxide (SiO x ) material to form the inorganic insulating layer 110c. For example, a silica (or silicon dioxide (SiO2)) material may be formed as the inorganic insulating layer 110c, but is not limited thereto, and may be formed of silicon dioxide (SiO2) and silicon nitride (SiN x ) form an inorganic insulating layer 110c.

[0092] The first buffer layer 111 may be disposed on the substrate 110. Specifically, a multi-buffer layer 111a may be disposed on the substrate 110, and an active buffer layer 111b may be disposed on the multi-buffer layer 111a.

[0093] The metal layer 125 may be disposed on the multi-buffer layer 111 a .

[0094] For example, the metal layer 125 may function as a light shielding member and may also be referred to as a light shielding layer.

[0095] The active buffer layer 111 b may be disposed on the metal layer 125 .

[0096] The first thin film transistor T1 may be disposed on the first buffer layer 111. The first thin film transistor T1 may include a first active layer A1, a first gate G1, a first source S1, and a first drain D1. Here, according to the design of the pixel circuit, the first source S1 may be used as a first drain, and the first drain D1 may be used as a first source.

[0097] The first active layer A1 may include amorphous silicon or polycrystalline silicon. For example, the first active layer A1 may include low temperature polycrystalline silicon (LTPS). For example, polycrystalline silicon material has a high mobility (100 cm 2 / Vs or more), so the energy consumption is low and the reliability is excellent. Therefore, the polysilicon material can be applied to a gate driver for a driving element, wherein the driving element drives a thin film transistor and / or a multiplexer (MUX) of a display element, etc., and is also used as an active layer A1 of a driving thin film transistor of the display device 100 according to an exemplary embodiment, but is not limited thereto. For example, according to the characteristics of the display device 100, the polysilicon material can also be used as an active layer A2 of a switching thin film transistor. An amorphous silicon (a-Si) material is deposited on the first buffer layer 111, and a dehydrogenation process and a crystallization process are performed to form polysilicon, and the polysilicon is patterned to form a first active layer A1. Here, the first active layer A1 may include a first channel region in which a channel is formed when the first thin film transistor T1 is driven, and a first source region and a first drain region located on both sides of the first channel region. The first source region refers to a portion of the first active layer A1 connected to the first source electrode S1, and the first drain region refers to a portion of the first active layer A1 connected to the first drain electrode D1. For example, the first source region and the first drain region are configured by ion doping (impurity doping) of the first active layer A1. The first source region and the first drain region may be generated by doping ions into polysilicon material, and the first channel region may refer to a portion where no ions are doped but polysilicon material remains.

[0098] The first gate insulating layer 112a may be disposed on the first active layer A1. The first gate insulating layer 112a may be made of silicon nitride (SiNx ) or silicon oxide (SiO x ) or a single layer or multiple layers thereof. In the first gate insulating layer 112a, a contact hole may be formed, through which the first source electrode S1 and the first drain electrode D1 of the first thin film transistor T1 are respectively connected to the first source region and the first drain region of the first active layer A1 of the first thin film transistor T1.

[0099] The first gate electrode G1 of the first thin film transistor T1 and the first capacitor electrode C1 of the storage capacitor Cst may be disposed on the first gate insulating layer 112 a .

[0100] At this time, the first gate G1 and the first capacitor electrode C1 may be formed of a single layer or a multilayer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or an alloy thereof. The first gate G1 may be formed on the first gate insulating layer 112a to overlap with the first channel region of the first active layer A1 of the first thin film transistor T1.

[0101] The first capacitor electrode C1 may be omitted based on the driving characteristics of the display device 100 and the structure and type of the thin film transistor. The first gate G1 and the first capacitor electrode C1 may be formed by the same process. In addition, the first gate G1 and the first capacitor electrode C1 may be formed of the same material on the same layer.

[0102] The first insulating layer 113a may be disposed over the first gate insulating layer 112a, the first gate G1, and the first capacitor electrode C1. The first insulating layer 113a may be made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a plurality of layers thereof. In the first insulating layer 113a, a contact hole for exposing the first source region and the first drain region of the first active layer A1 of the first thin film transistor T1 may be formed.

[0103] The second capacitor electrode C2 of the storage capacitor Cst may be disposed on the first insulating layer 113a. The second capacitor electrode C2 may be formed by a single layer or multiple layers formed by any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or their alloys. The second capacitor electrode C2 may be formed on the first insulating layer 113a and overlap with the first capacitor electrode C1. In addition, the second capacitor electrode C2 may be formed by the same material as the first capacitor electrode C1. Based on the driving characteristics of the display device 100 and the structure and type of the thin film transistor, the second capacitor electrode C2 may be omitted.

[0104] The second buffer layer 114 may be disposed on the first insulating layer 113a and the second capacitor electrode C2. The second buffer layer 114 may be made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a single layer or a multilayer thereof. A contact hole for exposing the first source region and the first drain region of the first active layer A1 of the first thin film transistor T1 may be formed in the second buffer layer 114. In addition, a contact hole for exposing the second capacitor electrode C2 of the storage capacitor Cst may be formed in the second buffer layer 114.

[0105] The second buffer layer 114 may be formed of a plurality of layers, but is not limited thereto.

[0106] The second active layer A2 of the second thin film transistor T2 may be disposed on the second buffer layer 114. Here, the second thin film transistor T2 may include a second active layer A2, a second gate insulating layer 112b, a second gate G2, a second source S2, and a second drain D2. Here, according to the design of the pixel circuit, the second source S2 may be used as a drain electrode, and the second drain D2 may be used as a source electrode.

[0107] In addition, the second active layer A2 may include a second channel region in which a channel is formed when the second thin film transistor T2 is driven, and a second source region and a second drain region located at both sides of the second channel region. The second source region may refer to a portion of the second active layer A2 connected to the second source electrode S2, and the second drain region may refer to a portion of the second active layer A2 connected to the second drain electrode D2.

[0108] The second active layer A2 may be formed of an oxide semiconductor. Oxide semiconductor materials have a large band gap compared to silicon materials, so that electrons cannot jump over the band gap in the off state. Therefore, oxide semiconductor materials have a low off current. Therefore, a thin film transistor including an active layer formed by an oxide semiconductor may be suitable for a switching thin film transistor that maintains a short on-time and a long off-time, but is not limited thereto. According to the characteristics of the display device 100, an oxide semiconductor may be used as a driving thin film transistor. In addition, since the off-current is small, the size of the auxiliary capacitor may be reduced, so that the oxide semiconductor may be suitable for a high-resolution display element. For example, the second active layer A2 may be formed of a metal oxide, and may be formed of, for example, various metal oxides such as indium gallium zinc oxide (IGZO). Here, it is described under the assumption that the second active layer A2 of the second thin film transistor T2 is composed of IGZO among various metal oxides, but is not limited thereto. Therefore, the active layer may be formed of another metal oxide such as indium zinc oxide (IZO), indium gallium tin oxide (IGTO) or indium gallium oxide (IGO) instead of IGZO.

[0109] The second active layer A2 may be formed by depositing a metal oxide on the second buffer layer 114, performing a heat treatment for stabilization, and then patterning the metal oxide.

[0110] The second gate insulating layer 112b may be disposed on the entire substrate 110 including the second active layer A2. For example, the second gate insulating layer 112b may be made of silicon nitride (SiN x ) or silicon oxide (SiO x ) or a multilayer thereof.

[0111] The second gate G2 may be disposed on the second gate insulating layer 112 b .

[0112] The second gate electrode 134 may be formed of a single layer or a multilayer formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0113] For example, a metal material is formed on the second gate insulating layer 112b, a photoresist pattern is formed on the metal material, and then the metal material is wet-etched using the photoresist pattern as a mask to form the second gate G2. As a wet etchant for etching the metal material, a material that selectively etches molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) constituting the metal material or an alloy thereof but does not etch the insulating material can be used.

[0114] The second insulating layer 113b may be disposed on the second gate insulating layer 112b and the second gate G2. A contact hole for exposing the first active layer A1 of the first thin film transistor T1 and the second active layer A2 of the second thin film transistor T2 may be formed in the second insulating layer 113b. For example, a contact hole for exposing the first source region and the first drain region of the first active layer A1 of the first thin film transistor T1 may be formed in the second insulating layer 113b. A contact hole for exposing the second source region and the second drain region of the second active layer A2 of the second thin film transistor T2 may be formed in the second insulating layer 113b.

[0115] The second insulating layer 113b may be configured as silicon nitride (SiN x ) or silicon oxide (SiO x ) or multiple layers thereof.

[0116] The first connection electrode CE1 , the first source electrode S1 and the first drain electrode D1 of the first thin film transistor T1 , and the second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 may be disposed on the second insulating layer 113 b .

[0117] The first connection electrode CE1 may be electrically connected to the second drain electrode D2 of the second thin film transistor T2. In addition, the first connection electrode CE1 may be electrically connected to the second capacitor electrode C2 of the storage capacitor Cst through a contact hole formed in the second buffer layer 114 and the second insulating layer 113b. That is, the first connection electrode CE1 may be used to electrically connect the second capacitor electrode C2 of the storage capacitor Cst and the second drain electrode D2 of the second thin film transistor T2 to each other.

[0118] Here, the first source S1 and the first drain D1 of the first thin film transistor T1 may be connected to the first active layer A1 of the first thin film transistor T1 through contact holes formed in the first gate insulating layer 112a, the first insulating layer 113a, the second buffer layer 114, and the second insulating layer 113b.

[0119] The second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2 may be connected to the second active layer A2 through a contact hole formed in the second insulating layer 113 b .

[0120] The first connection electrode CE1 , the first source S1 and the first drain D1 of the first thin film transistor T1 , and the second source S2 and the second drain D2 of the second thin film transistor T2 may be formed of the same material through the same process.

[0121] For example, the first connection electrode CE1, the first source S1 and the first drain D1 of the first thin film transistor T1, and the second source S2 and the second drain D2 of the second thin film transistor T2 may be formed by a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof. For example, the first connection electrode CE1, the first source S1 and the first drain D1 of the first thin film transistor T1, and the second source S2 and the second drain D2 of the second thin film transistor T2 may be formed by a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), but is not limited thereto.

[0122] The first connection electrode CE1 may be integrally formed to be connected to the second drain electrode D2 of the second thin film transistor T2 , but is not limited thereto.

[0123] The first planarization layer 115 a may be disposed over the first connection electrode CE1 , the first source S1 and the first drain D1 of the first thin film transistor T1 , the second source S2 and the second drain D2 of the second thin film transistor T2 , and the second insulating layer 113 b .

[0124] The first planarization layer 115a may be an organic layer that planarizes and protects upper portions of the first and second thin film transistors T1 and T2. For example, the first planarization layer 115a may be formed of an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0125] The second connection electrode CE2 may be disposed on the first planarization layer 115a. The second connection electrode CE2 may be connected to the second drain electrode D2 of the second thin film transistor T2 through the contact hole of the first planarization layer 115a. The second connection electrode CE2 may be used to electrically connect the second thin film transistor T2 and the first electrode 121 to each other. The second connection electrode CE2 may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or an alloy thereof. The second connection electrode CE2 may be formed of the same material as the second source electrode S2 and the second drain electrode D2 of the second thin film transistor T2.

[0126] The second planarization layer 115b may be disposed over the second connection electrode CE2 and the first planarization layer 115a. For example, the second planarization layer 115b may be formed of an organic material such as acrylic resin, epoxy resin, phenol resin, polyamide resin, or polyimide resin.

[0127] The light emitting diode 120 may be disposed on the second planarization layer 115 b .

[0128] The first electrode 121 may be disposed on the second planarization layer 115b. At this time, the first electrode 121 may be electrically connected to the second connection electrode CE2 through a contact hole disposed in the second planarization layer 115b. The first electrode 121 may be formed of a metal material.

[0129] When the display device 100 is a top emission type in which light emitted from the light emitting diode 120 is emitted above the substrate 110 (in which the light emitting diode 120 is disposed), the first electrode 121 may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be formed of a transparent conductive oxide such as ITO or IZO, and the reflective layer may be formed of silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0130] The bank 116a may be provided to cover the first electrode 121. A portion of the bank 116a corresponding to the light emitting region of the sub-pixel may be open. A portion of the first electrode 121 may be exposed through the open portion of the bank 116a (hereinafter referred to as the open region). In this case, the bank 116a may be made of a material such as silicon nitride (SiN x ) or silicon oxide (SiO x) or an organic insulating material such as benzocyclobutene resin, acrylic resin or imide resin, but is not limited thereto. A spacer 116b may be further disposed on the bank 116a.

[0131] The light emitting layer 122 may be disposed in and near the opening region of the bank 116a. Thus, the light emitting layer 122 may be disposed on the first electrode 121 exposed through the opening region of the bank 116a.

[0132] The second electrode 123 may be disposed on the light emitting layer 122 .

[0133] The light emitting diode 120 may be formed of a first electrode 121, a light emitting layer 122, and a second electrode 123. The light emitting layer 122 may include a plurality of organic films.

[0134] For example, the first electrode 121 may be an anode or a cathode. For example, the second electrode 123 may be a cathode or an anode.

[0135] The encapsulation layer 117 may be located on the light emitting diode 120 .

[0136] The encapsulation layer 117 may have a single-layer structure or a multi-layer structure. For example, the encapsulation layer 117 may include a first encapsulation layer 117a, a second encapsulation layer 117b, and a third encapsulation layer 117c.

[0137] For example, the first encapsulation layer 117a and the third encapsulation layer 117c may be composed of an inorganic film, and the second encapsulation layer 117b may be composed of an organic film. Among the first encapsulation layer 117a, the second encapsulation layer 117b and the third encapsulation layer 117c, the second encapsulation layer 117b is the thickest and may serve as a planarization layer.

[0138] The first encapsulation layer 117a may be disposed on the second electrode 123 and may be disposed closest to the light emitting diode 120. The first encapsulation layer 117a may be formed of an inorganic insulating material on which low temperature deposition may be performed. For example, the first encapsulation layer 117a may be formed of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON) or aluminum oxide (Al2O3). The first encapsulation layer 117a is deposited in a low temperature atmosphere, so that during the deposition process, damage to the light emitting layer 122 including an organic material that is susceptible to a high temperature atmosphere can be suppressed.

[0139] The second encapsulation layer 117b may be formed to have an area smaller than that of the first encapsulation layer 117a. In this case, the second encapsulation layer 117b may be formed to expose both ends of the first encapsulation layer 117a. The second encapsulation layer 117b may serve as a buffer to relieve stress between layers caused by bending of the flexible display device and improve planarization performance.

[0140] For example, the second encapsulation layer 117b may be formed of an organic insulating material such as acrylic resin, epoxy resin, polyimide, polyethylene, or silicon oxycarbon (SiOC). For example, the second encapsulation layer 117b may be formed by an inkjet method, but is not limited thereto.

[0141] The third encapsulation layer 117c may be formed over the substrate 110 on which the second encapsulation layer 117b is formed to cover the upper and side surfaces of the second encapsulation layer 117b and the first encapsulation layer 117a, respectively. At this time, the third encapsulation layer 117c may minimize or block external moisture or oxygen from penetrating into the first encapsulation layer 117a and the second encapsulation layer 117b. For example, the third encapsulation layer 117c may be made of a material such as silicon nitride (SiN x ), silicon oxide (SiOx), silicon oxynitride (SiON) or aluminum oxide (Al2O3) inorganic insulating materials.

[0142] In the non-display area NA, a dam may be further provided to block the overflow of the second encapsulation layer 117b constituting the encapsulation layer 117, but is not limited thereto. For example, the dam is formed in the non-display area NA to have a closed curve surrounding the display area AA and the first encapsulation layer 117a and the third encapsulation layer 117c are provided on the dam, and the overflow of the second encapsulation layer 117b may be blocked by the dam.

[0143] For example, a color filter may be disposed on the encapsulation layer 117 , but is not limited thereto.

[0144] The touch sensing layer may be disposed on the encapsulation layer 117 .

[0145] For example, the touch buffer film 118 a may be disposed over the third encapsulation layer 117 c , and the touch electrode TE may be disposed on the touch buffer film 118 a .

[0146] The touch electrode TE may include a touch sensor metal TS and a bridge metal BM located on different layers. A touch interlayer insulating film 118 b may be provided between the touch sensor metal TS and the bridge metal BM.

[0147] For example, the touch sensor metal TS may include a first touch sensor metal, a second touch sensor metal, and a third touch sensor metal disposed adjacent to each other. The first touch sensor metal and the second touch sensor metal are electrically connected. However, when the third touch sensor metal is disposed between the first touch sensor metal and the second touch sensor metal, the first touch sensor metal and the second touch sensor metal may be electrically connected through a bridge metal BM disposed on different layers. The bridge metal BM may be insulated from the touch sensor metal TS by the touch interlayer insulating film 118 b.

[0148] When the touch sensing unit is formed, chemicals (e.g., developer, etchant, etc.) used in the process, moisture from the outside, etc. may be generated. The touch buffer film 118a is provided, and the touch sensing unit is provided on the touch buffer film 118a to suppress the penetration of chemicals, moisture, etc. into the light emitting layer 122 including an organic material during the manufacture of the touch sensing unit. By doing so, the touch buffer film 118a can suppress damage to the light emitting layer 122 that is susceptible to chemicals or moisture.

[0149] The touch buffer film 118a may be formed of an organic insulating material formed at a temperature lower than a predetermined temperature (e.g., 100°C) to suppress damage to the light emitting layer 122 containing an organic material susceptible to high temperatures. The organic insulating material has a low dielectric constant of 1 to 3. For example, the touch buffer film 118a may be formed of an acrylic, epoxy, or siloxane-based material. When the flexible display device is bent, the encapsulation unit 117 may be damaged, and the touch sensor metal TS disposed above the touch buffer film 118a may be broken. Even if the flexible display device is bent, the touch buffer film 118a, which is composed of an organic insulating material and has a planarization property, can suppress damage to the encapsulation layer 117 and fracture of the metal TS and BM constituting the touch electrode TE.

[0150] The organic material layer 119 may be provided to cover the touch electrode TE. The organic material layer 119 may be composed of an organic insulating film.

[0151] According to an exemplary embodiment of the present disclosure, when the organic material layer 119 is formed, the developer used in the process may remain above the organic material layer 119, which will be described below with reference to FIG. Figure 7 Give a description.

[0152] For example, a polarizing layer may be disposed on the organic material layer 119 .

[0153] The polarizing layer suppresses reflection of external light on the display area AA of the substrate 110. When the display device 100 is used outdoors, external natural light enters, is reflected by the reflective layer included in the first electrode 121 of the light emitting diode 120, or is reflected by an electrode formed of metal and disposed under the light emitting diode 120. Therefore, due to the light reflected as described above, the image of the display device 100 may not be visibly recognized. The polarizing layer polarizes light entering from the outside to a specific direction, and suppresses the reflected light from being emitted to the outside of the display device 100.

[0154] The cover glass may be bonded to the polarizing layer through an adhesive layer. The adhesive layer may be used to bond components of the display device 100 to each other, and may be formed using, for example, an optically transparent display adhesive such as a pressure-sensitive adhesive, an optically clear adhesive (OCA), or an optically clear resin (OCR), but is not limited thereto.

[0155] The cover glass may protect components of the display device 100 from external impacts and suppress damage such as scratches.

[0156] In the following, we will refer to Figures 5 to 7 The plurality of wirings 130 are described in detail.

[0157] Figure 5 yes Figure 3 Graph of area A. Figure 6 According to an exemplary embodiment of the present disclosure Figure 3 Cross-sectional view along line BB'. Figure 7 According to another exemplary embodiment of the present disclosure Figure 3 Cross-sectional view along line BB'. Figure 8 According to an exemplary embodiment of the present disclosure Figure 3 Cross-sectional view along line CC'. Fig. 9 According to another exemplary embodiment of the present disclosure Figure 3 Cross-sectional view along line CC'. Fig.10 According to an exemplary embodiment of the present disclosure Fig. 9 A plan view of area D. Fig.11 is a plan view of a plurality of signal lines according to an exemplary embodiment of the present disclosure. Fig.12 yes Fig.11 Cross-sectional view along line EE'.

[0158] Figure 5 is to enlarge the exemplary embodiment according to the present disclosure Figure 3 FIG. 1 is a diagram of a plurality of wirings 130 of a display device 100 . Figure 6 is a cross-sectional view of at least one protection line ML according to an exemplary embodiment of the present disclosure. Fig.11 and Fig.12 They are a plan view and a cross-sectional view respectively showing a plurality of signal lines SL.

[0159] Reference Figure 5 According to an exemplary embodiment of the present disclosure, the display device 100 may include at least one protection line ML, which is arranged on the outside of the plurality of signal lines SL in the non-display area NA (such as the bending area BA), for example, closer to the end of the bending area BA than the plurality of signal lines SL in the width direction of the bending area BA.

[0160] For example, refer to Figure 3 , at least one protection line ML may be disposed at two outer ends of the bending area BA.

[0161] Reference Figure 6 and Fig.12 The bending area BA includes a first planarization layer 115a on the substrate 110 and a second planarization layer 115b on the first planarization layer 115a. A plurality of signal lines SL and at least one protection line ML may be disposed between the substrate 110 and the second planarization layer 115b.

[0162] Reference Figure 6 According to an exemplary embodiment of the present disclosure, at least one protection line may include a first wiring ML1 and / or a second wiring ML2 .

[0163] Figure 7 According to another exemplary embodiment of the present disclosure Figure 3 The cross-sectional view of the line BB' and Figure 5 In contrast, the third wiring ML3 and the overcoat layer 147 may be further disposed between the second planarization layer 115b and the protective layer MC. Figure 6 Duplicate description.

[0164] Reference Figure 7 The bending area BA includes a first planarization layer 115 a on the substrate 110 and a second planarization layer 115 b on the first planarization layer 115 a. A plurality of signal lines SL and at least one protection line ML may be disposed between the substrate 110 and the overcoat layer 147 .

[0165] Reference Figure 7 According to an exemplary embodiment of the present disclosure, at least one protection line ML may include a first wiring ML1 and / or a second wiring ML2 and / or a third wiring ML3 .

[0166] For example, the first wiring ML1 may be disposed on at least one of the substrate 110 , the first gate insulating layer 112 a , the first insulating layer 113 a , or the first planarization layer 115 a .

[0167] For example, the second wiring ML2 may be disposed on at least one of the substrate 110 , the first gate insulating layer 112 a , or the first insulating layer 113 a .

[0168] For example, the overcoat layer 147 may have the same material as the bank 116 a in the display area AA.

[0169] In the bending area BA, a protective layer (MC) may be further disposed on the second planarization layer 115b and / or the overcoat layer 147. For example, the protective layer MC may be an organic material. Exemplary embodiments of the present disclosure are not limited thereto.

[0170] When the panel is bent, tension is applied to the plurality of wirings 130 disposed over the substrate 110, causing breakage. Therefore, in order to suppress cracks, a protective layer MC is formed by coating a resin having a small thickness at a position to be bent to protect the plurality of wirings 130. For example, the protective layer MC disposed in the bending area BA can not only suppress breakage of the plurality of signal lines SL disposed in the bending area BA, but also adjust the neutral plane of the bending area BA.

[0171] For example, when evaluating the driving reliability of a product, there may be a problem that a wiring (e.g., a gate circuit line) provided in a bending region to supply a driving signal from a driving integrated circuit to a gate driver may be broken. For example, there is a problem that a signal supply wiring is corroded and broken by tetramethylammonium hydroxide (TMAH) remaining on the second planarization layer in the bending region.

[0172] For example, during the manufacturing process of the display device, mobile ions may be generated above the curved area. For example, a residual component TMAH of a developer used to develop an organic material layer may remain on the touch sensing layer. At this time, when the remaining TMAH reacts with water (H2O), TMAH dissociates to generate positive ions of TMA+ (e.g., N(CH3)4+).

[0173] After manufacturing the display device, for example, when the product is driven in a reliable environment of high temperature and high humidity, a voltage is applied to the gate circuit line set in the bending area. Due to the electric field generated at this time, the TMA+ positive ions remaining on the upper interface of the protective layer MC of the organic material of the bending area BA are attracted to the low voltage line in the gate circuit line to which the opposite polarity is applied. In addition, the following corrosion reaction equations (1) to (3) occur in sequence in the wiring containing aluminum and cause complete corrosion. For example, when driven at 1 Hz, as the time that a specific wiring in the gate circuit line maintains a low voltage increases, the TMA+ positive ions are easily attracted to the gate circuit line and cause corrosion.

[0174] Corrosion reaction formula (1): N(CH3)4OH+H2O->[N(CH3)4++OH-]+[H2O+H++OH-]

[0175] Corrosion reaction formula (2): Al->Al3++3e-, A13++2OH-->Al(OH)2+, Al3++3OH-->Al(OH)3,

[0176] Corrosion reaction formula (3): Al(OH)2++N(CH3)4OH<->Al(OH)3+N(CH3)4+

[0177] For example, this problem may become more serious when a thin film transistor formed of low temperature polysilicon and a thin film transistor formed of an oxide semiconductor are used together to be driven at a low voltage.

[0178] In an exemplary embodiment of the present disclosure, Figure 3 As shown in , at least one protection line ML may be included, which is disposed outside the plurality of signal lines SL (as gate circuit lines that transmit signals from the driving integrated circuit 150 disposed in the pad area PA to the gate driver 154), for example, closer to the outer end of the bending area BA than the plurality of signal lines SL in the width direction of the bending area BA. For example, a voltage lower than that of the plurality of signal lines SL is applied to the at least one protection line ML to suppress cracks generated in the plurality of signal lines SL.

[0179] According to an exemplary embodiment of the present disclosure, a voltage lower than the voltage of the plurality of signal lines SL and / or a negative voltage or a signal of the same voltage is applied to at least one protection line ML disposed at an end portion of the width of the bending area BA closer to the width of the bending area BA than the plurality of signal lines SL in the width direction of the bending area BA. Therefore, the voltage of at least one protection line ML is lower than the voltage of the plurality of signal lines SL. Therefore, even if the TMAH (tetramethylammonium hydroxide) remaining above the second planarization layer 115b reacts with moisture H2O to produce TMA+ positive ions, the TMA+ positive ions enter the at least one protection line ML transmitting a signal with a low voltage to react. Therefore, the TMA+ positive ions do not react with the plurality of signal lines SL, thereby suppressing cracks in the wiring (e.g., the plurality of signal lines SL) that supplies the drive signal from the drive integrated circuit 150 disposed in the pad area PA to the gate driver 154.

[0180] For example, refer to Figure 6 and Figure 7 , at least one protection line ML may be two or more or more. In an exemplary embodiment, at least one protection line ML may be one, and exemplary embodiments of the present disclosure are not limited thereto.

[0181] For example, refer to Figure 6 , at least one protection line ML may include a first wiring ML1 and / or a second wiring ML2. In an exemplary embodiment, the first wiring ML1 may be applied with a voltage lower than that of the signal line SL, a negative (-) voltage, or the same voltage. The second wiring ML2 is disposed below the first wiring ML1 to transmit a voltage higher than that of the signal line SL and / or the first wiring ML1 or a positive (+) signal or the same voltage signal. One end of the protection line ML (for example, one end of the first wiring ML1 and one end of the second wiring ML2) may be electrically connected to the driving integrated circuit 150. In an exemplary embodiment, one end of the first wiring ML1 and one end of the second wiring ML2 may be connected to the driving integrated circuit 150 through a link line, and the exemplary embodiments of the present disclosure are not limited thereto. For example, the second wiring ML2 may be disposed on the substrate 110, the first planarization layer 115a may be disposed on the second wiring ML2, the first wiring ML1 may be disposed on the first planarization layer 115a, the second planarization layer 115b may be disposed on the first wiring ML1, and the protection layer MC may be disposed on the second planarization layer 115b.

[0182] For example, a strong electric field E field is formed between the first wiring ML1 and the second wiring ML2, so that TMA+ ions generated in a high temperature and high humidity reliable environment are attracted to at least one protection line ML including the first wiring ML1 and the second wiring ML2 to be coupled, rather than being attracted to a plurality of signal lines SL to which a low voltage or a negative (-) voltage is applied. For example, the second wiring ML2 may include the same material as the first source S1 and the first drain D1, or may be provided on the same layer. For example, at least one protection line ML may be three-layered. For example, at least one protection line ML may include titanium (Ti) and aluminum (Al).

[0183] For example, refer to Figure 7 and Figure 8 , at least one protection line ML may include a first wiring ML1 and / or a second wiring ML2 and / or a third wiring ML3. In an exemplary embodiment, a voltage lower than a voltage of the signal line SL or a negative (-) voltage may be applied to the first wiring ML1. The second wiring ML2 may be disposed below the first wiring ML1, and the third wiring ML3 may be disposed above the first wiring ML1. A voltage equal to or higher than a voltage of the signal line SL and / or the first wiring ML1 and / or a positive (+) signal may be transmitted to the second wiring ML2 and the third wiring ML3. One end of the first wiring ML1, one end of the second wiring ML2, and one end of the third wiring ML3 may be electrically connected to the driving integrated circuit 150 through a link line.

[0184] For example, an electric field E field may be formed between the first wiring ML1 and the second wiring ML2, and an electric field E field may be formed between the first wiring ML1 and the third wiring ML3. Therefore, TMA+ ions generated in a high temperature and high humidity reliable environment are attracted to at least one protection line ML including the first wiring ML1, the second wiring ML2, and the third wiring ML3 to be coupled, rather than being attracted to a plurality of signal lines SL to which a low voltage or a negative (-) voltage is applied. Therefore, it is possible to suppress the coupling of TMA+ ions to the signal lines to suppress screen defects.

[0185] Reference Figure 8 , for example, the second planarization layer 115b may surround the side surface of the first planarization layer 115a. The first planarization layer 115a may surround the side surface of the second wiring ML2. The second planarization layer 115b may surround the side surface of the first wiring ML1. The outer coating layer 147 may surround the side surface of the third wiring ML3. The protective layer MC may surround the side surface of the second planarization layer 115b and / or the outer coating layer 147. The first wiring ML1 and / or the second wiring ML2 and / or the third wiring ML3 may include the same material, and exemplary embodiments of the present disclosure are not limited thereto.

[0186] For example, refer to Figure 3 , Figure 5 , Fig.11 and Fig.12 A plurality of signal lines SL disposed in the non-display area NA including the bending area BA according to an exemplary embodiment of the present disclosure are described. One end of the plurality of signal lines SL may be connected to the driving integrated circuit 150 disposed in the pad area PA, and the other end may be connected to the gate driver 154 of the non-display area NA.

[0187] According to an exemplary embodiment of the present disclosure, the plurality of signal lines SL may be formed of the same material on the same layer as the second connection electrode CE2 connected to the second drain electrode D2 of the second thin film transistor of the display area AA.

[0188] For example, since the plurality of signal lines SL are closer to the inner side of the display area AA of the substrate 110 from the outer side of the substrate 110 or the non-display area NA, the signal lines may be arranged in the order of start signals SL1 to SL4, clock signals SL5 to SL12, monitoring signals SL13 to SL16, high voltage signals SL17 and SL18, correction voltage signal SL19, low voltage signals SL20 and SL21, and initialization signals SL22 and SL23, but are not limited thereto.

[0189] According to an exemplary embodiment of the present disclosure, driving signals from a plurality of driving integrated circuits 150 may be supplied to the sub-pixels SP disposed in the display area AA via a plurality of signal lines SL and the gate driver 154 .

[0190] For example, the plurality of signal lines SL disposed in the non-display area NA including the bending area BA may be electrically connected to the plurality of driving lines 160 extending from the display area AA.

[0191] For example, Fig.11 and Fig.12 As shown, the plurality of signal lines SL may be electrically connected to the plurality of driving lines 160 extending from the display area AA through the first and second contact holes CNT1 and CNT2. For example, the plurality of driving lines 160 may be disposed on the same layer using the same material as the first gate G1.

[0192] For example, each driving line 160 may be configured as a gate line transmitting a gate signal, a gate high level voltage line, or a gate low level voltage line, but is not limited thereto.

[0193] According to an exemplary embodiment of the present disclosure, at least one protection line ML may be disposed outside the width direction of the plurality of signal lines SL in the bending area BA.

[0194] For example, one end of at least one protection line ML may be connected to the driving integrated circuit 150 , and may be applied with a voltage lower than that of the plurality of signal lines SL.

[0195] At least one protection line ML is disposed on the same layer using the same material as the second connection electrode CE2 connected to the second drain electrode D2 of the second thin film transistor in the display area AA.

[0196] For example, according to an exemplary embodiment of the present disclosure, the first wiring ML1 of at least one protection line ML may be configured by a wiring transmitting a signal having a negative (−) voltage.

[0197] For example, a signal having a voltage lower than that of the plurality of signal lines SL or a negative voltage is applied to at least one protection line ML disposed at the outer end of the bending area BA in the width direction of the bending area BA than the plurality of signal lines SL. Therefore, the voltage of at least one protection line ML is lower than the voltage of the plurality of signal lines SL. Therefore, even if the TMAH (tetramethylammonium hydroxide) remaining above the second planarization layer 115b reacts with the moisture H2O to produce TMA+ positive ions, the TMA+ positive ions enter and react with at least one protection line ML transmitting a signal having the lowest voltage. Therefore, the TMA+ positive ions do not react with the plurality of signal lines SL, thereby suppressing cracks in the wiring (e.g., the plurality of signal lines SL) that supplies the drive signal from the drive integrated circuit 150 disposed in the pad area PA to the gate driver 154.

[0198] For example, moisture H2O first penetrates from the outside of the display device 100. Figure 5As shown in FIG. 1 , when at least one protection line ML is disposed outside the bending area BA along the width direction of the plurality of bending areas BA, TMA+ positive ions generated by moisture penetrating from the outside of the bending area BA enter the at least one protection line ML for reaction. Therefore, the TMA+ positive ions are inhibited from entering the plurality of signal lines SL to inhibit cracks generated in the plurality of signal lines SL.

[0199] In an exemplary embodiment, at least one protection line ML is used to suppress TMA+ positive ions from entering the plurality of signal lines SL. Figure 5 and Figure 6 As shown, one end of at least one protection line ML may be electrically connected to the driving integrated circuit 150, and the other end may float between the first planarization layer 115a and the second planarization layer 115b without being electrically connected to another component. Figure 5 , the other end of at least one protection line ML may be set to the bending area BA, but may not be set in the connection area IA where the display area AA is connected to the bending area BA. Exemplary embodiments of the present disclosure are not limited thereto. For example, one end of at least one protection line ML may be connected to the driving integrated circuit 150 through a link line, and the other line may not be connected to the wiring of the display area AA.

[0200] Fig. 9 According to another exemplary embodiment of the present disclosure Figure 3 Cross-sectional view along line CC'.

[0201] Fig.10 yes Fig. 9 A plan view of area D.

[0202] exist Fig. 9 According to an exemplary embodiment of the present disclosure, Figure 8 The fourth wiring ML4 is added, and a redundant description will be omitted. For example, the second planarization layer 115b may surround a side surface of the fourth wiring ML4, and exemplary embodiments of the present disclosure are not limited thereto.

[0203] Reference Fig. 9 and Fig.10 According to an exemplary embodiment of the present disclosure, at least one protection line MLL may include at least one of a first wiring ML1, a second wiring ML2, a third wiring ML3, and a fourth wiring ML4. For example, the first wiring ML1 and the fourth wiring ML4 as at least one protection line MLL may be used as a panel crack detection (PCD) line. For example, the first wiring ML1 and the fourth wiring ML4 in the bending area BA are separated in a direction closer to the pad area PA, and the ends in a direction closer to the display area AA may be connected. For example, in the bending area BA, one end of the first wiring ML1 and the fourth wiring ML4 may be separated, and the other end may be connected.

[0204] At least one protection line MLL according to an exemplary embodiment of the present disclosure may be electrically connected to the driving integrated circuit 150 and detect a crack when a crack is generated.

[0205] For example, the input contact hole IP of at least one protection line MLL and the input pad of the driving integrated circuit 150 may be connected. For example, the output contact hole OP of at least one protection line MLL may be connected to the output pad of the driving integrated circuit 150. For example, the resistance measuring probe contacts the input pad and the output pad of the driving integrated circuit 150 to measure the resistance of the signal line as input and output.

[0206] For example, when the plurality of signal lines SL are broken, whether the plurality of signal lines SL are broken can be detected based on the changed resistance of one protection wiring MLL.

[0207] According to an exemplary embodiment of the present disclosure, at least one protection line MLL may protect a plurality of signal lines SL as gate driving signal lines and detect whether cracks occur to minimize a defect rate of a display device, thereby improving reliability.

[0208] In an exemplary embodiment, referring to Fig.10 At least a portion of at least one guard line MLL may be configured with an embossed structure or a concave-convex structure.

[0209] For example, refer to Fig.10 , the fourth wiring ML4 of at least one protection line MLL may include a zigzag pattern. For example, at least one protection line MLL includes a concave-convex embossed shape to increase the surface area compared to a straight line pattern, thereby effectively absorbing (adsorbing) TMAH ions. For example, when moisture penetrates along the end of the wiring, the path is increased by the embossed structure or the concave-convex structure, so that the penetration of moisture into the display device can be delayed.

[0210] The display device according to the exemplary embodiment of the present disclosure may be applicable to a mobile device, a video phone, a smart watch, a watch phone, a wearable device, a foldable device, a rollable device, a bendable device, a flexible device, a bending device, a sliding device, a variable device, a personal digital assistant, an e-book, a portable multimedia player (PMP), a personal digital assistant (PDA), an MP3 player, a mobile medical device, a desktop computer, a notebook computer, a netbook computer, a workstation, a navigation, a car navigation, a car display device, a device for a vehicle, a theater device, a theater display device, a television set, a wallpaper device, a sign device, a game device, a notebook, a monitor, a camera, a video camera, a consumer electronic device, etc. In addition, the display device of the present disclosure may also be applied to an organic light emitting lighting device or an inorganic light emitting lighting device.

[0211] Exemplary embodiments of the present disclosure may also be described as follows:

[0212] According to one aspect of the present disclosure, a display device is provided, including: a substrate including a non-display area and a display area, the non-display area including a bending area and a pad area; a gate driver disposed in the non-display area; a driving integrated circuit disposed in the pad area; a plurality of signal lines disposed in the bending area and connecting the driving integrated circuit and the gate driver to each other; and at least one protection line disposed at an end portion in a width direction of the bending area. One end of the at least one protection line is connected to the driving integrated circuit.

[0213] A voltage lower than that of the plurality of signal lines may be applied to at least one guard line.

[0214] A negative (-) voltage may be applied to at least one guard line.

[0215] The display device may also include: a first thin film transistor, arranged in the display area and including a first active layer, a first gate, a first source and a first drain, and at least one insulating layer arranged on the first gate; and a second thin film transistor, arranged on at least one insulating layer and including a second active layer, a second gate, a second source and a second drain.

[0216] The display device may further include: a first planarization layer disposed on the second source electrode and the second drain electrode; and a connection electrode disposed on the first planarization layer and connected to the second drain electrode. The plurality of signal lines may be disposed on the same layer using the same material as the connection electrode.

[0217] The display device may further include: a plurality of driving lines extending from the display area. The plurality of driving lines may be disposed on the same layer as the first gate electrode, and the plurality of signal lines may be respectively connected to the plurality of driving lines through contact holes.

[0218] At least one guard line may be provided on the same layer using the same material as the connection electrode.

[0219] The display device may further include: a first planarization layer disposed in the bending area on the substrate; and an overcoat layer disposed in the bending area on the first planarization layer. A plurality of signal lines and at least one protection line may be disposed between the substrate and the overcoat layer.

[0220] At least one guard line may be provided at an outer position than the plurality of signal lines in the bending region.

[0221] At least one protection line may not be connected to the wiring of the display area.

[0222] The display device may further include a first planarization layer on the substrate. The at least one protection line may include a first wiring and a second wiring, and the second wiring may be disposed between the substrate and the first planarization layer, and the first wiring may be disposed on the first planarization layer.

[0223] The first wiring can transmit a signal having a voltage lower than or the same voltage as the plurality of signal lines, and the second wiring can transmit a signal having a voltage higher than or the same voltage as the plurality of signal lines.

[0224] The display device may further include a second planarization layer on the first wiring and an overcoat layer on the second planarization layer. The at least one protection line may further include a third wiring, and the third wiring may be disposed between the second planarization layer and the overcoat layer.

[0225] The first wiring may transmit a signal of a negative (-) voltage, and the second wiring and the third wiring may transmit a signal of a positive (+) voltage.

[0226] The first wiring may transmit a signal having a voltage lower than that of the plurality of signal lines, and the second wiring and the third wiring may transmit a signal having a voltage higher than that of the plurality of signal lines.

[0227] At least a portion of at least one protection line may include a concavo-convex structure.

[0228] The driving integrated circuit may further include an input pad and an output pad. The at least one protection line may include a first wiring connected to the output pad and a fourth wiring connected to the input pad, and the first wiring and the fourth wiring may be separated at one end and connected at the other end.

[0229] The display device may further include a protective layer disposed on the second planarization layer and / or the overcoat layer.

[0230] The first planarization layer may surround the side surface of the second wiring, the second planarization layer may surround the side surface of the first wiring, and the overcoat layer may surround the side surface of the third wiring.

[0231] Two or more of the first wiring, the second wiring, and the third wiring may include the same material.

[0232] The first wiring and the fourth wiring may be located in the same layer.

[0233] According to one aspect of the present disclosure, a display device is provided, which may include: a substrate, including a non-display area and a display area, the non-display area including a bending area and a pad area; a gate driver, arranged in the non-display area; a driving integrated circuit, arranged in the pad area; a plurality of signal lines, arranged in the bending area and connecting the driving integrated circuit and the gate driver to each other; and at least one guard line, arranged on the outside of the signal line in the bending area, wherein a voltage applied to the at least one guard line is lower than a voltage applied to the plurality of signal lines.

Claims

1. A display device, comprising: A substrate, comprising a non-display area and a display area, wherein the non-display area comprises a bending area and a pad area; A gate driver, disposed in the non-display area; A driver integrated circuit is arranged in the pad area; a plurality of signal lines disposed in the bending region and connecting the driving integrated circuit and the gate driver to each other; as well as at least one protection line, arranged at an end portion in the width direction of the bending area; Wherein, one end of the at least one protection line is connected to the driving integrated circuit.

2. The display device according to claim 1, wherein: A voltage lower than that of the plurality of signal lines is applied to the at least one guard line.

3. The display device according to claim 1, wherein: A negative (-) voltage is applied to the at least one protection line.

4. The display device according to claim 1, further comprising: A first thin film transistor, disposed in the display area and comprising a first active layer, a first gate electrode, a first source electrode and a first drain electrode; at least one insulating layer, disposed on the first gate; as well as The second thin film transistor is disposed on the at least one insulating layer and includes a second active layer, a second gate electrode, a second source electrode, and a second drain electrode.

5. The display device according to claim 4, further comprising: A first planarization layer, disposed on the second source electrode and the second drain electrode; as well as a connecting electrode disposed on the first planarization layer and connected to the second drain electrode, The plurality of signal lines are provided on the same layer using the same material as the connection electrodes.

6. The display device according to claim 4, further comprising: A plurality of driving lines extending from the display area, The plurality of driving lines and the first gate are arranged on the same layer, and the plurality of signal lines are respectively connected to the plurality of driving lines through contact holes.

7. The display device according to claim 5, wherein: The at least one guard line is provided on the same layer using the same material as the connection electrode.

8. The display device according to claim 1, further comprising: a first planarization layer, the first planarization layer being disposed on the substrate in the curved region; as well as an outer coating layer disposed on the first planarization layer in the curved region, Wherein, the plurality of signal lines and the at least one protection line are arranged between the substrate and the outer coating layer.

9. The display device according to claim 1, wherein: The at least one guard line is provided at an outer position than the plurality of signal lines in the bending region.

10. The display device according to claim 1, wherein: The at least one protection line is not connected to the wiring of the display area.

11. The display device according to claim 1, further comprising: a first planarization layer, on the substrate, The at least one protection line includes a first wiring and a second wiring, and the second wiring is arranged between the substrate and the first planarization layer, and the first wiring is arranged on the first planarization layer.

12. The display device according to claim 11, wherein: The first wiring transmits a signal having a voltage lower than or the same voltage as the plurality of signal lines, and the second wiring transmits a signal having a voltage higher than or the same voltage as the plurality of signal lines.

13. The display device according to claim 11, further comprising: a second planarization layer on the first wiring; as well as an outer coating layer, on the second planarization layer, Wherein, the at least one protection line further includes a third wiring, and the third wiring is arranged between the second planarization layer and the outer coating layer.

14. The display device according to claim 13, wherein: The first wiring transmits a signal of a negative (-) voltage, and the second wiring and the third wiring transmit a signal of a positive (+) voltage.

15. The display device according to claim 13, wherein: The first wiring transmits a signal having a voltage lower than that of the plurality of signal lines, and the second wiring and the third wiring transmit a signal having a voltage higher than that of the plurality of signal lines.

16. The display device according to claim 1, wherein: At least a portion of the at least one protection line includes a concavo-convex structure.

17. The display device according to claim 10, wherein: The driver integrated circuit also includes an input pad and an output pad. The at least one protection line comprises: a first wiring connected to the output pad; and a fourth wiring connected to the input pad, and The first wiring and the fourth wiring are separated at the one end and connected at the other end. 18 . The display device according to claim 13 , further comprising a protective layer disposed on the second planarization layer and / or the overcoat layer.

19. The display device according to claim 13, wherein: The first planarization layer surrounds a side surface of the second wiring, the second planarization layer surrounds a side surface of the first wiring, and the overcoat layer surrounds a side surface of the third wiring.

20. The display device according to claim 13, wherein: Two or more of the first wiring, the second wiring, and the third wiring include the same material.

21. The display device according to claim 13, wherein: The first wiring and the fourth wiring are located in the same layer.

22. A display device comprising: A substrate, comprising a non-display area and a display area, wherein the non-display area comprises a bending area and a pad area; A gate driver, disposed in the non-display area; A driver integrated circuit is arranged in the pad area; a plurality of signal lines disposed in the bending region and connecting the driving integrated circuit and the gate driver to each other; as well as at least one protection line, the at least one protection line being arranged outside the signal line in the bending region, Wherein, a voltage applied to the at least one protection line is lower than a voltage applied to the plurality of signal lines.

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