Memory control circuit and control method thereof

Abstract

The invention discloses a memory control circuit and a control method thereof. The memory control circuit comprises an access control circuit, a connection pad circuit and a pad control circuit. The connection pad circuit includes a transmitter circuit and a receiver circuit. The transmitter circuit and the receiver circuit are connected with the memory through an external connection pad. The pad control circuit is connected between the access control circuit and the receiver circuit. The pad control circuit executes the read instruction to drive the receiver circuit to receive read data from the memory through the external pad, and the pad control circuit executes the write instruction or closes the output of the receiver circuit after receiving the read data, so that the receiver circuit enters a power-saving state. And executing the power-saving instruction to reduce the working current of the receiver circuit and fix the internal signal of the receiver circuit at a level, so that the receiver circuit enters a deep power-saving state.

Description

Technical Field

[0001] This case involves memory-related fields, and in particular, involves a memory control circuit and a power saving control method thereof. Background Art

[0002] In the past, in order to reduce the power consumption of memory (such as Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM)), the most common method is to frequently put the memory into power down mode. However, when the memory enters read mode from power down mode, the receiver (RX) cannot smoothly receive data when it wakes up, affecting the operation of the entire system. Summary of the invention

[0003] In some embodiments, a memory control circuit includes an access control circuit, a connection pad circuit, and a pad control circuit. The access control circuit sends a read instruction, a write instruction, or a power saving instruction. The connection pad circuit includes a transmitter circuit and a receiver circuit. The transmitter circuit and the receiver circuit are connected to the memory via an external pad. The pad control circuit is connected between the access control circuit and the receiver circuit. The pad control circuit executes the read instruction to drive the receiver circuit to receive a read data from the memory through the external pad. The pad control circuit executes the write instruction or receives the read data and turns off the output of the receiver circuit, so that the receiver circuit enters a power saving state, and then executes the power saving instruction to reduce the operating current of the receiver circuit and fix the internal signal of the receiver circuit at a level, so that the receiver circuit enters a deep power saving state.

[0004] In some embodiments, the receiver circuit includes: a current mirror circuit, a comparator group, an output stage and a switch circuit. The current mirror circuit is controlled by the pad control circuit. The current mirror circuit maps an input current to generate a working current. The comparator group is connected to the external pad. The comparator group is powered by the working current. The output stage is connected between the comparator group and the pad control circuit. The switch circuit is connected to the comparator group. The switch circuit is controlled by the pad control circuit.

[0005] In some embodiments, the switch circuit includes a working switch. The working switch is connected between the current mirror circuit and the comparator group. The working switch is controlled by the pad control circuit. In the deep power saving state, the pad control circuit further controls the working switch to disconnect the power supply path between the current mirror circuit and the comparator group for providing the working current to the comparator group.

[0006] In some embodiments, in the deep power saving state, the pad control circuit controls the switch circuit to respectively connect the input terminals of the comparator group to a power supply and a ground to force the level of the internal signal of the receiver circuit.

[0007] In some embodiments, in the power saving state and the deep power saving state, the pad control circuit turns off the output of the receiver circuit by forcing the output stage to a non-output state.

[0008] In some embodiments, the output stage is an AND gate, and the pad control circuit forces the output stage to a non-output state by providing a logic signal to an input terminal of the AND gate, and the logic signal is 0.

[0009] In some embodiments, the receiver circuit further includes a current switch. The current switch is connected between the current mirror circuit and ground. The current switch executes the power-off instruction to disconnect the current mirror circuit from the ground, so that the receiver circuit enters a power-off state.

[0010] In some embodiments, the comparator group includes a plurality of comparators. The plurality of comparators are connected in series between an external pad and a pad control circuit. In the deep power saving state, the pad control circuit controls the switch circuit to disconnect the current mirror circuit to turn off the first comparator of the plurality of comparators, and controls the switch circuit to respectively conduct the two input terminals of the remaining comparators of the plurality of comparators to a power supply and a ground, so as to force the level of the internal signal of the receiver circuit.

[0011] In some embodiments, the current mirror circuit includes a current mirror and a current regulating circuit. The current mirror maps an input current to a working current. The current regulating circuit is connected to the current mirror. The current mirror is controlled by the pad control circuit to adjust the magnitude of the input current.

[0012] In some embodiments, a control method of a memory control circuit includes receiving a read instruction. Executing the read instruction to receive a read data from a memory via a receiver circuit. After completing receiving the read data or executing a write instruction, controlling the receiver circuit to enter a power saving state. Executing a power saving instruction to control the receiver circuit to enter a deep power saving state from the power saving state. Wherein, the step of entering the power saving state includes turning off the output of the receiver circuit. Wherein, the step of entering the deep power saving state includes: turning off the output of the receiver circuit. Reducing the operating current of the receiver circuit to a minimum. And forcing the level of an internal signal of the receiver circuit.

[0013] In some embodiments, the power-off state is entered from the power-saving state or the deep power-saving state, wherein the step of entering the power-off state includes shutting down the receiver circuit.

[0014] In some embodiments, the step of entering the deep power saving state further includes disconnecting a power supply path that provides a working current to the receiver circuit.

[0015] In some embodiments, the step of forcing the level of the internal signal of the receiver circuit includes connecting a plurality of input terminals of the comparator group to a power supply and a ground respectively.

[0016] In some embodiments, the step of shutting down the output of the receiver circuit includes forcing an output stage of the receiver circuit to a non-output state.

[0017] In some embodiments, the output stage is an AND gate. The step of forcing the output stage of the receiver circuit to a non-output state is to provide a logic signal to an input terminal of the AND gate, and the logic signal is 0.

[0018] In some embodiments, the step of minimizing the operating current of the receiver circuit includes reducing an input current, and the operating current is generated by mirroring the input current.

[0019] In some embodiments, a power-off state is entered from a power-saving state or a deep power-saving state, wherein the step of entering the power-off state includes cutting off input current.

[0020] In some embodiments, the receiver circuit includes a plurality of comparators, and the step of forcing the level of the internal signal of the receiver circuit includes turning off a first comparator of the plurality of comparators and connecting two input terminals of the remaining comparators of the plurality of comparators to a power supply and a ground respectively.

[0021] In summary, the memory control circuit and control method of any embodiment can switch the memory control circuit in idle state from power saving mode to deep power saving mode, and make its receiver circuit enter deep power saving state from power saving mode, thereby greatly reducing the overall power consumption of the memory control circuit without reducing system performance. In other words, when a read operation is required, the memory control circuit can switch from deep power saving mode to read mode in real time, that is, it can wake up the receiver circuit in real time to smoothly receive the read data. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 FIG. 4 is a functional block diagram of a memory control circuit according to an embodiment of the present invention. Figure 2 The figure is a flow chart of a control method of a memory control circuit according to an embodiment of the present invention. Figure 3 for Figure 1 A functional block diagram of an embodiment of a receiver circuit. Figure 4 for Figure 2 A circuit diagram of an embodiment of a receiver circuit of FIG. DETAILED DESCRIPTION

[0023] See also Figure 1 , a memory control circuit 10, which is suitable for controlling the read and write operations of a memory 20. The memory control circuit 10 includes an access control circuit 110, a connection pad circuit 120, and a pad control circuit 130. The connection pad circuit 120 includes a transmitter circuit TX and a receiver circuit RX. The access control circuit 110 is connected to the pad control circuit 130. The connection pad circuit 120 is connected to the pad control circuit 130. The connection pad circuit 120 is connected to an external pad PAD. In other words, the pad control circuit 130 is connected between the access control circuit 110 and the connection pad circuit 120. Moreover, the connection pad circuit 120 is connected to the memory 20 through the external pad PAD. The transmitter circuit TX and the receiver circuit RX are connected between the external pad PAD and the pad control circuit 130.

[0024] See also Figure 1 and Figure 2 The access control circuit 110 is used to control the operation of the memory 20. Specifically, when a read operation is required for the memory 20, the access control circuit 110 sends a read command to the pad control circuit 130. After the pad control circuit 130 receives the read command (step S01), the pad control circuit 130 executes the received read command to perform a read operation, that is, drives the receiver circuit RX to receive the read data from the memory 20 via the external pad PAD (step S02).

[0025] When no read operation is performed, that is, when the memory control circuit 10 is idle or when a write operation is performed (that is, when a read instruction is executed or a write instruction is received), the memory control circuit 10 will enter a power save mode (step S03) to save power consumption. Specifically, when the pad control circuit 130 has completed executing a read instruction and received a write instruction (e.g., the memory control circuit 10 is idle or when a write operation is performed), the pad control circuit 130 will control the receiver circuit RX to enter a power save state (step S03). In the power save state (step S03), the pad control circuit 130 turns off the output of the receiver circuit RX.

[0026] Furthermore, when the memory control circuit 10 is temporarily idle, the memory control circuit 10 can further switch from the power saving mode to the deep power down mode, thereby significantly reducing the power consumption of the memory control circuit 10 without reducing the system performance. Specifically, when the memory control circuit 10 is to switch from the power saving mode to the deep power down mode, the access control circuit 110 sends a power saving instruction to the pad control circuit 130. After the pad control circuit 130 receives the power saving instruction (step S04), the pad control circuit 130 executes the power saving instruction to control the receiver circuit RX to enter the deep power saving state from the power saving state (step S05). In step S05, the pad control circuit 130 turns off the output of the receiver circuit RX, reduces a working current of the receiver circuit RX to a minimum, and forces the level of the internal signal of the receiver circuit RX. In some embodiments, in the deep power saving state (step S05), the internal signal of the receiver circuit RX can be forced to a level such as a power supply voltage or a ground voltage. Among them, the ground voltage can be 0V.

[0027] In this way, the memory control circuit 10 can turn off the output of the receiver circuit RX through the pad control circuit 130 when it is idle or performing a write operation to reduce the overall power consumption. In order to save more power consumption, the memory control circuit 10 can further reduce the operating current of the receiver circuit RX through the pad control circuit 130 and bind the internal signal of the receiver circuit RX to reduce power supply and avoid leakage. Therefore, when the memory control circuit 10 receives a read instruction in the power saving mode or the deep power saving mode, the pad control circuit 130 can immediately execute the read instruction and immediately wake up the receiver circuit RX to smoothly receive the read data, thereby not reducing system performance.

[0028] See also Figure 1 , Figure 3 and Figure 4 In some embodiments, the receiver circuit RX includes a current mirror circuit 121, a comparator group CPn, an output stage 125, and a switch circuit 123. The current mirror circuit 121 is connected to the pad control circuit 130, and the current mirror circuit 121 is controlled by the pad control circuit 130. The current mirror circuit 121 maps an operating current Iout according to an input current Iin based on its own circuit characteristics. The comparator group CPn is connected between the external pad PAD and the output stage 125, and the comparator group CPn is powered by the operating current Iout. The output stage 125 is connected between the comparator group CPn and the pad control circuit 130. The switch circuit 123 connects the current mirror circuit 121, the comparator group CPn, and the pad control circuit 130, so that the switch circuit 123 is controlled by the pad control circuit 130.

[0029] See also Figures 1 to 3In some embodiments, in step S04 and step S05 , the pad control circuit 130 turns off the output of the receiver circuit RX by forcibly controlling the output stage 125 to be in a non-output state, thereby reducing the overall power consumption of the memory control circuit 10 .

[0030] See also Figures 1 to 4 In one embodiment, the output stage 125 is an AND gate. Here, the pad control circuit 130 is connected to one input terminal of the AND gate output stage 125, and the comparator group CPn is connected to the other input terminal of the AND gate. In steps S04 and S05, the pad control circuit 130 can force the output stage 125 to a non-output state by providing a logic signal IE to the input terminal of the AND gate output stage 125, wherein the logic signal IE is 0.

[0031] In some embodiments, the memory control circuit 10 can be further switched from the power saving mode or the deep power saving mode to the power down mode, thereby significantly reducing the power consumption of the memory control circuit 10. Specifically, when the memory control circuit 10 is to be switched from the power saving mode or the deep power saving mode to the power down mode, the pad control circuit 130 receives a power down command (step S06), and the pad control circuit 130 executes the power down command to control the receiver circuit RX from the power saving state or the deep power saving state to the power down state (step S07). In step S07, the pad control circuit 130 executes the power down command to conduct the current mirror circuit 121 to the ground VSS, so that the receiver circuit RX enters the power down state.

[0032] See also Figure 4 In some embodiments, the receiver circuit RX further includes a current switch 127. The current switch 127 is connected between the current mirror circuit 121 and the ground VSS, and the current switch 127 is controlled by the pad control circuit 130. After the pad control circuit 130 receives the power-off instruction (step S06), in step S07, the pad control circuit 130 executes a read instruction or a write instruction to control the current switch 127 to disconnect the current mirror circuit 121 from the ground VSS. Specifically, when the receiver circuit RX is in any of the states of the read state, the power saving state, and the deep power saving state, the current switch 127 will remain in the on state. After receiving the power-off instruction, the pad control circuit 130 will control the current switch 127 to switch from the on state to the off state and remain in the off state, so that the current path between the current mirror circuit 121 and the ground VSS is disconnected and the input current Iin cannot flow, and the working current Iout cannot be mapped and generated, so that the entire receiver circuit RX has no power and stops working.

[0033] In some embodiments, the current switch 127 may be implemented by a transistor, which may be a bipolar junction transistor (BJT), a metal-oxide-semiconductor field-effect transistor (MOSFET, also abbreviated as MOS), a field-effect transistor (FET), or an insulated gate bipolar transistor (IGBT).

[0034] For example, the current switch 127 is an NMOS. Here, the two ends of the current switch 127 are connected to the current mirror circuit 121 and the ground VSS respectively. The control end of the current switch 127 is connected to the pad control circuit 130 and is used to receive the mode signal PD from the pad control circuit 130. The current switch 127 is normally in the on state, that is, it receives the mode signal PD of logic 0 or low level. In step S07, the pad control circuit 130 will change to output the mode signal PD of logic 1 or high level to the current switch 127, so that the current switch 127 executes the mode signal PD of logic 1 or high level and switches to the off state, thereby disconnecting the current mirror circuit 121 and the ground VSS, so as to turn off the input current Iin input to the current mirror circuit 121.

[0035] In some embodiments, in order to further save power consumption, in step S05 , the memory control circuit 10 can further stop supplying power to currently unused circuits in the receiver circuit RX through the pad control circuit 130 .

[0036] See also Figures 1 to 4 As shown, in some embodiments, the switch circuit 123 receiver circuit RX includes a working switch M35. The working switch M35 is connected between the current mirror circuit 121 and the comparator group CPn. The working switch M35 is controlled by the pad control circuit 130. Under normal conditions (e.g., the receiver circuit RX is in any state such as a reading state and a power saving state), the pad control circuit 130 controls the working switch M35 to maintain an on state to conduct the current mirror circuit 121 to the comparator group CPn. In other words, the working switch M35 in the on state serves as a power supply path for providing the working current Iout from the current mirror circuit 121 to the comparator group CPn. In the power saving state, in step S05, the pad control circuit 130 controls the working switch M35 to form an off state to disconnect the power supply path between the current mirror circuit 121 and the comparator group CPn.

[0037] In some embodiments, the working switch M35 can be implemented by a transistor such as a bipolar junction transistor, a metal oxide semiconductor field effect transistor, a field effect transistor, or an insulated gate bipolar transistor.

[0038] In one embodiment, in the power saving state in step S05 , the pad control circuit 130 may control the switch circuit 123 to connect multiple input terminals of the comparator group CPn to the power supply VDD (which provides the power supply voltage) or the ground VSS (which provides the ground voltage) to force the level of the internal signal of the receiver circuit RX.

[0039] In one embodiment, the comparator group CPn includes n comparators CP1-CP3. Where n is a positive integer greater than 1. These comparators CP1-CP3 are connected in series between the external pad PAD and the output stage 125. In other words, the output stage 125 is coupled between the last stage comparator CP3 and the pad control circuit 130. In some embodiments, the comparator group CPn can be a serial circuit composed of n comparators CP1-CP3.

[0040] In some embodiments, in step S05, the pad control circuit 130 controls the switch circuit 123 to connect the two input terminals (hereinafter referred to as the first terminal and the second terminal, respectively) of each of the comparators CP2 to CP3 of the second to last stage to the power supply VDD and the ground VSS, respectively, to force the level of the internal signal of the receiver circuit RX.

[0041] In some embodiments, the switch circuit 123 further includes 2(n-1) short-circuit switches M31-M34. The second-stage to last-stage comparators CP2-CP3 correspond to a pair of short-circuit switches M31-M34 respectively. The first end of each of the second-stage to last-stage comparators CP2-CP3 is connected to the power supply VDD via a short-circuit switch M31 / M32 of the corresponding two short-circuit switches M31, M33 / M32, M34, and the second end thereof is connected to the ground VSS via another short-circuit switch M33 / M34 of the corresponding two short-circuit switches M31-M32 / M33-M34. The control end of the same pair of short-circuit switches M31, M33 / M32, M34 is connected to the pad control circuit 130. In step S05, the pad control circuit 130 outputs a control signal SW to the control terminals of the short-circuit switches M31-M34, thereby turning on (conducting) the short-circuit switches M31-M34, thereby short-circuiting the first terminals of the second to last stage comparators CP2-CP3 to the power supply VDD and the second terminals thereof to the ground VSS. In this way, the input signals of the comparators CP2-CP3 are tied to the level of the power supply VDD or the ground VSS.

[0042] In one embodiment, the control of the control signal SW is determined by the mode signal PD, the logic signal IE, and the power saving instruction. When the mode signal PD is 0 and the logic signal IE is 1, the control signal SW is 1, and the memory control circuit 10 is in the read mode, and the receiver circuit RX is turned on; when the mode signal PD is 0 and the logic signal IE is 0, the control signal SW is 1, and the memory control circuit 10 is idle or performing a write operation, and the receiver circuit RX is turned off and enters a power saving state; when the mode signal PD is 0, the logic signal IE is 0, and a power saving instruction is received, the control signal SW is 0, and the memory control circuit 10 is idle or performing a write operation, and the receiver circuit RX is turned off and enters a deep power saving state; when the mode signal is 1, the control signal is 0, and the memory control circuit 10 is in the power-off mode, and the receiver circuit RX is turned off.

[0043] In one embodiment, each short-circuit switch M31 / M32 / M33 / M34 may be implemented by a transistor, and the transistor may be a bipolar junction transistor, a metal oxide semiconductor field effect transistor (MOS), a field effect transistor, or an insulated gate bipolar transistor.

[0044] For example, taking the number of n comparators CP1, CP2, CP3 as three, this switch circuit 123 includes four short-circuit switches M31, M32, M33, M34 and a working switch M35. The three comparators CP1, CP2, CP3 are connected in series between the external pad PAD and the output stage 125 in sequence. Among them, the first comparator CP1 of the comparator CP is connected to the current mirror circuit 121 via the working switch M35. The two output ends of the second-stage comparator CP2 are connected to the power supply VDD and the ground VSS via the short-circuit switches M31 and M33 respectively. The two output ends of the last comparator CP3 are connected to the power supply VDD and the ground VSS via the short-circuit switches M32 and M34 respectively. The control end of each short-circuit switch M31~M34 and the control end of the working switch M35 are connected to the pad control circuit 130, and are used to receive the control signal SW from the pad control circuit 130.

[0045] In step S05, the pad control circuit 130 controls the working switch M35 to be turned off to disconnect the power supply path between the current mirror circuit 121 and the first-stage comparator CP1 and the comparator group CPn, so that the first-stage comparator CP1 is turned off. The pad control circuit 130 controls the four short-circuit switches M31-M34 to be turned on to connect the two input terminals of the remaining comparators CP2 and CP3 to the power supply VDD and the ground VSS, respectively, so that the internal signal of the receiver circuit RX is forced to be at the level of the power supply VDD or the level of the ground VSS.

[0046] Take the case where the short-circuit switches M31-M32 are PMOS and the control ends of the short-circuit switches M33-M34 and the working switch M35 are NMOS. Here, the control ends of the short-circuit switches M31-M32 and the control end of the working switch M35 are provided with an inverter. At this time, one end of the working switch M35 is connected to the output end of the current mirror circuit 121, and the other end of the working switch M35 is connected to the power supply end of the first comparator CP1. The control end of the working switch M35 is connected to the pad control circuit 130 and is used to receive the control signal SW from the pad control circuit 130. One end of the short-circuit switches M31-M32 is connected to the power supply VDD, and the other end of the short-circuit switches M31-M32 is respectively connected to an input end of the second-stage comparator CP2 and an input end of the third-stage comparator CP3. One end of the short-circuit switches M33-M34 is connected to the ground VSS, and the other end of the short-circuit switches M31-M32 is respectively connected to the other input end of the second-stage comparator CP2 and the other input end of the third-stage comparator CP3. Control terminals of the short-circuit switches M31 ˜ M34 are connected to the pad control circuit 130 and are used to receive the control signal SW from the pad control circuit 130 .

[0047] Under normal conditions, the pad control circuit 130 outputs a control signal SW of logic 0 or a low level, so that the short-circuit switches M31 to M34 remain in the off state, and the working switch M35 remains in the off state. In step S05, the pad control circuit 130 changes to output a control signal SW of logic 1 or a high level, so that the short-circuit switches M31 to M34 execute the control signal SW and turn on (i.e., switch from the off state to the on state and remain in the on state), and at the same time, the working switch M35 executes the control signal SW and turns off (i.e., switches from the on state to the off state and remains in the off state).

[0048] See also Figures 1 to 4In some embodiments, the current mirror circuit 121 includes a current mirror CRm and a current regulating circuit CRt. The current regulating circuit CRt connects the current mirror CRm and the pad control circuit 130. The input side of the current mirror CRm is connected between the power supply VDD and the current regulating circuit CRt, and the output side of the current mirror CRm is connected between the power supply VDD and the switch circuit 123. The current regulating circuit CRt is connected between the input side of the current mirror CRm and the ground VSS. Here, the current regulating circuit CRt is controlled by the pad control circuit 130. The current regulating circuit CRt is used to adjust the size of the input current Iin. The current mirror CRm maps the input current Iin to the working current Iout, and provides the working current Iout to the comparator group CPn through the switch circuit 123. Here, the current regulating circuit CRt has a plurality of gears for adjusting the input current Iin to different current values. The pad control circuit 130 outputs a selection signal SEL indicating a designated level to the current regulating circuit CRt according to the current operation of the memory control circuit 10 and the system setting, so that the current regulating circuit CRt provides an impedance corresponding to the designated level according to the selection signal SEL, and the input current Iin has a current value of the corresponding designated level. In step S05, the pad control circuit 130 outputs a selection signal SEL indicating a minimum level to the current regulating circuit CRt, so that the current regulating circuit CRt executes the selection signal SEL and the input current Iin has a current value of the minimum level. In some embodiments, the selection signal SEL can be a digital signal.

[0049] In some embodiments, the current regulating circuit CRt can be connected to the ground VSS via the current switch 127. In steps S01 to S06, the current switch 127 is in the on state. In step S07, the current switch 127 is switched to and maintained in the off state to shut down the entire receiver circuit RX by shutting down the input current Iin of the current mirror CRm.

[0050] In some embodiments, the current mirror CRm can be implemented by a plurality of transistors M11 and M12. The current regulating circuit CRt can be implemented by a plurality of transistors M13 and M14 and a plurality of resistors R1 and R2. The transistors M11, M12, M13 and M14 can be bipolar junction transistors, metal oxide semiconductor field effect transistors, field effect transistors, or insulated gate bipolar transistors.

[0051] In some embodiments, the current mirror CRm includes two transistors M11 and M12. The current regulating circuit CRt includes two transistors M13 and M14 and two resistors R1 and R2. The first end of the transistor M11 is connected to the power supply VDD, and the second end of the transistor M11 is connected to the first end of the transistor M13 and the first end of the resistor R1. The third end of the transistor M11 is connected to the second end of the transistor M11 and the third end of the transistor M12. The first end of the transistor M12 is connected to the power supply VDD, and the second end of the transistor M12 is connected to the working switch M35. In other words, the working switch M35 is connected between the second end of the transistor M12 and the power supply end of the comparator CP1 of the first stage. The second end of the transistor M13 and the second end of the resistor R1 are connected to the first end of the transistor M14 and the first end of the resistor R2. The second end of the transistor M14 and the second end of the resistor R2 are connected to the first end of the current switch 127. The second end of the current switch 127 is connected to the ground VSS. The control terminals of the transistors M13 and M14 and the control terminal of the current switch 127 are connected to the pad control circuit 130 and are respectively connected to the selection signal SEL and the mode signal PD.

[0052] In some embodiments, the selection signal SEL may be a logic signal. The pad control circuit 130 sends logic signals to the transistors M13 and M14 of the current regulating circuit CRt, respectively, so that the current regulating circuit CRt adjusts the input current Iin according to the logic signal. The selection signal SEL may be a multi-bit logic signal, and the number of bits is the same as the number of transistors M13 and M14 of the current regulating circuit CRt. The multiple bits SEL of the selection signal SEL <1> , SEL <0> The transistors M13 and M14 of the current regulating circuit CRt are respectively corresponding to each other, so that each transistor M13 / M14 can select the corresponding bit SEL in the selection signal SEL. <1> / SEL <0> to control.

[0053] For example, taking the two transistors M13 and M14 of the current regulating circuit CRt as an example, at this time, the two bits SEL of the selection signal SEL <1> , SEL <0> (hereinafter referred to as the first SEL <1> With the second SEL <0> . The first SEL <1> Corresponding to transistor M13, and the second bit SEL <0> Corresponding to transistor M14. Therefore, the selection signal SEL has 4 combinations, and the 4 combinations correspond to 4 different levels of input current Iin.

[0054] When the pad control circuit 130 sends a selection signal SEL of 1 (ie, the first bit SEL <1> is 1) to the transistor M13 and sends a selection signal SEL of 1 (i.e., the second bit SEL <0> When the input current Iin is 1) to the transistor M14, the current regulating circuit CRt will adjust the input current Iin to the maximum value, and the operating current Iout generated by the current mirror CRm will also be the maximum value.

[0055] When the pad control circuit 130 sends a selection signal SEL of 0 (ie, the first bit SEL <1> is 0) to the transistor M13 and sends a selection signal SEL of 0 (ie, the second bit SEL <0> When the input current Iin is 0) and the transistor M14 is supplied, the current regulating circuit CRt will adjust the input current Iin to the minimum value, and the operating current Iout generated by the current mirror CRm will also be the maximum value.

[0056] When the pad control circuit 130 sends a selection signal SEL of 1 (ie, the first bit SEL <1> is 1) to transistor M13 and sends a selection signal SEL of 0 (i.e., the second bit SEL <0> 0) to the transistor M14, or when the pad control circuit 130 sends a selection signal SEL of 0 (ie, the first SEL <1> is 0) to the transistor M13 and sends a selection signal SEL of 1 (i.e., the second bit SEL <0> 1) to transistor M14, the current regulating circuit CRt will adjust the value of the input current Iin between the maximum value and the minimum value, for example, three quarters of the maximum value and one quarter of the maximum value respectively. Similarly, the operating current Iout generated by the current mirror CRm will also be between the maximum value and the minimum value.

[0057] Therefore, in this exemplary embodiment, in step S05, the pad control circuit 130 forcibly sends a logic signal of 00 to the control terminals of the two transistors M13 and M14 of the current regulating circuit CRt, so that the current regulating circuit CRt reduces the input current Iin to the minimum value. At this time, the operating current Iout generated by the current mirror CRm is also reduced to the minimum value, thereby achieving the goal of reducing the operating current Iout to the minimum.

[0058] In summary, the memory control circuit 10 and its control method of any embodiment can switch the idle memory control circuit 10 from the power saving mode to the deep power saving mode, and make its receiver circuit RX enter the deep power saving state from the power saving state, thereby greatly reducing the overall power consumption of the memory control circuit 10, and will not reduce the system performance. In other words, when a read operation is required, the memory control circuit 10 can switch from the deep power saving mode to the working mode for performing the read operation in real time, that is, it can wake up the receiver circuit RX in real time to smoothly receive the read data. Although the technical content of this case has been disclosed as above in various embodiments, it is not used to limit the scope of protection of this case. Any changes or modifications made by any person with ordinary knowledge in the field to which this case belongs without departing from the spirit of this case are within the scope of protection of this case. Therefore, the scope of protection of this case should be based on the content of the claims.

Explanation of symbols

[0059] 10: Memory control circuit 110: Access control circuit 120: Connection pad circuit 121: Current mirror circuit 123: Switching Circuit 125: Output stage 127: Current switch 130: pad control circuit 20: Memory PAD: External pad RX: Receiver Circuit TX: Transmitter circuit CPn: Comparator group Iin: Input current Iout: working current VDD: Power supply VSS: Ground R1: Resistor R2: Resistor M11: Transistor M12: Transistor M13: Transistor M14: Transistor M31: Short-circuit switch M32: Short-circuit switch M33: Short-circuit switch M34: Short-circuit switch M35: Working switch PD: Mode signal CP1: Comparator CP2: Comparator CP3: Comparator SW: control signal CRm: Current mirror CRt: Current regulation circuit SEL: Select signal SEL <1> :First SEL <0> : Second place IE:Logical signal S01~S07: Steps AND: AND Gate

Claims

1. A memory control circuit, characterized in that: include: an access control circuit, sending a read instruction, a write instruction or a power saving instruction; A connection pad circuit comprising: a transmitter circuit; and a receiver circuit, the transmitter circuit and the receiver circuit are connected to a memory via an external pad; and A pad control circuit is connected between the access control circuit and the receiver circuit. The pad control circuit executes the read instruction to drive the receiver circuit to receive a read data from the memory through the external pad; the pad control circuit executes the write instruction or closes the output of the receiver circuit after receiving the read data, so that the receiver circuit enters a power saving state, and then executes the power saving instruction to reduce an operating current of the receiver circuit and fix an internal signal of the receiver circuit at a level, so that the receiver circuit enters a deep power saving state.

2. The memory control circuit according to claim 1, wherein: The receiver circuit includes: a current mirror circuit, controlled by the pad control circuit, mirroring an input current to generate the working current; a comparator group connected to the external pad and powered by the working current; an output stage connected between the comparator set and the pad control circuit; and A switch circuit is connected to the comparator group and is controlled by the pad control circuit.

3. The memory control circuit according to claim 2, wherein: The switching circuit comprises: a working switch connected between the current mirror circuit and the comparator group and controlled by the pad control circuit; Wherein, in the deep power saving state, the pad control circuit further controls the working switch to disconnect the power supply path between the current mirror circuit and the comparator group for providing the working current to the comparator group.

4. The memory control circuit according to claim 2, wherein: In the deep power saving state, the pad control circuit forces the level of the internal signal of the receiver circuit by controlling the switch circuit to respectively connect the input terminals of the comparator group to a power supply and a ground.

5. The memory control circuit according to claim 2, wherein: In the power saving state and the deep power saving state, the pad control circuit turns off the output of the receiver circuit by forcing the output stage to a non-output state.

6. The memory control circuit according to claim 5, characterized in that: The output stage is an AND gate, and the pad control circuit forces the output stage to be in a non-output state by providing a logic signal to an input terminal of the AND gate, and the logic signal is 0.

7. The memory control circuit according to claim 2, wherein: The receiver circuit also includes: A current switch is connected between the current mirror circuit and a ground, and executes a power-off instruction to disconnect the current mirror circuit from the ground, so that the receiver circuit enters a power-off state.

8. The memory control circuit according to claim 2, wherein: The comparator group includes: A plurality of comparators connected in series between the external pad and the pad control circuit; Wherein, in the deep power saving state, the pad control circuit turns off the first comparator among the multiple comparators by controlling the switch circuit to disconnect the current mirror circuit and controls the switch circuit to respectively connect the two input terminals of the remaining comparators among the multiple comparators to a power supply and a ground to force the level of the internal signal of the receiver circuit.

9. The memory control circuit according to claim 2, wherein: The current mirror circuit includes: a current mirror, mapping the input current into the operating current; and A current regulating circuit is connected to the current mirror and is controlled by the pad control circuit to adjust the magnitude of the input current.

10. A control method for a memory control circuit, characterized in that: include: receiving a read instruction; Executing the read instruction to receive a read data from a memory via a receiver circuit; After receiving the read data or executing a write instruction, controlling the receiver circuit to enter a power saving state; and Executing a power saving instruction to control the receiver circuit to enter a deep power saving state from the power saving state; The step of entering the power saving state includes: turning off the output of the receiver circuit; and The steps of entering the deep power saving state include: turning off the output of the receiver circuit; reducing a working current of the receiver circuit to a minimum; and forcing a level of an internal signal of the receiver circuit.

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