Reconfigurable ternary content addressable storage unit and matching entry search method thereof

Abstract

This invention provides a reconfigurable tri-state content-addressable memory cell and its matching entry lookup method, relating to the field of non-volatile memory circuit design technology. The reconfigurable tri-state content-addressable memory cell includes a data storage module, a write control module, a first comparison module, and a second comparison module. The matching entry lookup method implemented based on this reconfigurable tri-state content-addressable memory cell can achieve two different search modes according to external control instructions. The first search mode can realize the tri-state data matching and lookup function of TCAM, and the second search mode, based on the first search mode, can realize the lookup of precise matching entries. This invention adopts a reconfigurable reuse approach, using the same circuit structure to not only realize the basic matching and lookup function of TCAM, but also to directly look up precise matching entries, saving hardware resources.

Description

Technical Field

[0001] This invention relates to the field of non-volatile memory circuit design technology, and in particular to a reconfigurable three-state addressable memory cell and a matching entry lookup method thereof. Background Technology

[0002] TCAM (Tri-State Content Addressable Memory) is widely used in applications requiring high-speed data lookup due to its high-speed and fully parallel data search capabilities. However, with the continuous shrinking of CMOS (Complementary Metal-Oxide-Semiconductor) feature sizes, the leakage current in traditional CMOS-based TCAMs is constantly increasing, leading to high standby power consumption. TCAMs based on non-volatile devices such as MTJ (Magnetic Tunnel Junction) are beginning to attract attention and research.

[0003] Writing based on the STT (Spin-Torque Transfer) effect is a widely used MTJ writing mechanism. However, the pursuit of faster writing speeds leads to relatively large STT write currents, which accelerate the aging of the MTJ barrier layer, resulting in poor write tolerance. The SOT (Spin-Orbit Transfer Torque) effect overcomes the shortcomings of STT writing. SOT writing directly overcomes the magnetic anisotropy field, causing the magnetization direction of the MTJ free layer to reverse, achieving high-speed switching. Furthermore, the write current passes directly through the heavy metal layer instead of the MTJ, avoiding damage to the barrier layer. However, to achieve deterministic switching of perpendicularly magnetically anisotropic MTJs, an additional magnetic field is required on top of SOT, increasing the writing complexity. To address these issues, an STT-assisted SOT MTJ writing method has emerged. This method utilizes the interaction between the STT and SOT effects to achieve effective MTJ switching under field-free conditions and shortens the write pulse width, thus improving switching speed, energy efficiency, and write tolerance.

[0004] The third state 'X' (ignorant bit) of TCAM acts as a wildcard, matching any search data among '0', '1', and 'X'. Therefore, TCAM typically requires a PE (priority encoder) to select the highest-priority matching entry to resolve the multiple matching problem caused by the third state 'X'. However, the PE can only select the entry with the highest degree of matching among multiple matching results, and this entry may still store the 'X' state. Therefore, TCAM cannot meet the needs of certain application scenarios requiring precise matching like BCAM (two-state content-addressable memory). Summary of the Invention

[0005] Purpose of the invention: To propose a reconfigurable tri-state content addressable memory cell based on STT-assisted SOT writing, and further to propose a matching entry lookup method based on this TCAM memory cell, so as to solve the above-mentioned problems proposed in the prior art.

[0006] To achieve the above-mentioned technical objectives, the technical solution adopted by the present invention is as follows:

[0007] A reconfigurable three-state content addressable storage unit includes four components: a data storage module, a write control module, a first comparison module, and a second comparison module.

[0008] The data storage module consists of two perpendicular magnetic anisotropic MTJs (magnetic tunnel junctions) and a heavy metal layer forming a four-port device. It includes a first fixed layer, a first barrier layer, a first free layer, and a heavy metal layer of the magnetic tunnel junction M0, and a second free layer, a second barrier layer, and a second fixed layer of the magnetic tunnel junction M1, which are stacked in sequence.

[0009] The write control module consists of P-type transistor P0 and N-type transistors N0, N1, and N2. The gate of transistor P0 is connected to the first control signal V0, its drain is connected to one end of the heavy metal layer, and its source is connected to the first bit line BL0. The gate of transistor N0 is connected to the word line WL, its drain is connected to the other end of the heavy metal layer, and its source is connected to the second bit line BLB0. The gate of transistor N1 is connected to the first source line SL, its drain is connected to the first fixed layer of M0, and its source is connected to the third bit line BL1. The gate of transistor N2 is connected to the second source line SLB, its drain is connected to the second fixed layer of M1, and its source is connected to the fourth bit line BLB1.

[0010] The first comparison module consists of an inverter INV0 and an N-type transistor N3. The input of the inverter is connected to the drain of transistor P0, and the output is connected to the gate of transistor N3. The drain of transistor N3 is connected to the first matching line ML0, and the source is grounded.

[0011] The second comparison module consists of P-type transistors P1 and P2 and N-type transistor N4. The gate of transistor P1 is connected to the second control signal V1, its drain is connected to the first fixed layer of the magnetic tunnel junction M0, and its source is connected to the power supply voltage VDD. The gate of transistor P2 is connected to the first fixed layer of the magnetic tunnel junction M0, its drain is connected to the drain of transistor N4, and its source is connected to the second matching line ML1. The gate of transistor N4 is connected to the second search mode enable signal SENX, and its source is grounded.

[0012] This invention utilizes STT-assisted SOT to flip the magnetization direction of the free layers of magnetic tunnel junctions M0 and M1 under field-free conditions, thereby efficiently enabling data writing to the memory cell. When writing data, transistors P0 and N0 first turn on in response to the word line signal WL and the first control signal V0. The first bit line BL0 and the second bit line BLB0 are connected to a control voltage to control a current pulse with a set direction in the heavy metal layer. Then, transistor N1 or N2 turns on in response to the first source line SL or the second source line SLB, and simultaneously, the third bit line BL1 or the fourth bit line BLB1 is connected to a control voltage, causing a current with a set direction to flow through magnetic tunnel junctions M0 or M1. When transistor N1 is on, the third bit line BL1 is connected to a control voltage, causing a current with a set direction to flow through magnetic tunnel junction M0, thereby changing the relative magnetization direction of magnetic tunnel junction M0. When transistor N2 is on, the fourth bit line BLB1 is connected to a control voltage, causing a current with a set direction to flow through magnetic tunnel junction M1, thereby changing the relative magnetization direction of magnetic tunnel junction M1.

[0013] The present invention also proposes a matching item search method using the reconfigurable three-state content storage unit, which includes two sets of search modes to achieve two matching search schemes for different purposes.

[0014] The first search mode performs the basic three-state matching lookup function of TCAM. When the stored data is in the third state 'X' or matches the search data, it means that the stored data matches the search data. The second search mode implements the exact matching lookup function of TCAM based on the first search mode. Among all matching entries after the first search mode, if and only if the stored data matches the search data, it means that the stored data matches the search data exactly. If the stored data is in the third state 'X', it is not an exact match.

[0015] When the first search mode is used, transistor N1 or N2 turns on in response to the first source line SL or the second source line SLB. The first bit line BL0 is connected to the power supply voltage VDD, and the third bit line BL1 and the fourth bit line BLB1 are grounded. The first control signal V0 is connected to the first control voltage VDD. BIAS1 A predetermined current is controlled to flow through transistor P0, which flows from the drain of transistor P0 through one of the magnetic tunnel junctions M0 and M1. The voltage at node Q0, where the drain of transistor P0 and one end of the heavy metal layer are connected, controls the switching of transistor N3 via the first inverter INV0, thereby controlling whether the first matching line ML0 is grounded through transistor N3. ML0 will not be grounded through transistor N3 only if the data stored in the memory cell matches the search data or is in the 'X' state.

[0016] When the second search mode is used, the fourth bit line BLB1 is grounded, and transistor N2 turns on in response to the second source line SLB. The second control signal V1 is connected to the second control voltage V. BIAS2A predetermined current is controlled to flow through transistor P1, which flows from the drain of transistor P1 through magnetic tunnel junctions M0 and M1. The voltage at node Q1, where the drains of transistors P1 and N1 are connected, is determined by the series resistance of the magnetic tunnel junctions M0 and M1. The voltage at node Q1 controls the switching of transistor P2 to control whether the second matching line ML1 is connected to the drain of transistor P2. Transistor N4 is turned on in response to the second search mode enable signal SENX, causing the drain of transistor P2 to be grounded through transistor N4. Node Q1 is high only when storing data in the 'X' state; transistor P2 is not turned on, and ML1 is not grounded through transistors P2 and N4.

[0017] Beneficial Effects: This invention proposes a reconfigurable tri-state content-addressable memory unit and its matching entry search method. This tri-state content-addressable memory unit can implement two different search modes according to external control instructions. The first search mode enables the tri-state data matching and search function of the TCAM, while the second search mode, based on the first search mode, enables the search for precise matching entries. This invention adopts a reconfigurable and reused approach, using the same circuit structure to not only implement the basic matching and search function of the TCAM but also to directly search for precise matching entries, thus saving hardware resources. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the circuit structure of TCAM in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the relevant signal timing when TCAM writes data in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the circuit structure and related signal timing of TCAM in the first search mode.

[0021] Figure 4 This is a schematic diagram of the circuit structure and related signal timing of TCAM in the second search mode. Detailed Implementation

[0022] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid obscuring the invention.

[0023] See Figure 1 This invention provides a reconfigurable tri-state content-addressable memory cell based on STT-assisted SOT, the circuit structure of which includes:

[0024] The data storage module consists of two MTJs (magnetic tunnel junctions) and a heavy metal layer, forming a non-volatile four-port device. It includes a first fixed layer 1, a first barrier layer 2, a first free layer 3, and a heavy metal layer 4 of a magnetic tunnel junction M0, and a second free layer 5, a second barrier layer 6, and a second fixed layer 7 of a magnetic tunnel junction M1, respectively. The first free layer 3 of M0 and the second free layer 5 of M1 are connected to the upper and lower surfaces of the heavy metal layer 4, respectively. In a specific embodiment, both magnetic tunnel junctions M0 and M1 are non-volatile devices, meaning that the data stored in the magnetic tunnel junctions will not be lost when power is off. Both magnetic tunnel junctions M0 and M1 are perpendicular magnetic anisotropic MTJs. By using a STT current to assist a SOT current, the magnetic tunnel junctions achieve effective reversible switching between high-resistance and low-resistance states to store 1 bit of information.

[0025] The write control module consists of P-type transistor P0 and N-type transistors N0, N1, and N2. The gate of transistor P0 is connected to the first control signal V0, its drain is connected to one end of the heavy metal layer 4, and its source is connected to the first bit line BL0. The gate of transistor N0 is connected to the word line WL, its drain is connected to the other end of the heavy metal layer 4, and its source is connected to the second bit line BLB0. The gate of transistor N1 is connected to the first source line SL, its drain is connected to the first fixed layer 1 of M0, and its source is connected to the third bit line BL1. The gate of transistor N2 is connected to the second source line SLB, its drain is connected to the second fixed layer 7 of M1, and its source is connected to the fourth bit line BLB1.

[0026] The first comparison module consists of an inverter INV0 and an N-type transistor N3. The input of the inverter is connected to the drain of transistor P0, and the output is connected to the gate of transistor N3. The drain of transistor N3 is connected to the first matching line ML0, and the source is grounded.

[0027] The second comparison module consists of P-type transistors P1 and P2 and an N-type transistor N4. The gate of transistor P1 is connected to the second control signal V1, its drain is connected to the first fixed layer 1 of the magnetic tunnel junction M0, and its source is connected to the power supply voltage VDD. The gate of transistor P2 is connected to the first fixed layer 1 of the magnetic tunnel junction M0, its drain is connected to the drain of transistor N4, and its source is connected to the second matching line ML1. The gate of transistor N4 is connected to the second search mode enable signal SENX, and its source is grounded.

[0028] When writing to a memory cell, the correspondence between the stored data and the resistance states of the magnetic tunnel junctions M0 and M1 is as follows: When the stored data is '1', magnetic tunnel junction M0 is in the AP state and M1 is in the P state; when the stored data is '0', magnetic tunnel junction M0 is in the P state and M1 is in the AP state; when the stored data is 'X', both magnetic tunnel junctions M0 and M1 are in the AP state. Here, AP represents that the relative magnetization directions of the magnetic tunnel junctions are antiparallel, corresponding to a high-resistance state, and P represents that the relative magnetization directions of the magnetic tunnel junctions are parallel, corresponding to a low-resistance state.

[0029] In the second search mode, when the stored data is '1' or '0', the resistance states of magnetic tunnel junctions M0 and M1 are complementary, meaning one is in a high-resistance state and the other in a low-resistance state. Therefore, the series resistance of M0 and M1 is small, the voltage division at node Q1 is small, transistor P2 is turned on, and the second matching line ML1 discharges to GND. When the stored data is the third state 'X', both magnetic tunnel junctions M0 and M1 are in a high-resistance state. Therefore, the series resistance of M0 and M1 is large, the voltage division at node Q1 is large, transistor P2 is turned off, and the second matching line ML1 remains at VDD. By combining the state of the first matching line ML0 after the first search mode ends and the state of the second matching line ML1 after the second search mode ends, it can be determined whether the stored data and the search data are precisely matched.

[0030] When data is written, the voltage of the second control signal V1 is VDD, and the voltage of the second search mode enable signal SENX is GND, so transistors P1 and N4 are turned off. The voltage of the first control signal V0 remains GND, and the voltage of the word line signal WL remains VDD. The first source line SL and the second source line SLB control the switching of transistors N1 and N2 during data writing to achieve magnetization direction reversal operations on magnetic tunnel junctions M0 and M1 in two stages. The first stage performs magnetization direction reversal operations on magnetic tunnel junction M0, and the second stage performs magnetization direction reversal operations on magnetic tunnel junction M1. The voltages of the first bit line BL0, the second bit line BLB0, the third bit line BL1, the fourth bit line BLB1, the first source line SL, and the second source line SLB determine whether the magnetic tunnel junction is written to the AP state or the P state.

[0031] like Figure 2 As shown in (a), when magnetic tunnel junction M0 or M1 needs to be written to the P state, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND. At this time, transistors P0 and N0 are both turned on. Simultaneously, the voltages of the first source line SL and the second source line SLB are both GND, and transistors N1 and N1 are both turned off. The voltage difference between the first bit line BL0 and the second bit line BLB0 will cause a current I in a predetermined direction to flow in the heavy metal layer. SOT Current I in the heavy metal layer SOTAfter a short period of time, the voltage on the second bit line BLB0 will change from GND to VDD, causing transistor N0 to change from on to off. Simultaneously, the voltage on the first source line SL (or the second source line SLB) will change from GND to VDDa, and the voltage on the third bit line BL1 (or the fourth bit line BLB1) will be GND, turning on transistor N1 (or N2). The voltage difference between the first bit line BL0 and the third bit line BL1 (or the fourth bit line BLB1) will then cause a current I in a predetermined direction to flow through the magnetic tunnel junction M0 (or M1). STT The current will flow from the drain of transistor P0 through the heavy metal layer, then into the free layer of M0 (or M1), and out from the fixed layer of M0 (or M1). Current I STT After a period of time, the magnetic tunnel junction will flip to the P state. It is worth noting that when using STT to assist SOT in changing the state of the magnetic tunnel junction, the current I... STT A small value is needed to achieve the state flip of the magnetic tunnel junction, so a voltage VDDa slightly higher than VDD is enough to allow sufficient STT current to flow through transistor N1 or N2.

[0032] like Figure 2 As shown in (b), when magnetic tunnel junction M0 or M1 needs to be written to the AP state, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND. At this time, transistors P0 and N0 are both turned on. At the same time, the voltages of the first source line SL and the second source line SLB are both GND, and transistors N1 and N1 are both turned off. Then, the voltage difference between the first bit line BL0 and the second bit line BLB0 will cause a current I in a set direction to be conducted in the heavy metal layer. SOT Current I in the heavy metal layer SOT After a short period of time, the voltage on the first bit line BL0 will change from VDD to GND, causing transistor P0 to change from on to off. Simultaneously, the voltage on the first source line SL (or the second source line SLB) will change from GND to VDDa, and the voltage on the third bit line BL1 (or the fourth bit line BLB1) will be VDD. Transistor N1 (or N2) will then turn on. The voltage difference between the second bit line BLB0 and the third bit line BL1 (or the fourth bit line BLB1) will cause a current I in a predetermined direction to flow through the magnetic tunnel junction M0 or M1. STT The current will flow from the drain of transistor N1 (or N2) into the fixed layer of M0 (or M1) and out from the free layer of M0 (or M1), then through the heavy metal layer to the drain of transistor N0. Current I STT After a period of time, the magnetic tunnel junction will flip to the AP state.

[0033] Specifically, if data '1' needs to be written to the memory cell, the magnetization direction of magnetic tunnel junctions M0 and M1 is reversed in two stages. In the first stage, the voltage of the second control signal V1 is VDD, and the voltage of the second search mode enable signal SENX is GND, so transistors P1 and N4 are turned off. The voltage of the first control signal V0 remains at GND, and the voltage of the word line signal WL remains at VDD. First, the voltage of the first source line SL and the second source line SLB is GND, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND, so transistors N1 and N2 are turned off, and P0 and N0 are turned on. Due to the voltage difference between the first bit line BL0 and the second bit line BLB0, a current I in a set direction is conducted in the heavy metal layer. SOT Current I in the heavy metal layer SOT After a short period of time, the voltage on the first bit line BL0 will change from VDD to GND, causing transistor P0 to change from on to off. Simultaneously, the voltage on the first source line SL changes from GND to VDDa, and the voltage on the third bit line BL1 becomes VDD, turning on transistor N1. The voltage difference between the second bit line BLB0 and the third bit line BL1 will then cause a current I in a predetermined direction to flow through the magnetic tunnel junction M0. STT The current will flow from the drain of transistor N1 into the fixed layer of M0 and out of the free layer of M0, then through the heavy metal layer to the drain of transistor N0. The current I STT After a period of time, the magnetic tunnel junction M0 will flip to the AP state.

[0034] In the second stage, the voltage of the second control signal V1 is VDD, and the voltage of the second search mode enable signal SENX is GND, so transistors P1 and N4 are turned off. The voltage of the first control signal V0 remains GND, and the voltage of the word line signal WL remains VDD. Initially, the voltages of the first and second source lines are GND, the voltage of the first bit line BL0 is VDD, and the voltage of the second bit line BLB0 is GND, so transistors N1 and N2 are turned off, and P0 and N0 are turned on. Due to the voltage difference between the first bit line BL0 and the second bit line BLB0, a current I in a set direction is conducted in the heavy metal layer. SOT Current I in the heavy metal layer SOT After a short period of time, the voltage of the second bit line BLB0 will change from GND to VDD, causing transistor N0 to change from on to off. Simultaneously, the voltage of the second source line SLB changes from GND to VDDa, and the voltage of the fourth bit line BLB1 is GND, turning on transistor N2. The voltage difference between the first bit line BL0 and the fourth bit line BLB1 will cause a current I in a predetermined direction to flow through the magnetic tunnel junction M1. STT The current will flow from the drain of transistor P0 through the heavy metal layer, then into the free layer of M1, and out from the fixed layer of M1. Current I STTAfter a period of time, the magnetic tunnel junction M1 will flip to the P state.

[0035] like Figure 3 As shown, when performing the first search mode, the first matching line ML0 is pre-charged to VDD through an external transistor in the initial state. The voltage of the word line signal WL is GND, the voltage of the second bit line BLB0 is GND, the voltage of the second control signal V1 is VDD, and the voltage of the second search mode enable signal SENX is GND, so transistors N0, P1, and N4 are all off. The voltages of the third bit line BL1 and the fourth bit line BLB1 are both GND. The first source line SL and the second source line SLB are complementary signals at this time: when searching for '1', the voltage of the first source line SL is VDD, and the voltage of the second source line SLB is GND, so transistor N1 is turned on and N2 is turned off; when searching for '0', the voltage of the first source line SL is GND, and the voltage of the second source line SLB is VDD, so transistor N1 is turned off and N2 is turned on. The voltage of the first control signal V0 is VDD. BIAS0 This causes a constant current I to flow through transistor P0. READ1 When searching for '1', the constant current I READ1 The current flows from the drain of P0 to the heavy metal layer, through the free layer, barrier layer, fixed layer of M0, and transistor N1, before flowing to GND; when searching for '1', the constant current I... READ1 The current flows from the drain of P0 to the heavy metal layer, through the free layer, barrier layer, fixed layer of M1, and transistor N2, before flowing to GND. The constant current I varies depending on whether the data is stored or searched. READ1 The magnetic tunnel junctions in the DC path have different resistance states, resulting in different voltage divisions at node Q0. The Q0 voltage controls the switching of transistor N3 via the first inverter INV0 to determine whether the first matching line ML0, which has been pre-charged to VDD, should be discharged. The voltage of the final first matching line ML0 indicates whether the stored data matches the searched data.

[0036] If the stored data and the search data match, that is, the stored data is in the third state 'X' or is the same as the search data, the constant current I... READ1 When the magnetic tunnel junction in the DC path is in a high-resistance state (AP), and point Q0 is at a high voltage, transistor N3 is turned off, resulting in the first matching line ML0 maintaining VDD; if the stored data and the search data do not match, i.e., the stored data and the search data are not the same, the constant current I... READ1 When the magnetic tunnel junction in the DC path is in a low-resistance state (P) and the voltage at point Q0 is low, transistor N3 is turned on, resulting in the first matching line ML0 discharging to GND through transistor N3.

[0037] Taking a search operation when the memory cell stores '1' as an example. When the stored data is '1', the magnetic tunnel junction M0 is in the AP state, and the magnetic tunnel junction M1 is in the P state. When searching for '1', the voltage of the first source line SL is VDD, and the voltage of the second source line SLB is GND. Therefore, transistor N1 is turned on, and N2 is turned off. The magnetic tunnel junction M0 will have a constant current I. READ1 In the DC path, since the magnetic tunnel junction M0 is in a high-resistance state, the voltage at node Q0 is high, transistor N3 is off, and the first matching line ML0 will remain at VDD. When searching for '0', the voltage at the first source line SL is GND, and the voltage at the second source line SLB is VDD, so transistor N1 is off and N2 is on. The magnetic tunnel junction M1 will then have a constant current I. READ1 In the DC path, since the magnetic tunnel junction M1 is in a low-resistance state, the voltage of node Q0 is low, the transistor N3 is turned on, and the first matching line ML0 will discharge to GND through N3.

[0038] The first search mode completes the basic three-state matching lookup function of the TCAM, and the matching result is reflected in the voltage of the first matching line ML0. When the stored data is in the third state 'X' or matches the search data, it means that the stored data matches the search data, and ML0 is always VDD. When the stored data differs from the search data, it means that the stored data does not match the search data, and ML0 will discharge to GND.

[0039] After the first search mode ends, the second search mode can be initiated based on the second search mode enable signal SENX. For example... Figure 4 As shown, when the second search mode is entered, the second matching line ML1 is pre-charged to VDD through an external transistor in the initial state. The voltage of the second search mode enable signal SENX is VDD, the voltage of the word line signal WL is GND, the voltage of the first control signal V0 is VDD, the voltages of the first bit line BL0, the second bit line BLB0, the third bit line BL1, and the fourth bit line BLB1 are all GND, the voltage of the first source line SL is GND, and the voltage of the second source line SLB is VDD. Therefore, transistors N2 and N4 are turned on, and P0, N0, and N1 are turned off. The voltage of the second control signal V1 is VDD. BIAS1 This causes a constant current I to flow through transistor P1. READ2The current flows from the drain of transistor P1 to the fixed layer of magnetic tunnel junction M0, through the barrier layer, free layer, and heavy metal layer of M0, and the free layer, barrier layer, fixed layer, and transistor N2 before flowing to GND. Node Q1 will generate different voltage divisions based on the series resistance of magnetic tunnel junctions M0 and M1. This voltage controls the switching of transistor P2 to determine whether the second matching line ML1, which has been pre-charged to VDD, should discharge. If the first matching line ML0 remains at VDD in the first search mode, and the second matching line ML1 discharges to GND in the second search mode, it indicates that the stored data and the search data are precisely matched; if the second matching line ML1 remains at VDD in the second search mode, it indicates that the stored data and the search data are not precisely matched.

[0040] Taking storing '1' and searching for '1' as an example, since the stored data and the search data are the same, the first matching line ML0 will remain at VDD after the first search mode ends. Because the magnetic tunnel junctions M0 and M1 are in AP and P states respectively when storing '1', and their series resistance is small, the voltage at node Q1 is small during the second search mode. Transistor P2 will then conduct, and the second matching line ML1 will discharge to GND, indicating that the stored data and the search data are precisely matched.

[0041] Taking storing 'X' and searching for '1' as an example, since the stored data is in the third state 'X', the first matching line ML0 will remain at VDD after the first search mode ends. Because the magnetic tunnel junctions M0 and M1 are both in the AP state when storing 'X', their series resistance is relatively large. Therefore, the voltage at node Q1 is relatively large during the second search mode, transistor P2 is cut off, and the second matching line ML1 will remain at VDD. This indicates that the stored data and the search data are not precisely matched, but rather matched due to storing the third state 'X'.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for finding matching entries in a reconfigurable three-state content-addressable storage unit, characterized in that, The reconfigurable tri-state content addressable storage unit includes a data storage module, a write control module, a first comparison module, and a second comparison module; The data storage module includes a first fixed layer, a first barrier layer, a first free layer, and a heavy metal layer of a magnetic tunnel junction M0, and a second free layer, a second barrier layer, and a second fixed layer of a magnetic tunnel junction M1, which are stacked in sequence. The write control module includes a P-type transistor P0 and N-type transistors N0, N1, and N2; wherein, the gate of the P-type transistor P0 is connected to the first control signal V0, the drain is connected to one end of the heavy metal layer, and the source is connected to the first bit line BL0. The gate of the N-type transistor N0 is connected to the word line WL, the drain is connected to the other end of the heavy metal layer, and the source is connected to the second bit line BLB0. The gate of the N-type transistor N1 is connected to the first source line SL, the drain is connected to the first fixed layer of the magnetic tunnel junction M0, and the source is connected to the third bit line BL1. The gate of N-type transistor N2 is connected to the second source line SLB, the drain is connected to the second fixed layer of magnetic tunnel junction M1, and the source is connected to the fourth bit line BLB1. The first comparison module includes an inverter INV0 and an N-type transistor N3; the input terminal of the inverter INV0 is connected to the drain of the P-type transistor P0, and the output terminal is connected to the gate of the N-type transistor N3; the drain of the N-type transistor N3 is connected to the first matching line ML0, and the source is grounded. The second comparison module includes P-type transistors P1 and P2 and N-type transistor N4; the gate of P-type transistor P1 is connected to the second control signal V1, the drain is connected to the first fixed layer of magnetic tunnel junction M0, and the source is connected to the power supply voltage VDD. The gate of P-type transistor P2 is connected to the first fixed layer of magnetic tunnel junction M0, the drain is connected to the drain of N-type transistor N4, and the source is connected to the second matching line ML1. The gate of N-type transistor N4 is connected to the second search mode enable signal SENX, and the source is grounded. Including the first search mode and the second search mode; The three-state matching and search function of TCAM is completed by the first search mode; The second search mode enables precise matching and search of TCAM based on the first search mode; After the first search mode ends, the state of the second search mode enable signal SENX determines whether to perform the second search mode. When using the first search mode: N-type transistors N1 or N2 turn on in response to the first source line SL or the second source line SLB. The first source line BL0 is connected to the power supply voltage VDD, and the third source line BL1 and the fourth source line BLB1 are grounded. The first control signal V0 is connected to the first control voltage V BIAS1 To control the conduction of a set current in transistor P0, the set current flows from the drain of P-type transistor P0 through one of the magnetic tunnel junctions M0 or M1; The voltage at node Q0, where the drain of P-type transistor P0 is connected to one end of the heavy metal layer, controls the switch of transistor N3 after passing through the first inverter INV0, thereby controlling whether the first matching line ML0 is grounded through transistor N3. Node Q0 is high voltage, inverter INV0 output voltage is low voltage, transistor N3 is turned off, and ML0 will not be grounded through transistor N3 if and only if the data stored in the memory cell is the same as the search data or is in the third state. When using the second search mode: The fourth bit line BLB1 is grounded, and the N-type transistor N2 turns on in response to the second source line SLB; The second control signal V1 is connected to the second control voltage V. BIAS2 To control the conduction of a set current in transistor P1, the set current flows from the drain of transistor P1 through magnetic tunnel junctions M0 and M1; The voltage at node Q1, where the drain of P-type transistor P1 and the drain of N-type transistor N1 are connected, will be determined by the series resistance of magnetic tunnel junctions M0 and M1. The voltage at node Q1 controls the switching of P-type transistor P2 to control whether the second matching line ML1 is connected to the drain of transistor P2. N-type transistor N4 turns on in response to the second search mode enable signal SENX, causing the drain of transistor P2 to be connected to ground through transistor N4; The switching state of transistor P2 determines whether the second matching line ML1 is connected to ground through transistor P2 and N4. Node Q1 is high voltage if and only if the data stored in the memory cell is in the third state 'X', transistor P2 will not be turned on, and ML1 will not be grounded through transistor P2 and N4.

2. The matching entry lookup method for reconfigurable tri-state content addressable storage units according to claim 1, characterized in that, When writing data: P-type transistor P0 and N-type transistor N0 are turned on in response to word line signal WL and first control signal V0. The first bit line BL0 and the second bit line BLB0 are connected to the control voltage to control the conduction of a current pulse in a set direction in the heavy metal layer. N-type transistors N1 or N2 turn on in response to the first source line SL or the second source line SLB.

3. The matching entry lookup method for reconfigurable tri-state content addressable storage units according to claim 2, characterized in that, When the N-type transistor N1 is turned on, the third bit line BL1 is connected to the fixed layer of the magnetic tunnel junction M0. The control voltage applied to the third bit line BL1 causes a current in a set direction to flow through the magnetic tunnel junction M0, thereby changing the relative magnetization direction of the magnetic tunnel junction M0.

4. The matching entry lookup method for reconfigurable tri-state content addressable storage units according to claim 2, characterized in that, When the N-type transistor N2 is turned on, the fourth bit line BLB1 is connected to the fixed layer of the magnetic tunnel junction M1. The control voltage connected to the fourth bit line BLB1 causes the magnetic tunnel junction M1 to flow with a current in a set direction, thereby changing the relative magnetization direction of the magnetic tunnel junction M1.

5. The matching entry lookup method for reconfigurable tri-state content addressable storage units according to claim 1, characterized in that, In the first search mode, when the stored data is in the third state or is consistent with the search data, it means that the stored data matches the search data; After the first search mode ends, among all the matching entries, if the stored data matches the search data, it means that the stored data and the search data are exactly matched. If the stored data is in the third state, it is not an exact match.

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