Chip packaging structure

Abstract

The invention discloses a chip packaging structure. The chip packaging structure comprises a first chip and a first conductive clamping piece, the first chip has a first surface and a second surface opposite to each other. The first conductive clamping piece is connected with the first surface of the first chip through a conductive material. The first conductive clamping piece comprises a flat area, a step-shaped structure and a first contact area. The stepped structure is located at the junction of the flat region and the first contact region and continuously surrounds the first contact region. According to the chip packaging structure, the ladder-shaped structure is arranged on the periphery of the contact area of the conductive clamping piece and the chip, the phenomenon of delamination caused by solder paste attachment in the packaging structure is effectively avoided, the product packaging reliability can be improved, and the cost can be effectively controlled.

Description

Technical Field

[0001] The present invention relates to chip packaging, and in particular to a chip packaging structure using a conductive clip. Background Art

[0002] Generally speaking, in the current chip packaging structure, the chip is electrically connected through a copper conductive clip, and solder paste is used as the connecting material between the conductive clip and the chip. Finally, a packaging material made of a dielectric material is used for packaging to form a chip packaging structure.

[0003] In order to enhance the bonding force between the conductive clip and the dielectric material, the surface of the conductive clip is usually roughened. However, when the conductive clip with roughened surface is reflowed, the liquid solder paste easily climbs from the side of the conductive clip to the top of the conductive clip due to the capillary phenomenon caused by the rough surface. The smooth surface of the solder paste easily causes delamination between it and the packaging material, thereby reducing the reliability of the chip packaging structure, which needs to be further solved. Summary of the invention

[0004] In view of this, the present invention proposes a chip packaging structure to effectively solve the above problems encountered in the prior art.

[0005] According to a specific embodiment of the present invention, a chip packaging structure is provided. In this embodiment, the chip packaging structure includes a first chip and a first conductive clip. The first chip has a first surface and a second surface opposite to each other. The first conductive clip is connected to the first surface of the first chip through a conductive material. The first conductive clip includes a first flat area, a first stepped structure and a first contact area. The first stepped structure is located at the junction of the first flat area and the first contact area, and the first stepped structure continuously surrounds the first contact area.

[0006] In one embodiment, the chip packaging structure further includes a substrate electrically connected to the second surface of the first chip.

[0007] In one embodiment, the chip packaging structure further includes a packaging material covering the first chip, at least a portion of the first conductive clip and a portion of the substrate.

[0008] In one embodiment, the first conductive clip has a rough surface.

[0009] In one embodiment, the chip packaging structure also includes a pad disposed on the first surface of the first chip, the pad being electrically connected to the first contact region of the first conductive clip through a conductive material, and the area of ​​the first contact region being less than or equal to the area of ​​the pad.

[0010] In one embodiment, the first stepped structure is formed by a stamping process.

[0011] In one embodiment, the chip package structure further includes a second chip that is horizontally separated from the first chip.

[0012] In one embodiment, the first conductive clip further includes a second contact region and a second stepped structure. The second contact region is separated from the first contact region and electrically connected to the second chip. The second stepped structure is located at the junction of the first flat region and the second contact region and the second stepped structure continuously surrounds the second contact region.

[0013] In one embodiment, the chip packaging structure further includes a second conductive clip separated from the first conductive clip and electrically connected to the second chip.

[0014] In one embodiment, the second conductive clip includes a second flat region, a second contact region and a second stepped structure. The second contact region is electrically connected to the second chip. The second stepped structure is located at the junction of the second flat region and the second contact region and the second stepped structure continuously surrounds the second contact region.

[0015] Compared with the prior art, the chip packaging structure proposed by the present invention has the following advantages and effects:

[0016] (1) Effectively improve reliability: The chip packaging structure proposed by the present invention has a stepped structure around the contact area between the conductive clip and the chip, so that the flowing conductive material (such as solder paste) cannot climb up to the top surface of the conductive clip along the rough surface of the conductive clip during reflow, thereby avoiding the phenomenon of delamination caused by solder paste climbing inside the packaging structure, thereby effectively improving the product packaging quality and process reliability; and

[0017] (2) Effectively control costs: Compared with the prior art, the chip packaging structure proposed in the present invention changes the position of the stepped structure without changing the process, so it does not lead to an increase in costs; in addition, if a stamping process is used instead of an etching process to form the stepped structure, the cost can be further reduced.

[0018] The advantages and spirit of the present invention may be further understood through the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 1 is a top view and a cross-sectional view of a chip packaging structure according to a specific embodiment of the present invention.

[0020] Figure 2 1 is a top view and a cross-sectional view of a chip packaging structure in another specific embodiment of the present invention.

[0021] Figure 3 1 is a top view and a cross-sectional view of a chip packaging structure in another specific embodiment of the present invention.

[0022] Description of main component symbols:

[0023] 1…Chip packaging structure

[0024] LF…Substrate

[0025] SD…conductive materials

[0026] DIE1…The first chip

[0027] F1…First Surface

[0028] F2…Second surface

[0029] CL1…First conductive clip

[0030] PAD…solder pad

[0031] W1…First flat area

[0032] ST1…First step structure

[0033] CA1…first contact area

[0034] N1…side

[0035] 2…Chip packaging structure

[0036] IC…Integrated Circuit

[0037] CL2…Second conductive clip

[0038] W2…Second flat area

[0039] ST2…Second step structure

[0040] CA2…Second contact area

[0041] BM…Ball metal layer

[0042] N2…side

[0043] S1…Source

[0044] S2…Source

[0045] G1…Gate

[0046] G2…Gate

[0047] D…Drain

[0048] S…Source

[0049] G…Gate

[0050] 3…Chip packaging structure

[0051] DIE2…Second chip

[0052] F3…Third surface

[0053] F4…Fourth surface DETAILED DESCRIPTION

[0054] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements / components using the same or similar reference numerals in the drawings and embodiments are intended to represent the same or similar parts.

[0055] According to a specific embodiment of the present invention, a chip packaging structure is provided, which increases the distance by setting a stepped structure around the contact area between the conductive clip and the chip without changing the process, so that the conductive material (such as solder paste) after reflow can only flow and climb to the side of the conductive clip and cannot further climb to the top surface of the conductive clip. Therefore, the delamination phenomenon caused by the solder paste climbing to the top surface of the conductive clip in the prior art can be effectively avoided, so as to achieve the specific effect of improving the product packaging quality and process reliability without increasing the cost.

[0056] Please refer to Figure 1 , Figure 1 The top view and the cross-sectional view of the chip packaging structure 1 in this embodiment are shown. It should be noted that the chip packaging structure 1 in this embodiment is a single chip packaging structure with a single conductive clip, but the present invention is not limited thereto.

[0057] like Figure 1 As shown, the chip packaging structure 1 includes a first chip DIE1, a first conductive clip CL1, a substrate LF, a pad PAD, a conductive material SD and a packaging material PM. The first chip DIE1 has a first surface F1 and a second surface F2 opposite to each other. The first conductive clip CL1 has a rough surface. The first conductive clip CL1 is electrically connected to the first surface F1 of the first chip DIE1 through the conductive material SD. The first conductive clip CL1 is also connected to the substrate LF. The substrate LF is electrically connected to the second surface F2 of the first chip DIE1 through the conductive material SD. In actual applications, the first chip DIE1 can be a power chip, the substrate LF can be a lead frame, the first conductive clip CL1 can be a copper sheet and the conductive material SD can be solder paste, but it is not limited thereto.

[0058] The first conductive clip CL1 includes a first flat area W1, a first stepped structure ST1 and a first contact area CA1. The first stepped structure ST1 is located at the junction of the first flat area W1 and the first contact area CA1 and the first stepped structure ST1 continuously surrounds the first contact area CA1 to achieve the effect of completely blocking the conductive material SD (such as solder paste) from adhering to the top surface of the first conductive clip CL1. In practical applications, the first stepped structure ST1 can be formed by a conventional etching process. In addition, if a stamping process is used instead of a conventional etching process to form the first stepped structure ST1, the cost can be further reduced.

[0059] The pad PAD is disposed on the first surface F1 of the first chip DIE1. The pad PAD is electrically connected to the first contact area CA1 of the first conductive clip CL1 through the conductive material SD. The area of ​​the first contact area CA1 is less than or equal to the area of ​​the pad PAD. The packaging material PM covers the first chip DIE1, at least part of the first conductive clip CL1 and part of the substrate LF.

[0060] When the chip packaging structure 1 is reflowed, since the first conductive clip CL1 has a rough surface, the conductive material SD located below the first stepped structure ST1 of the first conductive clip CL1 will flow outward and climb to the side surface N1 of the first stepped structure ST1 of the first conductive clip CL1 but cannot climb to the top surface of the first conductive clip CL1.

[0061] In another embodiment, please refer to Figure 2 , Figure 2 The top view and the cross-sectional view of the chip packaging structure 2 in this embodiment are shown in FIG. It should be noted that the chip packaging structure 2 in this embodiment is a single chip packaging structure with double conductive clips, but the present invention is not limited thereto.

[0062] like Figure 2 As shown, the chip packaging structure 2 includes a first chip DIE1, a first conductive clip CL1, a second conductive clip CL2, a substrate LF, an under ball metal layer BM, a pad PAD, a conductive material SD and a packaging material PM.

[0063] The first chip DIE1 has a first surface F1 and a second surface F2 opposite to each other. The first conductive clip CL1 and the second conductive clip CL2 both have rough surfaces. The first conductive clip CL1 is electrically connected to the first surface F1 of the first chip DIE1 through a conductive material SD. The second conductive clip CL2 is also electrically connected to the first surface F1 of the first chip DIE1 through a conductive material SD. The first conductive clip CL1 is also connected to a substrate LF. The second conductive clip CL2 is also connected to the substrate LF. The substrate LF is electrically connected to the second surface F2 of the first chip DIE1 through a ball metal layer BM.

[0064] The first conductive clip CL1 includes a first flat area W1, a first stepped structure ST1 and a first contact area CA1. The first stepped structure ST1 is located at the boundary between the first flat area W1 and the first contact area CA1, and the first stepped structure ST1 continuously surrounds the first contact area CA1, so as to completely block the conductive material SD (e.g., solder paste) from adhering to the top surface of the first conductive clip CL1. The second conductive clip CL2 includes a second flat area W2, a second stepped structure ST2 and a second contact area CA2. The second stepped structure ST2 is located at the boundary between the second flat area W2 and the second contact area CA2, and the second stepped structure ST2 continuously surrounds the second contact area CA2, so as to completely block the conductive material SD (e.g., solder paste) from adhering to the top surface of the second conductive clip CL2.

[0065] In practical applications, if the first stepped structure ST1 and the second stepped structure ST2 are formed by conventional etching process, the manufacturing cost will not be increased. If the stamping process is used instead of the conventional etching process to form the first stepped structure ST1 and the second stepped structure ST2, the cost can be further reduced.

[0066] The pad PAD is disposed on the first surface F1 of the first chip DIE1. The first contact area CA1 of the first conductive clip CL1 is electrically connected to the pad PAD through the conductive material SD. The area of ​​the first contact area CA1 is less than or equal to the area of ​​the pad PAD. The second contact area CA2 of the second conductive clip CL2 is electrically connected to the pad PAD through the conductive material SD. The area of ​​the second contact area CA2 is less than or equal to the area of ​​the pad PAD. The packaging material PM covers the first chip DIE1, at least a portion of the first conductive clip CL1, at least a portion of the second conductive clip CL2, and a portion of the substrate LF.

[0067] It should be noted that in this embodiment, the conductive material SD located below the first contact area CA1 and the second contact area CA2 serves as the source S1 and S2 respectively and the under ball metal layer BM serves as the drain D. The first chip DIE1 is also provided with gates G1 and G2 respectively connected to different integrated circuits IC, but not limited thereto.

[0068] When the chip packaging structure 2 is reflowed, since the first conductive clip CL1 has a rough surface, the conductive material SD (such as solder paste) located below the first stepped structure ST1 of the first conductive clip CL1 will begin to flow and climb up to the side surface N1 of the first stepped structure ST1 of the first conductive clip CL1, and will not be able to climb further to the top surface of the first conductive clip CL1.

[0069] Similarly, when the chip packaging structure 2 is reflowed, since the second conductive clip CL2 has a rough surface, the conductive material SD (such as solder paste) located below the second stepped structure ST2 of the second conductive clip CL2 will begin to flow and climb to the side surface N2 of the second stepped structure ST2 of the second conductive clip CL2, and will not be able to further climb to the top surface of the second conductive clip CL2.

[0070] In another embodiment, please refer to Figure 3 , Figure 3 The top view and the cross-sectional view of the chip packaging structure 3 in this embodiment are shown. It should be noted that the chip packaging structure 3 in this embodiment is a dual-chip packaging structure with a single conductive clip.

[0071] like Figure 3 As shown, the chip packaging structure 3 includes a first chip DIE1, a second chip DIE2, a first conductive clip CL1, a substrate LF, a pad PAD, a conductive material SD and a packaging material PM. In practical applications, the first chip DIE1 and the second chip DIE2 can be power chips, the substrate LF can be a lead frame, the first conductive clip CL1 can be a copper sheet and the conductive material SD can be solder paste, but it is not limited thereto.

[0072] The first chip DIE1 has a first surface F1 and a second surface F2 opposite to each other. The second chip DIE2 has a third surface F3 and a fourth surface F4 opposite to each other. The first conductive clip CL1 has a rough surface. The first conductive clip CL1 is electrically connected to the first surface F1 of the first chip DIE1 and the third surface F3 of the second chip DIE2 through a conductive material SD. The first conductive clip CL1 is also connected to a substrate LF. The substrate LF is electrically connected to the second surface F2 of the first chip DIE1 and the fourth surface F4 of the second chip DIE2 through a conductive material SD. In practical applications, the substrate LF may be a lead frame, the first conductive clip CL1 may be a copper sheet, and the conductive material SD may be solder paste, but is not limited thereto.

[0073] The first conductive clip CL1 includes a first flat region W1, a first stepped structure ST1, a first contact region CA1, a second flat region W2, a second stepped structure ST2, and a second contact region CA2. The first stepped structure ST1 is located at the boundary between the first flat region W1 and the first contact region CA1, and the first stepped structure ST1 continuously surrounds the first contact region CA1. The second stepped structure ST2 is located at the boundary between the second flat region W2 and the second contact region CA2, and the second stepped structure ST2 continuously surrounds the second contact region CA2.

[0074] In practical applications, if the first stepped structure ST1 and the second stepped structure ST2 are formed by conventional etching process, the manufacturing cost will not be increased. If the stamping process is used instead of the conventional etching process to form the first stepped structure ST1 and the second stepped structure ST2, the cost can be further reduced.

[0075] The pad PAD is disposed on the first surface F1 of the first chip DIE1. The pad PAD located above the first chip DIE1 is electrically connected to the first contact area CA1 of the first conductive clip CL1 through the conductive material SD. The pad PAD located above the second chip DIE2 is electrically connected to the second contact area CA2 of the first conductive clip CL1 through the conductive material SD. The areas of the first contact area CA1 and the second contact area CA2 are both less than or equal to the area of ​​the pad PAD. The packaging material PM covers the first chip DIE1, the second chip DIE2, at least part of the first conductive clip CL1 and part of the substrate LF.

[0076] It should be noted that in this embodiment, the conductive material SD located above and below the first chip DIE1 serves as the source S and the drain D respectively, and the conductive material SD located above and below the second chip DIE2 serves as the drain D and the source S respectively. The first chip DIE1 and the second chip DIE2 are also provided with gates G, which are respectively connected to the integrated circuit IC, but this is not limited to this.

[0077] When the chip packaging structure 3 is reflowed, since the first conductive clip CL1 has a rough surface, the conductive material SD (such as solder paste) located below the first stepped structure ST1 of the first conductive clip CL1 will begin to flow and climb up to the side surface N1 of the first stepped structure ST1 of the first conductive clip CL1, and will not be able to climb further to the top surface of the first conductive clip CL1.

[0078] Therefore, without changing the process, the chip packaging structure 1-3 sets a first stepped structure ST1 around the first contact area CA1 connecting the conductive clips CL1, CL2 and the chips DIE1, DIE2 to increase the distance, so that the conductive material SD (such as solder paste) after reflow can only climb to the side surface N1 of the first conductive clip CL1, and cannot further climb to the top surface of the first conductive clip CL1, so as to effectively avoid the delamination phenomenon caused by the solder paste climbing to the top surface of the conductive clip in the prior art, so the packaging quality and process reliability of the chip packaging structure 2 can be significantly improved.

[0079] Compared with the prior art, the chip packaging structure proposed by the present invention has the following advantages and effects:

[0080] (1) Effectively improve reliability: The chip packaging structure proposed by the present invention has a stepped structure around the contact area between the conductive clip and the chip, so that the conductive material (such as solder paste) flowing during reflow cannot climb up along the rough surface of the conductive clip to the top surface of the conductive clip, thereby avoiding the delamination phenomenon caused by the adhesion of solder paste inside the packaging structure, thereby effectively improving the product packaging quality and process reliability; and

[0081] (2) Effectively control costs: Compared with the prior art, the chip packaging structure proposed in the present invention changes the position of the stepped structure without changing the process, so it does not lead to an increase in costs; in addition, if a stamping process is used instead of an etching process to form the stepped structure, the cost can be further reduced.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: A first chip having a first surface and a second surface opposite to each other; and A first conductive clip is connected to the first surface of the first chip through a conductive material, wherein the first conductive clip includes a first flat area, a first stepped structure and a first contact area, the first stepped structure is located at the junction of the first flat area and the first contact area, and the first stepped structure continuously surrounds the first contact area.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a substrate electrically connected to the second surface of the first chip.

3. The chip packaging structure according to claim 2, characterized in that: The chip packaging structure further includes a packaging material covering the first chip, at least a portion of the first conductive clip and a portion of the substrate.

4. The chip packaging structure according to claim 1, characterized in that: The first conductive clip has a rough surface.

5. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes: A solder pad is disposed on the first surface of the first chip, the solder pad is electrically connected to the first contact region of the first conductive clip through the conductive material, and the area of ​​the first contact region is less than or equal to the area of ​​the solder pad.

6. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure also includes a second chip, which is horizontally separated from the first chip.

7. The chip packaging structure according to claim 6, characterized in that: The first conductive clip further comprises: A second contact region, disposed separately from the first contact region and electrically connected to the second chip; and The second stepped structure is located at the boundary between the first flat area and the second contact area, and the second stepped structure continuously surrounds the second contact area.

8. The chip packaging structure according to claim 6, characterized in that: The chip packaging structure further includes a second conductive clip, which is configured separately from the first conductive clip and is electrically connected to the second chip.

9. The chip packaging structure according to claim 7, characterized in that: The second conductive clip comprises: The second flat area; A second contact region electrically connected to the second chip; and The second stepped structure is located at the junction of the second flat area and the second contact area, and the second stepped structure continuously surrounds the second contact area.

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