Power module packaging structure and power transistor

Abstract

The invention provides a power module packaging structure and a power transistor. The power module packaging structure comprises a conductive support, a first pin, a second pin, a third pin, a plurality of metal oxide semiconductor transistors and depletion type III-V transistors. The first pin is electrically connected with the conductive support and is an extension part of the conductive support. The second and third pins are separated from the conductive bracket. The metal oxide semiconductor transistor and the depletion mode III-V group transistor are arranged on the conductive support side by side and are separated from each other. A first grid electrode, a first source electrode and a first drain electrode of the metal oxide semiconductor transistor are electrically connected to the second pin, the first pin and a second source electrode of the depletion type III-V transistor through a plurality of first bonding wires respectively. A second gate and a second drain of the depletion mode III-V transistor are electrically connected to the first pin and the third pin through a plurality of second bonding wires, respectively.

Description

Technical Field

[0001] The present invention relates to a power module packaging structure and a power transistor, and more particularly to a power module packaging structure and a power transistor having a cascade structure of a metal oxide semiconductor transistor and a depletion type III-V transistor. Background Art

[0002] III-V transistors, such as gallium nitride field effect transistors (GaN FETs), are often used in high-power and high-performance circuit applications due to their high efficiency and suitability for high-voltage operation. In addition, III-V transistors are often combined with other low-voltage operating transistors (such as silicon field effect transistors) to form power transistors with a cascade structure.

[0003] However, existing power transistors often bring about many unexpected non-ideal effects, and therefore it is necessary to avoid the unexpected non-ideal effects to improve the performance of the power transistors. Summary of the invention

[0004] An embodiment of the present invention provides a power module packaging structure. The power module packaging structure includes a conductive support, a first pin, a second pin, a third pin, a plurality of metal oxide semiconductor transistors and a depletion type III-V transistor. The first pin is electrically connected to the conductive support. The first pin is an extension of the conductive support. The second pin and the third pin are adjacent to the first pin and separated from the conductive support. The metal oxide semiconductor transistors are arranged side by side on the conductive support. The metal oxide semiconductor transistors respectively include a first gate, a first source and a first drain. The depletion type III-V transistor is arranged on the conductive support and separated from the metal oxide semiconductor transistor, and the depletion type III-V transistor includes a second gate, a second source and a second drain. The first gate, the first source and the first drain of the metal oxide semiconductor transistor are electrically connected to the second pin, the first pin and the second source respectively through a plurality of first bonding wires. The second gate and the second drain of the depletion type III-V transistor are electrically connected to the first pin and the third pin respectively through a plurality of second bonding wires.

[0005] Furthermore, an embodiment of the present invention provides a power transistor. The power transistor includes a plurality of metal oxide semiconductor transistors and a depletion type III-V transistor. The metal oxide semiconductor transistors each include a first gate, a first source and a first drain. The depletion type III-V transistor includes a second gate, a second source and a second drain. The metal oxide semiconductor transistor is connected in parallel between the second gate and the second source of the depletion type III-V transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1FIG. 4 is a perspective view of a power module packaging structure according to some embodiments of the present invention.

[0007] Figure 2A According to some embodiments of the present invention Figure 1 Circuit diagram of the mid-power module package structure.

[0008] Figure 2B According to some embodiments of the present invention Figure 1 Equivalent circuit diagram of a metal oxide semiconductor transistor in a medium power module package structure when in the on state.

[0009] Reference numerals:

[0010] 200: Conductive bracket

[0011] 200T,250T,302-1T,302-2T,302-3T,402T: Top

[0012] 202,204,206: Pins

[0013] 210-1,210-2,210-3,212-1,212-2,212-3,214-1,214-2,214-3,222,224: Bonding wire

[0014] 250: Insulated metal substrate

[0015] 252: Insulation layer

[0016] 254:Metal layer

[0017] 260:Drive

[0018] 300,300-1,300-2,300-3,300-n:Metal Oxide Semiconductor Transistor

[0019] 302-1,302-2,302-3,402:Semiconductor substrate

[0020] 302-1B,302-2B,302-3B,402B: Bottom

[0021] 400: Depletion-mode III-V transistor

[0022] 500: Power module packaging structure

[0023] B2: Matrix

[0024] D: Drain terminal

[0025] D1-1, D1-2, D1-3, D1-n, D2: drain

[0026] G: Gate terminal

[0027] G1-1, G1-2, G1-3, G1-n, G2: Gate

[0028] S: Source terminal

[0029] S1-1, S1-2, S1-3, S1-n, S2: Source

[0030] R1, R2, Rn: resistors DETAILED DESCRIPTION

[0031] In order to make the above and other purposes, features, and advantages of the present invention more clearly understood, preferred embodiments are given below and described in detail with reference to the accompanying drawings.

[0032] It is understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or parts. Therefore, a first element, component, region, layer, and / or part discussed below may be referred to as a second element, component, region, layer, and / or part without departing from the teachings of some embodiments of the present invention.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art to which this disclosure belongs. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0034] Some embodiments of the present invention may be understood in conjunction with the drawings, and the drawings of the embodiments of the present invention are also considered as part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn in proportion to the actual devices and components. The shapes and thicknesses of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. In addition, the structures and devices in the drawings are drawn in a schematic manner to clearly show the features of the embodiments of the present invention.

[0035] In some embodiments of the present invention, relative terms such as "lower", "upper", "horizontal", "vertical", "below", "above", "top", "bottom", etc. should be understood as the orientations shown in the paragraph and related drawings. Such relative terms are only for the convenience of description and do not mean that the device described therein needs to be manufactured or operated in a specific orientation. Terms related to bonding and connection, such as "connection" and "interconnection", etc., unless otherwise defined, may refer to two structures being in direct contact, or may also refer to two structures not being in direct contact, wherein there is another structure disposed between the two structures. Furthermore, such terms related to bonding and connection may also include situations where both structures are movable, or both structures are fixed.

[0036] Figure 1 1 is a perspective view of a power module package structure 500 according to some embodiments of the present invention. The power module package structure 500 includes a conductive support (lead frame) 200, leads (leads) 202, 204, 206, a plurality of metal oxide semiconductor transistors 300 and a depletion mode (depletion mode or D-mode) III-V transistor 400. In some embodiments, the power module package structure 500 includes a power transistor package structure. For example, the power transistor may be a cascade power amplifier, which may be formed by an enhanced mode (enhanced mode or E-mode) metal oxide semiconductor transistor 300 connected in series with a depletion mode III-V transistor 400. In some embodiments, the conductive support 200 may be formed by a conductive sheet including a pure metal, an alloy and a metal composite layer, wherein the conductive sheet of the metal composite layer includes a metal plate covered with a conductive layer with high oxidation resistance or high solder bonding strength, such as a silver-plated copper sheet. Therefore, the top surface 200T of the conductive support 200 is a conductive surface. In some embodiments, the conductive support 200 may be formed by stamping, cutting, or die-casting a conductive sheet.

[0037] like Figure 1 As shown, the pin 202 is an extension of the conductive support 200. In other words, the pin 202 is electrically connected to the conductive support 200 and there is no interface between the pin 202 and the conductive support 200. In addition, the pins 204 and 206 separated from each other are adjacent to the side of the conductive support 200 close to the first pin 202, and are respectively adjacent to the opposite sides of the first pin 202. Moreover, the pins 204 and 206 are separated from the conductive support 200 and the first pin 202. In addition, the pins 202, 204, and 206 can couple the source terminal (S), the gate terminal (G), and the drain terminal (D) of the power transistor disposed on the conductive support 200 to the external circuit of the power module packaging structure 500. In some embodiments, the conductive support 200 and the pins 204 and 206 may include the same or similar materials and formation methods.

[0038] The power module package structure 500 includes a plurality of metal oxide semiconductor transistors 300 (including metal oxide semiconductor transistors 300-1, 300-2, and 300-3 having the same electrical properties and structures) arranged side by side on the conductive support 200. In some embodiments, the number (n) of the metal oxide semiconductor transistors 300 is greater than or equal to two (n≧2). For example, the power module package structure 500 may include two, three, four, five, six or more metal oxide semiconductor transistors 300. Figure 1 In the illustrated embodiment, the power module package structure 500 includes three metal oxide semiconductor transistors 300 - 1 , 300 - 2 , and 300 - 3 , but the invention is not limited thereto.

[0039] like Figure 1 As shown, the metal oxide semiconductor transistors 300-1, 300-2, 300-3 respectively include semiconductor substrates 302-1, 302-2, 302-3, gates G1-1, G1-2, G1-3, sources S1-1, S1-2, S1-3, and drains D1-1, D1-2, D1-3. In some embodiments, the metal oxide semiconductor transistors 300-1, 300-2, 300-3 are enhanced mode Si MOSFETs or E-mode Si MOSFETs, which are used as switch elements for controlling the depletion mode III-V transistor 400. In some embodiments, the metal oxide semiconductor transistors 300-1, 300-2, 300-3 are vertical metal oxide semiconductor transistors. The gates G1-1, G1-2, G1-3 and the sources S1-1, S1-2, S1-3 of the MOS transistors 300-1, 300-2, 300-3 are disposed close to the top surfaces 302-1T, 302-2T, 302-3T of the semiconductor substrates 302-1, 302-2, 302-3. The drains D1-1, D1-2, D1-3 of the MOS transistors 300-1, 300-2, 300-3 are disposed close to the bottom surfaces 302-1B, 302-2B, 302-3B of the semiconductor substrates 302-1, 302-2, 302-3. In some embodiments, the MOS transistors 300-1, 300-2, 300-3 may be MOS transistor chips, and the gates G1-1, G1-2, G1-3 and the sources S1-1, S1-2, S1-3 may be pads electrically connected to the gates and sources of the MOS transistors.

[0040] In some embodiments, the power module package structure 500 further includes an insulating metal substrate 250 disposed between the conductive support 200 and the metal oxide semiconductor transistors 300-1, 300-2, 300-3, so that the metal oxide semiconductor transistors 300-1, 300-2, 300-3 are disposed side by side thereon. In some embodiments, the insulating metal substrate 250 may include an insulating layer 252 and a metal layer 254 disposed on the insulating layer 252. The metal layer 254 completely covers the surface of the insulating layer 252 away from the conductive support 200. In some embodiments, the drains D1-1, D1-2, D1-3 of the metal oxide semiconductor transistors 300-1, 300-2, 300-3, such as vertical metal oxide semiconductor transistors, contact the top surface of the metal layer 254 (i.e., the top surface 250T of the insulating metal substrate 250). In addition, the metal layer 254 is separated from the conductive support 200 by the insulating layer 252. Therefore, the drains D1-1, D1-2, and D1-3 of the metal oxide semiconductor transistors 300-1, 300-2, and 300-3 are electrically connected to each other through the metal layer 254, and separated from the conductive support 200 by the insulating layer 252. In some embodiments, the insulating layer 252 includes aluminum oxide ceramic or aluminum nitride ceramic, and the metal layer 254 includes copper. In some embodiments, the insulating metal substrate 250 includes a direct bonding copper (DBC) substrate.

[0041] In the power module package structure 500, the depletion type III-V transistor 400 is disposed on the conductive support 200. The depletion type III-V transistor 400 is disposed side by side with the metal oxide semiconductor transistors 300-1, 300-2, and 300-3, and is separated from the metal oxide semiconductor transistors 300-1, 300-2, and 300-3. In some embodiments, the depletion type III-V transistor 400 can be a depletion type III-V transistor chip. Figure 1As shown, the depletion-type III-V transistor 400 includes a semiconductor substrate 402, a gate G2, a source S2, and a drain D2, wherein the semiconductor substrate 402 is regarded as the bulk of the semiconductor substrate 402. In some embodiments, the gate G2, the source S2, and the drain D2 of the depletion-type III-V transistor 400 are disposed on a top surface 402T of the semiconductor substrate 402, and a bottom surface 402B of the semiconductor substrate (bulk) 402 contacts the conductive support 200 (electrically connected to the pin 202). In some embodiments, the depletion-type III-V transistor 400 may be a depletion-type III-V transistor wafer, and the gate G2, the source S2, and the drain D2 may be pads electrically connected to the gate, source, and drain of the depletion-type III-V transistor. In some embodiments, the depletion-mode III-V transistor 400 includes a depletion-mode GaN FET, such as a depletion-mode GaN high electron mobility transistor (HEMT), which has high voltage operation, low parasitic capacitance, low on-resistance (Rdson), and a reverse recovery current approaching zero, and is therefore suitable for operation at high frequency and high power density. In some embodiments, the breakdown voltage of the metal oxide semiconductor transistors 300-1, 300-2, and 300-3 is much lower than the breakdown voltage of the depletion-mode III-V transistor 400.

[0042] The power module package structure 500 uses bonding wires as electrical connections between the MOS transistors 300-1, 300-2, 300-3, the depletion-mode III-V transistor 400, the conductive support 200 (pin 202), and the pins 204 and 206. In some embodiments, the gates G1-1, G1-2, G1-3 of the MOS transistors 300-1, 300-2, 300-3 are electrically connected to the pins 204 through corresponding bonding wires 210-1, 210-2, 210-3, respectively. In detail, the bonding wires 210-1, 210-2, 210-3 corresponding to the gates G1-1, G1-2, G1-3 of the MOS transistors 300-1, 300-2, 300-3 are directly connected to the pins 204. The sources S1-1, S1-2, S1-3 of the MOS transistors 300-1, 300-2, 300-3 are electrically connected to the conductive support 200 (i.e., electrically connected to the pin 202) through the corresponding bonding wires 212-1, 212-2, 212-3, respectively. In detail, the bonding wires 212-1, 212-2, 212-3 corresponding to the sources S1-1, S1-2, S1-3 of the MOS transistors 300-1, 300-2, 300-3 are directly connected to the conductive support 200 (pin 202). The drains D1-1, D1-2, D1-3 of the MOS transistors 300-1, 300-2, 300-3 are electrically connected to the source S2 of the depletion-type III-V transistor 400 through the corresponding bonding wires 214-1, 214-2, 214-3. Specifically, the bonding wires 214 - 1 , 214 - 2 , 214 - 3 corresponding to the drains D1 - 1 , D1 - 2 , D1 - 3 of the MOS transistors 300 - 1 , 300 - 2 , 300 - 3 are directly connected to the metal layer 254 of the insulated metal substrate 250 and the source S2 of the depletion mode III-V transistor 400 .

[0043] In some embodiments, the gate G2 and the drain D2 of the depletion-mode III-V transistor 400 are electrically connected to the conductive support 200 (pin 202) and the pin 206 respectively through a plurality of bonding wires 222 and 224. In addition, the bulk of the depletion-mode III-V transistor 400 is electrically connected to the conductive support 200 (pin 202).

[0044] Figure 2A According to some embodiments of the present invention Figure 1The power module package structure 500 is a circuit diagram of the power module package structure 500. The power transistor in the power module package structure 500 includes a gate terminal G, a source terminal S, and a drain terminal D. The metal oxide semiconductor transistor 300 (including n (n≧2) metal oxide semiconductor transistors 300-1, 300-2...300-n, (in Figure 1 In the embodiment shown, the number of the metal oxide semiconductor transistors is equal to three (n=3, but the present invention is not limited thereto), each including a gate G1-1, G1-2 ... G1-n, a source S1-1, S1-2 ... S1-n, and a drain D1-1, D1-2 ... D1-n. In addition, the depletion type III-V transistor 400 has a drain D2, a gate G2, a source S2, and a bulk B2. In addition, the parasitic diodes formed by the PN junctions between the corresponding sources S1-1, S1-2 ... S1-n and the drains D1-1, D1-2 ... D1-n of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n are marked with diode circuit symbols.

[0045] like Figure 2A As shown, the drain D2 of the depletion-type III-V transistor 400 is coupled to the drain terminal D. In addition, the gates G1-1, G1-2, ... G1-n of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n are coupled to each other and to the gate terminal G. The sources S1-1, S1-2, ... S1-n of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n, the gate G2 of the depletion-type III-V transistor 400, and the bulk B2 are coupled to the source terminal S. The drains D1-1, D1-2, ... D1-n of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n are coupled to the source S2 of the depletion-type III-V transistor 400. In other words, the MOS transistors 300 - 1 , 300 - 2 . . . 300 - n are connected in parallel between the gate G2 and the source S2 of the depletion-type III-V transistor.

[0046] In some embodiments, the gate terminal G of the power module package structure 500 can be coupled to an external driver 260. The driver 260 provides a driving signal (not shown) to the gates G1-1, G1-2, ... G1-n of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n according to an input control signal (not shown) to control whether the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n are turned on, so as to further control whether the depletion type III-V transistor 400 connected in series with the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n is turned on.

[0047] like Figure 1 , Figure 2A As shown, the sources S1-1, S1-2...S1-n (e.g., sources S1-1, S1-2, S1-3) of the metal oxide semiconductor transistors 300-1, 300-2...300-n (e.g., metal oxide semiconductor transistors 300-1, 300-2, 300-3), the gate G2 and the bulk of the depletion type III-V transistor 400 are all electrically connected to the pin 202 (the source terminal (S) of the power transistor) through the conductive bracket 200. Therefore, the sources S1-1, S1-2...S1-n (e.g., sources S1-1, S1-2, S1-3) of the metal oxide semiconductor transistors 300-1, 300-2...300-n (e.g., sources S1-1, S1-2, S1-3) and the gate G2 and bulk of the depletion type III-V transistor 400 can be commonly grounded through the conductive support 200.

[0048] like Figure 1 , Figure 2A As shown, since the sources S1-1, S1-2 ... S1-n (e.g., sources S1-1, S1-2, S1-3) of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n (e.g., metal oxide semiconductor transistors 300-1, 300-2, 300-3) are all electrically connected to the pin 202 (the source terminal (S) of the power transistor), the drains D1-1, D1-2 ... D1-n (e.g., drains D1-1, D1-2, D1-3) of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n (e.g., metal oxide semiconductor transistors 300-1, 300-2, 300-3) are all electrically connected to the source S2 of the depletion-type III-V transistor 400. Therefore, the metal oxide semiconductor transistors 300-1, 300-2, ... 300-n (e.g., metal oxide semiconductor transistors 300-1, 300-2, 300-3) are connected in parallel to each other and are connected in series with the depletion type III-V transistor 400 to form a power transistor. In addition, the gate terminal (G) of the power transistor is coupled to the pin 204, the source terminal (S) of the power transistor is coupled to the conductive support 200 (pin 202), and the drain terminal (D) of the power transistor is coupled to the pin 206.

[0049] In some embodiments, when the metal oxide semiconductor transistors 300-1, 300-2...300-n (metal oxide semiconductor transistors 300-1, 300-2, 300-3) of the power module packaging structure 500 have slight variations in electrical parameters (such as breakdown voltage (Vbd), on-resistance, etc.) due to the process, the setting of the insulating metal substrate 250 can make the current flow evenly to each of the parallel metal oxide semiconductor transistors 300-1, 300-2...300-n (such as metal oxide semiconductor transistors 300-1, 300-2, 300-3) so that the enhancement mode metal oxide semiconductor transistor structure of the power transistor maintains the breakdown voltage and low on-resistance.

[0050] Figure 2B According to some embodiments of the present invention Figure 1 An equivalent circuit diagram of the metal oxide semiconductor transistor 300 of the medium power module package structure 500 in an on-state.

[0051] like Figure 2B As shown, when Figure 2A The metal oxide semiconductor transistors 300-1, 300-2 ... 300-n shown in the ON-state can be regarded as resistors R1, R2 ... Rn. In some embodiments, the resistors R1, R2 ... Rn have the same resistance value R, which is equivalent to the respective on-resistance values ​​(Rdson) of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n. When the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n are in the ON-state, the parallel on-resistance value of the metal oxide semiconductor transistors 300-1, 300-2 ... 300-n can be regarded as the parallel resistance value of the resistors R1, R2 ... Rn, which is one-nth of the respective resistance values ​​of the resistors R1, R2 ... Rn, that is, R / n. In a power transistor with a cascode structure, a plurality of parallel-connected MOS transistors 300-1, 300-2, ... 300-n may be used to replace a single existing MOS transistor as an enhancement mode MOS transistor structure of the power transistor, which can reduce the on-resistance while maintaining the breakdown voltage.

[0052] The existing power module packaging structure uses a single enhancement metal oxide semiconductor transistor in series with a depletion type III-V transistor to form a power transistor. The power transistor needs to have a low on-resistance to operate in a high frequency environment. In addition, since the gate of the depletion type III-V transistor and the source of the enhancement type metal oxide semiconductor transistor share a common ground, the drain of the enhancement type metal oxide semiconductor transistor as a switching element needs to be able to withstand a larger voltage to turn off the depletion type III-V transistor. Therefore, the voltage withstand characteristics (breakdown voltage) of a single enhancement type metal oxide semiconductor transistor become more important. However, increasing the breakdown voltage of the enhancement type metal oxide semiconductor transistor will increase the total on-resistance of the power transistor, which will affect the speed at which the power module packaging structure needs to operate in a high frequency environment.

[0053] The embodiment of the present invention provides a power module packaging structure and a power transistor. The power module packaging structure uses a plurality of parallel enhanced metal oxide semiconductor transistors (metal oxide semiconductor transistors 300) to replace the existing single enhanced metal oxide semiconductor transistor, so as to be connected in series with a depletion type III-V transistor (depletion type III-V transistor 400) as a power transistor. In some embodiments, an enhanced metal oxide semiconductor transistor having the same electrical properties (such as breakdown voltage (Vbd), on-resistance, etc.) is connected in parallel between the gate (gate G2) and the source (source S2) of the depletion type III-V transistor. The gate terminal (gate terminal G) of the power transistor is coupled to the plurality of gates (gate G1-1, G1-2...G1-n) of the enhanced metal oxide semiconductor transistor, and the source terminal (source terminal S) of the power transistor is coupled to the plurality of sources (source S1-1, S1-2...S1-n) of the enhanced metal oxide semiconductor transistor, the gate (gate G2) of the depletion type III-V transistor, and the base (base B2) of the depletion type III-V transistor. Furthermore, the drain terminal (drain terminal D) of the power transistor is coupled to the drain terminal (drain D2) of the depletion type III-V transistor. Compared with the existing power module packaging structure, the power module packaging structure of the embodiment of the present invention can reduce the on-resistance while maintaining the same breakdown voltage.

[0054] In some embodiments, the parallel-connected enhancement-mode metal oxide semiconductor transistors are disposed on a conductive support through an insulating metal substrate (insulating metal substrate 250, such as a copper-clad ceramic substrate (DBC)) to be separated from the depletion-mode III-V transistors, and the drains (drains D1-1, D1-2, ..., D1-n) of the enhancement-mode metal oxide semiconductor transistors are in contact with the metal layer of the insulating metal substrate, and then connected to the sources (source S2) of the depletion-mode III-V transistors through bonding wires. The provision of the insulating metal substrate can make the parallel-connected enhancement-mode metal oxide semiconductor transistors have uniform electrical performance, so that current can flow evenly through each of the parallel-connected enhancement-mode metal oxide semiconductor transistors, thereby preventing the enhancement-mode metal oxide semiconductor transistors with poor electrical properties due to process variations from being subjected to large currents during operation and causing burnout.

[0055] Although the present invention has been described above with reference to the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the attached claims.

Claims

1. A power module packaging structure, characterized in that: include: a conductive support; A first pin electrically connected to the conductive support, wherein the first pin is an extension of the conductive support; A second pin and a third pin, adjacent to the first pin and separated from the conductive bracket; A plurality of metal oxide semiconductor transistors are arranged side by side on the conductive support, and each of the metal oxide semiconductor transistors includes a first gate, a first source and a first drain; as well as a depletion type III-V transistor, disposed on the conductive support and separated from the metal oxide semiconductor transistor, the depletion type III-V transistor comprising a second gate, a second source and a second drain, wherein the first gate, the first source and the first drain of each of the metal oxide semiconductor transistors are electrically connected to the second lead, the first lead and the second source through a plurality of first bonding wires, respectively; and The second gate and the second drain of the depletion-type III-V transistor are electrically connected to the first pin and the third pin respectively through a plurality of second bonding wires.

2. The power module packaging structure according to claim 1, characterized in that: Also includes: An insulating metal substrate is disposed between the conductive support and the metal oxide semiconductor transistor, and the insulating metal substrate comprises: an insulating layer; and a metal layer disposed on the insulating layer, The first drain of each metal oxide semiconductor transistor contacts the metal layer, and the metal layer is separated from the conductive support by the insulating layer.

3. The power module packaging structure according to claim 2, characterized in that: The first bonding wire corresponding to the first drain of the metal oxide semiconductor transistor is directly connected to the metal layer and the second source.

4. The power module packaging structure according to claim 1, characterized in that: The first bonding wire corresponding to the first gate of each metal oxide semiconductor transistor is directly connected to the second pin.

5. The power module packaging structure according to claim 1, characterized in that: Each of the metal oxide semiconductor transistors is a vertical metal oxide semiconductor transistor, and the vertical metal oxide semiconductor transistor further includes a first semiconductor substrate, wherein the first gate and the first source of each of the metal oxide semiconductor transistors are arranged on a top surface of the first semiconductor substrate, and wherein the first drain of each of the metal oxide semiconductor transistors is arranged on a bottom surface of the first semiconductor substrate.

6. The power module packaging structure according to claim 1, characterized in that: The depletion-type III-V transistor further comprises a second semiconductor substrate, wherein the second gate, the second source and the second drain of the depletion-type III-V transistor are arranged on a top surface of the second semiconductor substrate, wherein a bottom surface of the second semiconductor substrate contacts the conductive support.

7. The power module packaging structure according to claim 5, characterized in that: The first source of each metal oxide semiconductor transistor, the second gate and the second base of the depletion type III-V group transistor are grounded via the conductive support.

8. The power module packaging structure according to claim 1, characterized in that: The metal oxide semiconductor transistors are connected in parallel with each other and are connected in series with the depletion type III-V transistor to form a power transistor.

9. The power module packaging structure according to claim 8, characterized in that: The power transistor includes a gate terminal, a source terminal and a drain terminal, wherein the gate terminal is coupled to the second pin, the drain terminal is coupled to the third pin and the source terminal is coupled to the conductive bracket.

10. The power module packaging structure according to claim 1, characterized in that: Each of the metal oxide semiconductor transistors is an enhancement mode silicon-based metal oxide semiconductor field effect transistor.

11. The power module packaging structure according to claim 1, characterized in that: The depletion mode III-V transistor is a gallium nitride field effect transistor.

12. A power transistor, characterized in that: include: A plurality of metal oxide semiconductor transistors, each of which comprises a first gate, a first source and a first drain; as well as a depletion-type III-V transistor comprising a second gate, a second source and a second drain, The metal oxide semiconductor transistor is connected in parallel between the second gate and the second source of the depletion type III-V group transistor.

13. The power transistor according to claim 12, characterized in that The first gates of the metal oxide semiconductor transistors are coupled to each other.

14. The power transistor according to claim 12, characterized in that The first drain of the metal oxide semiconductor transistor is coupled to the second source of the depletion mode III-V transistor.

15. The power transistor according to claim 12, characterized in that The power transistor includes a gate terminal, a source terminal and a drain terminal, wherein the gate terminal is coupled to the first gate of the metal oxide semiconductor transistor, the source terminal is coupled to the first source of the metal oxide semiconductor transistor, the second gate of the depletion type III-V transistor and a body of the depletion type III-V transistor, and the drain terminal is coupled to the second drain of the depletion type III-V transistor.

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