A new type of anti-backflow current circuit

Abstract

The present invention discloses a novel anti-backflow current circuit, which relates to the field of circuit technology, including a first circuit and a second circuit. The first circuit is composed of three logic gate circuits, transistors MP1, MP2, MP3, MP4, MN1, MN2 and MN3. When the circuit is in a power-off mode, the transistors MP1 and MN1 can be turned off in time. The second circuit is used to make the substrate potential VSUB of the transistor MP1 always select the highest potential in the power supply voltage VCC and the output terminal VOUT, thereby forming a good anti-backflow mechanism. The present invention can completely avoid the output to VCC or the appearance of a diode path to the ground when the circuit is powered off, and truly achieve zero current when the output is powered off, and by isolating the substrate potential of the output PMOS driver tube, it is allowed to always select the highest potential, reducing the generation of current spikes inside the circuit, and the anti-backflow current circuit will always be in an enabled off state due to its analog circuit and its special MOS diode inversion structure, and will not generate additional path consumption power consumption.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a novel backflow current prevention circuit. Background Art

[0002] When the chip is connected to the bus or transmits signals between two subsystems, the chip may lose power, while the power-on signal of the bus or other subsystems keeps its connection at a high level. If the chip is not equipped with an anti-backflow circuit, the high level at its port connection will pass through the inside of the chip, causing chip leakage current or even damage to the chip itself, and will also affect the transmission and communication between systems. Therefore, it is necessary to set up an anti-backflow current circuit. In the process of setting up the anti-backflow current circuit, the voltage change of some nodes inside the circuit is from 0 to gradually increase or even exceed the power supply voltage, which will cause a current spike inside the circuit when it is first started, resulting in increased power consumption and severe damage to the chip.

[0003] Therefore, a new type of anti-backflow current circuit is urgently needed to solve the above problems. Summary of the invention

[0004] In order to solve the above-mentioned deficiencies in the prior art, the present invention provides a novel backflow current prevention circuit, the circuit comprising a first circuit and a second circuit;

[0005] The first circuit comprises:

[0006] The first logic gate circuit is configured as follows: a first input terminal is connected to the data terminal Data, a second input terminal is connected to the driving terminal EN, and an output terminal is respectively connected to the source of the transistor MN2 and the drain of the transistor MP4. When at least one of the data terminal Data and the driving terminal EN is at a low level, the first logic gate circuit outputs a high level.

[0007] The second logic gate circuit is configured as follows: an input end is connected to the driving end EN, an output end is connected to the third logic gate circuit, and the second logic gate outputs a level opposite to the potential of the driving end EN;

[0008] The third logic gate circuit is configured as follows: a first input terminal is connected to the data terminal Data, a second input terminal is connected to the output terminal of the second logic gate circuit, and an output terminal is connected to the gate of the transistor MN1; when at least one of the data terminal Data and the output terminal of the second logic gate circuit is at a high level, the third logic gate circuit outputs a low level;

[0009] The gate of the transistor MN2 is connected to the voltage source VCC, the drain of the transistor MN2 and the source of the transistor MP4 are both connected to the gate of the transistor MP1, the source of the transistor MP1 is connected to the voltage source VCC, the drain of the transistor MP2 is connected to the gate of the transistor MP1, the source of the transistor MP2 is connected to the drain of the transistor MP3 and then connected to the output terminal VOUT, the gate of the transistor MP2 and the gate of the transistor MP3 are both connected to the voltage source VCC, the gate of the transistor MP4 and the source of the transistor MP3 are both connected to the drain of the transistor MN3, the gate of the transistor MN3 is connected to the driving terminal EN, the drain of the transistor MP1 is connected to the drain of the transistor MN1 and then connected to the output terminal VOUT, and the source of the transistor MN1 and the source of the transistor MN3 are both grounded;

[0010] The second circuit comprises:

[0011] It is used to be connected to the output terminal VOUT, and to make the substrate potential VSUB of the transistor MP1 always select the highest potential between the voltage source VCC and the output terminal VOUT.

[0012] The present invention is achieved through the following technical solutions:

[0013] When the circuit is working normally, the driving terminal EN will be set to a high level, and the circuit will enter the normal data transmission mode. When the data terminal Data potential is high, the output terminal VOUT potential is low. When the data terminal Data potential is low, the output terminal VOUT potential is high.

[0014] When the circuit enters the power-down mode, the power supply voltage VCC is 0V, the potential of the driving terminal EN will be set to a low level, and the circuit enters the power-down mode state. If the input port of the external subsystem maintains a high-level input at this time, the output terminal VOUT is at a high level. At this time, since the potential of the driving terminal EN is at a low level, the output of the first logic gate circuit is at a high level. At this time, VCC is 0V, the transistor MN2 is turned off, and the transistors MP2 and MP3 are both turned on. Because the gate potential EN of the transistor MN3 is at a low level, the transistor MN3 is turned off, resulting in the transistor MP4 also being turned off, that is, the output of the first logic gate circuit to the gate potential of the transistor MP1 is at a high level, and the transistor MP1 is turned off; and since the potential of the driving terminal EN is at a low level, the transistor MN2 is turned off, and the transistor MP4 is also turned off. That is, the gate potential of the transistor MP1 is at a high level, and the transistor MP1 is turned off. The output of the second logic gate circuit is high, and the output of the third logic gate circuit is low, which causes the gate potential of the transistor MN1 to be low, and the transistor MN1 is turned off; due to the existence of the second circuit, the substrate potential always selects the highest potential between the power supply voltage VCC and the output terminal VOUT voltage, and at this time VCC=0V, VOUT is high, so VOUT=VSUB, and the VSUB potential is high at this time, which is the substrate potential of the transistor MP1, and the substrate potentials output to other transistors are consistent, that is, the potential of the transistor MP1 also maintains a high potential at this time, and it will not form a current loop from the output terminal VOUT to the substrate, that is, the current cannot flow back into the power supply voltage VCC or the ground;

[0015] In addition, during the circuit startup process, the second circuit is used to ensure that the substrate potential VSUB of the transistor MP1 always selects the highest potential between the power supply voltage VCC and the output voltage VOUT, thereby reducing the generation of current spikes and lowering power consumption.

[0016] As an optional technical solution, the first logic gate circuit is a NAND gate circuit T1.

[0017] As an optional technical solution, the second logic gate circuit is a NOT gate circuit T2.

[0018] As an optional technical solution, the third logic gate circuit is a NOR gate circuit T3.

[0019] As an optional technical solution, the second circuit includes a transistor MP5, a transistor MP6, a transistor MP7, a transistor MP8, a transistor MP9 and a transistor MP10;

[0020] The output terminal VOUT is connected to the source of the transistor MP8 and the source of the transistor MP10, the gate of the transistor MP8 is connected to the gate of the transistor MP9, the gate and drain of the transistor MP8 are connected, the drain of the transistor MP8 is connected to the source of the transistor MP7, the gate and drain of the transistor MP7 are connected, the drain of the transistor MP7 is connected to the drain of the transistor MP6, and then the substrate potential VSUB is output, the gate and drain of the transistor MP6 are connected, the source of the transistor MP6 is connected to the drain of the transistor MP5, the gate and drain of the transistor MP5 are connected, the gate of the transistor MP5 is connected to the gate of the transistor MP10, the source of the transistor MP5 and the source of the transistor MP9 are both connected to the voltage source VCC, and the drain of the transistor MP9 is connected to the drain of the transistor MP10, and then the substrate potential VSUB is output.

[0021] As an optional technical solution, the transistor MP5 , the transistor MP6 , the transistor MP7 , the transistor MP8 , the transistor MP9 and the transistor MP10 are all P-type MOS transistors.

[0022] As an optional technical solution, the transistor MP1 , the transistor MP2 , the transistor MP3 and the transistor MP4 are all P-type MOS transistors.

[0023] As an optional technical solution, the transistor MN1, the transistor MN2, and the transistor MN4 are all N-type MOS transistors.

[0024] One or more technical solutions provided by the present invention have at least the following technical effects or advantages:

[0025] The invention discloses a novel backflow current prevention circuit. When the circuit loses power, it can not only completely avoid the occurrence of a diode path to the VCC or the ground, and truly realize zero current when the output loses power, but also isolate the substrate potential of the output PMOS driving tube, so that it is always in the highest potential between the power supply voltage and the output voltage, thereby reducing the generation of current spikes inside the circuit. In addition, due to its analog circuit and its special MOS diode inversion structure, the backflow current prevention circuit can always be in an enabled off state, and no additional path consumption power consumption will be generated. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings described herein are used to provide a further understanding of the embodiments of the present invention, constitute a part of the present invention, and do not constitute a limitation on the embodiments of the present invention;

[0027] Figure 1 It is a schematic diagram of a common output stage leakage current circuit in the prior art;

[0028] Figure 2 It is an electrical schematic diagram of a novel anti-backflow current circuit in the present invention;

[0029] Figure 3 is a schematic diagram of a second circuit in the present invention;

[0030] Figure 4 It is an equivalent schematic diagram of the second circuit in the present invention. DETAILED DESCRIPTION

[0031] In order to more clearly understand the above-mentioned purpose, features and advantages of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the embodiments of the present invention and the features in the embodiments can be combined with each other without conflict.

[0032] In the following description, many specific details are set forth to facilitate a full understanding of the present invention. However, the present invention may also be implemented in other ways different from those within the scope of this description. Therefore, the protection scope of the present invention is not limited to the specific embodiments disclosed below.

[0033] Example

[0034] Please refer to Figure 1 , Figure 1 It is a schematic diagram of a common output stage current circuit in the prior art, and its working principle is as follows:

[0035] When the circuit is working normally, the EN terminal will be set to a high level, and the circuit will perform normal data transmission mode. When the input data Data is at a high level, the output Vout is at a low level, and when Data is at a low level, the output Vout is at a high level.

[0036] When the circuit enters the power-down mode, the EN terminal will be set to a low level, the circuit enters the power-down mode state, the transistor MN is turned off, and the transistor MP is turned on. If the input port of the external subsystem maintains a high level input at this time, it will be transmitted to the output terminal Vout with a high level. At this time, a current path from Vout to Vcc is formed, which will cause leakage current and, in severe cases, damage the chip.

[0037] Please refer to Figure 2~Figure 3 , Figure 2 It is an electrical schematic diagram of a novel anti-backflow current circuit in the present invention. Figure 3 is a schematic diagram of a second circuit in the present invention, wherein the circuit includes a first circuit and a second circuit;

[0038] The first circuit comprises:

[0039] The first logic gate circuit is configured as follows: a first input terminal is connected to the data terminal Data, a second input terminal is connected to the driving terminal EN, and an output terminal is respectively connected to the source of the transistor MN2 and the drain of the transistor MP4. When at least one of the data terminal Data and the driving terminal EN is at a low level, the first logic gate circuit outputs a high level.

[0040] The second logic gate circuit is configured as follows: an input end is connected to the driving end EN, an output end is connected to the third logic gate circuit, and the second logic gate outputs a level opposite to the potential of the driving end EN;

[0041] The third logic gate circuit is configured as follows: a first input terminal is connected to the data terminal Data, a second input terminal is connected to the output terminal of the second logic gate circuit, and an output terminal is connected to the gate of the transistor MN1; when at least one of the data terminal Data and the output terminal of the second logic gate circuit is at a high level, the third logic gate circuit outputs a low level;

[0042] The gate of the transistor MN2 is connected to the voltage source VCC, the drain of the transistor MN2 and the source of the transistor MP4 are both connected to the gate of the transistor MP1, the source of the transistor MP1 is connected to the voltage source VCC, the drain of the transistor MP2 is connected to the gate of the transistor MP1, the source of the transistor MP2 is connected to the drain of the transistor MP3 and then connected to the output terminal VOUT, the gate of the transistor MP2 and the gate of the transistor MP3 are both connected to the voltage source VCC, the gate of the transistor MP4 and the source of the transistor MP3 are both connected to the drain of the transistor MN3, the gate of the transistor MN3 is connected to the driving terminal EN, the drain of the transistor MP1 is connected to the drain of the transistor MN1 and then connected to the output terminal VOUT, and the source of the transistor MN1 and the source of the transistor MN3 are both grounded;

[0043] The second circuit comprises:

[0044] It is used to be connected to the output terminal VOUT, and to make the substrate potential VSUB of the transistor MP1 always select the highest potential between the voltage source VCC and the output terminal VOUT.

[0045] This embodiment provides an implementation method of a first logic gate circuit, where the first logic gate circuit is a NAND gate circuit T1.

[0046] This embodiment provides an implementation method of a second logic gate circuit, and the second logic gate circuit is a NOT gate circuit T2.

[0047] This embodiment provides an implementation method of a third logic gate circuit, and the third logic gate circuit is a NOR gate circuit T3.

[0048] An embodiment of the present invention provides an implementation of a second circuit, wherein the second circuit includes a transistor MP5, a transistor MP6, a transistor MP7, a transistor MP8, a transistor MP9, and a transistor MP10;

[0049] The output terminal VOUT is connected to the source of the transistor MP8 and the source of the transistor MP10, the gate of the transistor MP8 is connected to the gate of the transistor MP9, the gate and drain of the transistor MP8 are connected, the drain of the transistor MP8 is connected to the source of the transistor MP7, the gate and drain of the transistor MP7 are connected, the drain of the transistor MP7 is connected to the drain of the transistor MP6, and then the substrate potential VSUB is output, the gate and drain of the transistor MP6 are connected, the source of the transistor MP6 is connected to the drain of the transistor MP5, the gate and drain of the transistor MP5 are connected, the gate of the transistor MP5 is connected to the gate of the transistor MP10, the source of the transistor MP5 and the source of the transistor MP9 are both connected to the voltage source VCC, and the drain of the transistor MP9 is connected to the drain of the transistor MP10, and then the substrate potential VSUB is output.

[0050] The working principle of this embodiment is as follows:

[0051] During the circuit startup process:

[0052] When the power supply voltage VCC>the voltage of the output terminal VOUT, the Vgs (threshold voltage) of the transistor MP9 is greater than the Vgs of the transistor MP10, and its driving capability transistor MP9>MP10, at this time the transistor MP9 is turned on, and the substrate potential VSUB=VCC;

[0053] When the power supply voltage VCC is less than the voltage of the output terminal VOUT, the Vgs of the transistor MP9 is less than the Vgs of the transistor MP10, and the driving capability of the transistor MP9 is less than that of the transistor MP10. At this time, the transistor MP10 is turned on, and the substrate potential VSUB=VOUT;

[0054] That is, the substrate potential of the PMOS tube always selects the highest potential between the power supply voltage VCC and the output terminal VOUT voltage.

[0055] When the circuit is working properly:

[0056] The driving end EN will be set to a high level, and the circuit will enter the normal data transmission mode. When the data end Data is at a high level, the output end VOUT is at a low level. When the data end Data is at a low level, the output end VOUT is at a high level.

[0057] When the circuit enters power-down mode:

[0058] The driving terminal EN is set to a low level, causing the transistor MN3 to be turned off. Since the transistor MN3 is an N-type MOS tube (high level conduction), and at this time the power supply voltage VCC=0V, the transistor MN2 is turned off, and the transistors MP2 and MP3 are turned on. Since the transistor MN2 is an N-type MOS tube (high level conduction), the transistors MP2 and MP3 are P-type MOS tubes (low level conduction). Since at least one input terminal of the NAND gate circuit T1 is a low level (the level of the driving terminal EN), the output terminal of the NAND gate circuit T1 outputs a high level. Since the transistors MP2 and MP3 are turned on, and the transistor MN3 is turned off, the transistor MP4 is turned off, so the gate voltage of the transistor MP1 is a high level. Since the transistor MP1 is a P-type MOS tube, the transistor MP1 is turned off;

[0059] Since the driving terminal EN is set to a low level, it outputs a high level after being processed by the NOT gate circuit T2, and since at least one input terminal of the NOR gate circuit T3 is at a high level, the output terminal potential of the NOR gate circuit T3 is at a low level, that is, the gate voltage of the transistor MN1 is at a low level, and since the transistor MN1 is an N-type MOS tube, the transistor MN1 is turned off;

[0060] When VCC=0V, VOUT is at a high level, that is, VCC<VOUT, at this time, the Vgs of transistor MP9 is less than the Vgs of transistor MP10, and its driving capability transistor MP9<MP10, at this time, transistor MP10 is turned on, and the substrate potential VSUB=VOUT;

[0061] Since both transistor MP1 and transistor MN1 are turned off at this time, the substrate potential VSUB = the potential of the output terminal VOUT, that is, VSUB is at a high level, and the diode potential output to its substrate is the same, and no current path from the output terminal VOUT to the substrate is formed. The current cannot flow back into the power supply voltage VCC or the ground, forming a good anti-backflow mechanism.

[0062] This embodiment isolates the substrate potential of the output PMOS driver tube, allowing it to always select the highest potential between the power supply voltage and the output terminal voltage, thereby forming a good anti-backflow mechanism. In addition, due to its analog circuit and its special MOS tube inverted structure (please refer to Figure 4 , Figure 4 is an equivalent schematic diagram of the second circuit in the present invention) will keep it in an enabled off state forever, and will not generate additional path power consumption.

[0063] Furthermore, the transistor MP5 , the transistor MP6 , the transistor MP7 , the transistor MP8 , the transistor MP9 and the transistor MP10 are all P-type MOS transistors.

[0064] Furthermore, the transistor MP1 , the transistor MP2 , the transistor MP3 , and the transistor MP4 are all P-type MOS transistors.

[0065] Furthermore, the transistor MN1 , the transistor MN2 , and the transistor MN4 are all N-type MOS transistors.

[0066] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0067] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A novel anti-backflow current circuit, characterized in that: comprising a first circuit and a second circuit; The first circuit comprises: The first logic gate circuit is configured as follows: a first input terminal is connected to the data terminal Data, a second input terminal is connected to the driving terminal EN, and an output terminal is respectively connected to the source of the transistor MN2 and the drain of the transistor MP4. When at least one of the data terminal Data and the driving terminal EN is at a low level, the first logic gate circuit outputs a high level. The second logic gate circuit is configured as follows: an input end is connected to the driving end EN, an output end is connected to the third logic gate circuit, and the second logic gate outputs a level opposite to the potential of the driving end EN; The third logic gate circuit is configured as follows: a first input terminal is connected to the data terminal Data, a second input terminal is connected to the output terminal of the second logic gate circuit, and an output terminal is connected to the gate of the transistor MN1; when at least one of the data terminal Data and the output terminal of the second logic gate circuit is at a high level, the third logic gate circuit outputs a low level; The gate of the transistor MN2 is connected to the voltage source VCC, the drain of the transistor MN2 and the source of the transistor MP4 are both connected to the gate of the transistor MP1, the source of the transistor MP1 is connected to the voltage source VCC, the drain of the transistor MP2 is connected to the gate of the transistor MP1, the source of the transistor MP2 is connected to the drain of the transistor MP3 and then connected to the output terminal VOUT, the gate of the transistor MP2 and the gate of the transistor MP3 are both connected to the voltage source VCC, the gate of the transistor MP4 and the source of the transistor MP3 are both connected to the drain of the transistor MN3, the gate of the transistor MN3 is connected to the driving terminal EN, the drain of the transistor MP1 is connected to the drain of the transistor MN1 and then connected to the output terminal VOUT, and the source of the transistor MN1 and the source of the transistor MN3 are both grounded; The second circuit comprises: It is used to be connected to the output terminal VOUT, and to make the substrate potential VSUB of the transistor MP1 always select the highest potential between the voltage source VCC and the output terminal VOUT.

2. A novel anti-backflow current circuit according to claim 1, characterized in that: The first logic gate circuit is a NAND gate circuit T1.

3. A novel anti-backflow current circuit according to claim 1, characterized in that: The second logic gate circuit is a NOT gate circuit T2.

4. A novel anti-backflow current circuit according to claim 1, characterized in that: The third logic gate circuit is a NOR gate circuit T3.

5. A novel anti-backflow current circuit according to claim 1, characterized in that: The second circuit includes a transistor MP5, a transistor MP6, a transistor MP7, a transistor MP8, a transistor MP9 and a transistor MP10; The output terminal VOUT is connected to the source of the transistor MP8 and the source of the transistor MP10, the gate of the transistor MP8 is connected to the gate of the transistor MP9, the gate and drain of the transistor MP8 are connected, the drain of the transistor MP8 is connected to the source of the transistor MP7, the gate and drain of the transistor MP7 are connected, the drain of the transistor MP7 is connected to the drain of the transistor MP6, and then the substrate potential VSUB is output, the gate and drain of the transistor MP6 are connected, the source of the transistor MP6 is connected to the drain of the transistor MP5, the gate and drain of the transistor MP5 are connected, the gate of the transistor MP5 is connected to the gate of the transistor MP10, the source of the transistor MP5 and the source of the transistor MP9 are both connected to the voltage source VCC, and the drain of the transistor MP9 is connected to the drain of the transistor MP10, and then the substrate potential VSUB is output.

6. A novel anti-backflow current circuit according to claim 5, characterized in that: The transistor MP5 , the transistor MP6 , the transistor MP7 , the transistor MP8 , the transistor MP9 and the transistor MP10 are all P-type MOS transistors.

7. A novel anti-backflow current circuit according to claim 1, characterized in that: The transistor MP1 , the transistor MP2 , the transistor MP3 and the transistor MP4 are all P-type MOS transistors.

8. A novel anti-backflow current circuit according to claim 1, characterized in that: The transistor MN1, the transistor MN2 and the transistor MN4 are all N-type MOS transistors.

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