High-voltage level shift circuit with adaptive dead zone

Abstract

The invention provides a high-voltage level shift circuit with an adaptive dead zone. The level shift circuit comprises a level shift module, a dv / dt noise detection module, a bank signal control module and an output module. According to the invention, the problem that dv / dt noise affects output through a signal chain is prevented by using a bank turn-off technology; the Blank time of dv / dt noise with different intensities is adaptively adjusted through the dv / dt noise detection module, so that the limitation on the minimum conduction time of an input signal in the application is solved; a low transmission delay, high dv / dt noise resistance and low minimum input signal conduction time are obtained, and the application requirements of a DCDC system and a driving circuit system are met.

Description

Technical Field

[0001] The invention relates to the field of power MOS driving circuits, and in particular to a high-voltage level shift circuit with an adaptive dead zone. Background Art

[0002] Since GaN power MOS has a lower FOM value than Si power MOS, it has been widely used in high-frequency and high-performance power drive circuits; in order to give full play to the performance of GaN power MOS, it is necessary to customize high-frequency, efficient and reliable level shift circuits. In high-frequency half-bridge GaN driver chips, the level shift circuit converts the input logic signal from a low level to a high-level logic output to control the high-voltage side GaN power MOS. The characteristics of GaN driver chips place high demands on the design of level shift circuits. Especially in high-frequency working applications, GaN driver chips operate at operating frequencies of tens of megahertz, which requires the level shift circuit to be able to work normally and have low propagation delays, while the minimum on-time limit for the input signal should be small enough. In order to maintain efficiency and avoid overheating of the GaN driver chip, the power consumption of the level shift circuit should be as low as possible, while being able to consume less of the limited charge on the bootstrap capacitor between the high-voltage domain power rails. The input and output capacitance of GaN power MOS is extremely small, which will cause high dv / dt noise exceeding 100V / ns when driven, which will affect the output logic of the level shift circuit and make the reliability of the level shift circuit unguaranteed. This requires the level shift circuit to have a high ability to resist dv / dt noise. GaN power MOS has no body diode. When the half-bridge driver chip works in the dead time, the negative voltage transient of the high-voltage domain ground can be lower than about -2V, which requires the level shift circuit to have a high negative power tolerance. Summary of the invention

[0003] Based on this, the purpose of the present invention is to propose a high-voltage level shift circuit with an adaptive dead zone, so as to ensure the high reliability of the level shift circuit when driving GaN, and to reduce the restriction on the minimum on-time of the input signal as much as possible.

[0004] In order to achieve the above object, the present invention proposes a high-voltage level shift circuit with an adaptive dead zone, which includes a level shift module, a dv / dt noise detection module, a blank signal control module, and an output module.

[0005] The level shift module includes: LDMOS tube M1, LDMOS tube M2, monostable trigger circuit one shoot1, monostable trigger circuit one shoot2, PMOS tube M4, PMOS tube M5, PMOS tube M7, PMOS tube M8, PMOS tube M10, PMOS tube M11, resistor R1, resistor R2, resistor R4, resistor R5, diode D1, diode D2; wherein the input signal is connected to the gate of the LDMOS tube M1 through one shoot1, and the input signal is connected to the gate of the LDMOS tube M1 through an inverter and one shoot2. shoot2 is connected to the gate of the LDMOS tube M2, and the sources of the LDMOS tubes M1 / M2 are grounded VSS; the sources of the PMOS tubes M4 / M5 are connected to the high-voltage power supply VDDH, and the gate and the drain are short-circuited and connected to the drain of the LDMOS tubes M1 / M2 and the PMOS tubes M7 / M8 at the same time; the sources of the NMOS tubes M10 / M11 are connected to the high-voltage ground VSW, and the gate and the drain are short-circuited and connected to the drain of the PMOS tubes M7 / M8 at the same time, which are recorded as signals VO2 / VO1; the signals VO2 / VO1 are connected to the high-voltage ground VSW through resistors R4 / R5 respectively; the resistors R1 / R2 are respectively between the drain and the source of the PMOS tubes M4 / M5; the high-voltage ground VSW is connected to the drain of the LDMOS tubes M1 / M2 through diodes D1 / D2 respectively.

[0006] The dv / dt noise detection module includes: an LDMOS tube M3, a PMOS tube M6, a PMOS tube M9, an NMOS tube M12, a resistor R3, a resistor R6, and a diode D3; wherein the LDMOS tube M3 is biased in a cut-off region, its gate and source are grounded to VSS, and its drain is connected to the gate and drain of the PMOS tube M6 and the drain of the PMOS tube M9; the sources of the PMOS tube M6 and the PMOS tube M9 are both connected to a high-voltage power supply VDDH; the gate and drain of the NMOS tube M12 are short-circuited, and are connected to the drain of the PMOS tube M9, which is recorded as a signal VO3; the signal VO3 is connected to a high-voltage ground VSW through the resistor R6; the high-voltage ground VSW is connected to the drain of the LDMOS tube M3 through the diode D3; the resistor R3 is connected in parallel between the drain and the source of the PMOS tube M6.

[0007] The above solution of the present invention includes at least the following beneficial effects:

[0008] In the embodiments of the present invention, a large dv / dt immunity is achieved by isolating the signal path through a switch. For the input pulse width limitation problem generated therefrom, a dv / dt noise detection circuit is adopted to replicate the influence of dv / dt noise on the signal path under the conditions of process, voltage and temperature changes, thereby generating an adaptive BLK pulse width to reduce the pulse width limitation of the input PWM signal; therefore, the final level shift circuit has low delay, high dv / dt noise resistance, low input pulse width limitation and good robustness.

[0009] Other features and advantages of the present invention will be set forth in the following description, or some features and advantages may be inferred or unambiguously determined from the description, or may be learned by implementing the above-mentioned technology of the present invention.

[0010] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a schematic diagram of the structure of a level shift circuit with high resistance to dv / dt noise in an adaptive dead zone in a specific embodiment of the present invention;

[0012] Figure 2 Schematic diagram of the structure of a traditional level shift circuit;

[0013] Figure 3 It is a schematic diagram of the circuit structure of a level shift module in a specific embodiment of the present invention;

[0014] Figure 4 This is a schematic diagram of the circuit structure of a dv / dt noise detection module in a specific embodiment of the present invention;

[0015] Figure 5 This is a schematic diagram of the circuit structure of a blank signal control module and an output module in a specific embodiment of the present invention;

[0016] Description of reference numerals:

[0017] 1 Level shift module circuit

[0018] 2dv / dt noise detection module circuit

[0019] 3blank signal control module and output module circuit

[0020] VDDH floating voltage domain high power rail power supply terminal

[0021] VSW floating voltage domain high power rail ground terminal

[0022] VDD power supply terminal

[0023] GND ground terminal

[0024] GND ground terminal

[0025] IN level shift circuit input

[0026] EN enable signal input terminal DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0029] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and is not limited to the embodiments set forth herein.

[0030] Please refer to 2 to Figure 5 As shown, the present invention proposes a high-voltage level shift circuit with an adaptive dead zone, and introduces four specific circuit structures, including a level shift module 1, a dv / dt noise detection module 2, a blank signal control module and an output module 3.

[0031] In a specific embodiment of the present invention, the level shift module includes: LDMOS tube M1, LDMOS tube M2, monostable trigger circuit one shoot1, monostable trigger circuit one shoot2, PMOS tube M4, PMOS tube M5, PMOS tube M7, PMOS tube M8, PMOS tube M10, PMOS tube M11, resistor R1, resistor R2, resistor R4, resistor R5, diode D1, diode D2; wherein the input signal is transmitted through one shoot1 is connected to the gate of the LDMOS tube M1, and the input signal is connected to the gate of the LDMOS tube M2 through an inverter and oneshoot2, and the source of the LDMOS tubes M1 / M2 is grounded VSS; the source of the PMOS tubes M4 / M5 is connected to the high-voltage power supply VDDH, and the gate and the drain are short-circuited and connected to the drain of the LDMOS tubes M1 / M2 and the PMOS tubes M7 / M8 at the same time; the source of the NMOS tubes M10 / M11 is connected to the high-voltage ground VSW, and the gate and the drain are short-circuited and connected to the drain of the PMOS tubes M7 / M8 at the same time, which is recorded as the signal VO2 / VO1; the signal VO2 / VO1 is connected to the high-voltage ground VSW through the resistors R4 / R5 respectively; the resistors R1 / R2 are respectively between the drain and the source of the PMOS tubes M4 / M5; the high-voltage ground VSW is connected to the drain of the LDMOS tubes M1 / M2 through the diodes D1 / D2 respectively.

[0032] In a specific embodiment of the present invention, the dv / dt noise detection module includes: an LDMOS tube M3, a PMOS tube M6, a PMOS tube M9, an NMOS tube M12, a resistor R3, a resistor R6, and a diode D3; wherein the LDMOS tube M3 is biased in a cut-off region, its gate and source are grounded to VSS, and its drain is connected to the gate and drain of the PMOS tube M6 and the drain of the PMOS tube M9; the sources of the PMOS tube M6 and the PMOS tube M9 are both connected to a high-voltage power supply VDDH; the gate and drain of the NMOS tube M12 are short-circuited and connected to the drain of the PMOS tube M9, which is recorded as a signal VO3; the signal VO3 is connected to a high-voltage ground VSW through the resistor R6; the high-voltage ground VSW is connected to the drain of the LDMOS tube M3 through the diode D3; and the resistor R3 is connected in parallel between the drain and source of the PMOS tube M6.

[0033] In a specific embodiment of the present invention, the blank signal control module and the output module include: a switch SW1, a switch SW2, a monostable trigger circuit one shoot3, a monostable trigger circuit one shoot4, an SR latch SR latch1, an SR latch SR latch2, and a plurality of logic gate circuits; the signal VO2 / signal VO1 is connected to the set end S1 and the reset end R1 of the SR latch SR latch1 through the switch SW1 / switch SW2 and an inverter respectively; the signal VO3 is connected to the input end of the monostable trigger circuit one shoot3 through two inverters, and the output of the input end of one shoot4 is ANDed with the enable signal EN and recorded as the reset signal RN; the set end S1 of the SR latch1 is connected to the input of the monostable trigger circuit one shoot3, and the output of one shoot3 is connected to the SR latch SR The set end S2 of latch2; the reset end of the SR latch SRlatch2 is connected to the reset signal RN, the output signal is recorded as signal BLK after passing through the inverter, and is recorded as signal BLKB after passing through the inverter again; the signals BLK and BLKB together control the opening and closing of the switches SW1 and SW2.

[0034] Specifically, the level shift module is used to: receive an input PWM signal, generate a single short pulse signal through a monostable circuit to drive the LDMOS; generate a pull-down current through the LDMOS, and the pull-down current is copied through a current mirror to act on the NMOS working in the high-voltage domain and generate a characteristic signal;

[0035] Specifically, the dv / dt noise detection module is used for: when no da / dt event occurs, the entire dv / dt noise detection module has a static power consumption of 0 because the LDMOS tube is biased in the cut-off region, which can ensure the low power consumption requirement of the circuit; when the floating voltage domain (VSW-VDDH) is pumped from a low voltage to a high voltage, a current of Cds*(dv / dt) is generated on the large parasitic capacitance between the drain and source of the LDMOS. Since the detection module and the signal link module work under the same conditions at this time, the detection module can generate an equal Cds*(dv / dt) current, which is used to determine whether the dv / dt event is over;

[0036] Specifically, the blank signal control module is used for: when the level shift module receives the input PWM signal, the characteristic signal is transmitted to the output, and at this time, the blank signal control module generates a BLK signal to control the switch SW1 / SW2 on the signal chain to turn off, so as to prevent the subsequent dv / dt noise from affecting the output through the switch, and the switch SW1 / SW2 will not be reset until the dv / dt noise detection module detects that the dv / dt event ends to prepare for the next input, that is, the width of the BLK signal is adaptively adjusted to reduce the limitation on the input signal pulse width;

[0037] Specifically, the output module is used to receive the logic signal to be output by the previous stage, and has latching and driving capabilities.

[0038] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A high-voltage level shift circuit with an adaptive dead zone, the level shift circuit comprising a level shift module, a dv / dt noise detection module, a blank signal control module, and an output module; characterized in that: When the input signal is logic "1", the level shift circuit works to output logic "1" in the high voltage domain. At this time, the circuit will generate a BLK signal to shut down the circuit to prevent dv / dt noise from affecting the output. At the same time, the dv / dt noise detection module will detect the time when the dv / dt noise affects the departure, and adaptively adjust the width of the BLK signal to reduce the limitation on the input signal pulse width.

2. A high voltage level shift circuit with adaptive dead zone according to claim 1, characterized in that: The level shift module includes: LDMOS tube M1, LDMOS tube M2, monostable trigger circuit one shoot1, monostable trigger circuit one shoot2, PMOS tube M4, PMOS tube M5, PMOS tube M7, PMOS tube M8, PMOS tube M10, PMOS tube M11, resistor R1, resistor R2, resistor R4, resistor R5, diode D1, diode D2; wherein the input signal is connected to the gate of the LDMOS tube M1 through one shoot1, and the input signal is connected to the gate of the LDMOS tube M1 through the inverter and one shoot2. shoot2 is connected to the gate of the LDMOS tube M2, and the sources of the LDMOS tubes M1 / M2 are grounded VSS; the sources of the PMOS tubes M4 / M5 are connected to the high-voltage power supply VDDH, and the gate and the drain are short-circuited and connected to the drain of the LDMOS tubes M1 / M2 and the PMOS tubes M7 / M8 at the same time; the sources of the NMOS tubes M10 / M11 are connected to the high-voltage ground VSW, and the gate and the drain are short-circuited and connected to the drain of the PMOS tubes M7 / M8 at the same time, which are recorded as signals VO2 / VO1; the signals VO2 / VO1 are connected to the high-voltage ground VSW through resistors R4 / R5 respectively; the resistors R1 / R2 are respectively between the drain and the source of the PMOS tubes M4 / M5; the high-voltage ground VSW is connected to the drain of the LDMOS tubes M1 / M2 through diodes D1 / D2 respectively.

3. A high voltage level shift circuit with adaptive dead zone according to claim 1, characterized in that: The dv / dt noise detection module includes: an LDMOS tube M3, a PMOS tube M6, a PMOS tube M9, an NMOS tube M12, a resistor R3, a resistor R6, and a diode D3; wherein the LDMOS tube M3 is biased in a cut-off region, its gate and source are grounded to VSS, and its drain is connected to the gate and drain of the PMOS tube M6 and the drain of the PMOS tube M9; the sources of the PMOS tube M6 and the PMOS tube M9 are both connected to a high-voltage power supply VDDH; the gate and drain of the NMOS tube M12 are short-circuited, and are connected to the drain of the PMOS tube M9, which is recorded as a signal VO3; the signal VO3 is connected to a high-voltage ground VSW through the resistor R6; the high-voltage ground VSW is connected to the drain of the LDMOS tube M3 through the diode D3; the resistor R3 is connected in parallel between the drain and the source of the PMOS tube M6.

4. A high voltage level shift circuit with adaptive dead zone according to claim 1, characterized in that: The blank signal control module and output module include: switch SW1, switch SW2, monostable trigger circuit one shoot3, monostable trigger circuit one shoot4, SR latch SR latch1, SR latch SR latch2, and a plurality of logic gate circuits; the signal VO2 / signal VO1 is connected to the set terminal S1 and reset terminal R1 of SR latch SR latch1 through switch SW1 / switch SW2 and an inverter respectively; the signal VO3 is connected to the input terminal of the monostable trigger circuit one shoot3 through two inverters, and the output of the input terminal of one shoot4 is ANDed with the enable signal EN and recorded as the reset signal RN; the set terminal S1 of SR latch1 is connected to the input of the monostable trigger circuit one shoot3, and the output of one shoot3 is connected to the set terminal S2 of SR latch SR latch2; the SR latch SR The reset terminal of latch2 is connected to the reset signal RN. The output signal is recorded as signal BLK after passing through an inverter, and is recorded as signal BLKB after passing through another inverter. The signals BLK and BLKB together control the opening and closing of switches SW1 and SW2.

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