Current steering DAC architecture

Abstract

The invention discloses a current-steering DAC (Digital-to-Analog Converter) architecture, which relates to a microelectronic circuit technology and comprises a differential dual decoding module, a multiplexer network, a switch driving circuit array and a current source array, the differential dual decoding module comprises two decoding units with consistent structures, namely a decoding unit I and a decoding unit II; the decoding unit I is provided with an input signal input end, the decoding unit II is provided with an inverted input signal input end, the decoding unit is provided with a low-order decoding signal output end, a second decoding signal output end and a third decoding signal output end, the low-order decoding signal output end is connected with the input end of the switch driving circuit array, and the third decoding signal output end is connected with the input end of the switch driving circuit array. The second decoding signal output end and the third decoding signal output end are respectively connected with the input end of the switch driving circuit array through the multiplexer network, and the multiplexer network is also provided with a shift control signal input end. According to the invention, the problems of transmission delay and large loss of high-voltage transmission under high frequency are reduced, and the conversion rate is improved.

Description

Technical Field

[0001] The present invention relates to microelectronic circuit technology, and more particularly, to a current steering DAC architecture. Background Art

[0002] As TFT products are widely used in wearable flexible electronic devices, electronic skin, bioelectric medical signal detection, etc., TFT DAC circuits are used in flexible sensor systems and other circuits to achieve the conversion from digital to analog. In order to achieve high conversion rate and high precision TFT DAC, current steering TFT DAC has been widely studied.

[0003] Figure 1 The current steering TFT DAC architecture in is a commonly used current steering TFT DAC architecture. Figure 2 For the structure of D latch, Figure 3 is the structure of the switch drive circuit array, Figure 4 It is a unit current source structure. When the electrical signal output by the thermometer decoder arrives at the rising edge of the clock, the D latch outputs the in-phase terminal signal Q and the inverting terminal signal QN to drive the switch drive circuit array. At this time, since the output of QN is delayed by the delay of an inverter I2 of Q, as shown in Figure 5 As shown, it will cause the windows of the in-phase output terminal signal Vp and the inverting output terminal signal Vn of the switch driving circuit array to be asymmetric, and even cause Vp and Vn to be high or low at the same time, increase the burrs of the output current, and deteriorate the SFDR; at the same time, when Vp and Vn are low at the same time, the common gate transistor Mcs and the current source transistor Mcm of the unit current source enter the cut-off region, and when the unit current source is turned on again, the related node capacitances of the common gate transistor Mcs and the current source transistor Mcm need to be charged, resulting in a decrease in the conversion rate; at the same time, because when the clock signal is at a level, the switch driving circuit array is driven by the inverter I1 and the inverter I2, which is equivalent to one inverter needing to drive another inverter and one input port of the switch driving circuit array. If the size of the inverters I1 and I2 is increased at this time, although the driving ability of the D latch can be enhanced, when the clock rising edge arrives, the thermometer decoding output signal needs to break the stronger gain loop of the inverters I1 and I2, resulting in an increase in delay, thereby resulting in a decrease in the conversion rate.

[0004] Figure 6 The capacitor bootstrap inverter in the circuit is the most commonly used logic gate in the circuit built with all NMOS TFT. However, if the capacitor bootstrap inverter does not flip for a long time, the capacitor C will leak charge, resulting in a decrease in the logic level swing VOUT. Figure 7In the TFT DAC digital circuit, when the capacitor bootstrap logic gate has a charge leakage, the logic level with reduced swing amplitude is insufficient to maintain the normal operation of the switch drive circuit array in the analog circuit, resulting in an error in the output current of the current steering TFT DAC.

[0005] The classic DEM (dynamic error matching) technique includes a random sequence generation circuit and a multiplexer network, wherein the multiplexer network is as follows: Figure 8 As shown, the traditional multiplexer network consists of a 2-to-1 selector, which consists of two TFT NMOS transmission gates and an inverter, such as Fig. 9 As shown. However, there is no PMOS in the 2-to-1 selector built with all TFT NMOS, such as Fig.10 As shown in the figure, when transmitting a high level, a threshold voltage Vth is lost, and the NMOS that is turned on is in the saturation region, resulting in a large resistance, which will cause a large voltage drop and delay when a high-frequency signal passes through. The series connection of multiple 2-to-1 selectors will increase the delay and significantly lose the high-frequency high-level voltage. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide a current-steering DAC architecture in view of the deficiencies in the prior art, which reduces the transmission delay and the voltage loss of high-frequency and high-voltage transmission.

[0007] A current steering DAC architecture described in the present invention includes a differential dual decoding module, a multiplexer network, a switch driving circuit array, and a current source array; the differential dual decoding module includes two decoding units with consistent structures, namely decoding unit one and decoding unit two; the decoding unit one is provided with an input signal input terminal, the decoding unit two is provided with an inverting input signal input terminal, the decoding unit is provided with a low-order decoding signal output terminal, a second decoding signal output terminal and a third decoding signal output terminal, the low-order decoding signal output terminal is connected to the input terminal of the switch driving circuit array, the second decoding signal output terminal and the third decoding signal output terminal are respectively connected to the input terminal of the switch driving circuit array through the multiplexer network, and the multiplexer network is also provided with a shift control signal input terminal, and the output terminal of the switch driving circuit array is connected to the input terminal of the current source array.

[0008] Preferably, an N-bit input signal is inputted into the input end of the decoding unit, and the decoding unit comprises an M-bit thermometer decoder and two (NM) / 2-bit thermometer decoders, the m-bit thermometer decoder is provided with a low-bit decoding signal output end, and the two (NM) / 2-bit thermometer decoders are respectively provided with a second decoding signal output end and a third decoding signal output end.

[0009] Preferably, the decoding signal output end of the (NM) / 2-bit thermometer decoder outputs a K-bit decoding output signal, the shift control signal input end inputs K as a shift control signal, the multiplexer network is composed of K rows and K columns of NMOSTFTs, the gate of each row of the NMOS TFTs inputs a shift control signal, the drains of each column of the NMOS TFTs are connected together, the drains of the K columns of the NMOS TFTs respectively input one of the K-bit decoding output signals in turn, and the source of each column of the NMOS TFTs serves as a K-bit network signal output end.

[0010] Preferably, the NMOS TFTs in the first column are arranged in the order of 1 to K, and the NMOS TFTs after the first column use the last NMOS TFT in the previous column as the first NMOS TFT in the current column, and the remaining NMOS TFTs in the previous column are shifted down one position as the arrangement of the NMOS TFTs in the current column.

[0011] Preferably, the current-steering DAC architecture further includes a random sequence generator, which inputs a clock signal CLK and outputs a K-bit shift control signal.

[0012] Preferably, input terminals of the two decoding units are both connected to D flip-flops.

[0013] Preferably, one of the D flip-flops inputs an input signal, an input terminal of another of the D flip-flops is connected to an inverter, and an input terminal of the inverter inputs the input signal.

[0014] Preferably, the current-steering DAC architecture further includes a timing refresh module, and an output end of the timing refresh module is simultaneously connected to two D flip-flops.

[0015] Preferably, the timing refresh module includes a plurality of 2-to-1 selectors, the input end of the 2-to-1 selector is connected to the output end of the D flip-flop, and the control end of the 2-to-1 selector inputs a timing refresh signal refresh.

[0016] Beneficial Effects

[0017] The advantages of the present invention are:

[0018] 1. Aiming at the charge leakage problem of the capacitor bootstrap logic gate built with all NMOS TFT, a timing refresh module is designed to supplement the charge leakage of the capacitor in the capacitor bootstrap logic gate, avoid the attenuation of the output swing of the capacitor bootstrap logic gate, and maintain the correct output current of the current steering TFT DAC.

[0019] 2. The differential dual thermometer decoding structure is adopted to ensure that the signals at the in-phase and inverting ends of the switch drive circuit input experience the same logic gate chain delay to arrive, thereby ensuring the symmetry of the rising and falling windows, reducing the burrs of the current output, and thus improving the SFDR.

[0020] 3. The differential dual thermometer decoding structure adopted enables the in-phase end decoding circuit to drive the in-phase end of the switch driving circuit, and the inverting end drives the inverting end of the switch driving circuit, thereby improving the driving capability of the switch driving circuit and improving the conversion rate of the current steering TFT DAC.

[0021] 4. In order to solve the problems of increased transmission delay and excessive loss of high-voltage transmission at high frequency caused by the series connection of multiple stages of 2-to-1 selectors in the multiplexer network, the present invention adopts a multiplexer network with a DEM structure composed of 1-to-7 selectors, which reduces the transmission delay and voltage loss of high-frequency and high-voltage transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of the structure of a traditional current-steering TFT DAC;

[0023] Figure 2 It is a schematic diagram of the D latch structure;

[0024] Figure 3 Schematic diagram of the switch driving circuit structure;

[0025] Figure 4 is a schematic diagram of the unit current source structure;

[0026] Figure 5 A curve diagram showing a large current glitch caused by asymmetric rising and falling windows in a switch driving circuit in the prior art;

[0027] Figure 6 It is a schematic diagram of the capacitor bootstrap logic gate structure;

[0028] Figure 7 A curve diagram showing a reduction in output swing of an output logic gate due to capacitor charge leakage in the related art;

[0029] Figure 8 A schematic diagram of a conventional multiplexer network structure supporting 3-bit shifting according to the present invention;

[0030] Fig. 9 This is a schematic diagram of the result of a 2-to-1 selector;

[0031] Fig.10 A schematic diagram of the structure of the threshold loss caused by the NMOS transmission gate;

[0032] Fig.11 A schematic diagram of the current steering DAC architecture of the present invention;

[0033] Fig.12 A schematic diagram of a curve showing that the switch driving circuit of the present invention symmetrically reduces current glitches in the rising and falling windows;

[0034] Fig.13 It is a schematic diagram of the framework of a 3-bit thermometer decoder 1 of the present invention;

[0035] Fig.14 It is a schematic diagram of the framework of a 3-bit thermometer decoder 2 of the present invention;

[0036] Fig.15 It is a schematic diagram of the framework of a 3-bit thermometer decoder 3 of the present invention;

[0037] Fig.16 It is a schematic diagram of the framework of a 3-bit thermometer decoder 4 of the present invention;

[0038] Fig.17 It is a schematic diagram of the framework of a 2-bit thermometer decoder 1 of the present invention;

[0039] Fig.18 It is a schematic diagram of the framework of a 2-bit thermometer decoder 2 of the present invention;

[0040] Fig.19 It is a schematic diagram of the improvement curve of conversion rate and SFDR of the present invention;

[0041] Fig. 20 This is a schematic diagram of the connection structure of the timing refresh module of the present invention;

[0042] Fig.21 It is a schematic diagram of the logic gate level of the timing refresh module of the present invention;

[0043] Fig. 22 The output current of the conventional current-steering TFT DAC is compared with the output current of the current-steering TFT DAC with a timing refresh module added;

[0044] Fig.23 It is a schematic diagram of the network structure of the multiplexer of the present invention;

[0045] Fig.24 Comparison diagram of a square wave signal transmitted through a multiplexer network. DETAILED DESCRIPTION

[0046] The present invention will be further described below in conjunction with the embodiments, but it does not constitute any limitation to the present invention. Any limited number of modifications made by anyone within the scope of the claims of the present invention are still within the scope of the claims of the present invention.

[0047] like Fig.11As shown, a current steering DAC architecture of the present invention is composed of a timing refresh module, a random sequence generator, a multiplexer network, a D flip-flop, a differential dual decoding module, a switch drive circuit array, and a current source array. Among them, the differential dual decoding module includes two decoding units with the same structure, namely decoding unit 1 and decoding unit 2. The decoding unit 1 is provided with an input signal input terminal, the decoding unit 2 is provided with an inverting input signal input terminal, the decoding unit is provided with a low-order decoding signal output terminal, a second decoding signal output terminal and a third decoding signal output terminal, the low-order decoding signal output terminal is connected to the input terminal of the switch drive circuit array, the second decoding signal output terminal and the third decoding signal output terminal are respectively connected to the input terminal of the switch drive circuit array through the multiplexer network, and the multiplexer network is also provided with a shift control signal input terminal, and the output terminal of the switch drive circuit array is connected to the input terminal of the current source array.

[0048] exist Fig.11 In the figure, CLK is the clock signal, refresh is the timing refresh signal, B0~B7 are 8-bit input signals, where B0 is the least significant bit and B7 is the most significant bit; is the inverted signal of B0~B7. When the clock rises, B0~B7 and At the same time, it is transmitted to the differential dual decoding module for decoding. The decoding of this embodiment adopts the 2+3+3 segmented thermometer decoding mode, that is, the lower 2 bits of B0 and B1 are decoded by thermometer, the middle 3 bits of B2 to B4 are decoded by thermometer, and the upper 3 bits of B5 to B7 are decoded by thermometer. The lower 2 bits are decoded using a dual thermometer. The middle 3 bits are decoded using a dual thermometer. The upper 3 bits are decoded using dual thermometers. After thermometer decoding, the signals La0~La2 and Lb0~Lb2 are inverted, the signals Ua0~Ua6 and Ub0~Ub6 are inverted, and the signals Ma0~Ma6 and Mb0~Mb6 are inverted. In the above signals, the signals La0~La2 and Lb0~Lb2 are respectively input into the same-phase input terminal and the inverted input terminal of the corresponding switch drive circuit. The signals Ua0~Ua6 and Ub0~Ub6 are connected to the multiplexer network, and then two groups of signals Dua0~Dua6 and Dub0~Dub6 with inverted phases are output respectively. The signals Dua0~Dua6 and Dub0~Dub6 are respectively input into the same-phase input terminal and the inverted input terminal of the corresponding switch drive circuit. Signals Ma0~Ma6 and signals Mb0~Mb6 are connected to the multiplexer network, and then two groups of signals Dma0~Dma6 and Dmb0~Dmb6 with opposite phases are output respectively. Signals Dma0~Dma6 and signals Dmb0~Dmb6 are respectively input into the same-phase input terminal and the opposite-phase input terminal of the corresponding switch driving circuit. Q1~Q7 are the shift control signals of the multiplexer network, which control the shift operation of the input signal of the multiplexer network. Vpl0~Vpl2 and Vnl0~Vnl2 output by the switch driving circuit array respectively control the same-phase switch and the opposite-phase switch of the lower 3-bit current source array, Vpu0~Vpu6 and Vnu0~Vnu2 respectively control the same-phase switch and the opposite-phase switch of the middle 7-bit current source array, Vpm0~Vpm6 and Vnm0~Vnm6 respectively control the same-phase switch and the opposite-phase switch of the upper 7-bit current source, and finally obtain the same-phase output current Ip and the opposite-phase output current In.

[0049] The present invention proposes that the input signals B0-B7 are obtained through an inverter at the input end to obtain their inverted signals. When the clock rising edge arrives, the two input signals will be decoded by the thermometer at the same time, and experience the same logic gate link delay. The decoded signals are synchronously input to the switch drive circuit, so that the windows of the in-phase output signal Vp and the inverting output signal Vn of the switch drive circuit are symmetrical, reducing the generation of current glitches, thereby improving SFDR. Fig.12 As shown. At the same time, the in-phase and inverting input terminals of the switch driving circuit are driven by the in-phase and inverting thermometer decoder circuits respectively, which enhances the driving capability of the switch driving circuit, thereby improving the conversion rate of the current steering TFT DAC. Fig.11 The inputs of the 3-bit thermometer decoder 1 and the 3-bit thermometer decoder 2 are inverted, and the decoding results are inverted to each other. The two are in a dual relationship. The 3-bit thermometer decoder 3 and the 3-bit thermometer decoder 4 also present a dual relationship, and the 2-bit thermometer decoder 1 and the 2-bit thermometer decoder 2 also present a dual relationship.

[0050] In this embodiment, the block diagrams of the 3-bit thermometer decoder 1 and the 3-bit thermometer decoder 2 are as follows: Fig.13 , Fig.14 As shown, the truth tables of the two are shown in Table 1 and Table 2.

[0051] Table 1 Truth table of 3-bit thermometer decoder 1

[0052] B7 B6 B5 Ma1 Ma2 Ma3 Ma4 Ma5 Ma6 Ma7 0 0 0 O 0 0 O 0 0 0 0 0 1 1 0 O 0 0 0 0 0 1 0 1 1 0 O 0 0 O 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 O 0 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

[0053] Table 2 Truth table of 3-bit thermometer decoder 2

[0054]

[0055] The block diagrams of the 3-bit thermometer decoder 3 and the 3-bit thermometer decoder 4 are shown in FIG. Fig.15 , Fig.16 As shown, the truth tables of the two are shown in Table 3 and Table 4.

[0056] Table 3 Truth table of 3-bit thermometer decoder 3

[0057] B4 B3 B2 Ua1 Ua2 Ua3 Ua4 Ua5 Ua6 Ua7 O 0 0 O 0 0 O 0 O 0 0 0 1 1 0 0 0 O 0 0 0 1 0 1 1 0 O O 0 0 0 1 1 1 1 1 0 O 0 0 1 0 0 1 1 1 1 O 0 0 1 0 1 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1

[0058] Table 4 Truth table of 3-bit thermometer decoder 4

[0059]

[0060] The block diagram of 2-bit thermometer decoder 1 and 2-bit thermometer decoder 2 is shown in Fig.17 , Fig.18 As shown, the truth tables of the two are shown in Table 5 and Table 6.

[0061] Table 5 Truth table of 2-bit thermometer decoder 1

[0062] B1 B0 La1 La2 La3 0 0 0 0 0 0 1 1 0 0 1 0 1 1 0 1 1 1 1 1

[0063] Table 6 Truth table of 2-bit thermometer decoder 2

[0064]

[0065] like Fig.19 As shown, taking an 8-bit current-steering TFT DAC as an example, when this architecture is adopted, the maximum conversion rate of the current-steering TFT DAC is 32KS / s, while the maximum conversion rate of the current-steering TFT DAC with a traditional architecture is 4KS / s. At the same time, SFDR is also improved compared with the traditional current-steering TFT DAC at the same input signal frequency.

[0066] In order to solve the problem of capacitor charge leakage under low-frequency signals in logic gates built with all NMOS TFTs, the present invention adds a timing refresh circuit module, such as Fig. 20As shown in the figure, this module is a 2-to-1 selector. That is, a 2-to-1 selector is added after the D flip-flop, which makes all input signals flip once within a certain period, realizes the replenishment of the capacitor charge in the capacitor bootstrap inverter, and keeps the swing VOUT of the logic gate level unchanged, as shown in the figure. Fig.21 shown.

[0067] Fig. 22 The output current of the traditional current steering TFT DAC and the output current of the current steering TFT DAC with a timing refresh module are shown. The output current of the traditional TFT current steering DAC will cause the current to leak due to the charge leakage of the capacitor bootstrap logic gate, resulting in a long-term erroneous current output, while the TFT current steering DAC with timing refresh avoids errors caused by capacitor leakage of the capacitor bootstrap logic gate by timing a cycle of refresh.

[0068] In order to solve the problem of greatly increased delay and significant loss of high-frequency high-level signals caused by the series connection of multiplexer switches, such as Fig.23 As shown, a 1-level 1-to-7 selector is used to build a multiplexer network, which avoids a significant increase in delay and a significant loss in high-frequency, high-level signal transmission. Specifically, the multiplexer network is composed of 7 rows and 7 columns of NMOS TFTs, the gate of each row of the NMOS TFTs inputs a shift control signal, the drains of each column of the NMOS TFTs are connected together, the drains of the 7 columns of the NMOS TFTs respectively input one of the 7-bit decoded output signals in turn, and the source of each column of the NMOS TFTs serves as a 7-bit network signal output terminal. Its specific layout structure is that the NMOS TFTs in the first column are arranged in order of 1 to 7, and the NMOS TFTs after the first column use the last NMOS TFT in the previous column as the first NMOS TFT in the current column, and the remaining NMOS TFTs in the previous column are all shifted down one position as the arrangement of the NMOS TFTs in the current column. For details, refer to Fig.23 layout.

[0069] exist Fig.23In the example, the signals Ma0~Ma6 output by the high 3-bit thermometer decoder are used as input, Dmma0~Dma6 are output signals, and Q1~Q7 are shift control signals generated by the random sequence generator. The working principle is as follows: when Q1 is high and Q2~Q7 is low, all transistors connected to Q1 are turned on, and the remaining transistors are turned off. At this time, MaO is transmitted to Dma0, Ma1 is transmitted to Dma1, Ma2 is transmitted to Dmma2, Ma3 is transmitted to Dmma3, Ma4 is transmitted to Dmma4, Ma5 is transmitted to Dma5, and Ma6 is transmitted to Dmma6, and there is no shift operation. When Q2 is high, Q3~Q7 and Q1 are low, all transistors connected to Q2 are turned on, and the rest of the transistors are turned off. At this time, Ma0 is transmitted to Dmal, Mal is transmitted to Dma2, Ma2 is transmitted to Dmma3, Ma3 is transmitted to Dma4, Ma4 is transmitted to Dmma5, Ma5 is transmitted to Dma6, and Ma6 is transmitted to Dmal, completing the right shift operation by 1 bit. And so on, the shift operation is completed, and the final displacement is shown in Table 7.

[0070] Table 7 Multiplexer network shift

[0071] Q1 Q2 Q3 Q4 Q5 Q6 Q7 Number of bits to shift right 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 2 O O 0 1 0 0 0 3 0 0 0 0 1 0 0 4 0 0 0 0 0 1 0 5 0 0 0 0 0 0 1 6

[0072] Among the Q1-Q7 signals generated by the random sequence generator matched with the multiplexer network proposed by the present invention, only one of the signals is output as a high level, and the other signals are output as low levels. Whenever the rising edge of the clock arrives, Q1-Q7 will be refreshed once. Fig.24 The comparison of the square wave signal transmission between the traditional multiplexer network and the multiplexer network of the present invention is shown. Relatively speaking, the speed and voltage loss of the square wave signal transmission of the multiplexer network of the present invention are better than those of the traditional multiplexer network.

[0073] The above is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several modifications and improvements can be made without departing from the structure of the present invention, which will not affect the effect of the implementation of the present invention and the practicality of the patent.

Claims

1. A current steering DAC architecture, characterized in that: It includes a differential dual decoding module, a multiplexer network, a switch driving circuit array, and a current source array; the differential dual decoding module includes two decoding units with the same structure, namely decoding unit 1 and decoding unit 2; the decoding unit 1 is provided with an input signal input terminal, the decoding unit 2 is provided with an inverting input signal input terminal, the decoding unit is provided with a low-order decoding signal output terminal, a second decoding signal output terminal and a third decoding signal output terminal, the low-order decoding signal output terminal is connected to the input terminal of the switch driving circuit array, the second decoding signal output terminal and the third decoding signal output terminal are respectively connected to the input terminal of the switch driving circuit array through the multiplexer network, and the multiplexer network is also provided with a shift control signal input terminal, and the output terminal of the switch driving circuit array is connected to the input terminal of the current source array.

2. A current steering DAC architecture according to claim 1, characterized in that: The input end of the decoding unit inputs an N-bit input signal, and the decoding unit includes an M-bit thermometer decoder and two (NM) / 2-bit thermometer decoders. The m-bit thermometer decoder is provided with a low-bit decoding signal output end, and the two (NM) / 2-bit thermometer decoders are respectively provided with a second decoding signal output end and a third decoding signal output end.

3. A current steering DAC architecture according to claim 2, characterized in that: The decoding signal output end of the (NM) / 2-bit thermometer decoder outputs a K-bit decoding output signal, the shift control signal input end inputs K as a shift control signal, the multiplexer network is composed of K rows and K columns of NMOS TFTs, the gate of each row of the NMOS TFTs inputs a shift control signal, the drains of each column of the NMOS TFTs are connected together, the drains of the K columns of the NMOS TFTs respectively input one of the K-bit decoding output signals in turn, and the source of each column of the NMOS TFTs serves as a K-bit network signal output end.

4. A current steering DAC architecture according to claim 3, characterized in that: The NMOS TFTs in the first row are arranged in the order of 1 to K. The NMOS TFTs after the first row use the last NMOS TFT in the previous row as the first NMOS TFT in the current row, and the remaining NMOS TFTs in the previous row are shifted down one position to form the arrangement of the NMOS TFTs in the current row.

5. The current steering DAC architecture according to claim 3, characterized in that: The current-steering DAC architecture further includes a random sequence generator, which inputs a clock signal CLK and outputs a K-bit shift control signal.

6. The current steering DAC architecture according to claim 1, characterized in that: The input ends of the two decoding units are both connected with D flip-flops.

7. A current steering DAC architecture according to claim 6, characterized in that: One of the D flip-flops inputs an input signal, and the input terminal of the other D flip-flop is connected to an inverter, and the input terminal of the inverter inputs the input signal.

8. The current steering DAC architecture according to claim 6, characterized in that: The current-steering DAC architecture further includes a timing refresh module, and an output end of the timing refresh module is simultaneously connected to two D flip-flops.

9. A current steering DAC architecture according to claim 8, characterized in that: The timing refresh module includes a plurality of 2-to-1 selectors, the input end of the 2-to-1 selector is connected to the output end of the D flip-flop, and the control end of the 2-to-1 selector inputs a timing refresh signal refresh.

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