Parallel processing large-bandwidth signal source equipment and calibration method

Abstract

The invention discloses a parallel processing large-bandwidth signal source device and a calibration method. The signal source device comprises a high-speed parallel digital signal processing board, an interaction unit, a large-bandwidth radio frequency front-end unit, a radio frequency output interface, an ultra-bandwidth antenna and an external clock port. A display control unit interface, a high-speed parallel digital signal processing core board, a radio frequency control interface, a high-speed parallel DAC, an intermediate frequency output interface, a clock input port and a clock unit are integrated on the high-speed parallel digital signal processing board. The signal source equipment provided by the invention is provided with a display screen, supports remote control, can realize large-bandwidth signal output, and can perform effective bandwidth flatness calibration and radio frequency output power calibration for the signal source equipment.

Description

Technical Field

[0001] The invention relates to a signal source, and in particular to a signal source device for parallel processing of a large bandwidth and a calibration method. Background Art

[0002] Currently, the main manufacturers of vector signal generators with frequencies up to 18G in the domestic market are Keysight Technologies and RS. The main shortcomings of their products include:

[0003] Most equipment controls are manually operated using display screens, touch screens, buttons, etc., or are controlled by computers using wired (network cables, USB cables, serial ports, etc.) connections, and most require the purchase of remote operation software plug-ins.

[0004] The real-time bandwidth of the device output signal is relatively narrow, and only a very small number of high-end signal sources have an output signal bandwidth greater than or equal to 1G. Summary of the invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a signal source device and calibration method for parallel processing of large bandwidth. The device itself has a display screen and supports remote control. At the same time, it can achieve large bandwidth signal output and can perform effective bandwidth flatness calibration and RF output power calibration for the signal source device.

[0006] The object of the present invention is achieved by the following technical solutions: A signal source device for parallel processing of large bandwidth, comprising: a high-speed parallel digital signal processing board, an interaction unit, a large-bandwidth radio frequency front-end unit, a radio frequency output interface, an ultra-wideband antenna and an external clock port;

[0007] The high-speed parallel digital signal processing board is integrated with a display control unit interface, a high-speed parallel digital signal processing core board, a radio frequency control interface, a high-speed parallel DAC, an intermediate frequency output interface, a clock input port and a clock unit; the high-speed parallel digital signal processing core board includes a display control unit and a high-speed parallel digital processing unit; the display control unit is connected to the interactive unit through the display control unit interface, and the display control unit is also connected to the high-speed parallel digital processing unit;

[0008] The input end of the high-speed parallel DAC is connected to the high-speed parallel digital processing unit, and the output end of the high-speed parallel DAC is connected to the ultra-wideband antenna through the intermediate frequency output interface, the large-bandwidth radio frequency front-end unit and the radio frequency output interface in sequence;

[0009] The external clock input interface is connected to the large-bandwidth radio frequency front-end unit, the clock input interface input end of the high-speed parallel digital signal processing board is connected to the large-bandwidth radio frequency front-end unit, and the output end is connected to the clock unit.

[0010] A high-speed parallel digital signal processing method for parallel processing of a large-bandwidth signal source device, wherein the high-speed parallel digital signal processing is mainly used to generate an intermediate frequency digital signal, which is transmitted to a high-speed parallel DAC to be converted into an intermediate frequency signal, wherein the signal includes a continuous wave signal (such as a single tone) and a digital modulation signal (such as a UWB pulse signal), and comprises the following steps:

[0011] S1. Continuous wave signal processing flow:

[0012] S101. The high-speed parallel digital processing unit (PL end) receives the single-tone frequency value f transmitted by the display control unit (PS end) out , the system clock frequency is f clk , using N parallel DDS (direct frequency synthesis technology) to generate intermediate frequency digital signals and high-speed parallel DAC input channels with the same configuration, and the sampling rate of each signal in the N channels is f clk , and the clock configuration is the same as that of the DAC;

[0013] S102. Output frequency f of each parallel DDS outb The calculation formula is: outb =f out %f clk , the frequency control word Δθ calculation formula is: Among them B θ(n) is the bit width of the frequency control word, % means remainder;

[0014] S103. Obtain N-phase frequency control words, and send each phase frequency control word to the 8-way parallel processing phase accumulator, and then obtain N-phase parallel waveform data through the sine lookup table, and output to N-way high-speed parallel DAC:

[0015] After obtaining the N-phase frequency control word, each time the clock pulse is triggered, the frequency control word of each phase is sent to the N-way parallel processing phase accumulator, and each phase accumulator is connected to a phase register. When the clock pulse is triggered, the phase register outputs the stored data to the phase accumulator; the data stored in the phase register is initially 0 or a preset initial frequency control word;

[0016] Each phase accumulator accumulates the output data in the phase register and the received frequency control word, and uses the accumulated result to update the data stored in the phase register as the output of the phase register when the next clock pulse is triggered, and at the same time sends the accumulated result to the sine lookup table as the address of the sine lookup table;

[0017] The sine lookup table is generated by the host computer software and put into the high-speed parallel digital processing unit in the form of a COE file. The sine lookup table stores the digital amplitude information of a complete cycle of a sine wave. The address of each lookup table corresponds to a phase point in the sine wave.

[0018] The sine lookup table maps the input address information into a sine wave amplitude signal to obtain N-phase high-speed parallel waveform data, and then outputs it to the N-channel high-speed parallel DAC data interface;

[0019] S104. High-speed parallel DAC performs digital-to-analog conversion to obtain an intermediate frequency analog signal, and completes high-speed parallel digital signal processing;

[0020] S2. Digital modulation signal processing flow:

[0021] S201. Generate a high-speed parallel digital modulation signal BIN file in the MALAB software in the host computer;

[0022] S202. Connect the host computer network port to the RJ45 network port of the signal source, and transmit the high-speed parallel digital modulation signal BIN file to the display control unit (PS end) through the network port. After the PS end receives the high-speed parallel digital modulation signal BIN file, it is stored in the EMMC;

[0023] S203. The high-speed parallel digital processing unit (PL end) receives the output signal parameters (output signal mode, output channel number, output algorithm enable, etc.) transmitted by the display control unit (PS end), and the high-speed parallel digital processing unit (PL end) reads the high-speed parallel digital modulation signal BIN file in the EMMC through the AXI protocol HP interface to the high-speed cache DDR mounted on the PL end for temporary storage;

[0024] S204. The high-speed parallel digital processing unit (PL end) reads the high-speed parallel digital modulation signal BIN file from the high-speed cache DDR and matches the data rate to the parallel data rate f of the high-speed parallel DAC clk Consistency;

[0025] S205. The high-speed parallel digital processing unit (PL end) performs parallel data up-sampling on the high-speed parallel digital modulation signal BIN file to obtain a high-speed parallel digital modulation signal.

[0026] S206. Transmit the high-speed parallel digital modulation signal to the high-speed parallel DAC, which performs digital-to-analog conversion to obtain an intermediate frequency analog signal, and then completes high-speed parallel digital signal processing.

[0027] In order to improve the accuracy of data processing, the signal source device can be pre-calibrated before high-speed parallel digital signal processing. Specifically: A calibration method for a parallel processing large bandwidth signal source device includes a bandwidth flatness calibration step and a radio frequency output power calibration step:

[0028] The bandwidth flatness calibration step comprises:

[0029] A101. Connect the computer to the debugging interface of the signal source through JTAG, and connect the intermediate frequency output interface of the signal source to the RF interface of the spectrum analyzer;

[0030] A102. After the computer is connected to the debugging interface through JTAG, it establishes a connection with the display control unit in the high-speed parallel digital signal processing core board, and sends a signal generation instruction to the high-speed parallel digital processing unit through the display control unit, so that the digital processing unit generates a signal, and after passing through the high-speed parallel DAC, the intermediate frequency is output at full power and the frequency is from f min to f max Output k single-tone signals uniformly, and read the power values ​​of the k points on the spectrum analyzer to obtain a two-dimensional record table of frequency and power, where f min is the preset minimum frequency, f max is the preset maximum frequency, k is the preset number of single tone signals;

[0031] A103. On the computer side, use MATLAB software to generate the filter tap array for flatness calibration:

[0032] A1031. Import the two-dimensional record table of frequency and power into the MATLAB software of the computer to form an array, and then perform normalization on the power values ​​in the array;

[0033] dbg1=dbbw_flip-max(dbbw_flip); dbg1 is the power normalization array, and dbbw_flip is the array formed by the imported power;

[0034] A1032. Perform data conversion on the power normalized data to obtain the converted linear representation array bwp1:

[0035] bwp1 = a^(dbg1 / b);

[0036] Where a and b are preset constants, and dbg1 / b means dividing each array in the power normalization array dbg1 by the constant b;

[0037] A1033. Convert the linear representation array bwp1 and take the inverse to get the expected in-band response of the correction filter. Manually add the edge tap coefficient c, which is a linear coefficient used to prevent overfitting, to get the filter calibration tap coefficient group bw_inv:

[0038] bw_inv=[c 1 / bwp1 c] / median(1 / bwp1)

[0039] Among them, 1 / bwp1 means the array obtained by taking the reciprocal of each element in the linear representation array bwp1; median means taking the median;

[0040] A1034. Perform ifft and cyclic shift on the filter calibration tap coefficient group bw_inv to obtain the filter tap array h_cor for flatness calibration:

[0041] Define the intermediate variable d = (length (dbbw_flip) + 1) / 2, then:

[0042] h_cor=circshift{ifft[circshift(bw_inv,-d),d]}

[0043] ifft means inverse fast Fourier transform, circshift means cyclic shift, and length means length;

[0044] A104. Generate the flatness calibration filter Verilog code based on the filter tap array used for flatness calibration. The specific operation is performed in Simulink:

[0045] The generated calibration filter Verilog code is placed in the digital processing unit. When the digital processing unit receives a signal generation instruction from the display control unit, the flatness calibration filter Verilog code is used to filter the generated signal to achieve flatness calibration.

[0046] The radio frequency output power calibration step comprises:

[0047] A201. Use an RF cable to connect the RF output interface of the signal source and the RF input interface of the spectrum analyzer; use a network cable to connect: network switch, test computer network port, signal source RJ45 network port, spectrum analyzer network port;

[0048] A202. Control the signal source to output a single tone signal with a frequency of F1, and control the signal source RF attenuator to attenuate S0; the computer reads the power of the corresponding frequency on the spectrum analyzer and records the power value;

[0049] A203. Keep the frequency unchanged and switch the attenuation value of the signal source to S=S0+ΔSdB until the attenuation value of the signal source is completed S=S max dB, and repeat A202 at each attenuation value to form a corresponding relationship between attenuation and power value at the current frequency; ΔS represents the attenuation step, S maxIndicates the maximum attenuation value;

[0050] A204. Switch to the next frequency point F = F1 + ΔFMHz, repeat step A203 until the frequency is F = F max , generating a three-dimensional table of frequency, attenuation and power values; where ΔF represents the frequency step, F max Indicates the maximum frequency value. Generally speaking, F max The difference from F1 is an integer multiple of ΔF;

[0051] A205. The three-dimensional table of frequency, attenuation and power values ​​finally generated is used as the initial configuration file, and is placed in the signal display control unit, and the configuration file is automatically loaded each time the system is started;

[0052] A206. Use table lookup: After setting the output frequency and power of the signal source, first query whether the frequency is in the three-dimensional table through the frequency value: if the frequency value is in the table, determine whether the power value is present. If the power value is present, return the attenuation value; if the power value is not in the table, and the power value is less than the maximum power value at the frequency in the table and greater than the minimum power value at the frequency in the table, use linear fitting to calculate the attenuation value corresponding to the power value and return the attenuation value;

[0053] The linear fitting calculation formula is Y=AX+B, where Y is the output power and X is the attenuation value. The power value between two points adjacent to Y in the table is used to calculate the values ​​of A and B, and then the values ​​are substituted into the formula Y=AX+B to obtain X=(YB) / A.

[0054] If the frequency value is not found in the table, use the value closest to the frequency in the table as the lookup frequency value, and repeatedly determine whether there is a power value process under the lookup frequency value to obtain the attenuation value, which is transmitted to the FPGA control module of the large-bandwidth RF front-end unit, and the FPGA control module performs attenuation control.

[0055] The overall architecture of the signal source application software adopts C / S software architecture, and the application mainly includes: display control layer and logic control layer.

[0056] Display control layer: mainly runs on the signal source device, based on the Linux operating system, and uses C++ remote programming. The main functions of the graphical operation interface are: to achieve a good user interaction experience and a simple interface style. It is mainly used to provide human-computer interface interaction functions, device screen management, device button service management and other functions.

[0057] Logical control layer: mainly runs on the signal source device, based on the Linux operating system, using C++ remote programming, mainly used for the realization of software functions of different types of signal function modules, distribution management of different types of signal test tasks, providing UDP services, and providing test process control of different types of signals. It realizes multiple signal configuration operations, provides fast configuration loading and saving, provides local control and remote control, facilitates users to control multiple scenarios, and provides fast configuration loading and saving.

[0058] The beneficial effects of the present invention are as follows: the device itself has a display screen, and has a Gigabit Ethernet and USB interface, and can support wired control. It also has a WiFi interface, and can be controlled by connecting to WiFi, supporting wireless remote control of devices such as mobile phones, and can achieve large-bandwidth signal output, and can effectively calibrate bandwidth flatness and RF output power for signal source devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 It is a schematic diagram of the principle of the present invention;

[0060] Figure 2 Generate a flow chart for the signal;

[0061] Figure 3 This is the overall block diagram of the large bandwidth RF front end unit;

[0062] Figure 4 This is a diagram of the RF link architecture of a large bandwidth RF front-end unit; Figure 5 It is a schematic diagram of the connection relationship between the signal source, the spectrum analyzer and the computer; Figure 6 This is a schematic diagram of the calibration instrument connection; Figure 7 The flowchart for obtaining the attenuation value is shown in FIG. DETAILED DESCRIPTION

[0063] The technical solution of the present invention is further described in detail below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following.

[0064] like Figure 1 As shown, a device for parallel processing of large bandwidth signal sources includes: a high-speed parallel digital signal processing board, an interaction unit, a large bandwidth radio frequency front-end unit, a radio frequency output interface, an ultra-wideband antenna and an external clock port;

[0065] The high-speed parallel digital signal processing board is integrated with a display control unit interface, a high-speed parallel digital signal processing core board, a radio frequency control interface, a high-speed parallel DAC, an intermediate frequency output interface, a clock input port and a clock unit; the high-speed parallel digital signal processing core board includes a display control unit and a high-speed parallel digital processing unit; the display control unit is connected to the interactive unit through the display control unit interface, and the display control unit is also connected to the high-speed parallel digital processing unit;

[0066] The input end of the high-speed parallel DAC is connected to the high-speed parallel digital processing unit, and the output end of the high-speed parallel DAC is connected to the ultra-wideband antenna through the intermediate frequency output interface, the large-bandwidth radio frequency front-end unit and the radio frequency output interface in sequence;

[0067] The external clock input interface is connected to the large-bandwidth radio frequency front-end unit, the clock input interface input end of the high-speed parallel digital signal processing board is connected to the large-bandwidth radio frequency front-end unit, and the output end is connected to the clock unit.

[0068] When an external clock signal is output from the external clock input port, the high-bandwidth RF front-end unit uses the clock signal output from the external clock port and transmits the clock signal to the clock unit through the clock output port. The clock unit provides a clock reference for the digital processing unit and the high-speed parallel DAC connection based on the received clock signal.

[0069] When there is no external clock signal output from the external clock input port, the high-bandwidth RF front-end unit uses the OCXO clock signal input from the local clock interface. The clock unit receives the configuration instructions from the high-speed parallel digital processing unit and generates a clock signal to transmit to the digital processing unit and the high-speed parallel DAC.

[0070] In an embodiment of the present application, the interactive unit includes a display screen and a keypad, the display and control unit interface includes a display interface and a control interface, the display screen is connected to the display interface, and the keypad (keyboard panel) is connected to the control interface.

[0071] In an embodiment of the present application, the high-speed parallel digital signal processing core board includes a display control unit (PS end) and a high-speed parallel digital processing unit (PL end); wherein the display control unit (PS end) jointly with the interactive unit (display screen and keyboard board) completes the interaction function with the user, obtains the parameters that the user needs to configure, and passes the parameters to the high-speed parallel digital processing unit (PL end); after the high-speed parallel digital processing unit (PL end) obtains the parameters, it performs parallel calculations, and finally generates a high-speed parallel digital signal and sends it to the high-speed parallel DAC.

[0072] In the embodiment of the present application, the high-speed parallel digital signal processing board is also integrated with an RJ45 interface with a built-in isolation transformer, a debugging interface, a USB3.0 interface chip CYUSB3014 and a TYPE-C interface; the RJ45 interface, the debugging interface, and the CYUSB3014 are all connected to the display management unit, and the TYPE-C interface is connected to the CYUSB3014. The high-speed parallel digital signal processing board is also integrated with a WIFI module and a first WIFI antenna interface; the signal source device also includes a second WIFI antenna interface and a WIFI antenna, wherein the display management unit is connected to the WiFi module, the WiFi module is connected to the first WIFI antenna interface, the first WiFi antenna interface is also connected to the second WiFi antenna interface, and the second WiFi antenna interface is also connected to the WiFi antenna.

[0073] In an embodiment of the present application, the signal source device further includes a power module, the power module includes a power interface, a power management unit, a battery interface and a battery; the power management unit is connected to an external power source via the power interface, and the power management unit is connected to the battery via the battery interface. The battery management unit is used to power the entire signal source device, and control the battery charging and discharging, and realize the battery charging status display. The specific charging and discharging control method is: when the external power supply is not powered, switch the battery to power the system; when the external power supply and the battery are powered at the same time, switch to the external power supply to power the system, and if the battery power is lower than the set threshold, the battery is charged while the external power supply is powering the system.

[0074] The large bandwidth RF front-end unit comprises a first filter, a first AMP amplifier, a first mixer, a second filter, a first digitally controlled attenuator, a second mixer, a second digitally controlled attenuator, a third filter, a second AMP amplifier, a third digitally controlled attenuator, a fourth filter, a third AMP amplifier and a fourth digitally controlled attenuator connected in sequence;

[0075] The large bandwidth RF front-end unit also includes a first local oscillator module, a second local oscillator module, a clock module and an FPGA control module; the clock module is used to receive an external clock or a local OCXO clock signal, and transmit it to the first local oscillator module and the second local oscillator module respectively, the first local oscillator module is used to generate a first local oscillator signal and transmit it to the local oscillator input end of the first mixer, and the second local oscillator module is used to generate a second local oscillator signal and transmit it to the local oscillator input end of the second mixer;

[0076] The FPGA control module is used to control the clock module to access the signal input from the external clock port when there is a clock signal input from the external clock port, and transmit the signal input from the external clock port to the clock unit through the clock input port, and switch to the local clock interface to access the local OCXO clock signal when there is no clock signal input from the external clock port;

[0077] The FPGA control module also controls the tuning frequency parameter control and the attenuation parameter of the large bandwidth RF front end unit according to the signal of the RF control interface.

[0078] The control of the tuning frequency parameter of the large-bandwidth RF front-end unit is achieved by controlling the first local oscillator module and the second local oscillator module; the control of the attenuation parameter of the large-bandwidth RF front-end unit is achieved by controlling the first digitally controlled attenuator to the fourth digitally controlled attenuator.

[0079] The high-speed parallel digital signal processing core board of the present invention adopts the ZYNQ-7100 processing chip, which is a chip integrating an ARM main control chip and an FPGA digital signal processor. It has ARM control capabilities and FPGA high-speed signal processing capabilities in one chip, greatly reducing the area of ​​the internal board.

[0080] In actual use, the ARM side mainly completes the implementation of the human-computer interaction interface, including the display, buttons, external network interface and other interfaces, which is convenient for users. The FPGA mainly completes the processing of digital signals, the generation of baseband digital signals, and drives the high-speed parallel DAC to generate intermediate frequency signals.

[0081] Among them, the RF control interface is mainly used to receive instructions from the digital processing unit to control the working state of the RF module, including the tuning frequency parameter control of the RF module and the attenuation parameter control of the RF module; in some embodiments, the frequency deviation control of the built-in clock crystal oscillator in the RF module and the module temperature detection can also be performed.

[0082] The system works as follows:

[0083] The display screen and buttons serve as a human-computer interaction interface. After receiving the operator's operating instructions, they send the operating instructions to the display management unit (PS end) on the high-speed parallel digital signal processing core board.

[0084] The display management unit decomposes the operation instructions, generates configuration commands, and sends the configuration data to the digital processing part of the digital processing unit (PL end) or the RF configuration module through the dedicated GP interface between the PS end and the PL end. The configuration commands mainly include: frequency configuration commands, power configuration commands, signal generation types, signal generation parameters, etc.

[0085] High-speed parallel digital processing unit (PL side) processing is mainly divided into three parts:

[0086] (1) The first part is to generate the system configuration. According to the software configuration command, configure the clock module output clock, which is used for the sampling clock of the high-speed parallel DAC and the interface data transmission clock. Configure the working mode of the high-speed parallel DAC module (the working mode refers to the JESD high-speed interface parameter configuration of the DAC, such as the JMOD parameters, etc.), and the working interface link is successful.

[0087] (2) The second part is the high-speed parallel digital signal generation module, which is divided into two parts: continuous wave signal and modulation signal.

[0088] The continuous wave signal is generated by parallel DDS technology.

[0089] The modulation signal generation process includes: BIN file generation, BIN file transmission path and FPGA data processing, DAC data processing and intermediate frequency signal generation.

[0090] ②BIN file generation is mainly done through the MALAB software in the host computer, or inside the FPGA.

[0091] ②BIN file transmission path and high-speed parallel digital signal processing: Generate a high-speed parallel digital modulation signal according to the command or download the BIN file from the PC. After the display control unit (PS end) receives the BIN file, it is first stored in the EMMC, and then read out by the high-speed parallel digital processing unit (PL end) through the HP interface in AXI to the DDR temporary storage of the PL end. The data read from the DDR is then sampled and power controlled in parallel in the high-speed parallel digital processing unit (PL end). After reaching the required signal required by the high-speed parallel DAC, the high-speed parallel digital processing unit completes the processing and sends the modulated high-speed parallel signal to the high-speed parallel DAC.

[0092] ③ High-speed parallel DAC data processing and intermediate frequency signal generation. After the FPGA high-speed modulated parallel signal is received, it is upsampled again inside the high-speed parallel DAC to a rate that matches the final sampling rate of the high-speed parallel DAC. The 1.8G intermediate frequency change processing is performed through the internal NCO of the high-speed parallel DAC. After digital filtering and high-speed parallel DAC conversion, the intermediate frequency digital signal is formed and sent to the input interface of the RF module. The RF is frequency-converted to the final required center frequency to complete the signal generation; the signal generation process is as follows: Figure 2 As shown;

[0093] (3) The third part is to convert the RF configuration instructions (mainly including frequency and power attenuation information) into an SPI interface, and send the RF configuration information to the FPGA processor of the RF module to complete the configuration of the RF module; after each interface configures the output frequency and power, the digital processing unit calculates and obtains the configuration data. The configuration information mainly includes the tuning frequency of the RF module and the output attenuation parameter configuration. Through the four-wire SPI timing, the SPI uses a 10M configuration clock to send the configuration data to the FPGA processor of the RF module.

[0094] When receiving the configuration tuning frequency, the RF module converts the tuning frequency into the configuration local oscillator LO1 and local oscillator LO2 to achieve the function of changing the output frequency;

[0095] When receiving the configuration RF attenuation, the RF module attenuates the RF to the RF attenuator configured to the final stage, thereby realizing the RF power configuration;

[0096] The configuration transmission protocol adopts the handshake configuration method. The configuration is first sent to the FPGA processor of the RF module. The FPGA processor of the RF module executes the configuration instructions to complete the configuration. After the configuration is completed, the digital processing unit reads the configuration results of the FPGA processor of the RF module to ensure that the FPGA processor executes the configuration information normally. The overall block diagram of the large bandwidth RF front-end unit is as follows Figure 3 As shown;

[0097] The clock module processes and accepts the configuration processed by the digital processing unit (PL end), locks the clock, and forms the sampling clock for the high-speed parallel DAC and the interface data transmission clock.

[0098] High-speed parallel DAC processing accepts the configuration of the digital processing unit (PL end), completes the high-speed parallel DAC configuration, receives the intermediate frequency digital signal, upsamples the intermediate frequency signal, and then performs 1.8GHz intermediate frequency conversion, filtering, and analogization of the high-speed digital signal. Through the intermediate frequency output interface, it outputs a broadband intermediate frequency analog signal with a fixed bandwidth and a center frequency of 1.8GHz.

[0099] The large-bandwidth RF front-end unit processes and receives the SPI configuration instructions transmitted by the digital processing unit (PL end) through the RF control interface to complete the output frequency and output power settings. The high-speed parallel DAC outputs a wideband intermediate frequency analog signal with a center frequency of 1.8GHz, performs intermediate frequency filtering, amplifies the intermediate frequency signal, performs the first mixing with the first local oscillator, and the generated signal is filtered and attenuated. It is then mixed with the second local oscillator for the second time. The generated signal is attenuated, filtered, and amplified twice to complete the RF signal in the output frequency range. The RF link architecture diagram of the large-bandwidth RF front-end unit is shown below: Figure 4 As shown;

[0100] The overall software has flatness correction within the mid-frequency band and the output power of 250MHz to 1800MHz is factory calibrated.

[0101] (1) IF output 1GHz bandwidth flatness calibration:

[0102] The IF output frequency is 1.8GHz, and the IF bandwidth is 1GHz. The actual output IF signal will have poor in-band signal flatness, resulting in poor in-band signal flatness of the final output RF signal. By calibrating the IF output flatness, the 1GHz bandwidth flatness of the IF output is greatly improved.

[0103] Device connection: See the device connection relationship Figure 4 , the computer is connected to the debugging interface of the signal source through JTAG, and the intermediate frequency output interface of the signal source is connected to the RF interface of the spectrum analyzer.

[0104] Calibration method:

[0105] ① Configure the DAC on the computer so that the DAC outputs the intermediate frequency at full power and evenly outputs 11 single-tone signals from 1.3GHz to 2.3GHz. Read the power values ​​of these 11 points on the spectrum analyzer to obtain a two-dimensional record table of frequency and power.

[0106] ② Generate a flatness calibration filter tap array in MATLAB, import the power two-dimensional table to form an array, and then normalize the power values ​​in the array.

[0107] Import the two-dimensional record table of frequency and power into the MATLAB software on the computer to form an array, and then log

[0108] The power values ​​in the group are normalized;

[0109] dbg1=dbbw_flip-max(dbbw_flip);

[0110] dbg1 is the power normalization array, and dbbw_flip is the array formed by importing power;

[0111] The power normalized data is converted to linear representation to obtain the converted linear representation array bwp1:

[0112] bwp1 = a^(dbg1 / b);

[0113] Where a and b are preset constants, dbg1 / b means dividing each array in the power normalization array dbg1 by the constant b; a is generally 10, and b is between 10 and 30;

[0114] Convert the linear representation array bwp1 and take the inverse to get the expected in-band response of the correction filter. Manually add the edge tap coefficient c, which is a linear coefficient used to prevent overfitting, to get the filter calibration tap coefficient group bw_inv:

[0115] bw_inv=[c 1 / bwp1 c] / median(1 / bwp1)

[0116] Among them, 1 / bwp1 means the array obtained by taking the reciprocal of each element in the linear representation array bwp1; median means taking the median; c is generally taken as 0.15;

[0117] Perform ifft and cyclic shift on the filter calibration tap coefficient group bw_inv to obtain the filter tap array h_cor for flatness calibration:

[0118] Define the intermediate variable d = (length (dbbw_flip) + 1) / 2, then:

[0119] h_cor=circshift{ifft[circshift(bw_inv,-d),d]}

[0120] ifft means inverse fast Fourier transform, circshift means cyclic shift, and length means length;

[0121] ③ Generate the flatness calibration filter tap array and generate the flatness calibration filter Verilog code. The specific operations are performed in Simulink: encapsulate the required functional module set into a subsystem in Simulink, and use the required Verilog module input and output as the input and output of the Simulink subsystem, use the BUFFER module to configure the output multi-phase number to 8, use the Convert module to configure the output fixed point 32, right-click the subsystem, select HDLWorkflow Advisor, and select Run All to generate the code.

[0122] ④Put the generated calibration filter Verilog code into the data processing module to complete signal filtering.

[0123] (2) RF output 250MHz~1800MHz power calibration, the calibration method is as follows:

[0124] ①Calibration instrument connection: The connection relationship is as follows Figure 6 As shown, use an RF cable to connect the RF output interface of the signal source and the RF input interface of the spectrum analyzer; use a network cable to connect: the network switch, the test computer network port, the signal source network port, and the spectrum analyzer network port.

[0125] ②Calibration operation 1: The computer controls the signal source to output a single-tone signal with a frequency of F1, and controls the signal source RF attenuator to attenuate S0; the computer reads the power of the corresponding frequency point on the spectrum analyzer; the output frequency point of the signal source, the attenuation value of the signal source RF attenuator, and the power value on the spectrum analyzer are recorded at this moment to form a correspondence between frequency, attenuation and power value; the attenuation value of the signal source is switched to S=S0+5dB, until the signal source attenuation value traverses to S=30dB, and the task of calibration operation 1 is repeated to form a three-dimensional table corresponding to frequency, attenuation and power value.

[0126] ③ Switch the next frequency point to F=F1+10MHz, repeat the calibration operation 1 until the frequency is F=18GHz, and generate the final three-dimensional table.

[0127] ④ The three-dimensional table corresponding to the frequency, attenuation and power values ​​finally generated is used as the initial configuration file and is placed in the signal source EMMC memory, and the configuration file is automatically loaded each time the system is started.

[0128] ⑤Use table lookup: After setting the output frequency and power of the signal source during use, first query whether there is such frequency in the three-dimensional table through the frequency value: if there is such frequency value in the table, determine whether there is such power value, and if there is such power value, return the attenuation value; if there is no such power value in the table, and the power value satisfies the requirement of being less than the maximum power value at the frequency in the table and greater than the minimum power value at the frequency in the table, then use linear fitting to calculate the attenuation value corresponding to the power value and return the attenuation value; if the frequency value is not found in the table, use the value closest to the frequency in the table as the table lookup frequency value, repeat the process of determining whether there is such power value under the table lookup frequency value, and obtain the attenuation value, thus completing the calibration and output process. For the specific process, please see Figure 7 .

[0129] ⑥ Linear fitting calculation formula Y = AX + B, Y is the output power, X is the attenuation value, find the power value between two points adjacent to Y in the table to calculate the values ​​of A and B, and then substitute it into the formula Y = AX + B to get

[0130] X = (YB) / A;

[0131] In the present invention, a small-volume portable design of the signal source is realized:

[0132] (1) Using the ZYNQ7100 chip, a chip integrates the ARM core (PS side) and FPGA logic (PL side). The PS side mainly improves the control and management capabilities, and can achieve better protocol control and human-machine interface. The PL side has more resources and greatly improved data processing capabilities. The 7100 is equivalent to Xilinx's XC7K410T level when compared with ordinary logic FPGAs. It can process more data in the same package size. Compared with the area occupied by traditional single ARM chips, FPGA chips and their peripherals, the PCB area is reduced by half when using the ZYNQ7100 chip.

[0133] (2) The RF module uses only one module to achieve 250MHz~1800MHz signal frequency conversion output, integrates two-stage local oscillator modules, and integrates a clock module to provide local OCXO and external clock switching functions.

[0134] In the present invention, the high-speed digital intermediate frequency signal generation method is improved, mainly the intermediate frequency signal generation module of the digital processing unit (PL end) is improved:

[0135] (1) The sampling rate of the intermediate frequency digital signal is 1.25GSPS, the signal bandwidth is 1GHz, and the signal rate is 1.25×16×2=40Gbps. If the data is directly processed in a single channel, the internal clock of the FPGA must be 1.25GHz, which cannot be achieved by the FPGA. Therefore, the interface is changed to a multi-phase parallel processing interface, and combined with the DAC configuration, it is determined to be an 8-phase parallel output, and the sampling clock of each phase in the FPGA is 156.25MHz. In this way, the single-channel high-speed signal is converted into 8-channel lower-rate signals for parallel processing. The parallel data is converted into an analog intermediate frequency signal output inside the DAC.

[0136] (2) Multiphase processing of intermediate frequency digital signals:

[0137] ① Output UWB intermediate frequency digital signal, convert the generated single-channel high-speed signal into 8-phase parallel processing data through the serial-to-parallel conversion module (take the 8Nth data of the serial data as the 1st phase, the 8N+1th data as the 2nd phase...the 8N+7th data as the 8th phase, N is a natural number) and transmit it to the DAC for conversion and output.

[0138] ② Output single-tone digital signal: Convert the single-channel DDS into an 8-phase parallel DDS. The DDS clock also uses 156.25MHz, generating a parallel DDS frequency of f out %156.25MHz, phases are 2π*i*f out / 1.25G, where i=0,1,...,7.

[0139] (3) Download the BIN file from the PC to generate digital modulation signal processing to overcome the slow reading and writing speed of EMMC. DDR supports high-speed reading and writing, but cannot be stored without power failure. The following method is used:

[0140] ①After the PC downloads the BIN file, first store the BIN file in the slow EMMC on the PS side for easy use next time.

[0141] ② Digital signal generation: first, through the high-speed HP data channel between PS and PL, the data in the EMMC on the PS side is taken out at a slow rate, cached in the DDR on the PL side, and then the DDR data is sent to the intermediate frequency signal processing channel through the high-speed parallel interface, and finally sent to the high-speed parallel DAC to complete the signal conversion

[0142] To improve the high-speed parallel DAC, the DAC38RF85 chip is used to convert the digital IF signal into an analog IF signal. The chip's built-in upsampling function is used to upsample the 1.25G sampling rate to 8G, as well as the chip's NCO frequency conversion function. The IF center frequency output is 1.8G, the frequency output range is 1.3G~2.3G, and the bandwidth is 1G.

[0143] The processing of the large-bandwidth RF front-end unit is improved, and the analog intermediate frequency signal is subjected to two-stage mixing and filtering. The mixer and filter are improved so that the output bandwidth finally reaches 1G, and the final output frequency is an ideal 250M~18G signal.

[0144] The above is a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art do not depart from the spirit and scope of the present invention, and should be within the scope of protection of the claims attached to the present invention.

Claims

1. A device for parallel processing of large bandwidth signal sources, characterized in that: include: High-speed parallel digital signal processing board, interactive unit, high-bandwidth RF front-end unit, RF output interface, ultra-wideband antenna and external clock port; The high-speed parallel digital signal processing board is integrated with a display control unit interface, a high-speed parallel digital signal processing core board, a radio frequency control interface, a high-speed parallel DAC, an intermediate frequency output interface, a clock input port and a clock unit; the high-speed parallel digital signal processing core board includes a display control unit and a high-speed parallel digital processing unit; the display control unit is connected to the interactive unit through the display control unit interface, and the display control unit is also connected to the high-speed parallel digital processing unit; The input end of the high-speed parallel DAC is connected to the high-speed parallel digital processing unit, and the output end of the high-speed parallel DAC is connected to the ultra-wideband antenna through the intermediate frequency output interface, the large-bandwidth radio frequency front-end unit and the radio frequency output interface in sequence; The external clock input interface is connected to the large-bandwidth radio frequency front-end unit, the clock input interface input end of the high-speed parallel digital signal processing board is connected to the large-bandwidth radio frequency front-end unit, and the output end is connected to the clock unit.

2. The device for parallel processing of large bandwidth signal sources according to claim 1, characterized in that: The interactive unit includes a display screen and a keypad, the display and control unit interface includes a display interface and a control interface, the display screen is connected to the display interface, and the keypad is connected to the control interface.

3. The device for parallel processing of large bandwidth signal sources according to claim 1, characterized in that: When the external clock input interface has an external clock signal output, the high-bandwidth RF front-end unit uses the clock signal output by the external clock input interface and transmits the clock signal to the clock unit through the clock input port. The clock unit provides a clock reference for the high-speed parallel digital processing unit and the high-speed parallel DAC connection according to the received clock signal. When there is no external clock signal output from the external clock input interface, the high-bandwidth RF front-end unit uses the OCXO clock signal input from the local clock interface. The clock unit receives the configuration instructions from the high-speed parallel digital processing unit and generates a clock signal to transmit to the high-speed parallel digital processing unit and the high-speed parallel DAC.

4. The device for parallel processing of large bandwidth signal sources according to claim 1, characterized in that: The display control unit is used to cooperate with the interactive unit to complete the interactive function with the user, obtain the parameters that the user needs to configure, and pass the parameters to the high-speed parallel digital processing unit; after the high-speed parallel digital processing unit obtains the parameters, it generates a high-speed parallel digital signal and sends it to the high-speed parallel DAC.

5. The device for parallel processing of large bandwidth signal sources according to claim 1, characterized in that: The high-speed parallel digital signal processing board is also integrated with an RJ45 interface with an isolation transformer, a debugging interface, a USB3.0 interface chip CYUSB3014 and a TYPE-C interface; the RJ45 interface, the debugging interface, and the CYUSB3014 are all connected to the display management unit, the TYPE-C interface is connected to the CYUSB3014, and the debugging interface includes a JTAG interface and a debugging serial port; The high-speed parallel digital signal processing board is also integrated with a WIFI module and a first WIFI antenna interface; the signal source device also includes a second WIFI antenna interface and a WIFI antenna, wherein the display management unit is connected to the WiFi module, the WiFi module is connected to the first WIFI antenna interface, the first WiFi antenna interface is also connected to the second WiFi antenna interface, the second WiFi antenna interface is also connected to the WiFi antenna, the WIFI antenna is for external mobile phones or laptops to receive, and the working state of the signal source is controlled by WiFi.

6. The device for parallel processing of large bandwidth signal sources according to claim 1, characterized in that: The signal source device further comprises a power module, wherein the power module comprises a power interface, a power management unit, a battery interface and a battery; The power management unit is connected to an external power source via a power interface, and is connected to a battery via a battery interface. The battery management unit is used to power the entire signal source device, control battery charging and discharging, display the battery charging status, and switch to external power supply to power the system when both external power supply and battery power are present.

7. The device for parallel processing of large bandwidth signal sources according to claim 1, characterized in that: The large bandwidth RF front-end unit comprises a first filter, a first AMP amplifier, a first mixer, a second filter, a first digitally controlled attenuator, a second mixer, a second digitally controlled attenuator, a third filter, a second AMP amplifier, a third digitally controlled attenuator, a fourth filter, a third AMP amplifier and a fourth digitally controlled attenuator connected in sequence; The large bandwidth RF front-end unit also includes a first local oscillator module, a second local oscillator module, a clock module and an FPGA control module; the clock module is used to receive an external clock or a local OCXO clock signal, and transmit it to the first local oscillator module and the second local oscillator module respectively, the first local oscillator module is used to generate a first local oscillator signal and transmit it to the local oscillator input end of the first mixer, and the second local oscillator module is used to generate a second local oscillator signal and transmit it to the local oscillator input end of the second mixer; The FPGA control module is used to control the clock module to access the signal input from the external clock port when there is a clock signal input from the external clock port, and transmit the signal input from the external clock port to the clock unit through the clock input port, and switch to the local clock interface to access the local OCXO clock signal when there is no clock signal input from the external clock port; The FPGA control module also controls the tuning frequency parameter control and the attenuation parameter of the large bandwidth RF front end unit according to the signal of the RF control interface.

8. The device for parallel processing of large bandwidth signal sources according to claim 1, characterized in that: The control of the tuning frequency parameter of the large-bandwidth RF front-end unit is achieved by controlling the first local oscillator module and the second local oscillator module; the control of the attenuation parameter of the large-bandwidth RF front-end unit is achieved by controlling the first digitally controlled attenuator to the fourth digitally controlled attenuator.

9. A high-speed parallel digital signal processing method for parallel processing of a signal source device with a large bandwidth, using the signal source device according to any one of claims 1 to 8, characterized in that: High-speed parallel digital signal processing is mainly used to generate intermediate frequency digital signals, which are transmitted to high-speed parallel DACs and converted into intermediate frequency signals. The signals include continuous wave signals and digital modulation signals, and include the following steps: S1. Continuous wave signal processing flow: S101. The high-speed parallel digital processing unit receives the single-tone frequency value f transmitted by the display control unit. out , the system clock frequency is f clk , using N parallel DDS to generate intermediate frequency digital signals and high-speed parallel DAC input channels, the sampling rate of each signal in the N channels is f clk , and the clock configuration is the same as that of the DAC; S102. Output frequency f of each parallel DDS outb The calculation formula is: outb =f out %f clk , the frequency control word Δθ calculation formula is: Among them B θ(n) is the bit width of the frequency control word, % means remainder; S103. Obtain N-phase frequency control words, and send each phase frequency control word to the 8-way parallel processing phase accumulator, and then obtain N-phase parallel waveform data through the sine lookup table, and output to the N-way high-speed parallel DAC, including: After obtaining the N-phase frequency control word, each time the clock pulse is triggered, the frequency control word of each phase is sent to the N-way parallel processing phase accumulator, and each phase accumulator is connected to a phase register. When the clock pulse is triggered, the phase register outputs the stored data to the phase accumulator; the data stored in the phase register is initially 0 or a preset initial frequency control word; Each phase accumulator accumulates the output data in the phase register and the received frequency control word, and uses the accumulated result to update the data stored in the phase register as the output of the phase register when the next clock pulse is triggered, and at the same time sends the accumulated result to the sine lookup table as the address of the sine lookup table; The sine lookup table is generated by the host computer software and put into the high-speed parallel digital processing unit in the form of a COE file. The sine lookup table stores the digital amplitude information of a complete cycle of a sine wave. The address of each lookup table corresponds to a phase point in the sine wave. The sine lookup table maps the input address information into a sine wave amplitude signal to obtain N-phase high-speed parallel waveform data, and then outputs it to the N-channel high-speed parallel DAC data interface; S104. High-speed parallel DAC performs digital-to-analog conversion to obtain an intermediate frequency analog signal, and completes high-speed parallel digital signal processing; S2. Digital modulation signal processing flow: S201. Generate a high-speed parallel digital modulation signal BIN file in the MALAB software in the host computer; S202. Connect the host computer network port to the RJ45 network port of the signal source, and transmit the high-speed parallel digital modulation signal BIN file to the display control unit through the network port. After the PS end receives the high-speed parallel digital modulation signal BIN file, it is stored in the EMMC; S203. The high-speed parallel digital processing unit receives the output signal parameters transmitted by the display control unit, and the high-speed parallel digital processing unit reads the high-speed parallel digital modulation signal BIN file in the EMMC through the AXI protocol HP interface to the PL-mounted cache DDR temporary storage; S204. The high-speed parallel digital processing unit reads the high-speed parallel digital modulation signal BIN file from the high-speed cache DDR and matches the data rate to the parallel data rate f of the high-speed parallel DAC. clk Consistency; S205. The high-speed parallel digital processing unit performs parallel data upsampling on the high-speed parallel digital modulation signal BIN file to obtain a high-speed parallel digital modulation signal; S206. Transmit the high-speed parallel digital modulation signal to the high-speed parallel DAC, which performs digital-to-analog conversion to obtain an intermediate frequency analog signal, and then completes high-speed parallel digital signal processing.

10. A calibration method for a parallel processing large bandwidth signal source device, used to calibrate the signal source device according to any one of claims 1 to 8, characterized in that: Includes bandwidth flatness calibration steps and RF output power calibration steps: The bandwidth flatness calibration step comprises: A101. Connect the computer to the debugging interface of the signal source through JTAG, and connect the intermediate frequency output interface of the signal source to the RF interface of the spectrum analyzer; A102. After the computer is connected to the debugging interface through JTAG, it establishes a connection with the display control unit in the high-speed parallel digital signal processing core board, and sends a signal generation instruction to the high-speed parallel digital processing unit through the display control unit, so that the digital processing unit generates a signal, and after passing through the high-speed parallel DAC, the intermediate frequency is output at full power and the frequency is from f min to f max Output k single-tone signals uniformly, and read the power values ​​of the k points on the spectrum analyzer to obtain a two-dimensional record table of frequency and power, where f min is the preset minimum frequency, f max is the preset maximum frequency, k is the preset number of single tone signals; A103. On the computer side, use MATLAB software to generate the filter tap array for flatness calibration: A1031. Import the two-dimensional record table of frequency and power into the MATLAB software of the computer to form an array, and then perform normalization on the power values ​​in the array; dbg1=dbbw_flip-max(dbbw_flip); dbg1 is the power normalization array, and dbbw_flip is the array formed by importing power; A1032. Perform data conversion on the power normalized data to obtain the converted linear representation array bwp1: bwp1 = a^(dbg1 / b); Where a and b are preset constants, and dbg1 / b means dividing each array in the power normalization array dbg1 by the constant b; A1033. Convert the linear representation array bwp1 and take the inverse to get the expected in-band response of the correction filter. Manually add the edge tap coefficient c, which is a linear coefficient used to prevent overfitting, to get the filter calibration tap coefficient group bw_inv: bw_inv=[c 1 / bwp1 c] / median(1 / bwp1) Among them, 1 / bwp1 means the array obtained by taking the reciprocal of each element in the linear representation array bwp1; median means taking the median; A1034. Perform ifft and cyclic shift on the filter calibration tap coefficient group bw_inv to obtain the filter tap array h_cor for flatness calibration: Define the intermediate variable d = (length (dbbw_flip) + 1) / 2, then: h_cor=circshift{ifft[circshift(bw_inv,-d),d]} ifft means inverse fast Fourier transform, circshift means cyclic shift, and length means length; A104. Generate the flatness calibration filter Verilog code based on the filter tap array used for flatness calibration. The specific operation is performed in Simulink: The generated calibration filter Verilog code is placed in the digital processing unit. When the digital processing unit receives a signal generation instruction from the display control unit, the flatness calibration filter Verilog code is used to filter the generated signal to achieve flatness calibration. The radio frequency output power calibration step comprises: A201. Use an RF cable to connect the RF output interface of the signal source and the RF input interface of the spectrum analyzer; use a network cable to connect: network switch, test computer network port, signal source RJ45 network port, spectrum analyzer network port; A202. Control the signal source to output a single tone signal with a frequency of F1, and control the signal source RF attenuator to attenuate S0; the computer reads the power of the corresponding frequency on the spectrum analyzer and records the power value; A203. Keep the frequency unchanged and switch the attenuation value of the signal source to S=S0+ΔSdB until the attenuation value of the signal source is completed S=S max dB, and repeat A202 at each attenuation value to form a corresponding relationship between attenuation and power value at the current frequency; ΔS represents the attenuation step, S max Indicates the maximum attenuation value; A204. Switch to the next frequency point F = F1 + ΔFMHz, repeat step A203 until the frequency is F = F max , generating a three-dimensional table of frequency, attenuation and power values; where ΔF represents the frequency step, F max Indicates the maximum frequency value; A205. The finally generated three-dimensional table of frequency, attenuation and power values ​​is used as an initial configuration file and placed in the signal display control unit, and the configuration file is automatically loaded each time the system is started; A206. Use table lookup: After setting the output frequency and power of the signal source, first query whether the frequency is in the three-dimensional table through the frequency value: if the frequency value is in the table, determine whether the power value is present. If the power value is present, return the attenuation value; if the power value is not in the table, and the power value is less than the maximum power value at the frequency in the table and greater than the minimum power value at the frequency in the table, use linear fitting to calculate the attenuation value corresponding to the power value and return the attenuation value; The linear fitting calculation formula is Y=AX+B, where Y is the output power and X is the attenuation value. The power value between two points adjacent to Y in the table is used to calculate the values ​​of A and B, and then the values ​​are substituted into the formula Y=AX+B to obtain X=(YB) / A. If the frequency value is not found in the table, use the value closest to the frequency in the table as the lookup frequency value, and repeatedly determine whether there is a power value process under the lookup frequency value to obtain the attenuation value, which is transmitted to the FPGA control module of the large-bandwidth RF front-end unit, and the FPGA control module performs attenuation control.

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