A decision feedback equalizer (DFE), receiver, and chip

Abstract

This application discloses a Direct Feedback Filter (DFE) to solve the signal distortion problem caused by inter-symbol interference during high-speed signal data transmission. The DFE includes: a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D flip-flop, and a configuration circuit. The input terminal of the reference voltage generator is connected to the configuration circuit, and the output terminal of the reference voltage generator is connected to the first-stage feedback filter circuit. The first-stage feedback filter circuit is connected to the reference voltage generator, the second-stage feedback filter circuit, and the configuration circuit. The second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D flip-flop, and the configuration circuit. The D flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit. The configuration circuit is connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit, and the D flip-flop.

Description

Technical Field

[0001] This application relates to the field of semiconductor integrated circuit technology, and in particular to a decision feedback equalizer (DFE), receiver, and chip. Background Technology

[0002] Digital communication occurs between transmitting and receiving devices via an intermediate communication medium or "channel" (e.g., fiber optic cable or insulated copper wire). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects the symbol sequence and attempts to reconstruct the transmitted data. A "symbol" is a state or valid condition of the channel that lasts for a fixed period of time, called a "symbol interval." Symbols can be, for example, voltage or current levels, optical power levels, phase values, or specific frequencies or wavelengths. The change from one channel state to another is called a symbol transition. Each symbol can represent one or more bits of data, and thus data can be represented by symbol transitions or by sequences of two or more symbols.

[0003] However, channel non-ideals often cause each symbol to disrupt the dispersion of its neighboring symbols; this effect is known as inter-symbol interference (ISI). ISI can make it difficult for receiving equipment to determine which symbols were transmitted in each interval, especially when ISI is combined with additive noise. Due to the presence of ISI, inaccurate sampling results and signal distortion are easily caused.

[0004] Therefore, how to solve the signal distortion caused by inter-symbol interference during high-speed signal data transmission has become an urgent technical problem to be solved. Summary of the Invention

[0005] This application provides a decision feedback equalizer (DFE) to solve the signal distortion problem caused by inter-symbol interference during high-speed signal data transmission.

[0006] This application also provides a receiver to solve the problem of signal distortion caused by inter-symbol interference during high-speed signal data transmission.

[0007] This application also provides a chip to solve the signal distortion problem caused by inter-symbol interference during high-speed signal data transmission.

[0008] The embodiments of this application adopt the following technical solutions:

[0009] In a first aspect, a decision feedback equalizer (DFE) includes: a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D flip-flop, and a configuration circuit. The input terminal of the reference voltage generator is connected to the configuration circuit, and the output terminal of the reference voltage generator is connected to the first-stage feedback filter circuit. The reference voltage generator is used to provide reference voltages of different magnitudes to the first-stage feedback filter circuit according to a reference voltage control signal generated by the configuration circuit. The first-stage feedback filter circuit is connected to the reference voltage generator, the second-stage feedback filter circuit, and the configuration circuit, respectively, and is used to receive an input signal at time T sent by the configuration circuit and the reference voltage generated by the reference voltage generator, and determine the relationship between the input signal at time T and the reference voltage. The voltage difference is calculated and output to the second-stage signal comparator; the second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D flip-flop, and the configuration circuit respectively, for inputting different sampling delays, wherein the sampling delay represents the delay of the signal relative to the sampling clock; the D flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit, for sampling the output voltage of the second-stage feedback filter circuit according to the sampling control signal sent by the configuration circuit; the configuration circuit is connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit, and the D flip-flop respectively, for determining the two-dimensional signal eye diagram according to the input signal at time T, the reference voltage, and the output voltage.

[0010] Secondly, embodiments of this application provide a receiver that includes the decision feedback equalizer (DFE) described in the first aspect.

[0011] Thirdly, embodiments of this application provide a chip that includes the decision feedback equalizer (DFE) described in the first aspect.

[0012] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0013] The decision feedback equalizer (DFE) provided in this embodiment includes: a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D flip-flop, and a configuration circuit. The input terminal of the reference voltage generator is connected to the configuration circuit, and the output terminal of the reference voltage generator is connected to the first-stage feedback filter circuit. This allows the reference voltage generator to provide different reference voltages to the first-stage feedback filter circuit based on a reference voltage control signal generated by the configuration circuit. The first-stage feedback filter circuit is connected to the reference voltage generator, the second-stage feedback filter circuit, and the configuration circuit, respectively, and receives the input signal at time T sent by the configuration circuit and the reference voltage generated by the reference voltage generator. The voltage difference between the input signal and the reference voltage at time T is determined and output to the second-stage signal comparator. The second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D flip-flop, and the configuration circuit to input different sampling delays. The D flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit to sample the output voltage of the second-stage feedback filter circuit according to the sampling control signal sent by the configuration circuit. The configuration circuit is connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit, and the D flip-flop to determine the two-dimensional signal eye diagram based on the input signal, reference voltage, and output voltage at time T. The decision feedback equalizer (DFE) provided in this embodiment consists of two independently configurable circuits (comparator circuit and signal delay circuit). Through these two feedback filter circuits, the configuration of the signal sampling reference voltage and the signal delay relative to the sampling clock can be independently adjusted, thereby better eliminating inter-symbol interference from past signals to the current signal and improving the reliability of the sampled data. Secondly, since the first two stages of the feedback filter circuit are configured relatively independently, in actual working scenarios, the area of ​​the feedback filter circuit can be optimized by reducing the comparator circuit or the signal delay circuit, based on the signal sampling reference voltage and the degree of influence of inter-symbol interference on the signal slew rate. Attached Figure Description

[0014] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0015] Figure 1 This is a schematic diagram of a second-order decision feedback equalizer (DFE) in the prior art.

[0016] Figure 2 This is a schematic diagram of the signal waveform changes when performing inter-symbol interference cancellation based on an existing second-order decision feedback equalizer (DFE).

[0017] Figure 3 A schematic diagram of a two-dimensional signal eye diagram provided in an embodiment of this application;

[0018] Figure 4 A schematic diagram of a second-order decision feedback equalizer (DFE) provided in an embodiment of this application;

[0019] Figure 5 A simplified second-order decision feedback equalizer (DFE) is provided as an embodiment of this application.

[0020] Figure 6 A schematic diagram of a two-dimensional signal eye diagram provided in an embodiment of this application;

[0021] Figure 7 A schematic diagram of another simplified second-order decision feedback equalizer (DFE) provided in this application embodiment;

[0022] Figure 8 This is a schematic diagram of a two-dimensional signal eye diagram provided in an embodiment of this application. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0025] This application provides a decision feedback equalizer (DFE) to solve the signal distortion problem caused by inter-symbol interference during high-speed signal data transmission.

[0026] Currently, decision feedback equalizers (DFEs) are commonly used in the receiver module (RX) of I / O interfaces to eliminate inter-symbol interference, avoid signal distortion, and thus effectively improve the receiver performance. A common second-order decision feedback equalizer (DFE) structure is as follows: Figure 1As shown, the system mainly consists of a feedback filter and a decision unit. The feedback section of this second-order decision feedback equalizer (DFE) uses information from the two preceding symbols d1 / d2 of the currently determined symbol d0 to determine the value of the current symbol d0 by judging the output of the feedback filter. One simple way to understand the working principle of a decision feedback equalizer (DFE) is to adjust the reference voltage value to avoid sampling errors in the data receiving circuit. Since changes in external input data do not cause instantaneous changes in the level in the data receiving circuit (it takes time for the level change to translate into a data change), increasing the data transmission rate or the clock signal frequency will reduce the time required for the level change in the data receiving circuit. For example, when external input data transitions from "0" to "1", the time it takes for the level to change in the data receiving circuit decreases. Ideally, the level in the data receiving circuit should be pulled up to 0.8, but in reality, it can only be pulled up to 0.6. In this case, by lowering the reference voltage, the actual level of 0.6 is ensured to still be greater than the reference voltage, and the data receiving circuit can sample and acquire the high-level input data. As another example, when external input data transitions from "1" to "0", the time it takes for the level to change in the data receiving circuit decreases. Ideally, the level in the data receiving circuit should be pulled down to 0.1, but in reality, it can only be pulled down to 0.3. In this case, by increasing the reference voltage, the actual level of 0.3 is ensured to still be less than the reference voltage, and the data receiving circuit can sample and acquire the low-level input data.

[0027] Based on the above principles, in the time domain, a decision feedback equalizer (DFE) can sequentially reduce all subsequent effects of the current symbol based on the decision result, thereby minimizing or even completely eliminating the inter-symbol interference (ISI) of the current symbol. In circuit implementation, a DFE can be implemented using a digital high-frequency filter. For example, for continuous input data, input data sampled after a T-period delay is weighted, added to the current input data, and then output, thereby reducing or completely eliminating ISI of the input data.

[0028] To use Figure 1 Taking an existing second-order decision feedback equalizer (DFE) for inter-symbol interference (ISI) cancellation as an example, assuming data B0, B1, B2, and B3 are transmitted sequentially on the transmission line, the values ​​of B0 and B1 will affect the signal level of data B2 due to ISI. For example... Figure 2 The diagram shows the waveform changes on the signal line when B0 and B1 take values ​​of 11, 01, 00, and 10, respectively. Figure 2 The shaded area represents the eye diagram size at which B2 can be correctly sampled.

[0029] Based on the waveform changes on the signal line, it can be seen that a two-dimensional signal eye diagram corresponding to the B2 data can be obtained under different combinations of B0 and B1 values, such as... Figure 3 As shown, the center point of the two-dimensional signal eye diagram corresponds to the optimal sampling identification voltage and sampling clock delay configuration for the B2 data. Therefore, it can be seen that the optimal sampling configuration for the B2 data is influenced by the values ​​of B0 and B1.

[0030] Based on the above analysis, it can be seen that the embodiments of this application design a decision feedback equalizer (DFE), such as... Figure 4 As shown, based on this decision feedback equalizer (DFE), the values ​​of the sampling reference voltage and the signal delay relative to the sampling clock can be adjusted in the front-end feedback filter circuit. This allows for the adjustment of the X-axis (i.e., the signal delay relative to the sampling clock) and Y-axis (i.e., the comparator reference voltage) coordinates in the two-dimensional signal eye diagram, thereby ensuring that the sampling point of B2 data falls as close as possible to the center of the two-dimensional signal eye diagram, thus maximizing the reliability of the sampled data.

[0031] like Figure 4 As shown in the embodiments of this application, the decision feedback equalizer (DFE) mainly consists of the following parts: a reference voltage generator, a first-stage feedback filter circuit, a second-stage feedback filter circuit, a D flip-flop, and a configuration circuit.

[0032] The input terminal of the reference voltage generator is connected to the configuration circuit, and the output terminal of the reference voltage generator is connected to the first-stage feedback filter circuit. It is used to provide reference voltages Vref of different magnitudes to the first-stage feedback filter circuit according to the reference voltage control signal generated by the configuration circuit.

[0033] The first-stage feedback filter circuit is connected to the reference voltage generator, the second-stage feedback filter circuit, and the configuration circuit, respectively. Figure 4 As shown in the embodiment of this application, the first-stage feedback filter circuit consists of four comparator circuits, which are used to receive the input signal at time T sent by the configuration circuit (hereinafter referred to as d0 for ease of description) and the reference voltage generated by the reference voltage generator, determine the voltage difference between the input signal at time T and the reference voltage, and output the voltage difference to the second-stage signal comparator.

[0034] In one implementation, the four comparator circuits in the first-stage feedback filter circuit can be used to input different reference voltages for the four different values ​​of the feedback signal at time T-1 and the feedback signal at time T-2. For ease of description, the feedback signal at time T-1 will be referred to as the d1 feedback signal and the feedback signal at time T-2 will be referred to as the d2 feedback signal.

[0035] In one implementation, the d1 feedback signal and the d2 feedback signal correspond to four different values, which may include: 11, 01, 00, 10. Figure 4 Vref_dfe0~Vref_dfe3 represent the different reference voltages input to the comparator circuit sampling the d0 data when the d1 feedback signal and the d2 feedback signal are 11, 01, 00, and 10, respectively.

[0036] It should be noted that the first-stage feedback filter circuit consisting of four comparator circuits is only an example. In one implementation, the first-stage feedback filter circuit can consist of multiple comparator circuits, including: comparator circuits numbered in ascending order of natural numbers from the 0th to the Nth comparator circuit, where N≤3.

[0037] The second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D flip-flop, and the configuration circuit, respectively, as follows: Figure 4 As shown in the embodiment of this application, the second-stage feedback filter circuit consists of four signal delay circuits for inputting different sampling delays, wherein the sampling delay represents the delay of the signal relative to the sampling clock.

[0038] In one implementation, the four signal delay circuits in the second-stage feedback filter circuit can be used to input different sampling delays for the four different values ​​of the d1 feedback signal and the d2 feedback signal.

[0039] In one implementation, the d1 feedback signal and the d1 feedback signal corresponding to four different values ​​can include: 11, 01, 00, 10. Figure 4 In the table, Td_delay0~Td_delay3 represent the phase delay configuration of the d0 data relative to the clock when the d1 feedback signal and the d2 feedback signal are 11, 01, 00, and 10, respectively.

[0040] It should be noted that the second-stage feedback filter circuit consisting of four signal delay circuits is merely an example. In one implementation, the second-stage feedback filter circuit can consist of multiple signal delay circuits, including signal delay circuits numbered sequentially from the 0th to the Mth, where M≤3.

[0041] In this embodiment, a D flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit, and is used to sample the output voltage of the second-stage feedback filter circuit according to the sampling control signal sent by the configuration circuit. The D flip-flop in the decision feedback equalizer (DFE) mainly provides data synchronization, delay, feedback, and hold / block functions. For example, in the DFE, the D flip-flop can be used to store the output data of the slicer, which is a digital signal transmitted through the channel and quantized by the slicer. The D flip-flop can synchronously store this data under the control of a clock signal, ensuring that data processing in the DFE is synchronous. Furthermore, in the feedback path of the DFE circuit, the D flip-flop can provide a delay function to ensure that the feedback signal is time-aligned with the current signal. It should be noted that implementing the above functions in the decision feedback equalizer (DFE) using a D flip-flop is a common technique in the art; therefore, the specific working principle of the D flip-flop is not described in detail in this embodiment.

[0042] The configuration circuit is connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit, and the D flip-flop, respectively, to determine the two-dimensional signal eye diagram based on the input signal, reference voltage, and output voltage at time T.

[0043] In a decision feedback equalizer (DFE), the configuration circuit is mainly used to implement functions such as decision feedback, ISI correction, and adaptive adjustment of tap coefficients to improve the performance and quality of the received signal. For example, the configuration circuit can correct ISI through a forward path and a feedback path. The forward path may include a CTLE or other types of equalizer, while the feedback path estimates and cancels the ISI of the current signal based on the decoded signal. It should be noted that implementing the above functions in a decision feedback equalizer (DFE) using a configuration circuit is a common technique in this field; therefore, the specific working principle of the configuration circuit will not be described in detail in this embodiment.

[0044] Additionally, it's worth noting that decision feedback equalizers (DFEs) typically include a pulse amplitude detector (PAD). The PAD's primary function is to detect and quantize the amplitude of the input signal; it functions as a 1-bit analog-to-digital converter (ADC). In a DFE, the PAD is usually used to convert continuous analog signals into discrete digital signals for subsequent digital signal processing.

[0045] It's important to note that in practical scenarios, when the values ​​of feedback signals D1 and D2 are 10 and 00 respectively, the reference voltage values ​​of the comparator circuit are quite close. Similarly, when the values ​​of feedback signals D1 and D2 are 11 and 01 respectively, the reference voltage values ​​of the comparator circuit are also quite close. In these cases, when the values ​​of feedback signals D1 and D2 are 10 and 00, a single comparator circuit can be used to input the reference voltage; and when the values ​​of feedback signals D1 and D2 are 11 and 01 respectively, a single comparator circuit can be used to input the reference voltage, thus enabling the... Figure 4 The decision feedback equalizer (DFE) shown is simplified to... Figure 4 The four comparator circuits in the first-stage feedback filter circuit are reduced to two comparator circuits, resulting in: Figure 5 The first simplified decision feedback equalizer (DFE) is shown. Utilizing... Figure 5 The first simplified decision feedback equalizer (DFE) shown can select different delay paths by setting different permutations and combinations of the values ​​of the d1 and d2 feedback signals.

[0046] Specifically, using the first simplified decision feedback equalizer (DFE), when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are 10 and 00, they can share a common comparator circuit input reference voltage; while when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are 11 and 01, they can share a common comparator circuit input reference voltage.

[0047] Assuming that data B0, B1, B2, and B3 are transmitted sequentially on the transmission line as an example, in this embodiment of the application, the following method is used: Figure 5 The first simplified decision feedback equalizer (DFE) shown can produce a two-dimensional signal eye diagram corresponding to the B2 data under different combinations of B0 and B1 values, as shown below. Figure 6 As shown.

[0048] Additionally, it's important to note that in practical scenarios, when the values ​​of feedback signals D1 and D2 are 11 and 00, respectively, the impact on the slew rate of subsequent signals is significant. Therefore, a longer delay is needed at the optimal sampling clock point in this case. Conversely, when the values ​​of feedback signals D1 and D2 are 10 and 01, the impact on the slew rate of subsequent signals is relatively small, thus requiring a shorter delay at the optimal sampling clock point. In this situation, when the values ​​of feedback signals D1 and D2 are 11 and 00, a single signal delay circuit can be used to set the sampling delay; and when the values ​​of feedback signals D1 and D2 are 10 and 01, a single signal delay circuit can be used to set the sampling delay. This allows for the targeting of... Figure 5The first simplified decision feedback equalizer (DFE) shown is further simplified to... Figure 5 The four signal delay circuits in the first simplified decision feedback equalizer (DFE) shown are reduced to two signal delay circuits, resulting in the following: Figure 7 The second simplified decision feedback equalizer (DFE) is shown. Utilizing... Figure 7 The second simplified decision feedback equalizer (DFE) shown can select different delay paths by using the results of the operation of the d1 feedback signal and the d2 feedback signal (e.g., XOR calculation).

[0049] Specifically, using the second simplified decision feedback equalizer (DFE), when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are 11 and 00, they can share a single signal delay circuit for input sampling delay; while when the corresponding values ​​of the d1 feedback signal and the d2 feedback signal are 10 and 01, they can share a separate signal delay circuit for input sampling delay.

[0050] Assuming that data B0, B1, B2, and B3 are transmitted sequentially on the transmission line as an example, in this embodiment of the application, the following method is used: Figure 7 The first simplified decision feedback equalizer (DFE) shown can produce a two-dimensional signal eye diagram corresponding to the B2 data under different combinations of B0 and B1 values, as shown below. Figure 8 As shown.

[0051] The decision feedback equalizer (DFE) provided in this embodiment consists of two independently configurable stages of feedback filter circuitry (a comparator circuit and a signal delay circuit). These two stages allow for independent adjustment of the configuration of the signal sampling reference voltage and the signal delay relative to the sampling clock. This better eliminates inter-symbol interference (ISI) from past signals affecting the current signal, improving the reliability of the sampled data. Furthermore, because the first two stages of the feedback filter circuit are configured relatively independently, in practical applications, the area of ​​the feedback filter circuit can be optimized by reducing the comparator circuit or the signal delay circuit, based on the signal sampling reference voltage and the degree of ISI affecting the signal slew rate.

[0052] In one embodiment, this application also provides a receiver that includes the decision feedback equalizer (DFE) provided in any of the above embodiments, in order to solve the problem that the prior art second-order decision feedback equalizer (DFE) can only eliminate inter-symbol interference in a single dimension, thus leading to inaccurate sampling results and signal distortion.

[0053] In one embodiment, this application also provides a chip that includes the decision feedback equalizer provided in any of the above embodiments, in order to solve the problem that the prior art second-order decision feedback equalizer (DFE) can only eliminate inter-symbol interference in a single dimension, thus leading to inaccurate sampling results and signal distortion.

[0054] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0055] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0056] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Any modifications, equivalent substitutions, improvements, etc., made by those skilled in the art under the guidance of this application without departing from the spirit and scope of protection of the claims should be included within the scope of the claims of this application. Many other forms can also be made, all of which fall within the protection scope of this application.

Claims

1. A decision feedback equalizer (DFE), characterized in that, include: Reference voltage generator, first-stage feedback filter circuit, second-stage feedback filter circuit, D flip-flop, and configuration circuit; The input terminal of the reference voltage generator is connected to the configuration circuit, and the output terminal of the reference voltage generator is connected to the first-stage feedback filter circuit, for providing reference voltages of different magnitudes to the first-stage feedback filter circuit according to the reference voltage control signal generated by the configuration circuit; The first-stage feedback filter circuit is connected to the reference voltage generator, the second-stage feedback filter circuit, and the configuration circuit, respectively, and is used to receive the input signal at time T sent by the configuration circuit and the reference voltage generated by the reference voltage generator, determine the voltage difference between the input signal at time T and the reference voltage, and output the voltage difference to the second-stage signal comparator. The second-stage feedback filter circuit is connected to the first-stage feedback filter circuit, the D flip-flop, and the configuration circuit respectively, and is used to input different sampling delays, wherein the sampling delay represents the delay of the signal relative to the sampling clock; The D flip-flop is connected to the second-stage feedback filter circuit and the configuration circuit, and is used to sample the output voltage of the second-stage feedback filter circuit according to the sampling control signal sent by the configuration circuit; The configuration circuit is connected to the reference voltage generator, the first-stage feedback filter circuit, the second-stage feedback filter circuit, and the D flip-flop, respectively, and is used to determine a two-dimensional signal eye diagram based on the input signal at time T, the reference voltage, and the output voltage.

2. The decision feedback equalizer (DFE) according to claim 1, characterized in that, The first-stage feedback filter circuit consists of multiple comparator circuits, including: comparator circuits numbered in ascending order of natural numbers from the 0th to the Nth comparator circuit, where N≤3.

3. The decision feedback equalizer (DFE) according to claim 2, characterized in that, The first-stage feedback filter circuit consists of four comparator circuits, which are used to input different reference voltages for the four different values ​​of the feedback signal at time T-1 and time T-2.

4. The decision feedback equalizer (DFE) according to claim 3, characterized in that, The feedback signals at time T-1 and time T-2 correspond to four different values, including: 11, 01, 00, and 10.

5. The decision feedback equalizer (DFE) according to claim 2, characterized in that, The first-stage feedback filter circuit consists of two comparator circuits, which are used to input different reference voltages for the four different values ​​of the feedback signal at time T-1 and the feedback signal at time T-2, respectively. Wherein, when the feedback signal at time T-1 and the feedback signal at time T-2 have values ​​of 10 and 00 respectively, they share a common comparator circuit input reference voltage; When the feedback signal at time T-1 and the feedback signal at time T-2 have values ​​of 11 and 01 respectively, they share a common comparator circuit input reference voltage.

6. The decision feedback equalizer (DFE) according to claim 1, characterized in that, The second-stage feedback filter circuit consists of multiple signal delay circuits, including: the 0th comparator circuit to the Mth signal delay circuit numbered in ascending order of natural numbers, where M≤3.

7. The decision feedback equalizer (DFE) according to claim 6, characterized in that, The second-stage feedback filter circuit consists of four signal delay circuits, which are used to input different sampling delays for the feedback signal at time T-1 and the feedback signal at time T-2 corresponding to four different values. The feedback signal at time T-1 and the feedback signal at time T-2 correspond to four different values, including: 11, 01, 00, and 10.

8. The decision feedback equalizer (DFE) according to claim 6, characterized in that, The second-stage feedback filter circuit consists of two signal delay circuits, which are used to input different sampling delays for the four different values ​​of the feedback signal at time T-1 and time T-2, respectively. Wherein, the feedback signal at time T-1 and the feedback signal at time T-2 have corresponding values ​​of 11 and 00, respectively, and share a common signal delay circuit for input sampling delay; When the feedback signal at time T-1 and the feedback signal at time T-2 have values ​​of 10 and 01 respectively, they share a common signal delay circuit for input sampling delay.

9. A receiver, characterized in that, Includes the decision feedback equalizer (DFE) as described in any one of claims 1-8.

10. A chip, characterized in that, Includes the decision feedback equalizer (DFE) as described in any one of claims 1-8.

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