DC balanced digital audio and video signal serializer and deserializer based on FPGA

Abstract

The present invention relates to the technical field of serial deserializer design, and discloses a DC balanced digital audio and video signal serial deserializer based on FPGA, including a serializer, a deserializer, a control configuration module, a power management module, a configuration storage module and a timing control module; the serializer is used to convert parallel digital audio and video data into a high-speed serial data stream; the deserializer is used to detect and repair abnormal data in the high-speed serial data stream using machine learning technology, and convert the repaired high-speed serial data stream back into parallel digital audio and video data; the control configuration module is used to configure the working parameters of the serializer and the deserializer through an external interface; the timing control module is used to manage the timing relationship inside the system to ensure the synchronization of data flow between different modules. The present invention solves the shortcomings of traditional deserializers in abnormality detection and repair, signal quality evaluation and parameter optimization, and improves the stability and quality of high-resolution digital audio and video data transmission.

Description

Technical Field

[0001] The invention relates to the technical field of serial deserializer design, and in particular to a direct current balanced digital audio and video signal serial deserializer based on FPGA. Background Art

[0002] With the rapid development of high-resolution digital audio and video technology, the transmission rate and quality requirements of audio and video data are increasing. The popularity of high-resolution video content, such as 4K, 8K video and high-fidelity audio, requires data transmission with higher bandwidth and lower latency. Serial data transmission has become the mainstream data transmission method in digital audio and video systems due to its high transmission efficiency, strong anti-interference ability, and simple wiring. However, in practical applications, high-speed serial data transmission faces many technical challenges.

[0003] During high-speed transmission, data integrity and accuracy are easily damaged due to electromagnetic interference, transmission jitter, hardware delay and environmental factors in the link. Common problems include signal jitter, bit errors, frame loss and frame duplication. These problems not only affect the quality of transmitted data, but may also cause audio and video content to freeze and lose audio during decoding, seriously affecting the user experience. In addition, when serial data is restored to parallel data at the receiving end, the requirements for clock recovery, decoding accuracy and buffering strategy are extremely high. If you are not careful, it may cause signal synchronization errors and data frame alignment problems, further reducing system performance.

[0004] Existing technologies usually rely on traditional hardware circuits and fixed algorithms for data repair and signal quality assessment. Although these methods can solve some problems to a certain extent, they lack the ability to flexibly adapt to complex anomalies. Especially in high-speed serial data streams, abnormal situations are often diverse and dynamically changing, and traditional methods have limited repair and optimization capabilities. They are more effective for fixed-pattern anomalies, but when dealing with the comprehensive repair needs of multiple anomaly types (such as bit errors, frame loss, and duplicate frames), there are problems such as poor real-time performance and insufficient repair accuracy, which limits system performance.

[0005] Therefore, in order to solve the above problems, the present invention proposes a DC balanced digital audio and video signal serializer and deserializer based on FPGA. Summary of the invention

[0006] In view of the problems in the related art, the present invention proposes a DC balanced digital audio and video signal serial deserializer based on FPGA to overcome the above technical problems existing in the existing related art.

[0007] To this end, the specific technical solution adopted by the present invention is as follows:

[0008] A DC balanced digital audio and video signal serializer and deserializer based on FPGA, including a serializer, a deserializer, a control configuration module, a power management module, a configuration storage module and a timing control module;

[0009] Wherein, the serializer is used to convert parallel digital audio and video data into a high-speed serial data stream;

[0010] The deserializer is used to detect and repair abnormal data in the high-speed serial data stream using machine learning technology, and convert the repaired high-speed serial data stream back into parallel digital audio and video data;

[0011] The control configuration module is used to configure the working parameters of the serializer and the deserializer through the external interface;

[0012] The power management module is used to provide a stable power supply;

[0013] The configuration storage module is used to store the startup configuration file of the FPGA;

[0014] The timing control module is used to manage the timing relationship within the system and ensure the synchronization of data flow between different modules.

[0015] Preferably, the serializer includes a parallel data input module, a clock generation module, a data encoding module, a serialization module and a serial data output module;

[0016] The parallel data input module is used to receive parallel audio and video data from the outside and perform formatting processing;

[0017] The clock generation module is used to generate multi-frequency clock signals required by the system, including parallel input data clock, encoding clock and serial output clock;

[0018] The data encoding module is used to encode the input parallel data;

[0019] The serialization module is used to convert the encoded parallel data into a high-speed serial data stream;

[0020] The serial data output module is used to output a serialized high-speed data stream and drive the signal to an external link.

[0021] Preferably, the deserializer includes a serial data receiving module, a repair adjustment module, a clock data recovery module, a data decoding module, a data deserialization module, a first-in-first-out buffer module and a parallel data output module;

[0022] The serial data receiving module is used to receive the serial data stream from the high-speed transmission link and complete the preliminary level conversion and differential signal reception;

[0023] The repair and adjustment module is used to predict the abnormal situation of the serial data stream based on machine learning technology and repair the abnormal data, and is also used to monitor and evaluate the quality of the received signal and dynamically adjust the deserializer parameters according to the evaluation results;

[0024] The clock data recovery module is used to extract the embedded clock signal from the repaired serial data stream according to the adjusted clock recovery parameters;

[0025] The data decoding module is used to decode the repaired serial data according to the adjusted decoding parameters;

[0026] The data deserialization module is used to convert the decoded high-speed serial data into a parallel data stream according to the adjusted deserialization parameters;

[0027] The first-in-first-out buffer module is used to buffer data according to the adjusted buffer strategy;

[0028] The parallel data output module is used to output the ultimately restored parallel audio and video data.

[0029] Preferably, the repair and adjustment module includes a data prediction and repair module and a quality assessment and adjustment module;

[0030] The data prediction and repair module is used to predict and repair abnormal data of the received serial data stream using machine learning technology based on historical traffic and frame sequence numbers;

[0031] The quality evaluation and adjustment module is used to monitor and evaluate the signal quality of the repaired serial data stream and dynamically adjust the deserializer parameters according to the evaluation results.

[0032] Preferably, the data prediction and repair module includes:

[0033] Obtain the characteristics of the serial data stream in the historical data, mark the abnormal parts and abnormal types in the historical data, the characteristics of the serial data stream include flow rate, data frame sequence number and inter-frame interval; construct a training set, and use the training set to train the random forest model and the long short-term memory network model respectively;

[0034] Acquire the real-time serial data stream features, perform noise filtering and feature extraction, and obtain an input feature set including frame number increment sequence, flow rate change, and frame check result; use the trained random forest model to identify the input feature set and obtain the abnormal type and abnormal range of the real-time serial data stream features;

[0035] Based on the trained long short-term memory network model, combined with the abnormal type and abnormal range of the real-time serial data stream characteristics, the abnormal data can be repaired for frame loss, duplicate frames and bit errors.

[0036] Preferably, using the trained long short-term memory network model to repair frame loss of abnormal data includes:

[0037] Obtain the frame number, inter-frame time interval, frame load data, frame loss type and abnormal range output by the classification model of the real-time serial data stream;

[0038] Select the windowed feature sequence before and after the frame loss, and perform normalization processing to form the time series input of the long short-term memory network model, where the windowed feature sequence includes frame number, time interval and load data;

[0039] The trained LSTM network model is used in combination with the time series input to predict the lost frame number within the abnormal range. The payload data of the lost frame is generated based on the LSTM network model and combined with the context features.

[0040] The predicted lost frame sequence number and load data are inserted into the original data stream to form a continuous repair data stream, and the repaired frame is subjected to data consistency check; based on the check result, the repaired complete serial data stream is output.

[0041] Preferably, using the trained long short-term memory network model to repair duplicate frames of abnormal data includes:

[0042] Obtain the frame number, inter-frame time interval, frame load data, repeated frame type and abnormal range output by the classification model of the real-time serial data stream;

[0043] Extract the windowed feature sequence before and after the repeated frame and perform normalization processing, wherein the windowed feature sequence includes frame number, time interval and load data;

[0044] Analyze the frame features within the abnormal range using the long short-term memory network model to confirm the location of redundant repeated frames; delete redundant repeated frames based on the analysis results, and adjust the inter-frame time interval and frame load data after repair based on the timing prediction of the long short-term memory network model;

[0045] Verify the frame number continuity and load consistency of the repaired data stream, verify the matching of the time interval with the normal mode, and output the repaired data stream based on the verification results to ensure that the frame number is unique and the data is complete.

[0046] Preferably, using the trained long short-term memory network model to perform error correction on abnormal data includes:

[0047] Obtain the frame sequence number, frame load data, frame check result, error type and abnormal range output by the classification model of the real-time serial data stream;

[0048] Extracting windowed feature sequences before and after the bit error frame and performing normalization processing, wherein the windowed feature sequence includes the frame sequence number, load context, and time interval;

[0049] The context features are input by the LSTM model to predict the correct payload content of the frames within the abnormal range; the payload data of the abnormal frames are replaced with the repair content predicted by the LSTM model, and the frame sequence number, frame header, and frame tail structure are kept unchanged;

[0050] Regenerate the checksum of the repair frame and perform consistency check to check the integrity and context consistency of the repair frame, and output the repaired data stream based on the check result to ensure that the load data is accurate and meets the protocol requirements.

[0051] Preferably, the quality assessment and adjustment module includes a signal quality detection module, a signal quality assessment module, a clock recovery parameter adjustment module, a decoding parameter adjustment module, a deserialization parameter adjustment module, a buffer strategy adjustment module and an optimization result output module;

[0052] The signal quality detection module is used to monitor the repaired serial data stream in real time and extract signal quality indicators, including bit error rate, frame loss rate, signal jitter, verification pass rate, frame sequence number continuity and data stream integrity;

[0053] The signal quality assessment module is used to generate a signal quality assessment result according to the signal quality indicator data to obtain a signal health score;

[0054] The clock recovery parameter adjustment module is used to dynamically adjust the clock recovery parameters according to the signal health score;

[0055] The decoding parameter adjustment module is used to dynamically adjust decoding related parameters according to the signal health score;

[0056] The deserialization parameter adjustment module is used to dynamically adjust the deserialization parameters according to the signal health score;

[0057] The buffer strategy adjustment module is used to dynamically adjust the buffer strategy according to the signal health score;

[0058] The optimization result output module is used to output the adjusted clock recovery parameters, decoding parameters, deserialization parameters and buffering strategy.

[0059] Preferably, the expression for signal quality evaluation is:

[0060] ;

[0061] In the formula, represents the signal health score, B represents the bit error rate, F represents the frame loss rate, J Indicates signal jitter, J max Indicates the maximum tolerable value of signal jitter. , , They represent the weight coefficients of bit error rate, frame loss rate and signal jitter respectively.

[0062] Compared with the prior art, the present invention provides a DC balanced digital audio and video signal serializer and deserializer based on FPGA, which has the following beneficial effects:

[0063] (1) The present invention can achieve accurate anomaly detection and repair, real-time signal quality evaluation and dynamic parameter optimization by introducing machine learning technology and dynamic parameter adjustment mechanism, successfully solving the shortcomings of traditional deserializers in anomaly detection and repair, signal quality evaluation and parameter optimization, significantly improving the stability and quality of high-resolution digital audio and video data transmission, enhancing the flexibility and adaptability of the system, and providing a reliable solution for modern audio and video systems.

[0064] (2) The present invention combines the random forest model with the long short-term memory (LSTM) model to accurately detect and repair various anomalies in serial data streams. The random forest model classifies real-time data streams through feature extraction and can quickly identify the types and ranges of anomalies such as bit errors, frame loss and duplicate frames. The LSTM model uses its ability to learn time series features to predict and repair abnormal data, ensuring that the repaired data has high continuity and consistency.

[0065] (3) The present invention introduces a dynamic signal quality evaluation and parameter optimization mechanism. By real-time monitoring of data stream quality indicators (such as bit error rate, jitter, frame loss rate, etc.) and combining the health scoring formula, the parameters of key modules can be dynamically adjusted according to the evaluation results, including clock recovery parameters, decoding strategy, deserialization logic and buffer strategy. This dynamic optimization mechanism significantly improves the system's adaptability to signal fluctuations and link anomalies, ensuring the stability and accuracy of data transmission.

[0066] (4) The clock recovery parameter adjustment module of the present invention can dynamically optimize the clock sampling frequency and phase lock according to the signal health score to reduce the impact of jitter on data transmission. The decoding parameter adjustment module can switch the decoding mode (such as switching from hard decoding to soft decoding) according to the change of the bit error rate to enhance the error correction capability. The deserialization parameter adjustment module can ensure the correct alignment of the data frame by dynamically adjusting the frame synchronization and segmentation step size. The buffer strategy adjustment module can dynamically adjust the buffer size and read-write strategy according to the flow change to smooth the flow fluctuation and reduce the delay.

[0067] (5) The dynamic adjustment mechanism of the present invention not only improves the robustness of the system, but also enhances its adaptability in complex environments. Through modular design, each part of the system can be independently developed and optimized, which improves the flexibility and scalability of the system. The configuration storage module supports fast reconfiguration to meet the needs of different application scenarios. The timing control module ensures the synchronization of data flow between modules within the system, avoiding problems caused by timing mismatch. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0069] Figure 1 The present invention is a structural block diagram of a DC balanced digital audio and video signal serial deserializer based on FPGA according to an embodiment of the present invention.

[0070] In the figure:

[0071] 1. Serializer; 2. Deserializer; 3. Control configuration module; 4. Power management module; 5. Configuration storage module; 6. Timing control module. DETAILED DESCRIPTION

[0072] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0073] According to an embodiment of the present invention, a DC balanced digital audio and video signal serializer and deserializer based on FPGA is provided.

[0074] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1As shown, according to one embodiment of the present invention, a DC balanced digital audio and video signal serial deserializer based on FPGA is provided, including a serializer 1, a deserializer 2, a control configuration module 3, a power management module 4, a configuration storage module 5, and a timing control module 6;

[0075] Wherein, the serializer 1 is used to convert parallel digital audio and video data into a high-speed serial data stream;

[0076] Specifically, the serializer 1 includes a parallel data input module, a clock generation module, a data encoding module, a serialization module and a serial data output module;

[0077] The parallel data input module is used to receive parallel audio and video data from the outside and perform formatting processing;

[0078] The clock generation module is used to generate multi-frequency clock signals required by the system, including parallel input data clock, encoding clock and serial output clock; the implementation method usually adopts a phase-locked loop (PLL) or a phase-locked loop circuit to provide a clock signal with high stability and low jitter;

[0079] The data encoding module is used to encode the input parallel data (such as 8b / 10b, 64b / 66b, etc.) to ensure the DC balance of the signal and reduce the bit error rate in transmission;

[0080] The serialization module is used to convert the encoded parallel data into a high-speed serial data stream, which is implemented by using a high-speed serial transceiver (such as SERDES) inside the FPGA or a custom serialization logic;

[0081] The serial data output module is used to output a serialized high-speed data stream and drive the signal to an external link;

[0082] The deserializer 2 is used to detect and repair abnormal data in the high-speed serial data stream using machine learning technology, and convert the repaired high-speed serial data stream back into parallel digital audio and video data;

[0083] Specifically, the deserializer 2 includes a serial data receiving module, a repair adjustment module, a clock data recovery module, a data decoding module, a data deserialization module, a first-in-first-out buffer module and a parallel data output module;

[0084] The serial data receiving module is used to receive the serial data stream from the high-speed transmission link and complete the preliminary level conversion and differential signal reception;

[0085] The repair and adjustment module is used to predict the abnormal situation of the serial data stream based on machine learning technology and repair the abnormal data, and is also used to monitor and evaluate the quality of the received signal and dynamically adjust the deserializer parameters according to the evaluation results;

[0086] The repair and adjustment module includes a data prediction and repair module and a quality assessment and adjustment module;

[0087] The data prediction and repair module is used to predict and repair abnormal data of the received serial data stream using machine learning technology based on historical traffic and frame sequence numbers;

[0088] Specifically, the data prediction and repair module includes:

[0089] Obtain the characteristics of the serial data stream in the historical data, and mark the abnormal parts and abnormal types (such as frame loss, duplicate frames, bit errors, etc.) in the historical data through rule detection or expert labeling. The characteristics of the serial data stream include flow rate, data frame sequence number and inter-frame interval, etc.;

[0090] Extract time series features (including the increment mode of frame numbers and the time interval between data frames), statistical features (including traffic statistics per second, such as the number of frames, data packet size, frame number jumps, and repetition patterns), bit error information (including the detected bit error location, CRC check results, etc.) and frame content features (including frame header and frame tail data structure, frame load mode), and construct a training set. Use the training set to train the random forest model and the long short-term memory network model respectively.

[0091] Acquire real-time serial data stream features, perform noise filtering (remove invalid frames, such as frames with insufficient power levels or error flags) and feature extraction (extract frame number increments, such as the difference between adjacent frame numbers, and calculate traffic features, such as frame rate and interval distribution), and obtain an input feature set that includes frame number increment sequences, traffic rate changes, and frame check results; use the trained random forest model to identify the input feature set and obtain the abnormal type and range of the real-time serial data stream features;

[0092] Based on the trained long short-term memory network model, combined with the abnormal type and range of the real-time serial data stream characteristics, the abnormal data is repaired for frame loss, duplicate frames and bit errors;

[0093] Using the trained long short-term memory network model to repair abnormal data frame loss includes:

[0094] Obtain the frame number, inter-frame time interval, frame load data, frame loss type and abnormal range output by the classification model of the real-time serial data stream;

[0095] Select the windowed feature sequence before and after the frame loss, and perform normalization processing to form the time series input of the long short-term memory network model, where the windowed feature sequence includes frame number, time interval and load data;

[0096] The trained LSTM network model is used in combination with the time series input to predict the lost frame number within the abnormal range. The payload data of the lost frame is generated based on the LSTM network model and combined with the context features.

[0097] Insert the predicted lost frame sequence number and payload data into the original data stream to form a continuous repair data stream, and perform data consistency check on the repaired frames; based on the check results, output the repaired complete serial data stream;

[0098] Using the trained long short-term memory network model to repair the abnormal data duplicate frames includes:

[0099] Obtain the frame number, inter-frame time interval, frame load data, repeated frame type and abnormal range output by the classification model of the real-time serial data stream;

[0100] Extracting the windowed feature sequence before and after the repeated frames and performing normalization processing, wherein the windowed feature sequence includes the frame number, time interval and load data;

[0101] Analyze the frame features within the abnormal range using the long short-term memory network model to confirm the location of redundant repeated frames; delete redundant repeated frames based on the analysis results, and adjust the inter-frame time interval and frame load data after repair based on the timing prediction of the long short-term memory network model;

[0102] Verify the continuity of the frame sequence number and the load consistency of the repaired data stream, verify the matching of the time interval with the normal mode, and output the repaired data stream based on the verification results to ensure that the frame sequence number is unique and the data is complete;

[0103] Using the trained long short-term memory network model to repair abnormal data errors includes:

[0104] Obtain the frame number, frame load data, frame check result, error type and abnormal range output by the classification model of the real-time serial data stream;

[0105] Extracting windowed feature sequences before and after the bit error frame and performing normalization processing, wherein the windowed feature sequence includes the frame sequence number, load context, and time interval;

[0106] The context features are input by the LSTM model to predict the correct payload content of the frames within the abnormal range; the payload data of the abnormal frames are replaced with the repair content predicted by the LSTM model, and the frame sequence number, frame header, and frame tail structure are kept unchanged;

[0107] Regenerate the checksum of the repair frame and perform consistency check to check the integrity and context consistency of the repair frame. Output the repaired data stream based on the check result to ensure that the payload data is accurate and meets the protocol requirements.

[0108] The quality assessment and adjustment module is used to monitor and assess the signal quality of the repaired serial data stream and dynamically adjust the deserializer parameters according to the assessment results;

[0109] Specifically, the quality assessment and adjustment module includes a signal quality detection module, a signal quality assessment module, a clock recovery parameter adjustment module, a decoding parameter adjustment module, a deserialization parameter adjustment module, a buffer strategy adjustment module and an optimization result output module;

[0110] The signal quality detection module is used to monitor the repaired serial data stream in real time and extract signal quality indicators, including bit error rate, frame loss rate, signal jitter, verification pass rate, frame sequence number continuity and data stream integrity;

[0111] The signal quality assessment module is used to generate a signal quality assessment result according to the signal quality indicator data to obtain a signal health score;

[0112] The expression for signal quality evaluation is:

[0113] ;

[0114] In the formula, represents the signal health score, B represents the bit error rate, F represents the frame loss rate, J Indicates signal jitter, J max Indicates the maximum tolerable value of signal jitter. , , Respectively represent the weight coefficients of bit error rate, frame loss rate and signal jitter;

[0115] The clock recovery parameter adjustment module is used to dynamically adjust the clock recovery parameters according to the signal health score. The clock recovery parameter adjustment specifically includes:

[0116] 1) When the signal health score is greater than a preset high signal quality threshold (preferably 0.9 in this embodiment), the clock recovery parameters maintain the current settings and do not need to be adjusted;

[0117] 2) When the signal health score is between the medium signal quality threshold (preferably 0.7 in this embodiment) and the high signal quality threshold, the clock sampling frequency or phase is fine-tuned to increase the anti-jitter mechanism (for example, increasing the bandwidth of the phase-locked loop filter);

[0118] 3) When the signal health score is less than or equal to the medium signal quality threshold, the frequency adjustment range of the phase-locked loop is increased, and the phase alignment algorithm of the clock and data is enhanced. If the jitter is obviously too high, the clock recovery module is triggered to be reinitialized;

[0119] The decoding parameter adjustment module is used to dynamically adjust decoding related parameters according to the signal health score. The decoding parameter adjustment specifically includes:

[0120] 1) When the signal health score is greater than a preset high signal quality threshold (preferably 0.9 in this embodiment), the current decoding mode (such as hard decoding) is used;

[0121] 2) When the signal health score is between the medium signal quality threshold (preferably 0.7 in this embodiment) and the high signal quality threshold, the mode is switched to soft decoding to improve the error correction capability for weak signals and the checksum table is adjusted according to the bit error rate (e.g., stronger error correction coding);

[0122] 3) When the signal health score is less than or equal to the medium signal quality threshold, the decoding rate is reduced, the decoding quality is improved, the error correction capability of the decoder is enhanced (such as using a stronger redundancy check code), and the signal demodulation parameters are recalibrated;

[0123] The deserialization parameter adjustment module is used to dynamically adjust the deserialization parameters according to the signal health score. The deserialization parameter adjustment specifically includes:

[0124] 1) When the signal health score is greater than the preset high signal quality threshold, the current deserialization logic and parameters are maintained;

[0125] 2) When the signal health score is between the medium signal quality threshold and the high signal quality threshold, the starting point and step size of the serial segmentation are fine-tuned according to the continuity of the frame sequence number, and the frame alignment deviation is detected and repaired;

[0126] 3) When the signal health score is less than or equal to the medium signal quality threshold, the deserialization redundant buffer is increased to ensure frame integrity. In case of traffic interruption or error, the deserialization module is triggered to be reinitialized, and the frame segmentation boundary is relocated based on the bit error position;

[0127] The buffer strategy adjustment module is used to dynamically adjust the buffer strategy according to the signal health score. The buffer strategy adjustment specifically includes:

[0128] 1) When the signal health score is greater than the preset high signal quality threshold, the buffer strategy maintains the current setting and the buffer size can be appropriately reduced to reduce latency;

[0129] 2) When the signal health score is between the medium signal quality threshold and the high signal quality threshold, the buffer size is dynamically adjusted to adapt to traffic fluctuations, optimizing the read and write priority of the buffer to ensure the smoothness of high-priority data;

[0130] 3) When the signal health score is less than or equal to the medium signal quality threshold, the buffer is increased to prevent data loss, and a traffic smoothing mechanism is introduced to reduce the pressure caused by traffic bursts. If the traffic is obviously abnormal, the buffer resources are reallocated;

[0131] The optimization result output module is used to output the adjusted clock recovery parameters, decoding parameters, deserialization parameters and buffering strategy;

[0132] The clock data recovery module is used to extract the embedded clock signal from the repaired serial data stream according to the adjusted clock recovery parameters, which is implemented by using a phase-locked loop (PLL) or a delay-locked loop (DLL) combined with an adaptive filter to improve clock stability;

[0133] The data decoding module is used to decode the repaired serial data according to the adjusted decoding parameters;

[0134] The data deserialization module is used to convert the decoded high-speed serial data into a parallel data stream according to the adjusted deserialization parameters;

[0135] The first-in-first-out buffer module is used to buffer data according to the adjusted buffer strategy;

[0136] The parallel data output module is used to output the finally restored parallel audio and video data;

[0137] The control configuration module 3 is used to configure the working parameters of the serializer and the deserializer through the external interface;

[0138] Specifically, the configuration of the serializer and deserializer operating parameters includes:

[0139] 1) Serializer parameter configuration:

[0140] Data serialization mode selection (such as the parallel-to-serial conversion rate);

[0141] Serial data frame format settings (such as frame header, frame trailer and frame interval);

[0142] Data packing strategy (e.g. batch size);

[0143] 2) Deserializer parameter configuration:

[0144] Set the deserialization segmentation step size and starting point to ensure matching with the serializer;

[0145] Data frame alignment strategy adjustment (such as synchronization frame identification);

[0146] Parameter adjustment of the buffering mechanism (such as buffer size and flushing strategy);

[0147] 3) Clock synchronization parameter configuration:

[0148] The clock synchronization mode of the serializer and deserializer (such as synchronous or asynchronous);

[0149] Clock recovery parameters (such as phase adjustment and frequency adjustment range);

[0150] 4) Coding and verification parameter configuration:

[0151] Data encoding mode setting (such as Manchester encoding, NRZ, etc.);

[0152] Verification parameter settings (such as CRC verification length and generator polynomial);

[0153] 5) Real-time adjustment support:

[0154] Allows dynamic adjustment of operating parameters through external interfaces to adapt to real-time signal changes or optimize performance;

[0155] The power management module 4 is used to provide a stable power supply to ensure the reliable operation of the serializer, deserializer and related modules, and specifically includes:

[0156] 1) Power conversion and distribution: convert the input power (such as AC or DC) into the required voltage levels (such as 1.2V, 3.3V, 5V), and distribute the appropriate power output according to the requirements of each module;

[0157] 2) Voltage stabilization function: Use a voltage stabilizer (such as LDO or switching regulator) to ensure the stability of the output voltage and suppress the impact of input power fluctuations on the system;

[0158] 3) Power supply monitoring: Real-time monitoring of power supply voltage, current and temperature status to ensure operation within a safe range, detect overvoltage, undervoltage or overcurrent conditions, and trigger protection mechanisms;

[0159] 4) Power protection: It has short circuit protection, over-current protection and over-temperature protection functions. In abnormal situations, it automatically cuts off the power output and notifies the control module;

[0160] 5) Low power management: Dynamically adjust the power supply to reduce energy consumption according to the system operation status, and support the module's sleep or standby mode power supply;

[0161] 6) Redundancy support: Provide backup power input interface or battery backup function to ensure the continuous operation of key systems when the main power fails;

[0162] 7) Interface support: Provide external control interface, support power supply parameter configuration and status query;

[0163] Through the above functions, the power management module ensures the reliability and stability of the entire system under various working conditions;

[0164] The configuration storage module 5 is used to store the startup configuration file of the FPGA to ensure that the FPGA can correctly load the configuration when the system is started and running. The specific functions include:

[0165] 1) Startup configuration file storage: saves the binary configuration file (such as bitstream file .bit or .bin) required for FPGA startup; supports the storage and selection of multiple versions of configuration files to facilitate version switching or updating;

[0166] 2) Non-volatile storage: Use non-volatile storage media (such as EEPROM, Flash, or SD card) to ensure that configuration files are not lost after power failure, and support high-reliability write and read operations;

[0167] 3) Configuration file loading: Automatically load the specified FPGA configuration file when the system is powered on or reset, and support triggering the reloading of the configuration file through the external control interface;

[0168] 4) File management: Provides file verification functions (such as CRC verification) to ensure the integrity of configuration files, and supports erase, write, and update operations on storage areas;

[0169] 5) Compatibility support: supports configuration file formats of multiple FPGA manufacturers and models, allowing FPGA configuration files to be updated through external interfaces to adapt to hardware upgrade requirements;

[0170] 6) Security protection: Provides encrypted storage and access control of configuration files to prevent unauthorized modification and reading, supports anti-tampering detection, and ensures that the loaded configuration files are credible;

[0171] 7) Status monitoring and feedback: monitor the operating status of the storage module, including storage space usage, read / write speed, and provide status feedback of configuration loading success or failure to the control module;

[0172] Through the above functions, the configuration storage module ensures the safe, efficient and reliable loading of FPGA startup configuration files, meeting the system's needs for flexibility and upgrades;

[0173] The timing control module 6 is used to manage the timing relationship within the system and ensure the synchronization of data flow between different modules. The specific functions include:

[0174] 1) Clock generation and distribution: Provide a unified reference clock signal for the system, which is used for timing synchronization of each module, and distribute clock signals of different frequencies and phases according to module requirements;

[0175] 2) Synchronous signal management: Generate and distribute synchronous signals to coordinate the operation timing of serializers, deserializers and other modules to ensure that all modules can work together in a unified clock domain during data flow;

[0176] 3) Multi-clock domain coordination: manage the timing relationship between multiple clock domains, prevent data desynchronization problems when clock domains interact, and provide a secure data transmission mechanism across clock domains (such as handshake protocols or synchronous FIFOs);

[0177] 4) Data flow timing control: manage the data flow order between modules to prevent data loss or duplication, dynamically adjust the processing order of data flow according to priority, and ensure the real-time performance of key data;

[0178] 5) Jitter and delay compensation: Detect clock jitter and signal delay inside the system and perform dynamic compensation to ensure timing stability and provide clock offset adjustment function to adapt to the delay requirements of different modules;

[0179] 6) Event triggering and time stamping: Supports timing-based event triggering mechanisms (such as timed interrupts or periodic tasks) to add timestamps to key frames or data packets in the data stream for subsequent processing and debugging;

[0180] 7) Real-time monitoring and feedback: Real-time monitoring of the timing status within the system, including clock accuracy, jitter amplitude and delay parameters, providing timing adjustment status feedback, and assisting the control module in optimizing synchronization performance;

[0181] Through the above functions, the timing control module ensures the efficient coordination of various modules within the system, maintains the accuracy and real-time nature of data flow, and thus improves the reliability and performance of the overall system.

[0182] To sum up, with the help of the above-mentioned technical scheme of the present invention, the present invention can realize accurate anomaly detection and repair, real-time signal quality evaluation and dynamic parameter optimization by introducing machine learning technology and dynamic parameter adjustment mechanism, successfully solves the shortcomings of traditional deserializers in anomaly detection and repair, signal quality evaluation and parameter optimization, significantly improves the stability and quality of high-resolution digital audio and video data transmission, enhances the flexibility and adaptability of the system, and provides a reliable solution for modern audio and video systems.

[0183] In addition, by combining the random forest model and the long short-term memory network (LSTM) model, the present invention can accurately detect and repair various anomalies in serial data streams. The random forest model classifies real-time data streams through feature extraction, and can quickly identify the types and ranges of anomalies such as bit errors, frame loss and duplicate frames. The LSTM model uses its ability to learn timing features to predict and repair abnormal data, ensuring that the repaired data has high continuity and consistency.

[0184] In addition, the present invention introduces a dynamic signal quality evaluation and parameter optimization mechanism. By real-time monitoring of data flow quality indicators (such as bit error rate, jitter, frame loss rate, etc.) and combining the health scoring formula, it can dynamically adjust the parameters of key modules according to the evaluation results, including clock recovery parameters, decoding strategy, deserialization logic and buffering strategy, etc. This dynamic optimization mechanism significantly improves the system's adaptability to signal fluctuations and link anomalies, ensuring the stability and accuracy of data transmission.

[0185] In addition, the clock recovery parameter adjustment module of the present invention can dynamically optimize the clock sampling frequency and phase lock according to the signal health score to reduce the impact of jitter on data transmission. The decoding parameter adjustment module can switch the decoding mode (such as switching from hard decoding to soft decoding) according to the change of the bit error rate to enhance the error correction capability. The deserialization parameter adjustment module ensures the correct alignment of data frames by dynamically adjusting the frame synchronization and segmentation step size. The buffer strategy adjustment module dynamically adjusts the buffer size and read-write strategy according to the flow change to smooth out the flow fluctuation and reduce the delay.

[0186] In addition, the dynamic adjustment mechanism of the present invention not only improves the robustness of the system, but also enhances its adaptability in complex environments. Through modular design, each part of the system can be independently developed and optimized, which improves the flexibility and scalability of the system. The configuration storage module supports rapid reconfiguration to meet the needs of different application scenarios. The timing control module ensures the synchronization of data flow between modules within the system, avoiding problems caused by timing mismatch.

[0187] The technical features of the above-mentioned embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification. A person of ordinary skill in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes the steps described in the above method, and the storage medium, such as ROM / RAM, a disk, an optical disk, etc.

[0188] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A DC balanced digital audio and video signal serializer / deserializer based on FPGA, characterized in that: It includes a serializer (1), a deserializer (2), a control configuration module (3), a power management module (4), a configuration storage module (5) and a timing control module (6); The serializer (1) is used to convert parallel digital audio and video data into a high-speed serial data stream; A deserializer (2), configured to detect and repair abnormal data in the high-speed serial data stream using machine learning technology, and convert the repaired high-speed serial data stream back into parallel digital audio and video data; The deserializer (2) includes a repair and adjustment module, and the repair and adjustment module includes: The data prediction and repair module is used to predict and repair abnormal data of the received serial data stream based on historical traffic and frame sequence numbers using machine learning technology, including: Obtain the characteristics of the serial data stream in the historical data, mark the abnormal parts and abnormal types in the historical data, the characteristics of the serial data stream include flow rate, data frame sequence number and inter-frame interval; construct a training set, and use the training set to train the random forest model and the long short-term memory network model respectively; Acquire the real-time serial data stream features, perform noise filtering and feature extraction, and obtain an input feature set including frame number increment sequence, flow rate change, and frame check result; use the trained random forest model to identify the input feature set and obtain the abnormal type and abnormal range of the real-time serial data stream features; Based on the trained long short-term memory network model, combined with the abnormal type and range of the real-time serial data stream characteristics, the abnormal data is repaired for frame loss, duplicate frames and bit errors; The quality assessment and adjustment module is used to monitor and assess the signal quality of the repaired serial data stream and dynamically adjust the deserializer parameters according to the assessment results.

2. The FPGA-based DC balanced digital audio and video signal serializer and deserializer according to claim 1, characterized in that: The serializer (1) comprises a parallel data input module, a clock generation module, a data encoding module, a serialization module and a serial data output module; The parallel data input module is used to receive parallel audio and video data from the outside and perform formatting processing; The clock generation module is used to generate multi-frequency clock signals required by the system, including parallel input data clock, encoding clock and serial output clock; The data encoding module is used to encode the input parallel data; The serialization module is used to convert the encoded parallel data into a high-speed serial data stream; The serial data output module is used to output a serialized high-speed data stream and drive the signal to an external link.

3. The FPGA-based DC balanced digital audio and video signal serializer and deserializer according to claim 1, characterized in that: The deserializer (2) further comprises a serial data receiving module, a clock data recovery module, a data decoding module, a data deserialization module, a first-in-first-out buffer module and a parallel data output module; The serial data receiving module is used to receive the serial data stream from the high-speed transmission link and complete the preliminary level conversion and differential signal reception; The clock data recovery module is used to extract the embedded clock signal from the repaired serial data stream according to the adjusted clock recovery parameters; The data decoding module is used to decode the repaired serial data according to the adjusted decoding parameters; The data deserialization module is used to convert the decoded high-speed serial data into a parallel data stream according to the adjusted deserialization parameters; The first-in-first-out buffer module is used to buffer data according to the adjusted buffer strategy; The parallel data output module is used to output the ultimately restored parallel audio and video data.

4. The FPGA-based DC balanced digital audio and video signal serializer and deserializer according to claim 1, characterized in that: Using the trained long short-term memory network model to repair abnormal data frame loss includes: Obtain the frame number, inter-frame time interval, frame load data, frame loss type and abnormal range output by the classification model of the real-time serial data stream; Select the windowed feature sequence before and after the frame loss and perform normalization processing to form the time series input of the long short-term memory network model, where the windowed feature sequence includes frame number, time interval and load data; The trained LSTM network model is used in combination with the time series input to predict the lost frame number within the abnormal range. The payload data of the lost frame is generated based on the LSTM network model and the context features. The predicted lost frame sequence number and load data are inserted into the original data stream to form a continuous repair data stream, and the repaired frame is subjected to data consistency check; based on the check result, the repaired complete serial data stream is output.

5. The FPGA-based DC balanced digital audio and video signal serializer and deserializer according to claim 1, characterized in that: Using the trained long short-term memory network model to repair the abnormal data duplicate frames includes: Obtain the frame number, inter-frame time interval, frame load data, repeated frame type and abnormal range output by the classification model of the real-time serial data stream; Extracting the windowed feature sequence before and after the repeated frames and performing normalization processing, wherein the windowed feature sequence includes the frame number, time interval and load data; Analyze the frame features within the abnormal range using the long short-term memory network model to confirm the location of redundant repeated frames; delete redundant repeated frames based on the analysis results, and adjust the inter-frame time interval and frame load data after repair based on the timing prediction of the long short-term memory network model; Verify the frame number continuity and load consistency of the repaired data stream, verify the matching of the time interval with the normal mode, and output the repaired data stream based on the verification results to ensure that the frame number is unique and the data is complete.

6. The FPGA-based DC balanced digital audio and video signal serializer and deserializer according to claim 1, characterized in that: Using the trained long short-term memory network model to repair abnormal data errors includes: Obtain the frame number, frame load data, frame check result, error type and abnormal range output by the classification model of the real-time serial data stream; Extracting windowed feature sequences before and after the bit error frame and performing normalization processing, wherein the windowed feature sequence includes the frame sequence number, load context, and time interval; The context features are input by the LSTM model to predict the correct payload content of the frames within the abnormal range; the payload data of the abnormal frames are replaced with the repair content predicted by the LSTM model, and the frame sequence number, frame header, and frame tail structure are kept unchanged; Regenerate the checksum of the repair frame and perform consistency check to check the integrity and context consistency of the repair frame, and output the repaired data stream based on the check result to ensure that the load data is accurate and meets the protocol requirements.

7. The FPGA-based DC balanced digital audio and video signal serializer and deserializer according to claim 1, characterized in that: The quality assessment and adjustment module includes a signal quality detection module, a signal quality assessment module, a clock recovery parameter adjustment module, a decoding parameter adjustment module, a deserialization parameter adjustment module, a buffer strategy adjustment module and an optimization result output module; The signal quality detection module is used to monitor the repaired serial data stream in real time and extract signal quality indicators, including bit error rate, frame loss rate, signal jitter, verification pass rate, frame sequence number continuity and data stream integrity; The signal quality assessment module is used to generate a signal quality assessment result according to the signal quality indicator data to obtain a signal health score; The clock recovery parameter adjustment module is used to dynamically adjust the clock recovery parameters according to the signal health score; The decoding parameter adjustment module is used to dynamically adjust decoding related parameters according to the signal health score; The deserialization parameter adjustment module is used to dynamically adjust the deserialization parameters according to the signal health score; The buffer strategy adjustment module is used to dynamically adjust the buffer strategy according to the signal health score; The optimization result output module is used to output the adjusted clock recovery parameters, decoding parameters, deserialization parameters and buffering strategy.

8. The FPGA-based DC balanced digital audio and video signal serializer and deserializer according to claim 7, characterized in that: The expression for signal quality evaluation is: In the formula, Q represents the signal health score, B represents the bit error rate, F represents the frame loss rate, J represents the signal jitter, and J max It represents the maximum tolerable value of signal jitter. ω1, ω2, and ω3 represent the weight coefficients of bit error rate, frame loss rate, and signal jitter, respectively.

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