Image sensor and signal reading circuit and method thereof
By keeping the gate signal of the previous reading row at a high level during the gate signal jump in the image sensor, the channel separation phenomenon caused by instability in the column signal line voltage is solved, and the voltage stability of the column signal line PXD is achieved.
Patent Information
- Application Number
- CN202411778271.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-04
- Publication Date
- 2025-03-18
AI Technical Summary
In the image sensor, when the column signal line switches the source follow transistor output of different rows, the column signal line voltage is unstable, resulting in channel separation phenomenon, resulting in the read first PD signal inconsistent with other PD signals sharing the same FD point.
The gate signal of the previous read row is maintained at a high level during the process of jumping from a low level to a high level in the process of jumping from a low level to a high level, thereby reducing the voltage fluctuation of the column signal line. The specific method includes maintaining the gate signal of the previous read line at a high level within a preset time when the gate signal starts to rise from a low level, or within a time period of the preset amplitude.
It is realized that when the column signal line switches the source follow transistor output of different rows, the voltage of the column signal line PXD is maintained to avoid channel separation.
Smart Images
Figure CN119653254A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of image sensors, and in particular to an image sensor and a signal readout circuit and method thereof. Background Art
[0002] As pixels become smaller and smaller, the opening surrounded by the metal layer gradually decreases. In order to increase the opening, a multi-pixel sharing structure has been developed in the prior art to meet the requirements of large array image sensors. In the multi-pixel sharing structure, multiple photodiodes (PD) share the same floating diffusion point (FD), thereby increasing the area of the photodiode 11. Figure 1 As shown, it is a 4-pixel sharing structure. The four transmission tubes TG_A1, TG_A2, TG_A3, and TG_A4 are connected to the same floating diffusion point FD_A, and drive the bit line PXD through the source follower transistor and the gate transistor A. The four transmission tubes TG_B1, TG_B2, TG_B3, and TG_B4 in the adjacent row are connected to the same floating diffusion point FD_B, and drive the column signal line PXD through the source follower and the gate transistor B.
[0003] Before reading the first PD at point FD_B, the column signal line PXD is switched from the control of point FD_A in the previous row to the control of point FD_B in the current row. When the source follower transistor outputs of different rows are switched, the selection signal SEL_A of the previous row jumps from a high level to a low level, and the selection signal SEL_B of the current row jumps from a low level to a high level. The simultaneous jump of the selection signals of the two rows affects PXD, causing the potential of PXD to drop.
[0004] like Figure 2 As shown, at time t1, the selection signal SEL_A jumps from a high level to a low level, and the selection signal SEL_B jumps from a low level to a high level. Due to the RC delay of the selection signal line, this process is usually slow. For example, at time t2, the selection signal SEL_A and the selection signal SEL_B are both at an intermediate level instead of a high level, and the voltage of PXD is affected by the gate voltage of the selection transistor A and the selection transistor B and is lower than the ideal value. Then the voltage of PXD slowly recovers as the gate voltage of the selection transistor B rises.
[0005] Compared with the first PD read after the source follower transistor outputs of different rows are switched, before reading other PDs at the current FD_B point, its PXD potential is always controlled by the same point FD_B, and there is no process in which the SEL signals of two rows jump at the same time. Therefore, before reading the first PD and other PDs, the stable trend of PXD is inconsistent. This inconsistency leads to channel separation, that is, the signal of the first PD read is inconsistent with the signals of other PDs sharing the same FD point. Summary of the invention
[0006] The object of the present invention is to provide an image sensor and a signal readout circuit and method thereof, which can stabilize the voltage of the column signal line when the column signal line switches the output of source follower transistors in different rows, thereby avoiding the channel separation phenomenon.
[0007] In order to achieve the above objectives, the present invention is implemented by the following technical solutions:
[0008] A signal reading method for an image sensor includes: when a column signal line switches the source follower transistor outputs of different rows, in the process that the selection signal of the current reading row jumps from a low level to a high level, the selection signal of the previous reading row is maintained at a high level within a preset time to reduce the voltage fluctuation of the column signal line.
[0009] Optionally, within a preset time when the strobe signal of the current read row starts to rise from a low level, the strobe signal of the previous read row is maintained at a high level.
[0010] Optionally, during the time period when the strobe signal of the current read row starts to rise from a low level to a preset amplitude, the strobe signal of the previous read row is maintained at a high level.
[0011] A signal readout circuit of an image sensor comprises: a gating transistor; a gating signal adjustment module, coupled to the gate of the gating transistor, for outputting a gating signal to the gating transistor; the gating signal adjustment module is configured to respond to a control signal so that: when a column signal line switches to output different source follower transistors, in the process that the gating signal of the current read row jumps from a low level to a high level, the gating signal of the previous read row is maintained at a high level to maintain the voltage stability of the column signal line.
[0012] Optionally, the control signal includes: a row decoding signal and a pulse signal; the pulse signal starts before the current read row is decoded and ends when the selection signal of the current read row jumps from a low level to a high level and meets a preset condition; the row decoding signal is at a high level when the current read row is decoded.
[0013] Optionally, the selection signal adjustment module includes: a Pmos tube, whose gate is coupled to the row decoding signal, whose source is coupled to a voltage, and whose drain outputs the selection signal; an adjustment unit, whose output end is coupled to the drain of the Pmos tube, and whose input end is coupled to the row decoding signal and the pulse signal.
[0014] Optionally, the adjustment unit includes: an NOR gate, whose input is coupled to the row decoding signal and the pulse signal, and the pulse signal is a positive pulse; a first Nmos tube, whose gate is coupled to the output of the NOR gate, the source is grounded, and the drain is coupled to the drain of the Pmos tube.
[0015] Optionally, the adjustment unit includes: a second Nmos tube, whose gate is coupled to the row decoding signal and whose drain is coupled to the drain of the Pmos tube; a third Nmos tube, whose gate is coupled to the pulse signal, whose source is grounded and whose drain is coupled to the source of the second Nmos tube, and the pulse signal is a negative pulse.
[0016] Optionally, the row decoding signal is a row decoding positive phase signal and / or a row decoding negative phase signal.
[0017] Optionally, the width of the pulse signal is controlled by a digital circuit.
[0018] An image sensor comprises the signal readout circuit of the image sensor as described above.
[0019] Compared with the prior art, the present invention has the following advantages:
[0020] The image sensor and its signal readout circuit and method provided by the present invention, when the column signal line switches the source follower transistor outputs of different rows, the selection signal of the current read row normally jumps from a low level to a high level. During the jump process, the selection signal of the previous read row is maintained at a high level for a certain period of time and is not switched to a low level with the address jump, so that when the column signal line switches the source follower transistor outputs of different rows, there is always a selection signal at a higher potential, so as to maintain the voltage stability of the column signal line PXD and avoid the channel separation phenomenon. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] In order to more clearly illustrate the technical solution of the present invention, the following briefly introduces the drawings required for the description. Obviously, the drawings described below are an embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work:
[0022] Figure 1 A structural diagram of an image sensor having a 4-pixel sharing structure;
[0023] Figure 2 for Figure 1 The waveform diagram of the strobe signal and the column signal line voltage of the image sensor during readout shown;
[0024] Figure 3 A structural diagram of a signal readout circuit provided by an embodiment of the present invention;
[0025] Figure 4 It is a structural diagram of the strobe signal adjustment module in the first embodiment;
[0026] Figure 5 for Figure 4Waveform diagrams of control signals, strobe signals and column signal line voltages in the illustrated embodiment;
[0027] Figure 6 is a structural diagram of a strobe signal adjustment module in the second embodiment;
[0028] Figure 7 for Figure 6 Waveform diagram of control signal, strobe signal and column signal line voltage in the illustrated embodiment. DETAILED DESCRIPTION
[0029] The scheme proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the implementation method of the present invention. In order to make the purposes, features and advantages of the present invention more obvious and easy to understand, please refer to the accompanying drawings. It should be noted that the structures, proportions, sizes, etc. illustrated in the accompanying drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no technical substantive significance. Any structural modification, change in proportional relationship or adjustment of size, without affecting the effects that the present invention can produce and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present invention.
[0030] In order to stabilize the voltage of the column signal line and avoid channel separation when the column signal line switches the output of source follower transistors in different rows, the present invention provides an image sensor and a signal readout circuit and method thereof. In particular, the image sensor is an image sensor with a multi-pixel sharing structure.
[0031] According to one embodiment of the present invention, a signal readout method for image sensor pixels is provided, comprising: when a column signal line switches source follower transistor outputs of different rows, in the process of the selection signal of the current read row jumping from a low level to a high level, the selection signal of the previous read row is maintained at a high level to maintain the voltage stability of the column signal line. In this embodiment, when the column signal line switches source follower transistor outputs of different rows, the gate voltage of the selection transistor of the current read row is affected by the address jump and begins to rise. During the rising process, the driving signal of the selection transistor of the previous read row is maintained at a high level for a period of time and is not switched to a low level with the address jump, thereby ensuring that when the source follower transistor is switched, there is always a selection signal at a higher potential to maintain the voltage stability of the column signal line PXD.
[0032] Specifically, the selection signal of the previous read row can be maintained at a high level within a preset time when the selection signal of the current read row starts to rise from a low level. Alternatively, the selection signal of the previous read row can be maintained at a high level within a time period when the selection signal of the current read row starts to rise from a low level to a preset amplitude. That is, when the selection signal of the current read row rises for a period of time or rises to a certain amplitude, the gate voltage of the selection tube of the previous read row starts to jump to a low level, thereby avoiding under-compensation and over-compensation.
[0033] The preset time and the preset amplitude can be determined by calibrating the image sensor in actual applications, as long as the voltage of the column signal line PXD can be kept stable.
[0034] According to one embodiment of the present invention, a signal readout circuit of an image sensor is provided. Figure 3 As shown, it includes: a selection transistor 21, the source of which is coupled to the source follower; a selection signal adjustment module 22, coupled to the gate of the selection transistor 21, for outputting a selection signal SEL to the selection transistor 21; the selection signal adjustment module 22 is configured to respond to a control signal 24, so that: when the column signal line switches the source follower transistor outputs of different rows, in the process of the selection signal SEL_B of the current read row jumping from a low level to a high level, the selection signal SEL_A of the previous read row is maintained at a high level to maintain the voltage stability of the column signal line PXD.
[0035] In this embodiment, the control signal 24 includes: a row decoding signal and a pulse signal Rsel_hold. The pulse signal Rsel_hold starts before the current read row is decoded, and ends when the selection signal SEL_B of the current read row jumps from a low level to a high level and meets a preset condition. "Preset condition" refers to the aforementioned "preset time for the selection signal of the current read row to rise from a low level" or "the time period for the selection signal of the current read row to rise from a low level to a preset amplitude". The row decoding signal includes a positive phase signal (i.e. ADDR_EN) and an inverted phase signal (i.e. ADDR_ENB), which is determined according to the specific function and connection relationship. The row decoding positive phase signal ADDR_EN is a high level when the current read row is decoded, so the row decoding inverted phase signal ADDR_ENB is a low level when the current read row is decoded.
[0036] Specific, combined Figure 4 and Figure 6As shown, the selection signal adjustment module 22 includes: a Pmos tube 221, whose gate is coupled to the row decoding inverted signal ADDR_ENB, whose source is coupled to a voltage RSEL_HIGH, and whose drain outputs the selection signal SEL; an adjustment unit 222, whose output end is coupled to the drain of the Pmos tube 221, and whose input end is coupled to the row decoding signal (positive phase signal ADDR_EN or inverted phase signal ADDR_ENB) and the pulse signal Rsel_hold.
[0037] Figure 4 An exemplary structure of the selection signal adjustment module 22 is shown. The adjustment unit 222 includes: a NOR gate 2221, whose input end is coupled to the row decoding positive phase signal ADDR_EN and the pulse signal Rsel_hold, and the pulse signal Rsel_hold is a positive pulse; a first Nmos tube 2222, whose gate is coupled to the output end of the NOR gate 2221, the source is grounded, and the drain is coupled to the drain of the Pmos tube 221.
[0038] When the current read row is decoded, the row decoding positive phase signal ADDR_EN is high level, and the row decoding negative phase signal ADDR_ENB is low level. The pulse width of the pulse signal Rsel_hold is controlled by a digital circuit. Specifically, the digital circuit generates the pulse signal Rsel_hold according to pre-calibrated data control.
[0039] When the pulse signal Rsel_hold is at a high level, the first NMOS tube 2222 is in a cut-off state. When the row address is switched, since the pulse signal Rsel_hold is at a high level, the selection signal SEL_A of the previous read row will be in a floating state, and the selection signal SEL_B of the current read row will jump from a low level to a high level. During the process of the selection signal SEL_B of the current read row jumping from a low level to a high level or after jumping to a high level, the pulse of the pulse signal Rsel_hold ends and returns to a low level, so the selection signal SEL_A of the previous read row jumps to a low level. In this process, there is a time period when the selection signals of two rows are at a high level at the same time, so the column signal line PXD will not be pulled very low, maintaining the stability of the PXD voltage. The falling edge of the pulse signal Rsel_hold can be during the process of the selection signal SEL_B rising to a high level or after rising to a high level, thereby avoiding under-compensation and over-compensation.
[0040] Combination Figure 5As shown in the waveform diagram, at time t1, the pulse signal Rsel_hold jumps to a high level in advance before the row address is switched, cutting off the ground path driven by the two row selection signals SEL, so that the selection signals SEL_A and SEL_B are both in a floating state. At time t2, the row address is switched, and the selection signal SEL_A is in a floating high level state because the ground path is cut off; and the selection signal SEL_B is driven by the power supply and jumps from a low level to a high level. At this time, the voltage of the column signal line PXD is still determined by the path of the selection signal SEL_A. At time t3, the pulse signal Rsel_hold jumps to a low level, so the ground path of the selection signal SEL_A is restored, and the selection signal SEL_A begins to jump from a high level to a low level, while the selection signal SEL_B has risen to a high level at this time, and the stability of the PXD voltage can continue to be maintained.
[0041] Figure 6 Another exemplary structure of the selection signal adjustment module 22 is shown. Figure 4 The difference between the illustrated embodiments is that the adjustment unit 222 includes: a second Nmos tube 2223, whose gate is coupled to the row decoding inverted signal ADDR_ENB, and whose drain is coupled to the drain of the Pmos tube 221; a third Nmos tube 2224, whose gate is coupled to the pulse signal Rsel_hold, whose source is grounded, and whose drain is coupled to the source of the second Nmos tube 2223, and the pulse signal Rsel_hold is a negative pulse.
[0042] When the current read row is decoded, the row decoding positive phase signal ADDR_EN is high, and the row decoding negative phase signal ADDR_ENB is low. The pulse signal Rsel_hold can control whether the path from the selection signal SEL to the ground is valid. When the address jumps, the path to the ground of the selection signal SEL_A of the previous read row is cut off, and the selection signal SEL_B of the current read row rises normally. After the selection signal SEL_B of the current read row rises for a certain time or rises to a certain value, the pulse signal Rsel_hold is returned to a high level, and the selection signal SEL_A of the previous read row drops to a low level.
[0043] Combination Figure 7As shown in the waveform diagram, at time t1, the pulse signal Rsel_hold jumps from a high level to a low level, and the ground paths of the selection signals SEL_A and SEL_B are cut off. At time t2, following the address jump, the selection signal SEL_B begins to rise to a high level, and the selection signal SEL_A is in a floating state, maintaining a high level voltage state, thereby maintaining the stability of the column signal line PXD voltage. At time t3, the pulse signal Rsel_hold jumps to a high level, the selection signal SEL_A begins to jump to a low level, and the selection signal SEL_B is not affected. During this process, the voltage of the column signal line PXD remains stable. Among them, the pulse width of the pulse signal Rsel_hold is controlled by a digital circuit, and the rising edge of the pulse signal Rsel_hold can be during the process of the selection signal SEL_B rising to a high level or after it rises to a high level, thereby avoiding under-compensation and over-compensation.
[0044] According to one embodiment of the present invention, an image sensor is provided, comprising the above-mentioned signal readout circuit of the image sensor. The image sensor is a multi-pixel sharing structure, each pixel row has the above-mentioned signal readout circuit, and a gating signal adjustment module is connected before the gating transistor of each pixel row, so as to provide an adjusted gating signal.
[0045] In summary, the image sensor and its signal readout circuit and method provided by the present invention, when the column signal line switches the source follower transistor outputs of different rows, the selection signal of the current read row normally jumps from a low level to a high level. During the jump process, the selection signal of the previous read row is maintained at a high level for a certain period of time and is not switched to a low level with the address jump, so that when the source follower transistor outputs of different rows are switched, there is always a selection signal at a higher potential, which reduces the voltage fluctuation of the column signal line, maintains the voltage stability of the column signal line PXD, and avoids the channel separation phenomenon.
[0046] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0047] Although the content of the present invention has been described in detail through the above preferred embodiments, it should be appreciated that the above description should not be considered as a limitation of the present invention. After reading the above content, it will be apparent to those skilled in the art that various modifications and substitutions of the present invention will occur. Therefore, the protection scope of the present invention should be limited by the appended claims.
Claims
1. A signal reading method for an image sensor, characterized in that: include: When the column signal line switches the source follower transistor outputs of different rows, the selection signal of the previous read row is maintained at a high level within a preset time during the process that the selection signal of the current read row jumps from a low level to a high level, so as to reduce the voltage fluctuation of the column signal line.
2. The signal reading method of the image sensor according to claim 1, characterized in that: During the time period when the strobe signal of the current read row starts to rise from a low level to a preset amplitude, the strobe signal of the previous read row is maintained at a high level.
3. A signal readout circuit for an image sensor, characterized in that: include: A gate transistor; A gating signal adjustment module, coupled to the gate of the gating transistor, for outputting a gating signal to the gating transistor; The selection signal adjustment module is configured to respond to the control signal so that: when the column signal line switches the source follower transistor outputs of different rows, during the process of the selection signal of the current read row jumping from a low level to a high level, the selection signal of the previous read row is maintained at a high level to maintain the voltage stability of the column signal line.
4. The signal readout circuit of the image sensor according to claim 3, characterized in that: The control signal includes: a row decoding signal and a pulse signal; The pulse signal starts before the current read row is translated, and ends when the selection signal of the current read row jumps from a low level to a high level and satisfies a preset condition; The row decoding signal is at a high level when the current read row is decoded.
5. The signal readout circuit of the image sensor according to claim 4, characterized in that: The strobe signal adjustment module comprises: A PMOS tube, a gate of which is coupled to the row decoding signal, a source of which is coupled to a voltage, and a drain of which outputs the selection signal; The adjustment unit has an output end coupled to the drain of the PMOS tube, and an input end coupled to the row decoding signal and the pulse signal.
6. The signal readout circuit of the image sensor according to claim 5, characterized in that: The adjustment unit comprises: A NOR gate, an input end of which is coupled to the row decoding signal and the pulse signal, wherein the pulse signal is a positive pulse; The first Nmos tube has a gate coupled to the output end of the NOR gate, a source connected to the ground, and a drain coupled to the drain of the Pmos tube.
7. The signal readout circuit of the image sensor according to claim 5, characterized in that: The adjustment unit comprises: A second Nmos tube, a gate of which is coupled to the row decoding signal, and a drain of which is coupled to the drain of the Pmos tube; The third Nmos tube has a gate coupled to the pulse signal, a source grounded, and a drain coupled to the source of the second Nmos tube, and the pulse signal is a negative pulse.
8. The signal readout circuit of the image sensor according to claim 4, characterized in that: The width of the pulse signal is controlled by a digital circuit.
9. The signal readout circuit of the image sensor according to claim 4, characterized in that: The row decoding signal is a row decoding positive phase signal and / or a row decoding negative phase signal.
10. An image sensor, characterized in that: The invention comprises a signal readout circuit of the image sensor according to any one of claims 3 to 9.