Method of fabricating a semiconductor structure, semiconductor structure, device and apparatus

Abstract

The application provides a semiconductor structure preparation method, a semiconductor structure, a device and equipment. The method comprises the following steps: forming a pair of first active structures and a pair of second active structures on two regions of a substrate along a first direction; forming isolation structures on the two regions of the substrate respectively to expose the pair of first active structures; forming a pair of front surface transistors based on the pair of first active structures; developing and exposing the pair of second active structures; forming a pair of back surface transistors based on the pair of second active structures; and etching the isolation structures located in a logic region after the pair of first active structures are exposed and / or the pair of second active structures are exposed, so that the height of the active structures located in the logic region is higher than the height of the active structures located in a storage region. The application can realize different heights of the active structures in the logic region and the storage region, which is beneficial to the demand of different regions of a chip for transistor properties.

Description

Technical Field

[0001] This application relates to the field of integrated semiconductors, and more particularly to a method for fabricating a semiconductor structure, a semiconductor structure, a device, and an apparatus. Background Technology

[0002] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Flip-chip stacked transistors, by integrating two layers of transistors in a vertical space, further increase transistor density and have become one of the key technologies for continuing the miniaturization of integrated circuits.

[0003] In related technologies, logic sections (e.g., logic transistors) and storage sections (e.g., static random-access memory, SRAM) can be integrated into a single chip. However, the internal structures of the logic sections or storage sections within the same chip are identical, which cannot meet the requirement that transistors in different regions of the chip have different properties. Summary of the Invention

[0004] This application provides a method for fabricating a semiconductor structure, a semiconductor structure, a device, and an apparatus, which can realize different heights of active structures in logic regions and memory regions, thus benefiting the different transistor properties required by different regions of the chip.

[0005] In a first aspect, embodiments of this application provide a method for fabricating a semiconductor structure. The method includes: forming a pair of first semiconductor structures on two regions along a first direction on a substrate, the pair of first semiconductor structures including at least a pair of first active structures and a pair of second active structures, the pair of first active structures being farther from the substrate relative to the pair of second active structures, and the two regions including a logic region and a storage region; forming isolation structures on the two regions of the substrate respectively to expose the pair of first active structures; forming a pair of front-side transistors based on the pair of first active structures, the pair of front-side transistors including a first front-side transistor located in the logic region and a second front-side transistor located in the storage region; performing a flip-flop operation on the pair of front-side transistors to expose the pair of second active structures; forming a pair of back-side transistors based on the pair of second active structures, the pair of back-side transistors including a first back-side transistor located in the logic region and a second back-side transistor located in the storage region; after exposing the pair of first active structures and / or the pair of second active structures, etching the isolation structures located in the logic region such that the height of the active structures located in the logic region is higher than the height of the active structures located in the storage region.

[0006] In one possible implementation, after exposing a pair of first active structures, etching an isolation structure located within a logic region includes: forming a first mask on the isolation structure and the first active structures located within a storage region; etching the isolation structure based on the first mask such that the height of the first active structures located within the logic region is higher than the height of the first active structures located within the storage region; and forming a pair of front-facing transistors based on the pair of first active structures, including: forming a first front-facing transistor based on the first active structures located within the logic region, and forming a second front-facing transistor based on the first active structures located within the storage region.

[0007] In one possible implementation, exposing a pair of second active structures includes: removing a substrate; thinning an isolation structure to a predetermined height to expose the pair of second active structures; after exposing the pair of second active structures, etching the isolation structure located within a logic region, including: forming a second mask on the retained isolation structure and second active structures located within a memory region; based on the second mask, etching the retained isolation structure to a predetermined height such that the height of the second active structure located within the logic region is higher than the height of the second active structure located within the memory region; and forming a pair of back-side transistors based on the pair of second active structures, including: forming a first back-side transistor based on the second active structures located within the logic region, and forming a second back-side transistor based on the second active structures located within the memory region.

[0008] In one possible implementation, the method further includes: when the first front transistor and the first back transistor form an SRAM, and the first front transistor is an N-type transistor, after exposing a pair of first active structures, etching an isolation structure located within the memory region such that the height of the first active structure located within the memory region is higher than the height of the second active structure located within the memory region.

[0009] In one possible implementation, after exposing a pair of first active structures, etching an isolation structure located within the storage region includes: forming a third mask on the isolation structure and the first active structures located within the logic region; etching the isolation structure based on the third mask such that the height of the exposed first active structures located within the storage region is higher than the height of the first active structures located within the logic region; exposing a pair of second active structures includes: removing a substrate; thinning the isolation structure to a predetermined height to expose a pair of second active structures, wherein the height of the second active structures located within the storage region is lower than the height of the first active structures located within the storage region.

[0010] In one possible implementation, a pair of first semiconductor structures are formed on two regions of a substrate along a first direction, comprising: providing a substrate; forming a first material layer and a second material layer on the substrate along the first direction; etching the second material layer, the first material layer, and a portion of the substrate to form a pair of first semiconductor structures, wherein the etched second material layer is a first active structure, the etched portion of the substrate is a second active structure, and the etched first material layer is an isolation layer for isolating the first active structure and the second active structure.

[0011] Secondly, embodiments of this application provide a semiconductor structure fabricated using the fabrication method described in the first aspect and any of its embodiments, comprising: a pair of front-side transistors and a pair of back-side transistors, wherein the pair of front-side transistors includes a first front-side transistor located within a logic region and a second front-side transistor located within a storage region, and the pair of back-side transistors includes a first back-side transistor located within a logic region and a second back-side transistor located within a storage region; wherein the height of the active structure located within the logic region is higher than the height of the active structure located within the storage region.

[0012] In one possible implementation, where the first front transistor and the first back transistor form an SRAM, and the first front transistor is an N-type transistor, the height of the first active structure located within the storage region is higher than the height of the second active structure located within the storage region.

[0013] Thirdly, embodiments of this application provide a semiconductor device, which includes the semiconductor structure described in the second aspect above.

[0014] Fourthly, embodiments of this application provide an electronic device, which includes: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is disposed on the circuit board.

[0015] In this application, a pair of first active structures and a pair of second active structures are formed on two regions of a substrate along a first direction; isolation structures are formed on the two regions of the substrate respectively to expose the pair of first active structures; a pair of front-side transistors are formed based on the pair of first active structures; the pair of second active structures are then flipped and exposed; a pair of back-side transistors are formed based on the pair of second active structures; after exposing the pair of first active structures and / or the pair of second active structures, the isolation structures located within the logic region are etched so that the height of the active structures within the logic region is higher than the height of the active structures within the memory region. Therefore, this application can simultaneously fabricate logic transistors and SRAM on two regions of the substrate, and can achieve different heights of the active structures in the logic transistors and SRAM, which is beneficial for meeting the transistor properties requirements of different regions of the chip.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] Figure 1 This is a schematic diagram of an implementation process of the semiconductor structure fabrication method in this application.

[0019] Figure 2 This is a top view of the semiconductor structure in an embodiment of this application;

[0020] Figures 3 to 8 This is a schematic diagram of the semiconductor structure in the first fabrication process of the embodiments of this application;

[0021] Figure 9 This is a schematic diagram of the first type of semiconductor structure in the embodiments of this application;

[0022] Figure 10 This is a top view of the semiconductor structure within the logic region or storage region in the embodiments of this application;

[0023] Figure 11 This is a schematic diagram of a second semiconductor structure in an embodiment of this application.

[0024] The above images:

[0025] 10. Front-side transistor located within the memory region; 11. Front-side transistor located within the logic region; 101. First fin structure located within the memory region; 111. First fin structure located within the logic region; 112. First source / drain structure; 113. First interlayer dielectric layer; 114. First gate structure; 115. First source / drain metal; 116. First metal interconnect layer; 12. Back-side transistor located within the logic region; 121. Second fin structure located within the logic region; 122. Second source / drain structure; 123. Second interlayer dielectric layer; 124. Second gate structure; 125. Second source / drain metal; 126. Second metal interconnect layer; 13. Back-side transistor located within the memory region; 131. Second fin structure located within the memory region; 20. Substrate; 21. First isolation structure; 22. First sidewall; 23. Insulating layer; 24. Carrier wafer; 25. Mask; 26. Second isolation structure; 27. Second sidewall; 28. MDI layer / BOX layer. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0027] With Moore's Law continuously evolving, further miniaturizing transistors is a hot research topic in the industry. Stacked transistors, through three-dimensional transistor stacking, can integrate two or more layers of transistors in vertical space, helping to further increase transistor integration density and improve circuit performance. It is considered one of the important technologies for continuing the miniaturization of integrated circuits.

[0028] With the continuous development of transistor technology, flip-chip stacking technology has emerged. Flip-chip stacked transistors take into account the issues of consistency of active regions of upper and lower transistors, defect density, alignment and thermal budget. This solution solves the long-standing problems of existing mainstream stacked transistor technologies, such as complex processes, fixed polarity (monolithic solution), difficult alignment, and high defect density of upper semiconductor materials (sequential solution), thereby promoting the industrialization of transistor stacking technology.

[0029] Currently, logic transistors and SRAM can be integrated into the same chip. However, the internal structures of the logic or storage sections within the same chip are identical, which cannot meet the needs of transistors in different areas of the chip having different properties.

[0030] Based on this, the present application provides a method for fabricating a semiconductor structure that can achieve different heights of the active structure of logic transistors and SRAM based on the formation of flip-chip stacked transistors, which is beneficial to the transistor properties required by different regions of the chip.

[0031] In the embodiments of this application, the above-described semiconductor structure can be applied to semiconductor devices such as processors and logic devices.

[0032] In some embodiments, the semiconductor structure may include a pair of front-side transistors and a pair of back-side transistors, the pair of front-side transistors including a first front-side transistor located in a logic region and a second front-side transistor located in a storage region, and the pair of back-side transistors including a first back-side transistor located in a logic region and a second back-side transistor located in a storage region; wherein the height of the first active structure located in the logic region is higher than the height of the first active structure located in the storage region, and / or the height of the second active structure located in the logic region is higher than the height of the second active structure located in the storage region.

[0033] In some embodiments, when the first front transistor and the first back transistor form an SRAM, and the first front transistor is an N-type transistor, the height of the first active structure located within the storage region is higher than the height of the second active structure located within the storage region.

[0034] In some embodiments, the transistor type may be, for example, a fin field-effect transistor (FinFET).

[0035] Figure 1 This is a schematic diagram illustrating one implementation process of the semiconductor structure fabrication method in this application, such as... Figure 1 As shown, the method for fabricating the semiconductor structure in the embodiments of this application may include:

[0036] Step S110: A pair of first semiconductor structures are formed on two regions of the substrate along the first direction.

[0037] In some embodiments, a pair of first semiconductor structures includes at least a pair of first active structures and a pair of second active structures, the pair of first active structures being farther from the substrate relative to the pair of second active structures, and the two regions including a logic region and a memory region.

[0038] As is understood, in this embodiment, two first semiconductor structures are formed in different regions of the substrate (logic region and memory region), and then logic transistors and SRAM are formed on these two first semiconductor structures respectively. The first direction is perpendicular to the growth direction of the substrate.

[0039] In one embodiment, where the first semiconductor structure includes only active structures (first active structure and second active structure), the substrate may be a silicon substrate. It is understood that the substrate may also be made of other semiconductor materials, and this application does not limit this.

[0040] In one embodiment, when the first semiconductor structure includes a first active structure, a second active structure, and an isolation layer located between the first active structure and the second active structure, the substrate may be a silicon-on-insulator (SOI) substrate.

[0041] In one embodiment, the SOI substrate comprises a three-layer structure: a thin top silicon layer, a buried oxide (BOX) layer, and a supporting base silicon layer. That is, a buried oxide (BOX) layer is disposed between the top silicon layer and the back silicon substrate, and the BOX layer subsequently serves as an isolation layer between the first and second active structures. Thus, the SOI substrate can achieve dielectric isolation of components in integrated circuits, eliminating the parasitic latch-up effect in bulk silicon CMOS circuits. Integrated circuits fabricated using SOI substrates also have advantages such as low parasitic capacitance, high integration density, high speed, simple process, low short-channel effect, and particular suitability for low-voltage, low-power circuits.

[0042] After providing a substrate, a portion of the substrate can be etched to form a plurality of active structures standing upright on the substrate. In one example, anisotropic etching can be performed on the substrate to obtain the active structures, which include a first active structure away from the substrate and a second active structure close to the substrate. The etching process can, for example, be at least one of dry etching, wet etching, reactive ion etching, or chemical oxide removal processes, and this application does not specifically limit the specific methods used.

[0043] In addition, when the first semiconductor structure includes a first active structure, a second active structure, and an isolation layer located between the first active structure and the second active structure, the implementation process of step S110 can be: providing a substrate; forming a first material layer and a second material layer on the substrate along a first direction; etching the second material layer, the first material layer, and a portion of the substrate to form a pair of first semiconductor structures, wherein the etched second material layer is the first active structure, the etched portion of the substrate is the second active structure, and the etched first material layer is a sacrificial layer.

[0044] In one embodiment, a silicon-germanium (SiGe) material layer can be epitaxially grown on the original silicon substrate, followed by an epitaxial silicon material layer. After etching, the epitaxial silicon material layer above the silicon-germanium material layer serves as the device layer for the front-side transistor, and the original silicon material layer below the silicon-germanium material layer serves as the device layer for the back-side transistor. The silicon-germanium material layer is a sacrificial layer, which can be used to form an isolation layer after subsequent etching. This will be explained later and will not be elaborated here.

[0045] Step S120: Form isolation structures on two regions of the substrate to expose a pair of first active structures.

[0046] Understandably, after forming the active structure, insulating material can be deposited on the substrate and the active structure to form an isolation structure that encloses a pair of second active structures. In this case, the isolation structure located in the logic region and the isolation structure located in the storage region have the same height, and the isolation structure is taller, also able to enclose a portion of the pair of first active structures.

[0047] For example, the isolation structure can also be called a shallow trench isolation (STI) structure. Insulating materials forming the isolation structure can, for example, be silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc.

[0048] In some embodiments, to facilitate subsequent processing, after the isolation structure is formed, it can be polished or chemical-mechanical planarized (CMP) so that different regions of the isolation structure have the same etching depth when etched later, thereby making the top height of the exposed active structure the same.

[0049] Step S130: Based on a pair of first active structures, form a pair of front-side transistors.

[0050] In some embodiments, a pair of front-side transistors includes a first front-side transistor located within a logic region and a second front-side transistor located within a storage region. Step S130 can be implemented by: forming the first front-side transistor based on the first active structure located within the logic region, and forming the second front-side transistor based on the first active structure located within the storage region.

[0051] Understandably, after the first active structure in the logic region and memory region is exposed, the front-side device of the logic transistor and the front-side device of the SRAM can be formed simultaneously based on the exposed first active structure. Since the operation of forming the front-side device of the logic transistor and the front-side device of the SRAM is the same, the following explanation will take the formation of a single front-side transistor as an example.

[0052] In some embodiments, step S130 can be implemented as follows: epitaxially growing a first source / drain structure on a first active structure; forming a first gate structure based on the first active structure; and depositing metal material on the first source / drain structure to form a first source / drain metal.

[0053] Understandably, after forming the isolation structure, semiconductor material can be deposited in the gate region of the semiconductor structure to form a first dummy gate structure; first sidewalls (spacers) are formed on both sides of the first dummy gate structure; and first source / drain structures are formed on the first active structures on both sides of the first dummy gate structure and the first sidewalls. The first sidewalls are used to isolate the first source / drain structures from the first gate structure. The structure of the first sidewalls can be configured according to actual needs, and this application embodiment does not specifically limit this.

[0054] In some embodiments, the semiconductor material forming the first dummy gate structure may be polycrystalline silicon (Poly Si), amorphous silicon, etc. For example, the first sidewall may have a single-layer structure, made entirely of the same material, such as porous silicon carbide hydride (SiCOH).

[0055] In the aforementioned case of forming a sacrificial layer, after forming the first dummy gate structure, the sacrificial layer located between the first and second active structures can be selectively removed to form a first groove. Then, a dielectric material is filled into the first groove to form an isolation layer. Because the first dummy gate structure provides structural support to the first active structure during the selective removal process, the position of the first active structure in the front-side transistor remains unchanged, and the first and second active structures maintain self-alignment. The dielectric material can, for example, be a low-K material. The isolation layer achieves electrical isolation between the front-side and back-side transistors by isolating the first and second active structures.

[0056] In some embodiments, the process of forming the first source-drain structure on the first active structure on both sides of the first pseudo-gate structure and the first sidewall can be as follows: etching the first active structure of the front transistor in the source-drain region to form the first source-drain groove, and performing source-drain epitaxial growth at the first source-drain groove to form the first source-drain structure.

[0057] Understandably, strained materials such as silicon germanium or silicon carbide can be selectively epitaxially grown in the source-drain trenches to fill the source-drain trenches of the front-side transistor, and then a first source-drain structure can be formed on the strained material through a heavy doping process.

[0058] In some embodiments, ion implantation can be performed on a portion of the first active structure on both sides of the first pseudo-gate structure and the first sidewall to form a first source-drain structure. Here, the implanted ions can include N-type ions or P-type ions, such as nitrogen ions, phosphorus ions, arsenic ions, etc. When the implanted ions are N-type ions, the front-side transistor is an N-type transistor; when the implanted ions are P-type ions, the front-side transistor is a P-type transistor.

[0059] In some embodiments, after forming the first source / drain structure, an interlayer medium may be deposited on the first source / drain structure to form a first interlayer medium layer.

[0060] For example, an insulating material (such as silicon dioxide) may be deposited over the first source / drain structure and the first active structure and planarized to form a first interlayer dielectric layer, which may cover the first source / drain structure and the first active structure.

[0061] After the first source-drain structure is formed, the gate structure of the front-side transistor can be formed, that is, the first gate structure is formed.

[0062] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to obtain a gate trench. An insulating material is deposited at the gate trench to form a first gate dielectric layer, and a metal material is deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute the first gate structure.

[0063] For example, the first gate dielectric layer may be composed of a silicon oxide layer and a hafnium oxide layer with a high K value, and the thicknesses of the silicon oxide layer and the hafnium oxide layer may be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer may be composed of multiple layers of electrode materials, each layer of which may include, but is not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide).

[0064] After the first gate structure is formed, metal material can be deposited on the first source / drain structure to form the first source / drain metal.

[0065] In some embodiments, when a first interlayer dielectric layer is formed after the first source / drain structure is formed, a portion of the first interlayer dielectric layer may be etched to expose the first source / drain structure, and a metallic material may be filled onto the first source / drain structure to form the first source / drain metal.

[0066] For ease of explanation, the first source / drain structure mentioned in the embodiments of this application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. Furthermore, the first source / drain metal, the first source / drain groove, the second source / drain structure, the second source / drain metal, the second source / drain groove, etc., are all similar to the first source / drain structure, where "source / drain" is an abbreviation for "source and / or drain".

[0067] In addition, in some embodiments, after the front-side transistor is fabricated, a first metal interconnect layer may be formed on the front-side transistor.

[0068] It is understood that performing back-end processes (such as inter-interconnect dielectric deposition, metal line formation, and lead-out pad formation) on the front-side transistor can form a first metal interconnect layer. The first metal interconnect layer may include at least one interconnect dielectric layer and an interconnect metal structure located within the interconnect electrolyte layer.

[0069] It should be noted that the first source / drain structure, the first interlayer dielectric layer, the first gate structure, the first source / drain metal, and the first metal interconnect layer can all be formed by standard steps of semiconductor fabrication processes, and the embodiments of this application do not specifically limit this.

[0070] Step S140: Flip a pair of front-side transistors to expose a pair of second active structures.

[0071] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the aforementioned first metal interconnect layer to form an insulating layer, and the insulating layer may be bonded to a carrier wafer. Subsequently, a pair of front-side transistors are flipped so that the substrate is placed on top.

[0072] In some embodiments, the process of exposing the second active structure in step S140 can be: removing the substrate; thinning the isolation structure to a preset height to expose a pair of second active structures, wherein the thinned isolation structure is used to isolate the CMOS transistor and the memory cell. In this case, if the isolation structure located in the logic region is not etched as described above, the isolation structure located in the logic region and the isolation structure located in the memory region have the same height. Here, the height of the etched structure can be set to be smaller, so that the height of the exposed second active structure is smaller.

[0073] In one example, the substrate can be removed after wafer flipping using polishing or chemical mechanical planarization.

[0074] Understandably, after removing the substrate, the top of the second active structure is flush with the top of the isolation structure. Therefore, the isolation structure can be thinned to a predetermined height, exposing the periphery of the second active structure, so that a back-side transistor can be formed based on the exposed periphery of the second active structure.

[0075] Step S150: Based on a pair of second active structures, form a pair of back-side transistors.

[0076] In some embodiments, a pair of back-side transistors includes a first back-side transistor located within a logic region and a second back-side transistor located within a storage region. Step S130 can be implemented by: forming the first back-side transistor based on the second active structure located within the logic region, and forming the second back-side transistor based on the second active structure located within the storage region.

[0077] Understandably, after the second active structure in the logic region and memory region is exposed, the back-side device of the logic transistor and the back-side device of the SRAM can be formed simultaneously based on the exposed second active structure. Since the operation of forming the back-side device of the logic transistor and the back-side device of the SRAM is the same, the following explanation will take the formation of a single back-side transistor as an example.

[0078] In some embodiments, step S150 can be implemented as follows: epitaxially growing a second source / drain structure on the second active structure; forming a second gate structure based on the second active structure; and depositing metal material on the second source / drain structure to form a second source / drain metal.

[0079] Understandably, after forming the isolation structure, semiconductor material can be deposited in the gate region of the semiconductor structure to form a second pseudo-gate structure; second sidewalls (spacers) are formed on both sides of the second pseudo-gate structure; and second source / drain structures are formed on the second active structures on both sides of the second pseudo-gate structure and the second sidewalls.

[0080] Understandably, strained materials such as silicon germanium or silicon carbide can be selectively epitaxially grown in the source-drain trenches to fill the source-drain trenches of the back transistor, and then a second source-drain structure can be formed on the strained material through a heavy doping process.

[0081] In some embodiments, ion implantation can also be performed on a portion of the second active structure on both sides of the second pseudo-gate structure and the second sidewall to form a second source-drain structure. Here, the implanted ions can include N-type ions or P-type ions, such as nitrogen ions, phosphorus ions, arsenic ions, etc. When the implanted ions are N-type ions, the back-side transistor is an N-type transistor; when the implanted ions are P-type ions, the back-side transistor is a P-type transistor.

[0082] In some embodiments, after forming the second source / drain structure, an interlayer medium can be deposited on the second source / drain structure to form a second interlayer medium layer.

[0083] After forming the second source-drain structure, the gate structure of the back transistor can be formed, that is, the second gate structure is formed.

[0084] In some embodiments, the second dummy gate structure formed above can be removed by an etching process to obtain a gate trench. An insulating material is deposited at the gate trench to form a second gate dielectric layer, and a metal material is deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute the second gate structure.

[0085] After forming the second gate structure, metal material can be deposited on the aforementioned second source / drain structure to form the second source / drain metal.

[0086] In some embodiments, when a second interlayer dielectric layer is formed after the second source / drain structure is formed, a portion of the second interlayer dielectric layer may be etched to expose the second source / drain structure, and a metallic material may be filled onto the second source / drain structure to form a second source / drain metal.

[0087] In addition, in some embodiments, a second metal interconnect layer may be formed on the back transistor after the back transistor has been fabricated.

[0088] It is understood that performing back-end processes (such as interconnect dielectric deposition, metal line formation, and lead-out pad formation) on the back-side transistor can form a second metal interconnect layer. The second metal interconnect layer may include at least one interconnect dielectric layer and an interconnect metal structure located within the interconnect electrolyte layer.

[0089] It should be noted that the second source / drain structure, the second interlayer dielectric layer, the second gate structure, the second source / drain metal, and the second metal interconnect layer can all be formed by standard steps of semiconductor fabrication processes, and the embodiments of this application do not specifically limit this.

[0090] Step S160: After exposing a pair of first active structures and / or a pair of second active structures, etch the isolation structure located in the logical region such that the height of the active structure located in the logical region is higher than the height of the active structure located in the storage region.

[0091] The following section first introduces the scheme for active structures etched in the logic region on the front side.

[0092] In some embodiments, after exposing a pair of first active structures, an isolation structure located within a logical region may be etched such that the height of the first active structure located within the logical region is higher than the height of the first active structure located within the storage region.

[0093] In some embodiments, the process of etching the isolation structure located in the logical region can be as follows: forming a first mask on the isolation structure and the first active structure located in the storage region; based on the first mask, etching the isolation structure to a preset height, so that the height of the first active structure located in the logical region is higher than the height of the first active structure located in the storage region.

[0094] Understandably, a first mask is first formed above the storage area. After forming the first mask, an isolation structure is etched based on the first mask. Since the isolation structure located in the storage area is covered by the first mask, only a portion of the isolation structure located in the logical area is etched away. Because the isolation structure encloses a portion of the active structure, after a portion of the isolation structure located in the logical area is etched away, the first active structure enclosed by this portion of the isolation structure will be exposed. Thus, the height of the first active structure located in the logical area will be higher than the height of the first active structure located in the storage area.

[0095] Furthermore, in the case of etching the isolation structure located within the logic region, step S130 can first remove the first mask, and then form a first front-side transistor based on the first active structure located within the logic region, and simultaneously form a second front-side transistor based on the first active structure located within the memory region. Since the height of the first active structure located within the logic region is higher than the height of the first active structure located within the memory region, the height of the first gate structure of the front-side transistor formed based on the first active structure is also higher in the logic region than in the memory region. Therefore, by etching the isolation structure located within the logic region, this application can increase the height of the active structure located within the logic region, so that the final formed logic transistor has a larger effective channel width (Weff). Moreover, the height of the active structure located within the memory region is lower than the height of the active structure located within the logic region; that is, the height of the active structure located within the memory region is smaller. This allows the final formed SRAM to achieve low leakage current and high noise tolerance. Therefore, this embodiment of the application can achieve different heights of the active structures in the logic region and the memory region by etching the isolation structure located within the logic region, which is beneficial for meeting the transistor properties requirements of different regions of the chip.

[0096] The following section introduces a scheme for etching active structures within the logic region on the back side.

[0097] In some embodiments, after exposing a pair of second active structures, the isolation structure located within the logical region can be etched such that the height of the second active structure located within the logical region is higher than the height of the second active structure located within the storage region.

[0098] In some embodiments, the process of etching the isolation structure located in the logical region can be as follows: forming a second mask on the reserved isolation structure and the second active structure located in the storage region; based on the second mask, etching the reserved isolation structure to a preset height, so that the height of the second active structure located in the logical region is higher than the height of the second active structure located in the storage region.

[0099] Understandably, a second mask is first formed above the storage area. After forming the second mask, the reserved isolation structure is etched based on it. Since the reserved isolation structure within the storage area is covered by the second mask, only a portion of the reserved isolation structure within the logical area is etched away. Because the reserved isolation structure encloses a portion of the active structure, after the reserved isolation structure within the logical area is partially etched away, the second active structure enclosed by this portion of the isolation structure will be exposed. Thus, the height of the second active structure within the logical area will be higher than the height of the second active structure within the storage area.

[0100] Since the height of the second active structure located in the logic region is higher than the height of the second active structure located in the memory region, the height of the second gate structure in the logic region of the front-side transistor formed based on the second active structure is also higher than the height of the second gate structure in the memory region. Therefore, by etching the isolation structure located in the logic region, this application can increase the height of the active structure located in the logic region, so that the final logic transistor has a larger effective gate width. Moreover, the height of the active structure located in the memory region is lower than the height of the active structure located in the logic region, that is, the height of the active structure located in the memory region is smaller. In this way, the final SRAM can achieve the effects of low leakage current and high noise margin. Therefore, the embodiments of this application can achieve different heights of the active structures in the logic region and the memory region by etching the isolation structure located in the logic region, which is beneficial to the transistor properties required by different regions of the chip.

[0101] The above describes etching the isolation structure located within the logical region separately on the front or back side, so that the height of the active structure located within the logical region is higher than the height of the active structure located within the storage region. In some embodiments, the isolation structure located within the logical region can also be etched on both the front and back sides; this application does not limit this approach.

[0102] Furthermore, in some embodiments, where the first front transistor and the first back transistor form an SRAM and the first front transistor is an N-type transistor, after exposing a pair of first active structures, an isolation structure located within the storage region is etched such that the height of the first active structure located within the storage region is higher than the height of the second active structure located within the storage region.

[0103] In some embodiments, after exposing a pair of first active structures, a third mask can be formed on the isolation structure and the first active structure located within the logical region; based on the third mask, the isolation structure is etched such that the height of the first active structure located within the storage region is higher than the height of the first active structure located within the logical region.

[0104] That is, in this embodiment, the isolation structure located in the logic region is not etched, but the isolation structure located on the side of the N-type transistor in the storage region is etched, so that the height of the active structure on the side of the N-type transistor is higher than the height of the active structure of the P-type transistor.

[0105] Understandably, in step S120, if the isolation structure located in the logic region and the isolation structure located in the storage region have the same height, a third mask can be formed above the logic region. Then, based on the third mask, the isolation structure is etched to a preset height, and a first front-side transistor (N-type transistor) is formed based on the exposed first active structure. After the wafer flipping, the height of the etched isolation structure is smaller so that the exposed second active structure is lower than the first active structure. Then, a first back-side transistor (P-type transistor) is formed based on the second active structure. Thus, in the SRAM formed, the height of the active structure on the N-type transistor side is higher than the height of the active structure on the P-type transistor side.

[0106] In SRAM devices, P-type transistors typically function as pull-up (PU) transistors, while N-type transistors function as pull-down (PD) and pass-gate (PG) transistors. In SRAM read operations, the voltage difference between the two bit lines is used to read the signal. When stored data is read, a pre-charge operation equalizes the voltages of the two bit lines, and then current flow is allowed by turning on the corresponding pass-gate transistor, thus changing the bit line voltage. In this process, the P-type transistor acts as a pull-up transistor, maintaining a stable voltage on the unselected bit line and providing current to replenish charge when needed. However, if the drive capability of the P-type transistor is too strong, it may generate unnecessary current during processing, increasing power consumption and potentially affecting read accuracy. In contrast, in read operations, the N-type transistor acts as a pull-down transistor, needing to quickly pull the bit line voltage down to create a sufficient voltage difference to read the data. Therefore, N-type transistors typically require a stronger drive capability to ensure read speed. In write operations, the N-type transistor also acts as one of the pass-gate transistors, responsible for writing data into the SRAM cell. Therefore, from a performance perspective, N-type transistors need sufficient drive capability and response speed to ensure correct data writing. Furthermore, from the perspective of SRAM stability and power consumption, P-type transistors with weaker drive capability mean that less current is required to maintain voltage stability, which helps reduce power consumption. At the same time, P-type transistors with weaker drive capability can also reduce noise and interference generated during read and write processes, thereby improving SRAM stability.

[0107] The smaller the height of the active structure of a transistor, the weaker its driving capability. For non-flip-chip stacked devices, the distance between the P-type and N-type transistors within an SRAM is relatively close, making it impossible to selectively etch the isolation structure of a particular transistor to change the height of its active structure. However, for flip-chip stacked devices, the P-type and N-type transistors within the SRAM are flip-chip mounted on different sides. Therefore, in this embodiment, the isolation structure located on the N-type transistor side can be etched to make the height of the active structure on the N-type transistor side higher than the height of the active structure of the P-type transistor, thereby helping to improve the performance of the SRAM device.

[0108] The above explanation uses the N-type transistor as an example. Similarly, when the N-type transistor is on the back, the isolation structure located in the storage area can also be etched so that the height of the active structure on the N-type transistor side is higher than the height of the active structure on the P-type transistor side. This will not be elaborated further here.

[0109] Furthermore, embodiments of this application can simultaneously etch isolation structures within the logic region and isolation structures within the storage region. In this case, if the transistor on one side of the storage region is an N-type transistor, the isolation structures in both the storage region and the logic region on that side can be etched simultaneously, and the isolation structure in the logic region can be etched again on the other side. This allows the height of the active structure in the logic region to be higher than the height of the active structure in the storage region, while the height of the active structure on the N-type transistor side of the storage region is higher than the height of the active structure on the P-type transistor side. This better meets the transistor performance requirements of different regions.

[0110] In this application, a pair of first active structures and a pair of second active structures are formed on two regions of a substrate along a first direction; isolation structures are formed on the two regions of the substrate respectively to expose the pair of first active structures; a pair of front-side transistors are formed based on the pair of first active structures; the pair of second active structures are then flipped and exposed; and a pair of back-side transistors are formed based on the pair of second active structures. After exposing the pair of first active structures and / or the pair of second active structures, the isolation structures located within the logic region are etched so that the height of the active structures within the logic region is higher than the height of the active structures within the memory region. Therefore, this application can simultaneously fabricate logic transistors and SRAM on two regions of the substrate, and can achieve different heights of the active structures in the logic transistors and SRAM, which is beneficial for meeting the transistor properties requirements of different regions of the chip.

[0111] Furthermore, embodiments of this application may also etch the isolation structure on one side of the N-type transistor within the storage region, so that the height of the active structure of the N-type transistor within the storage region is higher than the height of the source structure of the P-type transistor within the storage region, thereby improving the performance of the SRAM device while reducing power consumption.

[0112] The following describes a first method for fabricating a semiconductor structure provided in this application, using a fin-shaped active structure as an example. Specifically, the structure within the logic region is etched on the back side so that the height of the active structure of the front-side transistor located within the logic region is less than the height of the active structure of the back-side transistor. Figure 2 This is a top view of the semiconductor structure in an embodiment of this application. It should be noted that, for ease of understanding, only the active structure, gate structure, and source-drain structure are shown in the top view. Specifically, the AA' direction represents the logic region of the semiconductor structure along the tangential direction of the gate structure; the BB' direction represents the logic region of the semiconductor structure along the tangential direction of the source-drain structure; and the CC' direction represents the semiconductor structure along the tangential direction of the active structure.

[0113] Figures 3 to 8 This is a schematic diagram of the semiconductor structure in the first fabrication process according to an embodiment of this application. Figure 9 This is a schematic diagram of a first embodiment of the semiconductor structure according to this application. Wherein, Figures 3 to 9 (a) is a cross-sectional view of the semiconductor structure along the tangential direction of the gate structure (i.e., the AA' direction). Figures 3 to 9 (b) is a cross-sectional view of the semiconductor structure along the tangential direction of the source-drain structure (i.e., the BB' direction). Figures 3 to 9 (c) is a cross-sectional view of the semiconductor structure along the tangential direction of the active structure (i.e., the CC' direction).

[0114] In one example, the semiconductor fabrication process may include the following steps:

[0115] Step 1: Provide a raw substrate 20 (such as a Si substrate) to obtain the following... Figure 3 The structure shown.

[0116] Step 2: Etch substrate 20 to form first fin structure 111 and second fin structure 121; then fill with oxide to form first isolation structure 21, resulting in... Figure 4 The structure shown includes a first fin structure 111 that may include a first fin structure located within the storage area and a first fin structure located within the logic area.

[0117] Step 3: Based on the first fin-like structure in the two regions, form a first front-side transistor 10 located in the memory region and a second front-side transistor 11 located in the logic region, resulting in the following... Figure 5 The structure shown.

[0118] Understandably, firstly, a portion of the isolation structure 22 can be etched until the first fin structure is exposed; then, the gate region is opened by photolithography, and polysilicon is deposited in the gate region to form the first pseudo-gate structure; then, first sidewalls 22 can be formed on both sides of the first pseudo-gate structure; the first source / drain structure 112 is epitaxially grown based on the first fin structure 111 in the source / drain region, and an interlayer dielectric is deposited on the first source / drain structure 112 to form the first interlayer dielectric layer 113; then, the first pseudo-gate structure is removed, the first gate structure 114 is formed in the gate region, and the first source / drain metal 115 is formed on the first source / drain structure 112; the back-end process of the front transistor is completed to form the first metal interconnect layer 116.

[0119] Since the front-side transistor 10 located in the storage region and the front-side transistor 11 located in the logic region are formed synchronously, therefore Figure 5 The labels of the structures in the front transistor 10 located in the storage region and the front transistor 11 located in the logic region are the same.

[0120] Step 4: Following standard processes, wafer bonding is performed, followed by wafer flipping, substrate removal, and thinning of the first isolation structure 21 to expose the back-side active structure, resulting in the following... Figure 6 The structure shown.

[0121] Understandably, an oxide layer 23 can be deposited on the first metal interconnect layer 116 to form an insulating layer 23. A wafer 24 is bonded to the insulating layer 23 above the insulating layer 23. Then, the substrate is flipped to place the wafer on top. After that, the substrate 20 is removed and the first isolation structure 21 is thinned to expose the second fin structure on the back side.

[0122] Step 5: Form a mask 25 above the storage area to obtain the following... Figure 7 The structure shown.

[0123] Step 6: Based on mask 25, etch the first isolation structure 21 to form the second isolation structure 26 located within the logic region, resulting in... Figure 8 The structure shown.

[0124] Understandably, since the height of the second isolation structure 26 is lower than the height of the first isolation structure 21, the height of the second fin structure 121 located in the logic region is higher than the height of the second fin structure 131 located in the storage region.

[0125] Step 7: Based on the second fin structure 121 located within the logic region, a back-side transistor 12 is formed within the logic region, and based on the second fin structure 131 located within the memory region, a back-side transistor 13 is formed within the memory region, resulting in... Figure 9 The structure shown.

[0126] Understandably, the mask 25 can be removed first, and then the gate region can be opened simultaneously in both regions. Polysilicon can be deposited in the gate region to form a second pseudo-gate structure. Then, second sidewalls 27 can be formed on both sides of the second pseudo-gate structure. The second source / drain structure 122 is epitaxially grown based on the second fin structure 121 at the source / drain region. An interlayer dielectric is deposited on the second source / drain structure 122 to form a second interlayer dielectric layer 123. Then, the second pseudo-gate structure is removed, and a second gate structure 124 is formed in the gate region. A second source / drain metal 125 is formed on the second source / drain structure 122. The back-end process of the back transistor is completed to form a second metal interconnect layer 126.

[0127] Since the back-side transistor 13 located in the storage region and the back-side transistor 12 located in the logic region are formed synchronously, therefore Figure 9 The back-side transistor 13 located in the storage region and the back-side transistor 12 located in the logic region have the same labels for each structure.

[0128] The second type of semiconductor structure is introduced below. Figure 10 This is a top view of the semiconductor structure within the logic or storage region in an embodiment of this application. It should be noted that, for ease of understanding, only the active structure, gate structure, and source / drain structure are shown in the top view. Specifically, AA' is the direction along the tangent of the gate structure; BB' is the direction along the tangent of the source / drain structure; and CC' is the direction along the tangent of the active structure.

[0129] Figure 11 This is a schematic diagram of a second semiconductor structure according to an embodiment of this application. Unlike the first fabrication method, the substrate 20 in the first step is an SOI substrate. Therefore, after the fin structure is formed, the BOX layer 28 in the SOI substrate can be directly used as an isolation layer between the first fin structure and the second fin structure. Figure 11 Only the cross-sectional view of A-A' is shown in the image. Figure 11 In the image, (a) represents a logic transistor, and (b) represents SRAM. It can be seen that... Figure 11 The height of the active structure in a logic transistor is higher than the height of the active structure in an SRAM.

[0130] Furthermore, in some embodiments, the present application embodiments can also isolate the front transistor from the back transistor through a middle dielectric isolation (MDI) layer. Referring to the fabrication method of the first structure described above, unlike the fabrication method of the first structure, in the first step, a first material and a second material can be sequentially deposited on the substrate 20 to form a first material layer and a second material layer; the second material layer, the first material layer, and a portion of the substrate 20 are etched to form a fin structure, where the etched first material layer can serve as a sacrificial layer, and the etched second material layer forms the portion of the fin structure away from the substrate. Moreover, after forming the first source / drain structure in the third step, the sacrificial layer can be removed, and the groove formed after removing the sacrificial layer can be filled with isolation material to form an MDI layer 28, and then the remaining steps can be performed. In this way, the MDI layer can serve as an isolation structure between the front transistor and the back transistor.

[0131] Furthermore, the semiconductor structure provided in this application embodiment can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), and scanning transmission electron microscopy (STEM). Taking TEM as an example, this application embodiment can use TEM slicing to detect the above-mentioned semiconductor structure. The detection method is as follows: take cross-sections of the transistors in the logic region and memory region perpendicular to the direction of the active structure, and measure the height of the active structure on the front and back sides. Four height values ​​can be obtained. As long as the height values ​​of the active structure in the memory region and logic region on either side (front or back) are different, the detection method is satisfied.

[0132] This application provides a semiconductor device, including the semiconductor structure as described in the above embodiments. Specific limitations of the semiconductor structure can be found in the above-described semiconductor structure, and will not be repeated here.

[0133] This application provides an electronic device, including a circuit board and a semiconductor device as described in the above embodiments, wherein the semiconductor device is disposed on the circuit board. The semiconductor device includes the semiconductor structure described above. Specific limitations of the semiconductor structure can be found in the memory described above, and will not be repeated here.

[0134] In the description of the embodiments in this application, the terms "an embodiment," "an example," "a specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the embodiments of this application. In this application, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine different embodiments or examples described in this application, as well as features of different embodiments or examples.

[0135] The above description is merely a preferred embodiment of this application and is not intended to limit the application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A pair of first semiconductor structures are formed on two regions of a substrate along a first direction. The pair of first semiconductor structures includes at least a pair of first active structures and a pair of second active structures. The pair of first active structures are located away from the substrate relative to the pair of second active structures. The two regions include a logic region and a memory region. Isolation structures are formed on two regions of the substrate to expose the pair of first active structures; Based on the pair of first active structures, a pair of front-side transistors are formed, the pair of front-side transistors including a first front-side transistor located in the logic region and a second front-side transistor located in the memory region; The pair of front-side transistors are flipped to expose the pair of second active structures; Based on the pair of second active structures, a pair of back-side transistors are formed, the pair of back-side transistors including a first back-side transistor located in the logic region and a second back-side transistor located in the memory region; After exposing the pair of first active structures and / or the pair of second active structures, the isolation structure located within the logical region is etched such that the height of the active structure located within the logical region is higher than the height of the active structure located within the storage region.

2. The method according to claim 1, characterized in that, After exposing the pair of first active structures, etching the isolation structure located within the logical region includes: A first mask is formed on the isolation structure and the first active structure located within the storage area; Based on the first mask, the isolation structure is etched to a preset height so that the height of the first active structure located in the logical region is higher than the height of the first active structure located in the storage region. The formation of a pair of front-side transistors based on the pair of first active structures includes: The first front-side transistor is formed based on the first active structure located within the logic region, and the second front-side transistor is formed based on the first active structure located within the storage region.

3. The method according to claim 1 or 2, characterized in that, The exposure of the pair of second active structures includes: Remove the substrate; Thin the isolation structure to a predetermined height to expose the pair of second active structures; After exposing the pair of second active structures, etching the isolation structure located within the logical region includes: A second mask is formed on the reserved isolation structure and the second active structure located within the storage area; Based on the second mask, the reserved isolation structure is etched to a preset height, so that the height of the second active structure located in the logical region is higher than the height of the second active structure located in the storage region; The formation of a pair of back-side transistors based on the pair of second active structures includes: The first back-side transistor is formed based on the second active structure located within the logic region, and the second back-side transistor is formed based on the second active structure located within the memory region.

4. The method according to claim 1, characterized in that, The method further includes: In the case where the first front transistor and the first back transistor form a static random access memory (SRAM) and the first front transistor is an N-type transistor, after exposing the pair of first active structures, an isolation structure located in the memory region is etched so that the height of the first active structure located in the memory region is higher than the height of the second active structure located in the memory region.

5. The method according to claim 4, characterized in that, After exposing the pair of first active structures, etching the isolation structure located within the storage region includes: A third mask is formed on the isolation structure and the first active structure located within the logical region; Based on the third mask, the isolation structure is etched to a preset height so that the height of the first active structure located in the storage area is higher than the height of the first active structure located in the logic area; The exposure of the pair of second active structures includes: Remove the substrate; The isolation structure is thinned to a preset height to expose the pair of second active structures, wherein the height of the second active structure located within the storage area is lower than the height of the first active structure located within the storage area.

6. The method according to claim 1, characterized in that, The formation of a pair of first semiconductor structures on two regions of the substrate along a first direction includes: Provide a substrate; A first material layer and a second material layer are formed on the substrate along a first direction; The second material layer, the first material layer, and a portion of the substrate are etched to form the pair of first semiconductor structures, wherein the etched second material layer is the first active structure, the etched portion of the substrate is the second active structure, and the etched first material layer is a sacrificial layer. Before forming a pair of front-side transistors based on the pair of first active structures, the method further includes: Remove the sacrificial layer to form the first groove; A dielectric material is filled into the first groove to form an isolation layer, which is used to isolate the first active structure and the second active structure.

7. A semiconductor structure, prepared using the preparation method according to any one of claims 1 to 6, characterized in that, include: A pair of front-side transistors and a pair of back-side transistors, the pair of front-side transistors including a first front-side transistor located in a logic region and a second front-side transistor located in a memory region, the pair of back-side transistors including a first back-side transistor located in a logic region and a second back-side transistor located in a memory region; wherein the height of the active structure located in the logic region is higher than the height of the active structure located in the memory region.

8. The semiconductor structure according to claim 7, characterized in that, When the first front transistor and the first back transistor form a static random access memory (SRAM), and the first front transistor is an N-type transistor, the height of the first active structure located within the memory region is higher than the height of the second active structure located within the memory region.

9. A semiconductor device, characterized in that, include: The semiconductor structure as described in claim 7 or 8.

10. An electronic device, characterized in that, include: The circuit board and the semiconductor device as described in claim 9, wherein the semiconductor device is disposed on the circuit board.

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