A preparation process of a high-voltage fast recovery diode and the fast recovery diode

Abstract

The embodiment of the present application provides a preparation process of a high-voltage fast recovery diode and the fast recovery diode, the third oxide layer, the fourth oxide layer and the fifth oxide layer are subjected to dry etching until a side wall area is formed on the side wall of the first oxide layer and the second oxide layer close to the third injection area, so that the step of needing to carry out contact hole photolithography in the prior art can be reduced, cost is reduced, and the fast recovery diode with high voltage and fast recovery characteristics is realized.

Description

TECHNICAL FIELD

[0001] The embodiments of the present application belong to the technical field of semiconductor technology, and particularly relate to a preparation process of a high-voltage fast recovery diode and the fast recovery diode. BACKGROUND

[0002] The main performance parameters of the fast recovery diode are high voltage and short reverse recovery time, etc. At present, the high voltage can be improved by terminal structure in addition to epitaxy. The reverse recovery time is reduced by controlling the minority carrier lifetime and forming recombination centers in the drift region of the device by platinum diffusion, electron irradiation or hydrogen (helium) implantation.

[0003] The specific process flow of the fast recovery diode device manufacturing process at present is as follows: N-type substrate wafer preparation → thermal oxide layer growth field oxidation → GR lithography, etching, photoresist removal → GR implantation, oxidation diffusion → AA lithography etching, photoresist removal → P well implantation, P push → N+ lithography, etching, implantation, photoresist removal → dielectric layer deposition (TEOS + silicon nitride + BPSG) → contact hole lithography, wet etching + dry etching, photoresist removal → dielectric layer reflow → platinum source coating → platinum diffusion → aqua regia cleaning → metal deposition → metal lithography, etching, photoresist removal → passivation layer deposition → passivation layer lithography, etching, photoresist removal → back thinning and back gold.

[0004] The fast recovery diode structure using the above manufacturing process at present is shown in the following schematic diagram: Figure 1

[0005] As can be seen from the above process flow and structure schematic diagram, the dielectric layer has three layers, which are the first oxide layer C, the silicon nitride layer B and the third oxide layer A (doped with phosphorus and boron), and the contact hole etching is first wet etching of the third oxide layer, and then dry etching of the silicon nitride layer and the first oxide layer. The process is relatively long, and the cost is relatively high. SUMMARY

[0006] In order to solve or alleviate the problems in the prior art, the embodiments of the present application provide a preparation process of a high-voltage fast recovery diode and the fast recovery diode.

[0007] In a first aspect, the embodiments of the present application provide a preparation process of a high-voltage fast recovery diode, comprising:

[0008] A first oxide layer is grown on the surface of a wafer, and the first oxide layer is subjected to lithography to obtain a first opening;

[0009] A first ion implantation is performed on the wafer at a position corresponding to the first opening to form a first implantation region having a first doping type;

[0010] ​A second oxide layer is formed on the wafer top surface and the top surface of the first oxide layer at the position corresponding to the first opening;

[0011] The first oxide layer and the second oxide layer on the side of the first implantation region are subjected to photoetching to remove the first oxide layer and the second oxide layer on the wafer top surface, and a third oxide layer is grown on the wafer top surface where the first oxide layer and the second oxide layer are removed;

[0012] A second implantation region with the first doping type is formed by a second ion implantation in the region where the third oxide layer is located, and the second implantation region has an overlapping region with the first implantation region, wherein the wafer has the second doping type;

[0013] The first oxide layer and the second oxide layer on the side of the first implantation region away from the second implantation region are subjected to photoetching to remove the first oxide layer and the second oxide layer on the wafer top surface, and a third implantation region with the second doping type is formed by a third ion implantation in the region where the first oxide layer and the second oxide layer are removed;

[0014] The third implantation region is subjected to a push processing, and a fourth oxide layer is formed on the wafer top surface where the third implantation region is located;

[0015] A fifth oxide layer is deposited on the top surfaces of the second oxide layer, the third oxide layer and the fourth oxide layer;

[0016] Dry etching is performed on the third oxide layer, the fourth oxide layer and the fifth oxide layer until a side wall region is formed on the side wall of the first oxide layer and the second oxide layer close to the third implantation region;

[0017] A metal layer is deposited on the wafer top surface of the third oxide layer, the fourth oxide layer and the fifth oxide layer, and on the top surface of the second oxide layer, and photoetching is performed on the metal layer in the regions corresponding to the first implantation region and the third implantation region to form a second opening;

[0018] A passivation layer is deposited on the top surface of the metal layer, and photoetching is performed on the passivation layer to form a third opening in the region where the first implantation region is located, and an electrode is led out through the third opening.

[0019] As a preferred embodiment of the present application, the first implantation region and the second implantation region are of P-type doping type, and the third implantation region and the wafer are of N-type doping type.

[0020] As a preferred embodiment of the present application, the impurities injected by the first and second implantation regions are boron elements, the energy range of the boron elements injected by the first implantation region is 100KeV-500KeV, and the injection dose range is 5E12-5E13; the energy range of the boron elements injected by the second implantation region is 30KeV-120KeV, and the injection dose range is 1E13-1E14.

[0021] As a preferred embodiment of the present application, after the first implantation region is formed, the method further comprises:

[0022] The first implantation region is subjected to a drive-in process, the drive-in temperature is 1100-1250℃, the drive-in time is 200-480 minutes, and the thickness of the second implantation region is 6-12 microns.

[0023] As a preferred embodiment of the present application, after the second implantation region is formed, the method further comprises:

[0024] The second implantation region is subjected to a drive-in process, the drive-in temperature is 1050-1200℃, the drive-in time is 60-180 minutes, and the junction depth of the third implantation region is about 4-8 microns.

[0025] As a preferred embodiment of the present application, the thickness of the first oxide layer is 6000-14000 angstroms, the thickness of the second oxide layer is 15-20k angstroms, the thickness of the fourth oxide layer is 150-350 angstroms, and the thickness of the fifth oxide layer is 1500-3000 angstroms.

[0026] As a preferred embodiment of the present application, after the side wall regions are formed on the side walls of the first and second oxide layers close to the third implantation region, the method further comprises:

[0027] A metal ion sputtering process is performed to form metal ions in the wafer.

[0028] As a preferred embodiment of the present application, after the sixth oxide layer is subjected to photolithography to form a third opening in the region where the first implantation region is located, the method further comprises:

[0029] The back surface of the wafer is subjected to a thinning process, and then a second metal layer is arranged on the back surface of the wafer.

[0030] Compared with the prior art, the embodiment of the present application reduces the need for contact hole photolithography in the prior art by performing dry etching on the third, fourth and fifth oxide layers until the side wall regions are formed on the side walls of the first and second oxide layers close to the third implantation region, thereby reducing costs and realizing a fast recovery diode with high voltage and fast recovery characteristics.

[0031] In a second aspect, the embodiments of the present application further provide a high-voltage fast-recovery diode prepared by the preparation process of any one of the first aspect.

[0032] Compared with the prior art, the high-voltage fast-recovery diode provided by the embodiments of the present application has the same beneficial effects as the technical solutions provided by the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are included to provide a further understanding of the present application, illustrate embodiments of the present application and together with the description given below, serve to explain the present application. The present application is not intended to be unduly limited by the illustrative embodiments and descriptions that follow, which are introduced to explain the principles of the present application. In reference to the drawings:

[0034] Figure 1 is a structural schematic diagram of a high-voltage fast-recovery diode provided by the prior art;

[0035] Figure 2 is a preparation process flowchart of a high-voltage fast-recovery diode provided by the embodiments of the present application;

[0036] Figures 3-15 is a structural schematic diagram of each step of the preparation process of a high-voltage fast-recovery diode provided by the embodiments of the present application. DETAILED DESCRIPTION

[0037] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative work should fall within the scope of protection of the present application.

[0038] In a first aspect, the embodiments of the present application provide a preparation process of a high-voltage fast-recovery diode, comprising:

[0039] Step S01, growing a first oxide layer 02 on the surface of a wafer 01, and performing photoetching on the first oxide layer 02 to obtain a first opening 03;

[0040] It should be noted that the above description refers to Figure 2 and Figure 3, a first oxide layer 02 of 6000A-14000A is formed on the single crystal silicon wafer 01, and then a first opening 03 is formed by etching after a photoetching and a wet etching, and finally the photoresist is removed. The first oxide layer 02 mainly plays a passivation role on the surface of the wafer 01, and the first opening 03 is formed by etching, mainly for ion implantation in the wafer 01 at the position corresponding to the first opening 03.

[0041] Step S02, a first ion implantation is performed on the wafer 01 at the position corresponding to the first opening 03 to form a first implantation region 04 with a first doping type;

[0042] It should be noted that, with reference to Figure 2 and Figure 4 In the embodiment of the present application, P-type ion implantation is performed on the first implantation region 04, and the ion implantation mainly includes boron element, the energy range of the boron element is 100KeV-500KeV, and the dose range is 5E12-5E13.

[0043] After the first implantation region 04 is formed, it further includes:

[0044] The first implantation region 04 is subjected to a push processing, the push temperature is 1100℃-1250℃, the push time is 200 minutes-480 minutes, and the junction depth of the first implantation region 04 is 6-12 microns.

[0045] Step S03, with reference to Figure 2 and Figure 5 A second oxide layer 05 is formed on the surface of the wafer 01 at the position corresponding to the first opening 03 and the upper surface of the first oxide layer 02;

[0046] It should be noted that the oxidation temperature of the second oxide layer 05 is 1000℃-1100℃, the thickness is 15kA-20kA oxide layer, and the main role of the second oxide layer 05 is to passivate the upper surface of the wafer 01 in the region where the first implantation region 04 is located.

[0047] Step S04, the first oxide layer 02 and the second oxide layer 05 on one side of the first implantation region 04 are subjected to photoetching to remove the first oxide layer 02 and the second oxide layer 05 on the upper surface of the wafer 01, and a third oxide layer 06 is grown on the upper surface of the wafer 01 after removing the first oxide layer 02 and the second oxide layer 05;

[0048] It should be noted that, with reference to Figure 2 , Figure 6 and Figure 7In order to implant the second implant region 07, the first oxide layer 02 and the second oxide layer 05 on the side of the first implant region 04 need to be removed by photolithography, and a third oxide layer 06 is pre-grown on the wafer 01 to protect the surface of the wafer 01.

[0049] Step S05: A second ion implantation is performed on the region where the third oxide layer 06 is located to form a second implant region 07 having a first doping type, and the second implant region 07 has an overlapping region with the first implant region 04, wherein the wafer 01 has a second doping type.

[0050] It should be noted that, referring to Figure 2 and Figure 8 , the P-type ion implantation is performed to form the second implant region 07, and the ion implantation mainly includes boron elements, the energy range of the boron elements is 30KeV-120KeV, and the dose range is 1E13-1E14.

[0051] After the second implant region 07 is formed, the following steps are further included:

[0052] The second implant region 07 is subjected to a push processing, the push temperature is 1050-1200℃, and the push time is 60-180 minutes.

[0053] In the embodiment, the first implant region 04 and the second implant region 07 have the same doping type, and both are P-type, and the first implant region 04 and the second implant region 07 have an overlapping region.

[0054] Step S06: The first oxide layer 02 and the second oxide layer 05 on the side of the first implant region 04 away from the second implant region 07 are removed by photolithography, and a third ion implantation is performed on the region where the first oxide layer 02 and the second oxide layer 05 are removed to form a third implant region 08 having a second doping type;

[0055] It should be noted that, referring to Figure 2 and Figure 9 , in order to form the third implant region 08, the first oxide layer 02 and the second oxide layer 05 on the side of the first implant region 04 away from the second implant region 07 need to be removed by photolithography, the third implantation is N-type, and the third implant region 08 is a cutoff ring of a fast recovery diode.

[0056] Step S07: The third implant region 08 is subjected to a push processing, and a fourth oxide layer 09 is formed on the surface of the wafer 01 where the third implant region 08 is located;

[0057] It is to be noted that, referring to Figure 2 and Figure 10 , the third implant region 08 also needs to be advanced, at this time, the third implant region 08 extends towards the first implant region 04 on the side close to the first implant region 04. Subsequently, oxygen is passed to form a fourth oxide layer 09 on the upper surface of the wafer 01, the thickness of the fourth oxide layer 09 is 150A-350A, and the first oxide layer 02 is mainly to passivate the upper surface of the wafer 01 where the third implant region 08 is located.

[0058] Step S08, depositing a fifth oxide layer 10 on the upper surfaces of the second oxide layer 05, the third oxide layer 06 and the fourth oxide layer 09;

[0059] It is to be noted that, referring to Figure 2 and Figure 11 , subsequently, a fifth oxide layer 10 needs to be deposited on the upper surfaces of the second oxide layer 05, the third oxide layer 06 and the fourth oxide layer 09, the thickness of the fifth oxide layer 10 is 1500A-3000A, and the deposition of the fifth oxide layer 10 is performed by a gas phase chemical deposition method. The fifth oxide layer 10 is mainly prepared for forming an oxide layer side wall 11.

[0060] Step S09, dry etching the third oxide layer 06, the fourth oxide layer 09 and the fifth oxide layer 10 until a side wall region 11 is formed on the side walls of the first oxide layer 02 and the second oxide layer 05 close to the third implant region 08;

[0061] It is to be noted that, referring to Figure 2 and Figure 12 , by dry etching an oxide layer with a thickness of 2500A-4000A, an oxide layer side wall 11 is formed on the side walls of the first oxide layer 02 and the second oxide layer 05 close to the third implant region 08.

[0062] The embodiment of the present application reduces the need for contact hole photolithography in the prior art by dry etching the third oxide layer, the fourth oxide layer and the fifth oxide layer until a side wall region is formed on the side walls of the first oxide layer and the second oxide layer close to the third implant region, thereby reducing costs and realizing a fast recovery diode with high voltage and fast recovery characteristics.

[0063] As a preferred embodiment of the present application, referring to Figure 2 and Figure 13 , after the side wall region 11 is formed on the side walls of the first oxide layer 02 and the second oxide layer 05 close to the third implant region 08, the method comprises:

[0064] Performing a metal ion 14 sputtering process to form a metal ion 14 in the wafer 01.

[0065] In the embodiment of the present application, the metal ions 14 are platinum, and the metal ions 14 are formed in the wafer 01 by sputtering treatment and then diffusion of the metal platinum.

[0066] Step S10, removing the third oxide layer 06, the fourth oxide layer 09 and the fifth oxide layer 10 from the upper surface of the wafer 01, the second oxide layer 05 from the upper surface, and depositing the first metal layer 12 on the wafer 01, and performing photolithography on the first metal layer 12 corresponding to the first injection area 04 and the third injection area 08 to form the second opening 13.

[0067] It should be noted that, with reference to Figure 2 , Figure 14 and Figure 15 , the second opening 13 is formed by this step, mainly to isolate the circuit inside the wafer 01 so as not to be induced.

[0068] Step S11, depositing the sixth oxide layer on the upper surface of the metal layer, and performing photolithography on the sixth oxide layer to form the third opening 16 in the first injection area 04, and the electrode is led out through the third opening 16.

[0069] It should be noted that, through the third opening, the circuit inside the wafer 01 can be led out.

[0070] Step S12, thinning the back of the wafer 01, and then setting a second metal layer on the back of the wafer 01.

[0071] In a second aspect, the embodiment of the present application also provides a high-voltage fast recovery diode prepared by the preparation process of any one of the first aspect.

[0072] Compared with the prior art, the beneficial effects of the high-voltage fast recovery diode of the embodiment of the present application are the same as those of the technical solutions provided in the first aspect, which will not be repeated here.

[0073] Finally, it should be pointed out that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A fabrication process of a high-voltage fast-recovery diode, characterized in that, The method comprises the following steps: growing a first oxide layer on a wafer surface and performing photoetching on the first oxide layer to obtain a first opening; performing first ion implantation on the wafer surface corresponding to the first opening to form a first implantation region with a first doping type; generating a second oxide layer on the wafer surface and the upper surface of the first oxide layer corresponding to the first opening; performing photoetching on the first oxide layer and the second oxide layer on one side of the first implantation region to remove the first oxide layer and the second oxide layer on the wafer surface, and growing a third oxide layer on the wafer surface from which the first oxide layer and the second oxide layer are removed; performing second ion implantation on the region where the third oxide layer is located to form a second implantation region with the first doping type, the second implantation region having an overlapping region with the first implantation region, wherein the wafer has a second doping type; performing photoetching on the first oxide layer and the second oxide layer on the side of the first implantation region away from the second implantation region to remove the first oxide layer and the second oxide layer on the wafer surface, and performing third ion implantation on the region from which the first oxide layer and the second oxide layer are removed to form a third implantation region with the second doping type; performing a drive-in treatment on the third implantation region while forming a fourth oxide layer on the wafer surface where the third implantation region is located; depositing a fifth oxide layer on the upper surfaces of the second oxide layer, the third oxide layer and the fourth oxide layer; performing dry etching on the third oxide layer, the fourth oxide layer and the fifth oxide layer until a side wall region is formed on the side wall of the first oxide layer and the second oxide layer close to the third implantation region; depositing a first metal layer on the wafer surface from which the third oxide layer, the fourth oxide layer and the fifth oxide layer are removed, and on the upper surface of the second oxide layer, and performing photoetching on the first metal layer corresponding to the regions where the first implantation region and the third implantation region are located to form a second opening; depositing a sixth oxide layer on the upper surface of the first metal layer, and performing photoetching on the sixth oxide layer to form a third opening in the region where the first implantation region is located, and leading out an electrode through the third opening.

2. The process for fabricating a high voltage fast recovery diode as claimed in claim 1, wherein, The first implantation region and the second implantation region are P-type doping type, and the third implantation region and the wafer are N-type doping type.

3. The process for fabricating a high voltage fast recovery diode as claimed in claim 2 wherein, The implanted impurities of the first implantation region and the second implantation region are elemental boron, the energy range of the boron element implanted in the first implantation region is 100KeV-500KeV, and the implantation dose range is 5E12-5E13; the energy range of the boron element implanted in the second implantation region is 30KeV-120KeV, and the implantation dose range is 1E13-1E14.

4. The process for fabricating a high voltage fast recovery diode as claimed in claim 1, wherein, After the first implantation region is formed, the method further comprises the following steps: performing a drive-in treatment on the first implantation region, the drive-in temperature is 1100℃-1250℃, the drive-in time is 200 minutes-480 minutes, and the thickness of the second implantation region is 6-12 microns.

5. The process for fabricating a high voltage fast recovery diode as claimed in claim 1, wherein, After the second implantation region is formed, the method further comprises the following steps: performing a drive-in treatment on the second implantation region, the drive-in temperature is 1050℃-1200℃, the drive-in time is 60 minutes-180 minutes, and the junction depth of the third implantation region is about 4-8 microns.

6. The process for fabricating a high voltage fast recovery diode as claimed in claim 1, wherein, The first oxide layer has a thickness of 6000A-14000A, the second oxide layer has a thickness of 15kA-20kA, the fourth oxide layer has a thickness of 150A-350A, and the fifth oxide layer has a thickness of 1500A-3000A.

7. The process for fabricating a high voltage fast recovery diode as claimed in claim 1, wherein, The method further comprises, after forming the sidewall regions on the sidewalls of the first and second oxide layers adjacent to the third implant region: A metal ion sputtering process is performed to form metal ions in the wafer.

8. The process for fabricating a high voltage fast recovery diode as claimed in claim 1, wherein, The method further comprises, after performing the photolithography on the sixth oxide layer to form the third opening in the region where the first implant region is located: A thinning process is performed on the back surface of the wafer, and then a second metal layer is arranged on the back surface of the wafer.

9. A high voltage fast recovery diode, characterized by, The method is prepared by the preparation process according to any one of claims 1-8.

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