Non-volatile memory cell structure and forming method thereof

Abstract

In an embodiment of the invention, a ferroelectric random access memory (FeRAM) cell may include an oxide insertion layer between an electron barrier layer and a metal glue layer of a source / drain region of the FeRAM cell. The oxide insertion layer may improve thermal stability of the electron barrier layer and minimize or prevent dissociation and / or outward diffusion of the electron barrier layer at high processing temperatures. Therefore, the oxide insertion layer can enable the metal glue layer to be formed on the electron barrier layer with low surface roughness, which can enable the adhesive force between the metal glue layer of the source / drain region and the source / drain electrode to be increased. In this manner, the oxide insertion layer may enable the FeRAM cell to achieve low resistance and / or may reduce the likelihood of failure in the FeRAM cell, and the like.

Description

Technical Field

[0001] The embodiments of the present invention relate to a non-volatile memory cell structure and a forming method thereof. Background Art

[0002] A ferroelectric random access memory (FeRAM) cell is a random access storage unit that utilizes a ferroelectric field effect transistor (FeFET) including a ferroelectric (FE) layer to selectively store information based on the polarization of the ferroelectric layer. For example, a first voltage may be applied to a gate structure of the FeFET to polarize the ferroelectric layer into a first polarization configuration corresponding to a programmed state of the FeRAM cell, and a second voltage may be applied to the gate structure to polarize the ferroelectric layer into a second polarization configuration corresponding to an erased state of the FeRAM cell. Summary of the invention

[0003] According to one embodiment of the present invention, a non-volatile memory cell structure includes a bottom gate electrode, a memory layer, a metal oxide channel layer, and a plurality of source / drain regions. The memory layer is located above the bottom gate electrode. The metal oxide channel layer is located above the memory layer. A plurality of source / drain regions are located in a dielectric layer above the metal oxide channel layer. A source / drain region among the plurality of source / drain regions includes: an electron barrier layer located on the metal oxide channel layer; an oxide insertion layer located on the electron barrier layer; a metal glue layer located on the oxide insertion layer; and a source / drain electrode located on the metal glue layer.

[0004] According to one embodiment of the present invention, a method for forming a nonvolatile memory cell structure comprises the following steps. A bottom gate electrode of the nonvolatile memory cell structure is formed. A ferroelectric layer of the nonvolatile memory cell structure is formed above the bottom gate electrode. A metal oxide channel layer of the nonvolatile memory cell structure is formed above the ferroelectric layer. A dielectric layer is formed above the metal oxide channel layer. A groove is formed in the dielectric layer to expose the metal oxide channel layer through the groove. An electron barrier layer is formed on the metal oxide channel layer in the groove. An oxide insertion layer is formed on the electron barrier layer in the groove. A metal glue layer is formed on the oxide insertion layer in the groove. A source / drain electrode of the nonvolatile memory cell structure is formed on the metal glue layer.

[0005] According to one embodiment of the present invention, a nonvolatile memory cell structure includes a seed layer, a ferroelectric layer, a metal oxide channel layer, and a plurality of source / drain regions. The ferroelectric layer is located above the seed layer. The metal oxide channel layer is located above the ferroelectric layer. A plurality of source / drain regions are located in a dielectric layer above the metal oxide channel layer. A source / drain region among the plurality of source / drain regions includes: an electron barrier layer located on the metal oxide channel layer; an oxide insertion layer located on the electron barrier layer; a metal glue layer located on the oxide insertion layer; and a source / drain electrode located on the metal glue layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features in the drawings are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1 is a diagram of an example environment in which the systems and / or methods described herein may be implemented.

[0008] Figure 2 is a diagram of an example nonvolatile memory cell structure described herein.

[0009] Figure 3A and Figure 3B is a graph of an example of the surface roughness of the metal paste layer described herein.

[0010] FIG. 4A to FIG. 4O is a diagram of an example implementation of a structure for forming a nonvolatile memory cell as described herein.

[0011] FIG. 5A to FIG. 5D is a diagram of examples of elemental compositions of source / drain electrodes described herein.

[0012] Figure 6 is a graph of examples of resistivity of source / drain electrodes described herein.

[0013] Figure 7 is a diagram of an example of the crystal phase composition of the source / drain electrodes described herein.

[0014] Figure 8 is a diagram of an example nonvolatile memory cell structure described herein.

[0015] FIG. 9A to FIG. 9G is a diagram of an example implementation of a structure for forming a nonvolatile memory cell as described herein.

[0016] Fig.10 is a diagram of a portion of an example semiconductor device described herein.

[0017] Fig.11 is a diagram of example components of the devices described herein.

[0018] Fig.12 is a flow chart of an exemplary process associated with forming the ferroelectric nonvolatile memory described herein. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different features of the provided target. Specific examples of components and arrangements are described below to simplify the disclosure. Of course, these are only examples and are not intended to be limiting. For example, the following description of forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed to be in direct contact, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. The same reference number refers to the same component or similar components, and unless otherwise explicitly stated, the same material composition and the same function are assumed for components with the same reference number.

[0020] In addition, for ease of description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and the like may be used herein to describe the relationship of one component or feature shown in a figure to another (other) component or feature. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figure. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly. Components with the same reference number refer to the same component, and unless otherwise expressly indicated, components with the same reference number are assumed to have the same material composition and the same thickness range.

[0021] In some cases, a ferroelectric random access memory (FeRAM) cell structure may include a metal oxide channel layer (e.g., a channel layer comprising a metal oxide material or a metal oxide semiconductor material) located above a ferroelectric layer and a plurality of source / drain regions located above the metal oxide channel layer. The use of a metal oxide channel layer may enable the FeRAM cell structure to achieve reduced current leakage relative to an elemental semiconductor channel or a III-V compound semiconductor channel. However, the source / drain region may include one or more conductive metal materials, and the metal oxide material may be susceptible to electron migration from the source / drain region. Electron migration may cause an increase in contact resistance between the metal oxide channel layer and the source / drain region.

[0022] In some cases, an electron barrier layer may be included between the metal oxide channel layer and the source / drain region to minimize or prevent electron migration between the metal oxide channel layer and the source / drain region. However, the electron barrier layer may include one or more materials that are prone to dissociation and / or outward diffusion at high processing temperatures. When a metal glue layer is deposited on the electron barrier layer to prepare for forming source / drain electrodes in the source / drain region, the material of the metal glue layer may be deposited at a high deposition temperature (e.g., approximately 350 degrees Celsius to approximately 800 degrees Celsius or greater than 800 degrees Celsius). The high deposition temperature may cause the dissociation and / or outward diffusion of the electron barrier layer, which may result in an increase in the surface roughness of the metal glue layer and a reduction in the adhesion between the metal glue layer and the source / drain electrode. This may result in the source / drain electrodes not being able to adhere to the underlying metal oxide channel layer and / or may result in the formation of voids or other types of discontinuities in the source / drain electrodes, which may increase resistance in the FeRAM cell and / or render the FeRAM cell inoperable.

[0023] In some embodiments described herein, the FeRAM cell may include an oxide insertion layer between the electron barrier layer and the metal paste layer in the source / drain region of the FeRAM cell. The oxide insertion layer may improve the thermal stability of the electron barrier layer and minimize or prevent the dissociation and / or outward diffusion of the electron barrier layer at high processing temperatures. Therefore, the oxide insertion layer may enable the metal paste layer to be formed on the electron barrier layer with a low surface roughness, which may increase the adhesion between the metal paste layer in the source / drain region and the source / drain electrode. In this way, the oxide insertion layer may enable the FeRAM cell to achieve low resistance and / or may reduce the possibility of failure in the FeRAM cell, etc.

[0024] In addition, in some embodiments described herein, quasi-atomic layer deposition (quasi-ALD) technology can be used to form source / drain electrodes in the source / drain region to reduce the bus resistance of the FeRAM cell, thereby improving the operating efficiency of the FeRAM cell. The quasi-ALD technology includes using a chemical vapor deposition (CVD) tool, in which a tungsten pulse-purge (PPW) process is performed in a manner similar to ALD. Multiple tungsten (W) precursor gas inflow pulses are performed during the duration of the continuous hydrogen (H2) reaction gas inflow, wherein the tungsten precursor gas inflow pulses are separated in time by multiple nitrogen (N2) gas purges. The quasi-ALD technology described herein can increase a specific crystalline phase in the source / drain electrode, which can enable the source / drain electrode to achieve a larger grain size than when the quasi-ALD technology is not used. The larger grain size enables the FeRAM cell to achieve a reduced bus resistance.

[0025] Figure 1 1 is a diagram of an example environment 100 in which the systems and / or methods described herein may be implemented. Figure 1 As shown in , the example environment 100 may include a plurality of semiconductor processing tools 102-112 and a wafer / die transport tool 114. The plurality of semiconductor processing tools 102-112 may include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, a plating tool 112, and / or another type of semiconductor processing tool. The tools included in the example environment 100 may be included in a semiconductor clean room, a semiconductor foundry, a semiconductor processing facility, and / or a manufacturing facility, among other facilities.

[0026] Deposition tool 102 is a semiconductor processing tool that includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer on a substrate (e.g., a wafer). In some embodiments, deposition tool 102 includes a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-density plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, a low-pressure CVD (LPCVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or another type of CVD tool. In some embodiments, deposition tool 102 includes a physical vapor deposition (PVD) tool (e.g., a sputtering tool or another type of PVD tool). In some implementations, deposition tool 102 includes an epitaxial tool configured to form layers and / or regions of a device by epitaxial growth. In some implementations, example environment 100 includes multiple types of deposition tools 102 .

[0027] The exposure tool 104 is a semiconductor processing tool capable of exposing the photoresist layer to a radiation source, such as an ultraviolet (UV) light source (e.g., a deep UV light source, an extreme UV (EUV) light source, and / or the like), an x-ray source, an electron beam (e-beam) source, and / or the like. The exposure tool 104 may expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern may include one or more semiconductor device layer patterns for forming one or more semiconductor devices, may include patterns for forming one or more structures of a semiconductor device, may include patterns for etching various portions of a semiconductor device, and / or the like. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0028] The developing tool 106 is a semiconductor processing tool capable of developing the photoresist layer that has been exposed to the radiation source to develop the pattern transferred to the photoresist layer from the exposure tool 104. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by dissolving the exposed portions or the unexposed portions of the photoresist layer using a chemical developer.

[0029] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, wafer, or semiconductor device. For example, the etching tool 108 may include a wet etching tool, a dry etching tool, and / or the like. In some embodiments, the etching tool 108 includes a chamber filled with an etchant, and the substrate is placed in the chamber for a specific period of time to remove a specific amount of one or more portions of the substrate. In some embodiments, the etching tool 108 may use plasma etching or plasma assisted etching to etch one or more portions of the substrate, which may involve isotropic etching or directional etching of the one or more portions using an ionized gas.

[0030] The planarization tool 110 is a semiconductor processing tool capable of grinding or planarizing various layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or another type of planarization tool that grinds or planarizes a layer or surface of a deposited material or a plated material. The planarization tool 110 may grind or planarize the surface of a semiconductor device using a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive grinding). The planarization tool 110 may utilize abrasive and corrosive chemical slurries in combination with a polishing pad and a retaining ring (e.g., typically having a larger diameter than the semiconductor device). The polishing pad and the semiconductor device may be pressed together by a dynamic polishing head and held in place by a retaining ring. The dynamic polishing head may rotate using different rotation axes to remove material and smooth any irregular topography of the semiconductor device, thereby flattening or planarizing the semiconductor device.

[0031] The plating tool 112 is a semiconductor processing tool capable of plating a substrate (e.g., a wafer, a semiconductor device, and / or the like) or a portion of a substrate with one or more metals. For example, the plating tool 112 may include a copper plating device, an aluminum plating device, a nickel plating device, a tin plating device, a compound material or alloy (e.g., tin-silver, tin-lead, and / or the like) plating device, and / or a plating device for one or more other types of conductive materials, metals, and / or similar types of materials.

[0032] The wafer / die transporter 114 includes a mobile robot, a robotic arm, a tram or rail car, an overhead hoist transport (OHT) system, an automated materially handling system (AMHS), and / or another type of device configured to transport substrates and / or semiconductor devices between semiconductor processing tools 102-112, between processing chambers of the same semiconductor processing tool, and / or to transport substrates and / or semiconductor devices to and from other locations (e.g., wafer racks, storage chambers, and / or the like). In some embodiments, the wafer / die transporter 114 may be a programmed device configured to travel a specific path and / or may be semi-automatically or automatically operated. In some embodiments, the example environment 100 includes multiple wafer / die transporters 114.

[0033] For example, the wafer / die transporter 114 may be included in a cluster tool or another type of tool including multiple processing chambers, and may be configured to transport substrates and / or semiconductor devices between the multiple processing chambers, between a processing chamber and a buffer area, between a processing chamber and an interface tool (e.g., an equipment front end module (EFEM)), and / or between a processing chamber and a transport carrier (e.g., a front opening unified pod (FOUP)), etc. In some embodiments, the wafer / die transporter 114 may be included in a multi-chamber (or cluster) deposition tool 102, which may include a pre-cleaning process chamber (e.g., for cleaning or removing oxides, oxidation, and / or other types of contaminants or byproducts from substrates and / or semiconductor devices) and multiple types of deposition process chambers (e.g., process chambers for depositing different types of materials, process chambers for performing different types of deposition operations). In some embodiments, the wafer / die transporter 114 is configured to transport substrates and / or semiconductor devices between processing chambers of the deposition tool 102 without breaking or removing the vacuum (or at least partial vacuum) between the processing chambers and / or between processing operations in the deposition tool 102 described herein.

[0034] In some embodiments, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport 114 may perform one or more semiconductor processing operations described herein. For example, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport 114 may form a bottom gate electrode of a nonvolatile memory cell structure; a ferroelectric layer of the nonvolatile memory cell structure may be formed over the bottom gate electrode; a metal oxide channel layer of the nonvolatile memory cell structure may be formed over the ferroelectric layer; a dielectric layer may be formed over the metal oxide channel layer; a recess may be formed in the dielectric layer to expose the metal oxide channel layer through the recess; an electron barrier layer may be formed on the metal oxide channel layer in the recess; an oxide insertion layer may be formed on the electron barrier layer in the recess; a metal glue layer may be formed on the oxide insertion layer in the recess; and / or a source / drain electrode of the nonvolatile memory cell structure may be formed on the metal glue layer, etc. In some implementations, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport tool 114 may implement a combination of FIG. 4A to FIG. 4O , FIG. 9A to FIG. 9G and / or Fig.12 One or more of the described semiconductor processing operations, as well as other semiconductor processing operations.

[0035] Figure 1 The number and arrangement of devices shown in are provided as one or more examples. Figure 1 There may be additional devices, fewer devices, different devices, or devices arranged in a different manner than those shown in . In addition, Figure 1 Two or more of the devices shown in the figure may be implemented in a single device, or Figure 1 The single device shown in can be implemented as multiple distributed devices. Additionally or alternatively, one or more devices of the example environment 100 can implement one or more functions described as being implemented by another set of devices of the example environment 100.

[0036] Figure 2 is a diagram of an exemplary nonvolatile memory cell structure 200 described herein. The nonvolatile memory cell structure 200 may include a ferroelectric nonvolatile memory cell structure (e.g., a FeRAM cell). The nonvolatile memory cell structure 200 described herein may include an oxide insertion layer, which enables a metal glue layer to be formed on an electron barrier layer of the nonvolatile memory cell structure 200 with a low surface roughness, which may increase the adhesion between the metal glue layer and the source / drain electrodes in the source / drain regions of the nonvolatile memory cell structure 200. In this way, the oxide insertion layer included in the nonvolatile memory cell structure 200 may enable the nonvolatile memory cell structure 200 to achieve low resistance and / or may reduce the possibility of failure in the nonvolatile memory cell structure 200, etc.

[0037] like Figure 2As shown in FIG. 1 , a nonvolatile memory cell structure 200 may include an isolation layer 202 and a bottom gate electrode 204 included in the isolation layer 202. The bottom gate electrode 204 may also be referred to as a buried electrode and may be a gate of the nonvolatile memory cell structure 200. The bottom gate electrode 204 may be electrically coupled to a word line of a nonvolatile memory array including the nonvolatile memory cell structure 200. The isolation layer 202 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluoride-doped silicate glass (FSG), low-k dielectric materials, and / or another suitable electrically insulating material. The bottom gate electrode 204 may include one or more conductive metal materials having a relatively low coefficient of thermal expansion (CTE). Examples of such conductive metal-containing materials include platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), iron (Fe), nickel (Ni), cobalt (Co), chromium (Cr), beryllium (Be), antimony (Sb), iridium (Ir), molybdenum (Mo), osmium (Os), thorium (Th), vanadium (V) and / or their alloys, etc.

[0038] The nonvolatile memory cell structure 200 may include a stress relief layer 206 located above and / or on the bottom gate electrode 204. The stress relief layer 206 may include an oxide-containing material configured to reduce stress caused by thermal expansion and / or contraction in the nonvolatile memory cell structure 200 and / or reduce other types of stress experienced by the nonvolatile memory cell structure 200. Examples of oxide-containing materials for the stress relief layer 206 include tantalum pentoxide (Ta2O5), potassium oxide (K2O), rubidium oxide (Rb2O), strontium oxide (SrO), barium oxide (BaO), amorphous vanadium oxide (α-V2O3), amorphous chromium oxide (α-Cr2O3), amorphous gallium oxide (α-Ga2O3), amorphous iron oxide (α-Fe2O3), amorphous titanium oxide (α-Ti2O3), amorphous indium oxide (α-In2O3), yttrium aluminum perovskite (yttrium aluminum perovskite), and amorphous vanadium oxide (α-V2O3). aluminumperovskite) (YAlO3 or YAP), bismuth oxide (Bi2O3), ytterbium oxide (Yb2O3), dysprosium oxide (Dy2O3), gadolinium oxide (Gd2O3), strontium titanium oxide (SrTiO3), dysprosium scandium oxide (DyScO3), terbium scandium oxide (TbScO3), gadolinium scandium oxide (GdScO3), neodymium scandium oxide (NdScO3), neodymium gallium oxide (NdGaO3) and / or lanthanum strontium tantalum aluminate (tantalum lanthanum strontium aluminate) (LaSrAlTaO3 or LSAT), etc. In some embodiments, the stress relief layer 206 includes a bilayer epitaxial structure including lanthanum strontium manganese oxide (LaSrMnO3 or LSMO) and SrTiO3, LSMO and DyScO3, LSMO and TbScO3, LSMO and GdScO3, LSMO and NdScO3, LSMO and NdGaO3, and / or LSMO and LSAT, etc. In some embodiments, the thickness of the stress relief layer 206 is included in the range of approximately 0.5 nanometers to approximately 5 nanometers. However, other values ​​of the range are also within the scope of the present disclosure.

[0039] The nonvolatile memory cell structure 200 may include a seed layer 208 located above and / or on the stress release layer 206. The seed layer 208 may provide a substrate on which the ferroelectric layer 210 of the nonvolatile memory cell structure 200 is formed. The seed layer 208 may include a single-layer structure or a multi-layer structure. The seed layer 208 may mainly have a cubic phase, a tetragonal phase, and / or an orthorhombic phase (for example, wherein the cubic phase, the tetragonal phase, and / or the orthorhombic phase are greater than the monoclinic phase). The seed layer 208 may include one or more oxide materials, such as zirconium oxide (ZrO or ZrO2), yttrium oxide (Y2O3), hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium zirconium oxide (HfxZr1-xOy) and / or another oxide material. In some embodiments, the thickness of the seed layer 208 is included in the range of approximately 0.1 nanometers to approximately 5 nanometers. However, other values ​​of the range are also within the scope of the present disclosure.

[0040] The ferroelectric layer 210 may be included on and / or above the seed layer 208. The ferroelectric layer 210 may include a ferroelectric material having oxygen vacancy and / or including primarily cubic, tetragonal, and / or orthorhombic phases (e.g., wherein the cubic, tetragonal, and / or orthorhombic phases are greater than the monoclinic phase). Examples include hafnium oxide (e.g., HfO or HfO2), zirconium oxide (e.g., ZrO2), HfZrO or HZO (e.g., HfxZr1-xOy, where x is 0 to 1, such as Hf0.5Zr0.5O2), hafnium silicon oxide (e.g., HfSiO), hafnium lanthanum oxide (e.g., HfLaO), aluminum nitride (AlN), aluminum scandium nitride (e.g., AlScN), PBT (e.g., PbZrO3), lead zirconate titanate (PZT) (e.g., Pb[ZrxTi1-x]O3 (0≤x≤1)), lanthanum-doped lead zirconate titanate (PZT), and poly(vinylpyrrolidone) oxide (e.g., poly(vinylpyrrolidone) oxide (e.g., poly(vinylpyrrolidone) oxide). zirconatetitanate, PLZT) (e.g., Pb1-xLaxZr1-yTiyO3), barium titanate (e.g., BaTiO3), lead titanate (e.g., PbTiO3), lead metaniobate (e.g., PbNb2O6), lithium niobate (e.g., LiNbO3), lithium tantalate (e.g., LiTaO3), lead magnesium niobate (PMN) (e.g., PbMg1-3Nb2 / 3O3), lead scandium tantalate (PST) (e.g., PbSc1 / 2Ta1 / 2O3), strontium bismuth tantalate (SBT) (e.g., SrBi2Ta2O9), sodium bismuth titanate (BNT) (e.g., Bi1 / 2Na1 / 2TiO3), and / or combinations thereof, etc. In some embodiments, the ferroelectric material may include dopants, such as scandium (Sc), lanthanum (La), calcium (Ca), barium (Ba), yttrium (Y), strontium (Sr), and / or gadolinium (Gd), etc. In some implementations, the thickness of the ferroelectric layer 210 is included in the range of approximately 0.1 nanometers to approximately 100 nanometers. However, other values ​​of the range are also within the scope of the present disclosure.

[0041] The nonvolatile memory cell structure 200 may include a barrier layer 212 located above and / or on the ferroelectric layer 210. The barrier layer 212 may include a combination of silicon (Si) and hafnium oxide (HfO2). The barrier layer 212 may have a silicon to hafnium oxide ratio greater than approximately 1:10. However, other values ​​are within the scope of the present disclosure. Additionally and / or alternatively, the barrier layer 212 may include one or more of silicon (Si), magnesium (Mg), aluminum (Al), lanthanum (La), yttrium oxide (Y2O3), nitrogen (N), calcium (Ca), scandium (Sc), strontium (Sr), and / or gadolinium (Gd), among other materials. In some embodiments, the oxygen to zirconium concentration or the oxygen to hafnium concentration at the interface between the barrier layer 212 and the ferroelectric layer 210 may be greater than or equal to approximately 1:1. However, other values ​​are within the scope of the present disclosure. In some embodiments, the thickness of barrier layer 212 is included in the range of approximately 0.1 nanometers to approximately 10 nanometers. However, other values ​​of the range are also within the scope of the present disclosure.

[0042] The nonvolatile memory cell structure 200 may include a metal oxide channel layer 214 located above and / or on the barrier layer 212. The metal oxide channel layer 214 may include one or more metal oxide materials or metal oxide semiconductor materials. Examples include indium gallium zinc oxide (InGaZnO or IGZO), amorphous IGZO (α-IGZO), and / or tin gallium zinc oxide (SnGaZnO or SGZO), among others. In some implementations, hafnium (Hf), zirconium (Zr), titanium (Ti), aluminum (Al), tantalum (Ta), strontium (Sr), barium (Ba), scandium (Sc), magnesium (Mg), lanthanum (La), and / or gadolinium (Gd) may be used in place of gallium in the metal oxide channel layer 214 to achieve a lower concentration of oxygen vacancies and / or to achieve lower surface states.

[0043] The nonvolatile memory cell structure 200 may include source / drain regions 216 and 218 located above and / or on the metal oxide channel layer 214. The bottom gate electrode 204, the ferroelectric layer 210, the metal oxide channel layer 214, and the source / drain regions 216 and 218 may correspond to a ferroelectric field effect transistor (FeFET) of the nonvolatile memory cell structure 200. The source / drain regions may be referred to as a source or a drain, individually or collectively, depending on the context. The source / drain region 216 may be included in a dielectric layer 220 above the metal oxide channel layer 214. The dielectric layer 220 may include one or more dielectric materials, such as oxides, nitrides, silicon oxide (SiOx), silicon nitride (SixNy), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable electrically insulating material. In some implementations, the height or thickness of source / drain regions 216 and / or 218 can be included in a range of approximately 10 nanometers to approximately 600 nanometers. However, other values ​​of the range are also within the scope of the present disclosure.

[0044] To transition the nonvolatile memory cell structure 200 to a programmed state, a first gate voltage (e.g., a positive gate voltage +VG) may be applied to the bottom gate electrode 204. This biases the electron charge carriers of the electron / hole pairs in the ferroelectric layer 210 toward the bottom gate electrode 204. A zero voltage (0 volts) may be applied to the source / drain region 216, and the source / drain region 218 may be grounded. This places the metal oxide channel layer 214 in a non-conductive state, thereby biasing the hole charge carriers of the electron / hole pairs in the ferroelectric layer 210 toward the metal oxide channel layer 214.

[0045] To transition the nonvolatile memory cell structure 200 to the erased state, a second gate voltage (e.g., a negative gate voltage -VG) may be applied to the bottom gate electrode 204. A zero voltage (0 volts) may be applied to the source / drain region 216, and the source / drain region 218 may be grounded. This places the metal oxide channel layer 214 in a conductive state. This biases the hole charge carriers of the electron / hole pairs in the ferroelectric layer 210 toward the bottom gate electrode 204 and biases the electron charge carriers of the electron / hole pairs in the ferroelectric layer 210 toward the metal oxide channel layer 214.

[0046] The source / drain regions 216 and 218 may each include an electron barrier layer 222, an oxide insertion layer 224 located on and / or on the electron barrier layer 222, a metal paste layer 226 located on and / or on the oxide insertion layer 224, and a source / drain electrode 228 located on and / or on the metal paste layer 226. The electron barrier layer 222 may be directly included on the metal oxide channel layer 214 and between the metal oxide channel layer 214 and the oxide insertion layer 224, the metal paste layer 226, and the source / drain electrode 228. The electron barrier layer 222 may also extend along the sidewalls of the source / drain electrode 228, so that the electron barrier layer 222 is directly included on the dielectric layer 220 and between the dielectric layer 220 and the oxide insertion layer 224, the metal paste layer 226, and the source / drain electrode 228.

[0047] The electron barrier layer 222 may be included to minimize or prevent electron migration between the metal oxide channel layer 214 and the source / drain electrodes 228 of the source / drain regions 216 and / or 218. The electron barrier layer 222 may enable tuning of the Schottky barrier height between the source / drain electrodes 228 and the metal oxide channel layer 214 to improve the electrical performance of the non-volatile memory cell structure 200. Additionally and / or alternatively, the electron barrier layer 222 may provide resistance to the penetration of carbon, hydrogen, and / or nitrogen downward into the metal oxide channel layer 214. In some embodiments, the thickness of the electron barrier layer 222 may be included in the range of approximately 1 nanometer to approximately 20 nanometers. If the thickness of the electron barrier layer 222 is less than approximately 1 nanometer, voids and / or other interruptions may occur in the electron barrier layer 222, thereby reducing the electron barrier performance of the electron barrier layer 222. Selecting a thickness greater than approximately 20 nanometers for the electron barrier layer 222 may result in an increase in the resistance of the source / drain regions 216 and / or 218, which may result in a decrease in the switching speed of the non-volatile memory cell structure 200. Selecting a thickness within a range of approximately 1 nanometer to approximately 20 nanometers for the electron barrier layer 222 enables the electron barrier layer 222 to provide sufficient electron migration resistance while enabling the source / drain regions 216 and / or 218 to achieve sufficiently low resistance. However, other values ​​of the thickness of the electron barrier layer 222 and ranges other than approximately 1 nanometer to approximately 20 nanometers are also within the scope of the present disclosure.

[0048] In some embodiments, the electron barrier layer 222 may include a binary conductive metal oxide, such as indium oxide (InO), zinc oxide (ZnO), and / or tin oxide (SnO), etc. In some embodiments, the electron barrier layer 222 may include a ternary conductive metal oxide, such as indium zinc oxide (InZnO or IZO), aluminum zinc oxide (AlZnO or AZO), and / or indium tin oxide (InSnO or ITO), etc. In some embodiments, the electron barrier layer 222 may include another type of conductive metal oxide, such as tin IGZO (SnIGZO) and / or magnesium IGZO (MgIGZO), etc.

[0049] The oxide insertion layer 224 may be included on the metal oxide channel layer 214 and between the electron barrier layer 222 and the metal paste layer 226 and the source / drain electrode 228. The oxide insertion layer 224 may also extend along the sidewalls of the source / drain electrode 228, so that the oxide insertion layer 224 is included between the dielectric layer 220 and the sidewalls of the source / drain electrode 228.

[0050] The oxide insertion layer 224 may be included to reduce, minimize, and / or prevent intermixing between the electron barrier layer 222 and the metal paste layer 226. Since the oxide insertion layer 224 may protect the electron barrier layer 222 from and / or during high temperature semiconductor processing operations associated with the nonvolatile memory cell structure 200, the oxide insertion layer 224 may reduce, minimize, and / or prevent intermixing between the electron barrier layer 222 and the metal paste layer 226. The oxide insertion layer 224 may reduce, minimize, and / or prevent outdiffusion and / or dissociation of the electron barrier layer 222, which may otherwise occur due to high temperature semiconductor processing operations associated with the nonvolatile memory cell structure 200 and which may otherwise cause intermixing of the electron barrier layer 222 and the metal paste layer 226. The intermixing of the electron barrier layer 222 and the metal paste layer 226 may otherwise result in high surface roughness in the metal paste layer 226, which may result in low binding energy between the metal paste layer 226 and the source / drain electrodes 228. The low binding energy may otherwise result in delamination between the metal paste layer 226 and the source / drain electrodes 228 and failure of the nonvolatile memory cell structure 200. The oxide insertion layer 224 may enable the metal paste layer 226 to achieve low surface roughness (e.g., due to minimizing or preventing the intermixing of the electron barrier layer 222 and the metal paste layer 226), which may increase the adhesion between the metal paste layer 226 and the source / drain electrodes 228. Therefore, the oxide insertion layer 224 may reduce, minimize, and / or prevent delamination between the metal paste layer 226 and the source / drain electrodes 228 and / or failure of the nonvolatile memory cell structure 200.

[0051] In some embodiments, the thickness of the oxide insertion layer 224 may be included in a range of approximately 0.5 angstroms (e.g., one monolayer) to approximately 5 nanometers. If the thickness of the oxide insertion layer 224 is less than approximately 0.5 angstroms, voids and / or other discontinuities may occur in the oxide insertion layer 224, thereby causing intermixing between the electron barrier layer 222 and the metal paste layer 226. Selecting a thickness greater than approximately 5 nanometers for the oxide insertion layer 224 may result in an increase in the resistance of the source / drain regions 216 and / or 218 (e.g., due to less available space for the source / drain electrodes 228), which may result in a decrease in the switching speed of the non-volatile memory cell structure 200 and / or may result in a decrease in the gap filling efficiency of the source / drain electrodes 228. Selecting a thickness for the oxide insertion layer 224 in a range of approximately 0.5 angstroms to approximately 5 nanometers enables the oxide insertion layer 224 to provide sufficient intermixing barrier while enabling the source / drain regions 216 and / or 218 to achieve sufficiently low resistance. However, other values ​​of the thickness of the oxide insertion layer 224 and ranges other than approximately 0.5 angstroms to approximately 5 nanometers are also within the scope of the present disclosure.

[0052] In some embodiments, the oxide insertion layer 224 may include an oxide semiconductor material, such as gallium oxide (GaO) and / or silicon oxide (SiOx, such as SiO2), etc. In some embodiments, the oxide insertion layer may include a metal oxide material, such as zirconium oxide (ZrOx, such as ZrO2), hafnium oxide (HfOx, such as HfO2), and / or aluminum oxide (AlxOy, such as Al2O3), etc. In some embodiments, the oxide insertion layer 224 may include a high dielectric constant (high-k) dielectric material, such as a dielectric material having a dielectric constant greater than that of silicon oxide. In some embodiments, the oxide insertion layer 224 includes a plurality of materials, such as a plurality of oxide semiconductor materials, a plurality of metal oxide materials, a plurality of high dielectric constant dielectric materials, and / or combinations thereof.

[0053] The metal paste layer 226 may be included on the metal oxide channel layer 214 and between the oxide insertion layer 224 and the source / drain electrode 228. The metal paste layer 226 may also extend along the sidewalls of the source / drain electrode 228 so that the metal paste layer 226 is included between the dielectric layer 220 and the source / drain electrode 228. The metal paste layer 226 may be included to promote adhesion of the source / drain electrode 228 to the dielectric layer 220 and / or to promote adhesion of the source / drain electrode 228 to the metal oxide channel layer 214. The metal paste layer 226 may include one or more metal materials, such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu) and / or gold (Au), etc.

[0054] The source / drain electrodes 228 may be electrically coupled to one or more metallization layers to electrically couple the source / drain electrodes 228 to a power source or an electrical ground, etc. The source / drain electrodes 228 may include one or more metal materials, such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), ruthenium (Ru), cobalt (Co), copper (Cu) and / or gold (Au), etc.

[0055] As mentioned above, Figure 2 are provided as examples. Other examples may differ from those for Figure 2 Examples of illustration.

[0056] Figure 3A and Figure 3B is a graph of an example of the surface roughness of the metal paste layer described herein. Figure 3A The example 300 in FIG. 1 is an example of a nonvolatile memory cell structure that does not include an oxide insertion layer 224, and Figure 3B The example 302 in FIG. 1 is an example of the nonvolatile memory cell structure 200 (including the oxide insertion layer 224 ).

[0057] like Figure 3A and Figure 3B As shown in , omitting the oxide insertion layer 224 in Example 300 results in intermixing between the electron barrier layer 222 and the metal paste layer 226, while including the oxide insertion layer 224 in Example 302 can prevent intermixing between the electron barrier layer 222 and the metal paste layer 226. The intermixing in Example 300 results in high surface roughness of the metal paste layer 226, which can result in reduced adhesion between the metal paste layer 226 and the source / drain electrodes 228 and / or increase the likelihood of delamination between the metal paste layer 226 and the source / drain electrodes 228. In contrast, the lack of intermixing in Example 302 achieves low surface roughness relative to Example 300, which can increase adhesion between the metal paste layer 226 and the source / drain electrodes 228 and / or reduce the likelihood of delamination between the metal paste layer 226 and the source / drain electrodes 228.

[0058] As mentioned above, Figure 3A and Figure 3B are provided as examples. Other examples may differ from those for Figure 3A and Figure 3B Examples of illustration.

[0059] FIG. 4A to FIG. 4O FIG. 4 is a diagram of an example implementation 400 of forming the nonvolatile memory cell structure 200 described herein. In some implementations, the combination of the semiconductor processing tools 102 to 112 described herein may be implemented using one or more of the semiconductor processing tools 102 to 112 described herein. FIG. 4A to FIG. 4OIn some embodiments, another type of semiconductor processing tool may be used to perform the combined FIG. 4A to FIG. 4O One or more of the semiconductor processing operations described.

[0060] like Figure 4A As shown in , the operations described in the example implementation 400 can be performed in conjunction with the isolation layer 202. The isolation layer 202 can be formed on and / or on a substrate (e.g., a semiconductor substrate (e.g., a silicon (Si) wafer)) or on and / or on another layer of a semiconductor device. The deposition tool 102 can be used to use PVD techniques, ALD techniques, CVD techniques, oxidation techniques, combined Figure 1 Another type of deposition technique and / or another suitable deposition technique is described to deposit the isolation layer 202. In some implementations, after the isolation layer 202 is deposited, the isolation layer 202 can be planarized using a planarization tool 110.

[0061] like Figure 4B and Figure 4C As shown in FIG. 4 , the bottom gate electrode 204 may be formed in the isolation layer 202. The bottom gate electrode 204 may be formed in the isolation layer 202 in the recess 402. Alternatively, the bottom gate electrode 204 may be formed on the isolation layer 202.

[0062] In some embodiments, the isolation layer 202 is etched using the pattern in the photoresist layer to form the groove 402. In these embodiments, a deposition tool 102 can be used to form a photoresist layer on the isolation layer 202. The photoresist layer can be exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. The photoresist layer can be developed using a development tool 106 and some portions of the photoresist layer can be removed to expose the pattern. An etching tool 108 can be used to etch the isolation layer 202 based on the pattern to form a groove 402 in the isolation layer 202. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to etching the isolation layer 202 based on the pattern.

[0063] The deposition tool 102 and / or the plating tool 112 may use CVD technology, PVD technology, ALD technology, electroplating technology, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1The bottom gate electrode 204 may be deposited in the recess 402 using a deposition technique other than the deposition techniques described above. In some embodiments, after depositing the bottom gate electrode 204, the planarization tool 110 may perform a CMP operation to planarize the bottom gate electrode 204.

[0064] like Figure 4D As shown in , a stress relief layer 206 can be formed on and / or on the isolation layer 202 and on and / or on the bottom gate electrode 204. A seed layer 208 can be formed on and / or on the stress relief layer 206. In some embodiments, an in-situ thermal annealing operation can be performed using the deposition tool 102 while the stress relief layer 206 and / or the seed layer 208 are deposited using the deposition tool 102, and the in-situ thermal annealing operation can include thermally annealing the stress relief layer 206 and / or the seed layer 208. The thermal annealing operation can increase the crystallinity of the stress relief layer 206 and / or the seed layer 208. The deposition tool 102 can be used to deposit the stress relief layer 206 and / or the seed layer 208 using an ALD technique or a pulse layer deposition (PLD) technique. The deposition tool 102 may heat the stress relief layer 206 and / or the seed layer 208 to a temperature in the range of approximately 300 degrees Celsius to approximately 700 degrees Celsius for approximately 30 seconds to approximately 10 minutes to achieve crystallinity of the stress relief layer 206 and / or the seed layer 208. However, other values ​​of these ranges are also within the scope of the present disclosure. In addition, the stress relief layer 206 may be formed as a quasi-single crystal metal oxide.

[0065] like Figure 4E As shown in FIG. 1 , a ferroelectric layer 210 may be formed on and / or on the seed layer 208. The seed layer 208 facilitates the growth of the ferroelectric layer 210 with a specific crystal structure and / or a specific grain size. The deposition tool 102 may be used to deposit the ferroelectric layer 210 using an ALD technique, a CVD technique, a PVD technique, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 The ferroelectric layer 210 can be deposited using a deposition technique other than the deposition techniques described above. In some embodiments, after depositing the ferroelectric layer 210, the planarization tool 110 can perform a CMP operation to planarize the ferroelectric layer 210.

[0066] like Figure 4F As shown in FIG. 1 , a barrier layer 212 may be formed on and / or over the ferroelectric layer 210. The deposition tool 102 may be used to deposit the ferroelectric layer using an ALD technique, a CVD technique, a PVD technique, or a combination thereof. Figure 1Another deposition technique described and / or in addition to the above combination Figure 1 Deposition techniques other than those described above deposit barrier layer 212. In some embodiments, after depositing barrier layer 212, planarization tool 110 can perform a CMP operation to planarize barrier layer 212.

[0067] like Figure 4G As shown in FIG. 1 , a metal oxide channel layer 214 may be formed on and / or over the barrier layer 212. The deposition tool 102 may be used to deposit metal oxides using ALD techniques, CVD techniques, PVD techniques, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 The metal oxide channel layer 214 may be deposited by a deposition technique other than the deposition techniques described above. In some embodiments, after depositing the metal oxide channel layer 214, the planarization tool 110 may perform a CMP operation to planarize the metal oxide channel layer 214. In some embodiments, a precursor gas mixture (which may be referred to as a "cocktail") used to deposit the ferroelectric layer 210 may be selected to achieve a suitable electron mobility and surface state of the ferroelectric layer 210. The mixture may include a mixture of solid metal precursors. A low pressure vessel (LPV) may be used to evaporate the mixture and the resulting evaporated precursor mixture may be introduced (e.g., pulsed) into an ALD reaction chamber containing the non-volatile memory cell structure 200. When depositing the metal oxide channel layer 214, the evaporated precursor mixture may react with the barrier layer 212 and / or the ferroelectric layer 210.

[0068] like Figure 4H As shown in FIG. 1 , a dielectric layer 220 may be formed on and / or over the metal oxide channel layer 214. The deposition tool 102 may be used to deposit dielectric layers using ALD techniques, CVD techniques, PVD techniques, oxidation techniques, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 The dielectric layer 220 may be deposited using a deposition technique other than the deposition techniques described above. In some embodiments, after depositing the dielectric layer 220 , the planarization tool 110 may perform a CMP operation to planarize the dielectric layer 220 .

[0069] like Fig. 4IAs shown in , recesses 404 and 406 may be formed in and / or through the dielectric layer 220 so that the top surface of the metal oxide channel layer 214 is exposed through the recesses 404 and 406. In some embodiments, the dielectric layer 220 is etched using the pattern in the photoresist layer to form the recesses 404 and 406. In these embodiments, a deposition tool 102 may be used to form a photoresist layer on the dielectric layer 220. The photoresist layer may be exposed to a radiation source using an exposure tool 104 to pattern the photoresist layer. A development tool 106 may be used to develop the photoresist layer and remove portions of the photoresist layer to expose the pattern. An etching tool 108 may be used to etch the dielectric layer 220 based on the pattern to form recesses 404 and 406 in the dielectric layer 220. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some implementations, a photoresist removal tool can be used to remove remaining portions of the photoresist layer (eg, using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an alternative technique to pattern-based etching of the dielectric layer 220 .

[0070] like Figure 4J As shown in FIG. 4 , an electron barrier layer 222 of source / drain regions 216 and 218 may be formed in recesses 404 and 406, respectively. Deposition tool 102 may be used to use ALD technology, CVD technology, PVD technology, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 Deposition techniques other than the described deposition techniques conformally deposit the electron barrier layer 222. The electron barrier layer 222 may be formed on the bottom surface of the recesses 404 and 406 corresponding to the top surface of the metal oxide channel layer 214 exposed in the recesses 404 and 406. In addition, the electron barrier layer 222 may be formed on the sidewalls of the recesses 404 and 406 corresponding to the dielectric layer 220.

[0071] like Figure 4K As shown in FIG. 4 , an oxide insertion layer 224 of source / drain regions 216 and 218 may be formed in recesses 404 and 406, respectively. Deposition tool 102 may be used to deposit the source / drain regions 216 and 218 using ALD techniques, CVD techniques, PVD techniques, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 Deposition techniques other than those described conformally deposit oxide insertion layer 224. Oxide insertion layer 224 may be formed on electron barrier layer 222 over the bottom surface of recesses 404 and 406. In addition, oxide insertion layer 224 may be formed on electron barrier layer 222 over the sidewalls of recesses 404 and 406 corresponding to dielectric layer 220.

[0072] like Figure 4L As shown in FIG. 4 , a metal paste layer 226 of source / drain regions 216 and 218 may be formed in recesses 404 and 406, respectively. Deposition tool 102 may be used to perform deposition using ALD technology, CVD technology, PVD technology, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 A deposition technique other than the described deposition technique conformally deposits the metal paste layer 226. The metal paste layer 226 may be formed on the oxide insertion layer 224 over the bottom surface of the recesses 404 and 406. In addition, the metal paste layer 226 may be formed on the oxide insertion layer 224 over the sidewalls of the recesses 404 and 406 corresponding to the dielectric layer 220.

[0073] like Figure 4M As shown in FIG. 4 , source / drain electrodes 228 of source / drain regions 216 and 218 may be formed in recesses 404 and 406, respectively. Deposition tool 102 and / or plating tool 112 may be used to deposit the source / drain regions 216 and 218 using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, or a combination thereof. Figure 1 Another deposition technique described and / or another suitable deposition technique is used to deposit the source / drain electrode 228. The source / drain electrode 228 can fill the remaining areas of the recesses 404 and 406. In some implementations, after depositing the source / drain electrode 228, the source / drain electrode 228 can be planarized using a planarization tool 110.

[0074] In some implementations, a quasi-ALD technique is used to deposit source / drain electrodes 228 of source / drain regions 216 and 218. Quasi-ALD techniques include using a CVD tool (eg, deposition tool 102) in which a tungsten pulse-purge (PPW) process is performed in an ALD-like manner.

[0075] Figure 4N An exemplary quasi-ALD operation is shown. Figure 4N As shown in , the quasi-ALD operation may include a plurality of precursor gas pulse durations 414 performed using a metal precursor gas source 408. During the precursor gas pulse durations 414, the metal precursor gas source 408 is supplied to a processing chamber of a CVD tool. The precursor gas pulse durations 414 may be separated in time by a plurality of nitrogen (N2) gas purges 416. During the nitrogen purges 416, the supply of the metal precursor gas source 408 is cut off, and a nitrogen gas source 410 is provided to the processing chamber of the CVD tool to purge the remaining metal precursor gas source 408 from the processing chamber. The precursor gas pulse durations 414 and the nitrogen purges 416 are performed in a cyclic manner during a duration in which a hydrogen (H2) reactant gas 412 is continuously flowed into the processing chamber of the CVD tool.

[0076] The use of precursor gas pulsing duration 414 and nitrogen purge 416 during the continuous flow of hydrogen reactant gas 412 can enable the source / drain electrodes 228 to achieve a larger grain size than when the quasi-ALD technique is not used. Since the fluorine in the metal precursor gas source 408 (which may include, for example, tungsten hexafluoride (WF6)) will limit the further growth of tungsten of the source / drain electrodes, the absorption of the metal precursor gas source 408 can be self-limiting. Therefore, the metal precursor gas source 408 can be pulsed for a relatively short duration in the precursor gas pulsing duration 414 to achieve a monolayer of chemically adsorbed tungsten hexafluoride, followed by a nitrogen purge 416 for removing residual metal precursor gas source 408. The duration of the nitrogen purge 416 may be greater than the duration of the precursor gas pulse 414 to allow the hydrogen reactant gas 412 to react primarily with the chemically adsorbed tungsten hexafluoride, which results in the formation of tungsten (W) and hydrofluoric acid (HF) byproducts (e.g., WF6+3H2→W+6HF). For example, the duration of the precursor gas pulse 414 may be within a range of approximately 0.5 seconds to approximately 3 seconds, while the duration of the nitrogen purge 416 may be within a range of approximately 5 seconds to approximately 10 seconds. As another example, the ratio of the duration of the nitrogen purge 416 to the duration of the precursor gas pulse 414 may be within a range of approximately 5:3 to approximately 20:1. However, other values ​​of these ranges are also within the scope of the present disclosure. The hydrogen reactant gas 412 may be continuously supplied for a duration included within the range of approximately 10 seconds to approximately 30 seconds before being stopped to enable a chamber purge to remove residual hydrogen reactant gas 412, residual tungsten precursor, and / or residual hydrofluoric acid byproducts from the processing chamber of the CVD tool.

[0077] Thus, using the nitrogen purge 416 during the continuous flow of the hydrogen reactant gas 412 enables a monolayer of chemically adsorbed tungsten hexafluoride to form quickly and be converted to deposited tungsten, which reduces the effect of the self-limiting nature of tungsten hexafluoride on the deposition rate. In this way, the quasi-ALD technique described herein can increase the deposition rate of the material of the source / drain electrode 228, which can enable the source / drain electrode 228 to achieve a larger grain size.

[0078] In some implementations, a combination of quasi-ALD techniques and non-quasi-ALD CVD techniques may be used to form the source / drain electrodes 228 of the source / drain regions 216 and 218. For example, a combination of Figure 4N The quasi-ALD technique described herein forms a first portion of the source / drain electrode 228 on and / or above the metal paste layer 226, and may be combined with Fig.4OThe described non-quasi-ALD CVD technique forms a second portion of the source / drain electrode 228 on and / or above the first portion. The first portion can enable the source / drain electrode 228 to achieve low resistance, and the second portion (having a smaller grain size than the first portion) can enable the source / drain electrode 228 to achieve improved gap filling performance and low stress. In some embodiments, the ratio of the thickness of the first portion to the thickness of the second portion can be included in the range of approximately 1:1 to approximately 1:2. However, other values ​​of the range are also within the scope of the present disclosure.

[0079] like Fig.4O As shown in FIG. 4 , the non-quasi-ALD CVD technique may include a precursor gas pulse duration 414 and a nitrogen purge 416. However, in combination with Figure 4N Before the described quasi-ALD technique, the precursor gas pulsation duration 414 and the nitrogen purge 416 were not cycled during the continuous supply of the hydrogen reactant gas 412. Instead, the metal precursor gas source 408 and the hydrogen reactant gas 412 were supplied to the processing chamber of the CVD tool during the precursor gas pulsation duration 414, without using the nitrogen source 410. The nitrogen source 410 was supplied only during the nitrogen purge 416, during which the metal precursor gas source 408 and the hydrogen reactant gas 412 were not supplied to the processing chamber of the CVD tool. In addition, the duration of the precursor gas pulsation duration 414 of the non-quasi-ALD CVD technique is greater than the duration of the precursor gas pulsation duration 414 of the quasi-ALD technique. For example, the duration of the precursor gas pulse duration 414 of the non-quasi-ALD CVD technique may be within a range of approximately 10 seconds to approximately 30 seconds, while the duration of the precursor gas pulse duration 414 of the quasi-ALD technique may be within a range of approximately 0.5 seconds to approximately 3 seconds. However, other values ​​of these ranges are also within the scope of the present disclosure.

[0080] As mentioned above, FIG. 4A to FIG. 4O are provided as examples. Other examples may differ from those for FIG. 4A to FIG. 4O Examples of illustration.

[0081] FIG. 5A to FIG. 5D 2 is a diagram of an example of the elemental composition of the source / drain electrode 228 described herein. Figure 4N The quasi-ALD technique described above is used to form the source / drain electrode 228 of the nonvolatile memory cell structure and for the nonvolatile memory cell structure 200 (wherein the combination of Figure 4N An example of elemental composition is shown in Figure 2 (a quasi-ALD technique is described to form source / drain electrodes 228).

[0082] Figure 5A Shows where no binding is used Figure 4NAn example 500 of a tungsten (W) composition (corresponding to data curve 502) of a nonvolatile memory cell structure of source / drain electrodes 228 and a tungsten (W) composition (corresponding to data curve 504) of a nonvolatile memory cell structure 200 using a quasi-ALD technique is described. The tungsten composition is shown as a function of elemental intensity 506 and depth 508 in the source / drain electrodes 228. Figure 5A As shown in Figure 4N The tungsten composition of the nonvolatile memory cell structure formed by the quasi-ALD technique described above for forming the source / drain electrodes 228 is similar to the tungsten composition of the nonvolatile memory cell structure 200, which means that the tungsten composition of the nonvolatile memory cell structure 200 is similar to the tungsten composition of the nonvolatile memory cell structure 200. Figure 4N The described quasi-ALD technique does not adversely affect the tungsten composition of the source / drain electrodes 228 in the nonvolatile memory cell structure 200 .

[0083] Figure 5B Shows where no binding is used Figure 4N An example 510 of hydrogen (H2) composition (corresponding to data curve 512) of a nonvolatile memory cell structure of a source / drain electrode 228 formed using a quasi-ALD technique and hydrogen (H2) composition (corresponding to data curve 514) of a nonvolatile memory cell structure 200 is shown. The hydrogen composition is shown as a function of elemental intensity 516 and depth 518 in the source / drain electrode 228. Figure 5B As shown in Figure 4N The hydrogen composition of the nonvolatile memory cell structure formed by the quasi-ALD technique described above for forming the source / drain electrodes 228 is similar to the hydrogen composition of the nonvolatile memory cell structure 200, which means that the hydrogen composition of the nonvolatile memory cell structure 200 is similar to the hydrogen composition of the nonvolatile memory cell structure 200. Figure 4N The described quasi-ALD technique does not adversely affect the hydrogen composition of the source / drain electrodes 228 in the nonvolatile memory cell structure 200 .

[0084] Figure 5C Shows where no binding is used Figure 4N An example 520 of oxygen (O2) composition (corresponding to data curve 522) of a nonvolatile memory cell structure of source / drain electrodes 228 and oxygen (O2) composition (corresponding to data curve 524) of a nonvolatile memory cell structure 200 using a quasi-ALD technique is described. The oxygen composition is shown as a function of element intensity 526 and depth 528 in the source / drain electrodes 228. Figure 5C As shown in , where no combination is used Figure 4N The oxygen composition of the nonvolatile memory cell structure formed by the quasi-ALD technique described above for forming the source / drain electrodes 228 is similar to the oxygen composition of the nonvolatile memory cell structure 200, which means that the oxygen composition of the nonvolatile memory cell structure 200 is similar to the oxygen composition of the nonvolatile memory cell structure 200. Figure 4N The described quasi-ALD technique does not adversely affect the oxygen composition of the source / drain electrodes 228 in the nonvolatile memory cell structure 200 .

[0085] Figure 5D Shows where no binding is used Figure 4N An example 530 of the fluorine (F) composition of a nonvolatile memory cell structure (corresponding to data curve 532) and the fluorine (F) composition of the nonvolatile memory cell structure 200 (corresponding to data curve 534) using the quasi-ALD technique described above is shown. The fluorine composition is shown as a function of the element intensity 536 and the depth 538 in the source / drain electrode 228. Figure 5D As shown in Figure 4N The fluorine composition of the non-volatile memory cell structure formed by the quasi-ALD technique described above for forming the source / drain electrodes 228 is similar to the fluorine composition of the non-volatile memory cell structure 200, which means that the fluorine composition of the non-volatile memory cell structure 200 is similar to the fluorine composition of the non-volatile memory cell structure 200. Figure 4N The described quasi-ALD technique does not adversely affect the fluorine composition of the source / drain electrodes 228 in the non-volatile memory cell structure 200 .

[0086] As mentioned above, FIG. 5A to FIG. 5D are provided as examples. Other examples may differ from those for FIG. 5A to FIG. 5D Examples of illustration.

[0087] Figure 6 is a graph of an example 600 of the resistivity of the source / drain electrodes 228 described herein. Figure 4N The quasi-ALD technique is described to form a non-volatile memory cell structure of source / drain electrodes 228 (corresponding to data curve 602) and for a non-volatile memory cell structure in which a combination of Figure 4N An example of resistivity is shown for a nonvolatile memory cell structure 200 (corresponding to data curve 604 ) illustrating a quasi-ALD technique to form source / drain electrodes 228 . Resistivity is shown as a function of resistivity 606 and thickness 608 of source / drain electrodes 228 .

[0088] like Figure 6 As shown in FIG. 6 , the resistivity 606 of the source / drain electrode 228 generally decreases as the thickness 608 increases. However, due to the use of a combination of Figure 4N The quasi-ALD technique described above is used to achieve a larger grain size, so that for the same thickness 608, the source / drain electrodes 228 of the nonvolatile memory cell structure 200 are smaller than those without the use of the bonding Figure 4N The quasi-ALD technique described above is used to form the source / drain electrodes 228 of the nonvolatile memory cell structure. For example, at a thickness of approximately 430 angstroms, compared to the structure without the use of the bonding Figure 4NThe source / drain electrodes 228 of the nonvolatile memory cell structure using the quasi-ALD technique described above to form the source / drain electrodes 228 have a resistivity of approximately 19.4 ohm-centimeter (Ω-cm). The source / drain electrodes 228 of the nonvolatile memory cell structure 200 may have a resistivity of approximately 16.9 ohm-cm.

[0089] As mentioned above, Figure 6 are provided as examples. Other examples may differ from those for Figure 6 Examples of illustration.

[0090] Figure 7 is a diagram of an example 700 of the crystalline phase composition of the source / drain electrode 228 described herein. Figure 4N The quasi-ALD technique is described to form a non-volatile memory cell structure of source / drain electrodes 228 (corresponding to data curve 702) and for a non-volatile memory cell structure in which a combination of Figure 4N An example of a crystalline phase composition is shown for a nonvolatile memory cell structure 200 (corresponding to data curve 704 ) using a quasi-ALD technique to form source / drain electrodes 228 . The crystalline phase composition is shown as a function of phase intensity 706 .

[0091] like Figure 7 As shown in , where no combination is used Figure 4N The nonvolatile memory cell structure and the nonvolatile memory cell structure 200 both include a crystal phase composition with a specific dominant crystal phase. The dominant crystal phases are (110) crystal phase 708, (200) crystal phase 710, and (211) crystal phase 712, wherein the (110) crystal phase 708 has the largest phase intensity 706. However, in combination with Figure 4N The described quasi-ALD technique enables the source / drain electrodes 228 of the nonvolatile memory cell structure 200 to have a larger phase intensity 706 for the (110) crystalline phase 708, the (200) crystalline phase 710, and the (211) crystalline phase 712, and especially for the (110) crystalline phase 708. This enables the grain size of the source / drain electrodes 228 of the nonvolatile memory cell structure 200 to be larger, which helps to make the resistivity of the source / drain electrodes 228 of the nonvolatile memory cell structure 200 lower.

[0092] As mentioned above, Figure 7 are provided as examples. Other examples may differ from those for Figure 7 Examples of illustration.

[0093] Figure 88 is a diagram of an exemplary nonvolatile memory cell structure 800 described herein. The nonvolatile memory cell structure 200 may include a ferroelectric nonvolatile memory cell structure (e.g., a FeRAM cell). The nonvolatile memory cell structure 200 described herein may include an oxide insertion layer, which enables a metal glue layer to be formed on an electron barrier layer of the nonvolatile memory cell structure 200 with a low surface roughness, which may increase the adhesion between the metal glue layer and the source / drain electrodes of the source / drain region of the nonvolatile memory cell structure 200. In this way, the oxide insertion layer included in the nonvolatile memory cell structure 200 may enable the nonvolatile memory cell structure 200 to achieve low resistance and / or may reduce the possibility of failure in the nonvolatile memory cell structure 200, etc.

[0094] like Figure 8 As shown in FIG. 8 , the nonvolatile memory cell structure 800 may include a combination and arrangement of layers and / or structures similar to the nonvolatile memory cell structure 200. However, in the nonvolatile memory cell structure 800, the electron barrier layer 222 and the oxide insertion layer 224 are omitted from the sidewalls of the source / drain regions 216 and 218. In other words, the electron barrier layer 222 and the oxide insertion layer 224 are included only between the metal oxide channel layer 214 and the bottom surface of the metal paste layer 226 and between the metal oxide channel layer 214 and the bottom surface of the source / drain electrode 228. The metal paste layer 226 is directly included on the dielectric layer 220 between the sidewalls of the dielectric layer 220 and the source / drain electrode 228.

[0095] Omitting the electron barrier layer 222 and the oxide insertion layer 224 from the sidewalls of the source / drain electrodes 228 can provide a larger volume for the source / drain electrodes 228 to form the source / drain regions 216 and 218, while still providing an electron barrier function and intermixing barrier in the nonvolatile memory cell structure 800. This can further reduce the resistance of the source / drain regions 216 and 218. In contrast, leaving the electron barrier layer 222 and the oxide insertion layer 224 on the dielectric layer 220 can result in less time, lower cost, and less complexity in manufacturing the nonvolatile memory cell structure 200, since fewer etch-back operations are performed when manufacturing the nonvolatile memory cell structure 200 relative to the nonvolatile memory cell structure 800.

[0096] As mentioned above, Figure 8 are provided as examples. Other examples may differ from those for Figure 8 Examples of illustration.

[0097] FIG. 9A to FIG. 9G FIG. 9 is a diagram of an example implementation 900 for forming the nonvolatile memory cell structure 800 described herein. In some implementations, the combination of the semiconductor processing tools 102 to 112 described herein may be implemented using one or more of the semiconductor processing tools 102 to 112 described herein. FIG. 9A to FIG. 9G In some embodiments, another type of semiconductor processing tool may be used to perform the combined FIG. 9A to FIG. 9G One or more of the semiconductor processing operations described.

[0098] like Fig.9A As shown in FIG. 4A to FIG. 4I One or more of the semiconductor processing operations described are performed to form components of the nonvolatile memory cell structure 800 , such as the isolation layer 202 to the metal oxide channel layer 214 and the dielectric layer 220 , and to form the recesses 902 and 904 in the dielectric layer 220 .

[0099] like Fig. 9B As shown in FIG. 1 , an electron barrier layer 222 of source / drain regions 216 and 218 may be formed in recesses 902 and 904, respectively. Deposition tool 102 may be used to use ALD technology, CVD technology, PVD technology, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 Deposition techniques other than the described deposition techniques conformally deposit the electron barrier layer 222. The electron barrier layer 222 may be formed on the bottom surfaces of the grooves 902 and 904 corresponding to the top surfaces of the metal oxide channel layer 214 exposed in the grooves 902 and 904. In addition, the electron barrier layer 222 may be formed on the sidewalls of the grooves 902 and 904 corresponding to the dielectric layer 220.

[0100] like Fig. 9C As shown in , a first etch-back operation may be performed to remove portions of the electron barrier layer 222 from the sidewalls of the recesses 902 and 904. The first etch-back operation may be performed using an etching tool 108 using a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. After the first etch-back operation, the electron barrier layer 222 may remain on and / or on the bottom surfaces of the recesses 902 and 904.

[0101] like Fig.9D As shown in FIG. 1 , an oxide insertion layer 224 of source / drain regions 216 and 218 may be formed in recesses 902 and 904, respectively. Deposition tool 102 may be used to deposit the source / drain regions 216 and 218 using ALD techniques, CVD techniques, PVD techniques, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 Deposition techniques other than those described conformally deposit oxide insertion layer 224. Oxide insertion layer 224 may be formed on electron barrier layer 222 over the bottom surfaces of recesses 902 and 904. In addition, oxide insertion layer 224 may be formed directly on the sidewalls of recesses 902 and 904 corresponding to dielectric layer 220.

[0102] like Fig.9E As shown in , a second etch-back operation may be performed to remove some portions of the oxide insertion layer 224 from the sidewalls of the recesses 902 and 904. The second etch-back operation may be performed using an etching tool 108 using a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique. After the second etch-back operation, the oxide insertion layer 224 may remain on the electron barrier layer 222 on the bottom surfaces of the recesses 902 and 904.

[0103] like Fig.9F As shown in FIG. 1 , a metal paste layer 226 of source / drain regions 216 and 218 may be formed in recesses 902 and 904, respectively. Deposition tool 102 may be used to perform deposition using ALD technology, CVD technology, PVD technology, or a combination thereof. Figure 1 Another deposition technique described and / or in addition to the above combination Figure 1 Deposition techniques other than those described conformally deposit the metal paste layer 226. The metal paste layer 226 may be formed on the oxide insertion layer 224 over the bottom surfaces of the recesses 902 and 904. In addition, the metal paste layer 226 may be formed directly on the sidewalls of the recesses 902 and 904 corresponding to the dielectric layer 220.

[0104] like Figure 9G As shown in FIG. 1 , source / drain electrodes 228 of source / drain regions 216 and 218 may be formed in recesses 902 and 904, respectively. Deposition tool 102 and / or plating tool 112 may be used to deposit the source / drain regions 216 and 218 using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, or a combination thereof. Figure 1 The source / drain electrodes 228 may be deposited by another deposition technique described above and / or another suitable deposition technique. The source / drain electrodes 228 may fill the remaining areas of the recesses 902 and 904. In some embodiments, after depositing the source / drain electrodes 228, the source / drain electrodes 228 may be planarized using a planarization tool 110. In some embodiments, a combination of Figure 4N Quasi-ALD technology and / or combination described Fig.4O The non-quasi-ALD CVD technique described forms the source / drain electrodes 228 .

[0105] As mentioned above, FIG. 9A to FIG. 9G are provided as examples. Other examples may differ from those for FIG. 9A to FIG. 9G Examples of illustration.

[0106] Fig.101 is a diagram of a portion of an example semiconductor device 1000 described herein. Semiconductor device 1000 includes an example of a memory device (e.g., static random access memory (SRAM), dynamic random access memory (DRAM)), a logic device, a processor, an input / output device, or another type of semiconductor device including one or more transistors.

[0107] The semiconductor device 1000 includes a substrate 1002 and one or more fin structures 1004 formed on the substrate 1002. The semiconductor device 1000 includes one or more stacked layers, and the one or more stacked layers include a dielectric layer 1006, an etch stop layer (ESL) 1008, a dielectric layer 1010, an ESL 1012, a dielectric layer 1014, an ESL 1016, a dielectric layer 1018, an ESL 1020, a dielectric layer 1022, an ESL 1024, and a dielectric layer 1026, etc. The dielectric layers 1006, 1010, 1014, 1018, 1022, and 1026 are included to electrically isolate various structures of the semiconductor device 1000. The dielectric layers 1006, 1010, 1014, 1018, 1022, and 1026 include silicon nitride (SiNx), an oxide (e.g., silicon oxide (SiOx) and / or another oxide material), and / or another type of dielectric material. The ESLs 1008, 1012, 1016, 1020, and 1024 include layers formed of materials configured to allow selective etching of various portions of the semiconductor device 1000 (or layers included in the semiconductor device 1000) or to protect various portions of the semiconductor device 1000 from etching to form one or more structures included in the semiconductor device 1000.

[0108] like Fig.10 As further shown in FIG. 1 , the semiconductor device 1000 includes a plurality of epitaxial (epi) regions 1028 grown and / or otherwise formed on and / or around portions of the fin structure 1004. The epitaxial regions 1028 are formed by epitaxial growth. In some embodiments, the epitaxial regions 1028 are formed in recessed portions of the fin structure 1004. The recessed portions may be formed by strained source drain (SSD) etching and / or another type of etching operation of the fin structure 1004. The epitaxial regions 1028 serve as source regions or drain regions of transistors included in the semiconductor device 1000.

[0109] The epitaxial region 1028 is electrically connected to a metal source or drain contact 1030 of a transistor included in the semiconductor device 1000. The metal source or drain contact (MD or CA) 1030 includes cobalt (Co), ruthenium (Ru) and / or another conductive material or metal material. The transistor further includes a gate 1032 (MG), which is formed of polycrystalline silicon material, metal (e.g., tungsten (W) or another metal) and / or another type of conductive material. The metal source or drain contact 1030 is electrically isolated from the gate 1032 by one or more sidewall spacers, and the one or more sidewall spacers include a spacer 1034 located in each side of the metal source or drain contact 1030 and a spacer 1036 located on each side of the gate 1032. The spacers 1034 and 1036 include silicon oxide (SiOx), silicon nitride (SiXNy), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), and / or another suitable material. In some implementations, the spacers 1034 are omitted from the sidewalls of the source or drain contact 1030 .

[0110] like Fig.10 As further shown in FIG. 1 , metal source or drain contact 1030 and gate 1032 are electrically connected to one or more types of interconnects. The interconnects electrically connect transistors of semiconductor device 1000 and / or electrically connect the transistors to other regions and / or components of semiconductor device 1000. In some embodiments, the interconnects electrically connect the transistors to a back end of line (BEOL) region of semiconductor device 1000.

[0111] The metal source or drain contact 1030 is electrically connected to a source or drain interconnect 1038 (e.g., a source / drain via or VD). One or more of the gates 1032 are electrically connected to a gate interconnect 1040 (e.g., a gate via or VG). Interconnects 1038 and 1040 include a conductive material such as tungsten, cobalt, ruthenium, copper, and / or another type of conductive material. In some embodiments, the gate 1032 is electrically connected to the gate interconnect 1040 via a gate contact 1042 (CB or MP) to reduce the contact resistance between the gate 1032 and the gate interconnect 1040. The gate contact 1042 includes tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), as well as other examples of conductive materials.

[0112] like Fig.10As further shown in FIG. 1 , interconnects 1038 and 1040 are electrically connected to a plurality of BEOL layers, each of which includes one or more metallization layers and / or vias. As an example, interconnects 1038 and 1040 may be electrically connected to an M0 metallization layer including conductive structures 1044 and 1046. The M0 metallization layer is electrically connected to a V0 via layer including vias 1048 and 1050. The V0 via layer is electrically connected to an M1 metallization layer including conductive structures 1052 and 1054. In some embodiments, the BEOL layers of semiconductor device 1000 include additional metallization layers and / or vias that connect semiconductor device 1000 to a package.

[0113] One or more nonvolatile memory cell structures 200 and / or nonvolatile memory cell structures 800 may be included in the BEOL region of the semiconductor device 1000. For example, the nonvolatile memory cell structures 200 and / or the nonvolatile memory cell structures 800 may be included in one or more of the BEOL layers of the semiconductor device 1000. In these examples, the nonvolatile memory cell structures 200 and / or the nonvolatile memory cell structures 800 may be included in one or more of the dielectric layers 1010, 1014, 1018, 1022, 1026 and / or another dielectric layer in the BEOL region of the semiconductor device 1000. In addition, the non-volatile memory cell structure 200 and / or the non-volatile memory cell structure 800 may be electrically connected to one or more of the conductive structures 1044, 1046, 1052, 1054 and / or another conductive structure in the BEOL region of the semiconductor device 1000; and / or may be electrically connected to one or more of the through holes 1048, 1050 and / or another through hole in the BEOL region of the semiconductor device 1000.

[0114] As mentioned above, Fig.10 are provided as examples. Other examples may differ from those for Fig.10 Examples of illustration.

[0115] Fig.11 1 is a diagram of example components of the apparatus 1100 described herein. In some implementations, one or more of the semiconductor processing tools 102-112 and / or the wafer / die transport 114 may include one or more apparatuses 1100 and / or one or more components of the apparatus 1100. Fig.11 As shown in , device 1100 may include a bus 1110 , a processor 1120 , a memory 1130 , an input component 1140 , an output component 1150 , and / or a communication component 1160 .

[0116] The bus 1110 may include one or more components that enable wired and / or wireless communication between the components of the device 1100. The bus 1110 may, for example, connect the components of the device 1100 via an operational coupling, a communicative coupling, an electronic coupling, and / or an electrical coupling. Fig.11 Two or more components shown are coupled together. For example, bus 1110 may include electrical connectors (e.g., wiring, traces and / or leads) and / or wireless buses. Processor 1120 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application-specific integrated circuit and / or another type of processing component. Processor 1120 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 1120 may include one or more processors that can be programmed to implement one or more operations or processes described elsewhere herein.

[0117] Memory 1130 may include volatile memory and / or non-volatile memory. For example, memory 1130 may include random access memory (RAM), read only memory (ROM), a hard disk drive, and / or another type of memory (e.g., flash memory, magnetic memory, and / or optical memory). Memory 1130 may include internal memory (e.g., RAM, ROM, or hard disk drive) and / or removable memory (e.g., removable via a universal serial bus connector). Memory 1130 may be a non-transitory computer-readable medium. Memory 1130 may store information related to the operation of device 1100, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 1130 may include, for example, one or more memories coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 1120) via bus 1110. The communicative coupling between the processor 1120 and the memory 1130 may enable the processor 1120 to read and / or process information stored in the memory 1130 and / or store information in the memory 1130 .

[0118] Input components 1140 may enable device 1100 to receive input, such as user input and / or sensed input. For example, input components 1140 may include a touch screen, a keyboard, a keypad, a mouse, a button, a microphone, a switch, a sensor, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. Output components 1150 may enable device 1100 to provide output, such as via a display, a speaker, and / or a light emitting diode. Communication components 1160 may enable device 1100 to communicate with other devices via wired connectors and / or wireless connectors. For example, communication components 1160 may include a receiver, a transmitter, a transceiver, a modem, a network adapter, and / or an antenna.

[0119] The device 1100 may implement one or more operations or processes described herein. For example, a non-transitory computer-readable medium (e.g., memory 1130) may store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 1120. The processor 1120 may execute the set of instructions to implement one or more operations or processes described herein. In some embodiments, the execution of the set of instructions by one or more processors 1120 causes the one or more processors 1120 and / or the device 1100 to implement one or more operations or processes described herein. In some embodiments, a hardwired circuitry may be used instead of the instructions or in combination with the instructions to implement one or more operations or processes described herein. Additionally or alternatively, the processor 1120 may be configured to implement one or more operations or processes described herein. Therefore, the embodiments described herein are not limited to any particular combination of hardwired circuitry and software.

[0120] Fig.11 The number and arrangement of components shown in are provided as examples. Fig.11 , device 1100 may include additional components, fewer components, different components, or components arranged in a different manner. Additionally or alternatively, one set of components (e.g., one or more components) of device 1100 may perform one or more functions described as being performed by another set of components of device 1100.

[0121] Fig.12 1 is a flow chart of an exemplary process 1200 associated with forming the ferroelectric nonvolatile memory described herein. In some implementations, one or more semiconductor processing tools (eg, one or more of semiconductor processing tools 102-112) are used to implement Fig.12Additionally or alternatively, one or more components of the apparatus 1100 (e.g., the processor 1120, the memory 1130, the input component 1140, the output component 1150, and / or the communication component 1160) may be used to implement Fig.12 One or more process blocks are shown.

[0122] like Fig.12 As shown in , the process 1200 may include forming a bottom gate electrode of a nonvolatile memory cell structure (block 1210). For example, as described herein, the bottom gate electrode 204 of the nonvolatile memory cell structure (e.g., the nonvolatile memory cell structure 200, the nonvolatile memory cell structure 800) may be formed using one or more of the semiconductor processing tools 102-112.

[0123] like Fig.12 As further shown in the process 1200, the process 1200 may include forming a ferroelectric layer (210) of a non-volatile memory cell structure over the bottom gate electrode (block 1220). For example, the ferroelectric layer 210 of the non-volatile memory cell structure may be formed over the bottom gate electrode 204 using one or more of the semiconductor processing tools 102-112 as described herein.

[0124] like Fig.12 As further shown in the process 1200, the process 1200 may include forming a metal oxide channel layer of the nonvolatile memory cell structure above the ferroelectric layer (block 1230). For example, the metal oxide channel layer 214 of the nonvolatile memory cell structure may be formed above the ferroelectric layer 210 using one or more of the semiconductor processing tools 102-112 as described herein.

[0125] like Fig.12 As further shown in FIG. 1 , process 1200 may include forming a dielectric layer over the metal oxide channel layer (block 1240). For example, dielectric layer 220 may be formed over metal oxide channel layer 214 using one or more of semiconductor processing tools 102-112 as described herein.

[0126] like Fig.12 As further shown in FIG. 1 , process 1200 may include forming a recess in the dielectric layer to expose the metal oxide channel layer through the recess (block 1250). For example, recess 404 may be formed in dielectric layer 220 to expose metal oxide channel layer 214 through recess 404 using one or more of semiconductor processing tools 102-112 as described herein.

[0127] like Fig.12As further shown in FIG. 1 , process 1200 may include forming an electron barrier layer on the metal oxide channel layer in the recess (block 1260). For example, electron barrier layer 222 may be formed on metal oxide channel layer 214 in recess 404 using one or more of semiconductor processing tools 102-112 as described herein.

[0128] like Fig.12 As further shown in FIG. 1 , process 1200 may include forming an oxide insertion layer on the electron barrier layer in the recess (block 1270). For example, oxide insertion layer 224 may be formed on electron barrier layer 222 in recess 404 using one or more of semiconductor processing tools 102-112 as described herein.

[0129] like Fig.12 As further shown in FIG. 1 , process 1200 may include forming a metal paste layer on the oxide insertion layer in the recess (block 1280). For example, metal paste layer 226 may be formed on oxide insertion layer 224 in recess 404 using one or more of semiconductor processing tools 102-112 as described herein.

[0130] like Fig.12 As further shown in FIG. 1 , the process 1200 may include forming a source / drain electrode of a nonvolatile memory cell structure on the metal paste layer (block 1290). For example, the source / drain electrode 228 of the nonvolatile memory cell structure may be formed on the metal paste layer 226 using one or more of the semiconductor processing tools 102 to 112 as described herein.

[0131] Process 1200 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in combination with one or more other processes described elsewhere herein.

[0132] In a first embodiment, forming the source / drain electrodes 228 includes performing a chemical vapor deposition operation using a metal precursor gas source 408 to deposit the source / drain electrodes 228 in the recess 404 , wherein the metal precursor gas source 408 is pulsed during the chemical vapor deposition operation.

[0133] In a second embodiment, either alone or in combination with the first embodiment, forming the source / drain electrode 228 includes performing a chemical vapor deposition operation using a metal precursor gas source 408 to deposit the source / drain electrode 228 in the recess 404, wherein the metal precursor gas source 408 is pulsedly supplied for a plurality of precursor gas pulse durations 414 during the chemical vapor deposition operation, and wherein the plurality of precursor gas pulse durations 414 are temporally separated by a plurality of nitrogen (N2) gas purges 416, wherein the metal precursor gas source 408 is purged using a nitrogen gas source 410 during the plurality of nitrogen gas purges 416.

[0134] In a third embodiment alone or in combination with one or more of the first and second embodiments, a ratio of a duration of a nitrogen purge 416 among the multiple nitrogen purges 416 to a duration of a precursor gas pulsation duration 414 among the multiple precursor gas pulsation durations 414 is within a range of approximately 5:3 to approximately 20:1.

[0135] In a fourth embodiment alone or in combination with one or more of the first to third embodiments, hydrogen (H 2 ) reactant gas 412 is continuously supplied during the plurality of precursor gas pulse durations 414 and the plurality of nitrogen purges 416 .

[0136] In a fifth embodiment, either alone or in combination with one or more of the first to fourth embodiments, forming the source / drain electrode 228 includes: performing a first chemical vapor deposition operation using a metal precursor gas source 408 to deposit a first portion of the source / drain electrode 228 in the recess 404, wherein the metal precursor gas source 408 is pulsedly supplied during the first chemical vapor deposition operation; and performing a second chemical vapor deposition operation to deposit a second portion of the source / drain electrode 228 in the recess 404 above the first portion, wherein the metal precursor gas source 408 is continuously supplied during the second chemical vapor deposition operation.

[0137] In a sixth embodiment alone or in combination with one or more of the first to fifth embodiments, the crystal grain size of the first portion is greater than the crystal grain size of the second portion.

[0138] In a seventh embodiment alone or in combination with one or more of the first to sixth embodiments, forming an electron barrier layer includes forming an electron barrier layer on the sidewalls of the groove, wherein forming an oxide insertion layer includes forming an oxide insertion layer on the electron barrier layer on the sidewalls of the groove, and wherein forming a metal glue layer includes forming a metal glue layer on the oxide insertion layer on the sidewalls of the groove.

[0139] In an eighth embodiment alone or in combination with one or more of the first to seventh embodiments, forming an electron barrier layer includes forming an electron barrier layer on the sidewalls of the groove and performing an etching operation to remove the electron barrier layer from the sidewalls of the groove, so that the electron barrier layer remains only on the metal oxide channel layer in the groove, and wherein forming an oxide insertion layer includes forming an oxide insertion layer on the sidewalls of the groove.

[0140] In a ninth embodiment alone or in combination with one or more of the first to eighth embodiments, forming the oxide insertion layer includes performing another etching operation to remove the oxide insertion layer from the sidewalls of the recess so that the oxide insertion layer remains only on the electron barrier layer in the recess.

[0141] In a tenth embodiment alone or in combination with one or more of the first to ninth embodiments, forming the metal glue layer includes forming the metal glue layer on the sidewalls of the groove, and wherein forming the source / drain electrodes includes forming the source / drain electrodes so that the metal glue layer is located between the source / drain electrodes and the sidewalls of the groove.

[0142] although Fig.12 Example blocks of process 1200 are shown, however, in some embodiments, compared to Fig.12 1, process 1200 may include additional blocks, fewer blocks, different blocks, or blocks arranged in a different manner. Additionally or alternatively, two or more of the blocks of process 1200 may be performed in parallel.

[0143] In this way, the FeRAM cell may include an oxide insertion layer between the electron barrier layer and the metal glue layer in the source / drain region of the FeRAM cell. The oxide insertion layer may improve the thermal stability of the electron barrier layer and minimize or prevent the dissociation and / or outward diffusion of the electron barrier layer at high processing temperatures. Therefore, the oxide insertion layer may enable the metal glue layer to be formed on the electron barrier layer with a low surface roughness, which may increase the adhesion between the metal glue layer in the source / drain region and the source / drain electrode. In this way, the oxide insertion layer may enable the FeRAM cell to achieve low resistance and / or may reduce the possibility of failure in the FeRAM cell, etc.

[0144] As described in more detail above, some embodiments described herein provide a nonvolatile memory cell structure. The nonvolatile memory cell structure includes a bottom gate electrode. The nonvolatile memory cell structure includes a memory layer located above the bottom gate electrode. The nonvolatile memory cell structure includes a metal oxide channel layer located above the memory layer. The nonvolatile memory cell structure includes a plurality of source / drain regions in a dielectric layer located above the metal oxide channel layer, wherein a source / drain region among the plurality of source / drain regions includes: an electron barrier layer located on the metal oxide channel layer; an oxide insertion layer located on the electron barrier layer; a metal glue layer located on the oxide insertion layer; and a source / drain electrode located on the metal glue layer.

[0145] In one embodiment, the oxide insertion layer comprises an oxide semiconductor material.

[0146] In one embodiment, the oxide insertion layer comprises a metal oxide material.

[0147] In one embodiment, the oxide insertion layer comprises a high-k dielectric material.

[0148] In one embodiment, the thickness of the oxide insertion layer is within a range of approximately 0.5 angstroms to approximately 5 nanometers.

[0149] As described in more detail above, some embodiments described herein provide a method. The method includes forming a bottom gate electrode of a nonvolatile memory cell structure. The method includes forming a ferroelectric layer of the nonvolatile memory cell structure above the bottom gate electrode. The method includes forming a metal oxide channel layer of the nonvolatile memory cell structure above the ferroelectric layer. The method includes forming a dielectric layer above the metal oxide channel layer. The method includes forming a groove in the dielectric layer to expose the metal oxide channel layer through the groove. The method includes forming an electron barrier layer on the metal oxide channel layer in the groove. The method includes forming an oxide insertion layer on the electron barrier layer in the groove. The method includes forming a metal glue layer on the oxide insertion layer in the groove. The method includes forming a source / drain electrode of the nonvolatile memory cell structure on the metal glue layer.

[0150] In one embodiment, forming the source / drain electrodes comprises: performing a chemical vapor deposition operation using a metal precursor gas source to deposit the source / drain electrodes in the recesses, wherein the metal precursor gas source is pulsed during the chemical vapor deposition operation.

[0151] In one embodiment, forming the source / drain electrode includes: performing a chemical vapor deposition operation using a metal precursor gas source to deposit the source / drain electrode in the groove, wherein the metal precursor gas source is pulsedly supplied for multiple precursor gas pulsation durations during the chemical vapor deposition operation, and wherein the multiple precursor gas pulsation durations are temporally spaced apart by multiple nitrogen (N2) gas purges, wherein the metal precursor gas source is purged using a nitrogen source during the multiple nitrogen purges.

[0152] In one embodiment, a ratio of a duration of a nitrogen purge in the plurality of nitrogen purges to a duration of a precursor gas pulsation in the plurality of precursor gas pulsation durations is within a range of approximately 5:3 to approximately 20:1.

[0153] In one embodiment, hydrogen (H 2 ) reactant gas is continuously supplied during the plurality of precursor gas pulse durations and the plurality of nitrogen gas purges.

[0154] In one embodiment, forming the source / drain electrode includes: performing a first chemical vapor deposition operation using a metal precursor gas source to deposit a first portion of the source / drain electrode in the groove, wherein the metal precursor gas source is pulsedly supplied during the first chemical vapor deposition operation; and performing a second chemical vapor deposition operation to deposit a second portion of the source / drain electrode in the groove above the first portion, wherein the metal precursor gas source is continuously supplied during the second chemical vapor deposition operation.

[0155] In one embodiment, the crystal grain size of the first portion is larger than the crystal grain size of the second portion.

[0156] In one embodiment, forming the electron barrier layer includes: forming the electron barrier layer on the sidewall of the groove; forming the oxide insertion layer includes: forming the oxide insertion layer on the electron barrier layer on the sidewall of the groove; and forming the metal glue layer includes: forming the metal glue layer on the oxide insertion layer on the sidewall of the groove.

[0157] In one embodiment, forming the electron barrier layer includes: forming the electron barrier layer on the sidewalls of the groove; and performing an etching operation to remove the electron barrier layer from the sidewalls of the groove, so that the electron barrier layer remains only on the metal oxide channel layer in the groove; and forming the oxide insertion layer includes: forming the oxide insertion layer on the sidewalls of the groove.

[0158] In one embodiment, forming the oxide insertion layer includes: performing another etching operation to remove the oxide insertion layer from the sidewall of the groove, so that the oxide insertion layer remains only on the electron barrier layer in the groove.

[0159] In one embodiment, forming the metal paste layer includes: forming the metal paste layer on the sidewall of the groove; and forming the source / drain electrode includes: forming the source / drain electrode so that the metal paste layer is located between the source / drain electrode and the sidewall of the groove.

[0160] As described in more detail above, some embodiments described herein provide a nonvolatile memory cell structure. The nonvolatile memory cell structure includes a seed layer. The nonvolatile memory cell structure includes a ferroelectric layer located above the seed layer. The nonvolatile memory cell structure includes a metal oxide channel layer located above the ferroelectric layer. The nonvolatile memory cell structure includes a plurality of source / drain regions in a dielectric layer located above the metal oxide channel layer, wherein a source / drain region among the plurality of source / drain regions includes: an electron barrier layer located on the metal oxide channel layer; an oxide insertion layer located on the electron barrier layer; a metal glue layer located on the oxide insertion layer; and a source / drain electrode located on the metal glue layer.

[0161] In one embodiment, the oxide insertion layer includes at least one of the following: gallium oxide (GaO), silicon oxide (SiOx), hafnium oxide (HfOx), aluminum oxide (AlxOy), and zirconium oxide (ZrOx).

[0162] In one embodiment, the metal paste layer is further located between the sidewalls of the source / drain electrodes and the dielectric layer and is in contact with the sidewalls of the source / drain electrodes and the dielectric layer.

[0163] In one embodiment, the electron barrier layer, the oxide insertion layer and the metal paste layer are further located between the sidewalls of the source / drain electrodes and the dielectric layer.

[0164] As used herein, “satisfies a threshold” may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, less than or equal to a threshold, equal to a threshold, not equal to a threshold, or the like, depending on the context.

[0165] The features of several embodiments are summarized above so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications to them without departing from the spirit and scope of the present disclosure.

Claims

1. A non-volatile memory cell structure, characterized in that include: a bottom gate electrode; a memory layer located above the bottom gate electrode; A metal oxide channel layer, located above the memory layer; as well as A plurality of source / drain regions are located in the dielectric layer above the metal oxide channel layer, A source / drain region among the plurality of source / drain regions comprises: An electron barrier layer, located on the metal oxide channel layer; an oxide insertion layer, located on the electron barrier layer; a metal paste layer, located on the oxide insertion layer; and The source / drain electrode is located on the metal paste layer.

2. The nonvolatile memory cell structure according to claim 1, characterized in that The oxide insertion layer includes an oxide semiconductor material.

3. The nonvolatile memory cell structure according to claim 1, characterized in that The oxide insertion layer includes a metal oxide material.

4. The nonvolatile memory cell structure according to claim 1, characterized in that The oxide insertion layer includes a high-k dielectric material.

5. The nonvolatile memory cell structure according to claim 1, characterized in that The thickness of the oxide insertion layer is in the range of 0.5 angstroms to 5 nanometers.

6. A method for forming a non-volatile memory cell structure, characterized in that include: forming a bottom gate electrode of a nonvolatile memory cell structure; forming a ferroelectric layer of the nonvolatile memory cell structure above the bottom gate electrode; forming a metal oxide channel layer of the nonvolatile memory cell structure above the ferroelectric layer; forming a dielectric layer over the metal oxide channel layer; forming a groove in the dielectric layer to expose the metal oxide channel layer through the groove; forming an electron barrier layer on the metal oxide channel layer in the groove; forming an oxide insertion layer on the electron barrier layer in the groove; forming a metal paste layer on the oxide insertion layer in the groove; as well as The source / drain electrodes of the nonvolatile memory cell structure are formed on the metal paste layer.

7. The method according to claim 6, characterized in that Forming the source / drain electrodes comprises: performing a chemical vapor deposition operation using a metal precursor gas source to deposit the source / drain electrodes in the recesses, The metal precursor gas source is pulsed during the chemical vapor deposition operation.

8. The method according to claim 6, characterized in that Forming the source / drain electrodes includes: performing a chemical vapor deposition operation using a metal precursor gas source to deposit the source / drain electrodes in the recesses, wherein the metal precursor gas source is pulsed during the chemical vapor deposition operation for a plurality of precursor gas pulse durations, and The plurality of precursor gas pulse durations are temporally separated by a plurality of nitrogen purges in which the metal precursor gas source is purged using a nitrogen source.

9. A non-volatile memory cell structure, characterized in that include: seed layer; a ferroelectric layer located above the seed layer; a metal oxide channel layer located above the ferroelectric layer; as well as A plurality of source / drain regions are located in the dielectric layer above the metal oxide channel layer, A source / drain region among the plurality of source / drain regions comprises: An electron barrier layer, located on the metal oxide channel layer; an oxide insertion layer, located on the electron barrier layer; a metal paste layer, located on the oxide insertion layer; and The source / drain electrode is located on the metal paste layer.

10. The nonvolatile memory cell structure according to claim 9, characterized in that The oxide insertion layer comprises at least one of the following: Gallium oxide, silicon oxide, hafnium oxide, aluminum oxide, and zirconium oxide.

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