A vertical sub-1nm gate length field effect transistor and a preparation method thereof

Abstract

The present invention relates to the technical field of transistor fabrication, and provides a vertical sub-1nm gate length field-effect transistor and a fabrication method, comprising: a stepped substrate, a graphene gate, a low dielectric constant dielectric layer, a high dielectric constant dielectric layer, a two-dimensional thin film channel, and a contact metal; the stepped substrate has a stepped structure, and by using the stepped substrate as a support layer for the graphene gate, the graphene in the graphene gate adheres to the side wall of the stepped substrate; the low dielectric constant dielectric layer is used as a backfill step to engage with the stepped structure of the stepped substrate to fill the stepped structure of the stepped substrate; the high dielectric constant dielectric layer is provided as a gate dielectric layer on top of the low dielectric constant dielectric layer; the two-dimensional thin film channel is provided on top of the high dielectric constant dielectric layer, and the contact metal is provided on the two-dimensional thin film channel to form an electrical connection with the two-dimensional thin film channel. The present invention innovatively proposes how to fabricate single-gate and multi-gate transistors with a vertical gate length of less than 1 nanometer.

Description

Technical Field

[0001] The present invention relates to the technical field of transistor fabrication, and particularly to a vertical sub-1nm gate length field effect transistor and a fabrication method thereof. Background Art

[0002] In the field of microelectronics technology, the continuous reduction of transistor size is the core driving force for the development of the industry. With the progress of technology, the feature size of transistors has approached the sub-10 nanometer level, and traditional planar silicon-based devices face major challenges at this scale. To overcome these challenges, the industry has begun to explore new transistor structures, including double-gate, multi-gate, and gate-all-around designs. Although these new structures can continue Moore's Law, they often require more complex manufacturing processes and higher costs.

[0003] Traditional planar field effect transistors (FETs) form a conductive channel in a silicon substrate through doping technology, constructing a metal-oxide-semiconductor (MOS) structure. In this design, as the channel length continues to shorten, the control ability of the metal gate over the channel gradually weakens, leading to an increasingly serious short-channel effect problem. To solve this problem, the industry has proposed various new transistor structures, including finFETs, fully depleted silicon-on-insulator (FD-SOI) FETs, and gate-all-around nanowire FETs.

[0004] FinFETs enhance the control ability of the gate over the channel by designing the channel into a three-dimensional structure, effectively alleviating the short-channel effect. However, with further technological development, when the transistor size is further reduced to below 10 nanometers, the cost problem of this design becomes particularly prominent. FD-SOI FETs improve the control ability of the gate over the channel by forming an oxide layer between the silicon film and the insulator, reducing leakage current and the Kink effect (warping effect), but at the same time, they also bring larger leakage current and lateral bipolar transistor effects, and the manufacturing cost is high.

[0005] Gate-all-around nanowire FETs provide stronger control through a gate design that surrounds the entire channel, but this design faces many technical challenges in the manufacturing process, including complex gate manufacturing, nanowire and contact problems, and dependence on non-silicon materials, which all increase the manufacturing cost and reduce the compatibility with traditional CMOS processes.

[0006] Although the above technical solutions have made certain progress in enhancing the control ability of the gate over the conductive channel, how to further reduce the effective channel length while not relying on the accuracy of the lithography machine remains the focus of current research. Two-dimensional materials, due to their atomic layer thickness, are ideal choices for ultra-thin bodies, effectively suppressing the short-channel effect and showing superior properties to traditional silicon-based materials in many aspects, and are regarded as potential mainstream materials for the next-generation CMOS process.

[0007] At present, research on transistors based on two-dimensional materials has made extensive progress, but how to use its atomic layer thickness to prepare transistors with extremely narrow effective gate lengths is still an urgent problem to be solved. Studies have reduced the gate length to 1 nanometer by using carbon nanotubes as gates. In recent studies, a research team proposed a sub-nanometer transistor with a horizontal gate structure and a vertical channel, but this structure cannot be integrated with planar transistor technology, and its speed improvement is limited due to its large capacitance. In addition, the team also proposed the use of molybdenum disulfide (MoS 2 ) is generated as a planar transistor structure with sub-nanometer gates, but the generation of this structure is random and difficult to achieve large-scale array preparation.

[0008] In summary, the semiconductor industry currently has no clear solution to achieve transistors with a gate length of less than 1 nanometer that are compatible with planar transistor processes and can be prepared in scalable arrays. This remains a technical bottleneck that needs to be overcome urgently. Summary of the invention

[0009] The present invention provides a vertical sub-1nm gate length field effect transistor and a preparation method, which are used to solve the problem in the prior art that it is difficult to carry out large-scale array preparation of transistors with a gate length of less than 1nm, and innovatively proposes how to prepare vertical single-gate and multi-gate transistors with a gate length of less than 1 nanometer.

[0010] The present invention provides a vertical sub-1nm gate length field effect transistor, comprising:

[0011] Step substrate, graphene gate, low dielectric constant dielectric layer, high dielectric constant dielectric layer, two-dimensional thin film channel and contact metal;

[0012] The step substrate has a step structure, and the step substrate is used as a support layer of the graphene grid, so that the graphene in the graphene grid is attached to the side wall of the step substrate;

[0013] The low dielectric constant dielectric layer acts as a backfill step and meshes with the step structure of the step base to fill the step structure of the step base;

[0014] The high dielectric constant dielectric layer is arranged on top of the low dielectric constant dielectric layer as a gate dielectric layer;

[0015] The two-dimensional thin film channel is arranged on the top of the high dielectric constant dielectric layer, and the contact metal is arranged on the two-dimensional thin film channel to form an electrical connection with the two-dimensional thin film channel.

[0016] According to a vertical sub-1 nm gate length field effect transistor provided by the present invention, the step substrate includes a side wall and a horizontal portion, and the side wall and the horizontal portion are both set to insulating material.

[0017] According to a vertical sub-1nm gate length field effect transistor provided by the present invention, the graphene gate serves as the gate, with a thickness of sub-1nm, and the vertical graphene is transferred to the sidewall of the stepped substrate by a wet transfer method;

[0018] Pattern the graphene on the sidewall of the stepped substrate by photolithography so that the graphene has a target structure.

[0019] According to a vertical sub-1nm gate length field effect transistor provided by the present invention, after the low dielectric constant dielectric layer backfills the stepped structure of the stepped substrate, polish the area below the joint of the low dielectric constant dielectric layer and the stepped structure by chemical mechanical polishing to obtain a vertical graphene surface.

[0020] The present invention also provides a method for fabricating a vertical sub-1nm gate length field effect transistor, including:

[0021] Etch a stepped substrate through a deep silicon etching device;

[0022] Generate an initial silicon dioxide layer on the surface of the stepped structure through a thermal oxidation device;

[0023] Remove the initial silicon dioxide layer using a buffered oxide etchant to obtain a smooth silicon surface;

[0024] Generate a first silicon dioxide layer on the silicon surface through an inductively coupled plasma enhanced chemical vapor deposition device, where the first silicon dioxide layer is a substrate silicon dioxide layer;

[0025] Transfer graphene to the sidewall of the stepped substrate with a silicon dioxide layer by wet transfer and pattern it;

[0026] Complete the deposition of the graphene contact metal through photolithography, generate a seed layer on the graphene surface by angled deposition, and generate a second silicon dioxide layer on the surface of the seed layer through an inductively coupled plasma enhanced chemical vapor deposition device;

[0027] Grind the area below the junction of the first silicon dioxide layer and the second silicon dioxide layer by chemical mechanical polishing to obtain vertical graphene and a flat wafer interface;

[0028] Generate a high dielectric constant dielectric layer on the wafer surface above the vertical graphene, and construct a two-dimensional thin film channel on the top of the high dielectric constant dielectric layer;

[0029] Deposit the contact metal of the two-dimensional material on the two-dimensional thin film channel to complete the fabrication of the transistor.

[0030] According to a method for fabricating a vertical sub-1nm gate length field effect transistor provided by the present invention, the step of removing the initial silicon dioxide layer using a buffered oxide etchant to obtain a smooth silicon surface includes:

[0031] The initial silicon dioxide layer on the surface of the stepped structure is rinsed with a BOE solution, and the initial silicon dioxide layer is oxidized and etched. After removing the initial silicon dioxide layer, a silicon surface is obtained.

[0032] According to a method for fabricating a vertical sub-1nm gate-length field-effect transistor provided by the present invention, the method of transferring graphene to the sidewall of a stepped substrate with a silicon dioxide layer by wet transfer and patterning includes:

[0033] Transfer graphene to the sidewall of the stepped substrate with a silicon dioxide layer by wet transfer;

[0034] Make the graphene vertically adhere to the sidewall of the step by a set stress release method;

[0035] Perform photolithographic patterning on the graphene on the sidewall of the step so that the graphene has a specific structure.

[0036] According to a method for fabricating a vertical sub-1nm gate-length field-effect transistor provided by the present invention, the method of transferring graphene to the sidewall of a stepped substrate with a silicon dioxide layer by wet transfer includes:

[0037] Coat a polymer support layer on the surface of the graphene;

[0038] Continue to coat a photoresist layer on the surface of the graphene with the polymer support layer;

[0039] Pattern the photoresist layer to form a stress transfer region without photoresist and a stress protection region with photoresist, and construct a composite sacrificial coating;

[0040] Transfer the graphene with the composite sacrificial coating to the target substrate;

[0041] Among them, the target substrate is the sidewall of a stepped substrate with a silicon dioxide layer.

[0042] According to a method for fabricating a vertical sub-1nm gate-length field-effect transistor provided by the present invention, the method of transferring the graphene with the composite sacrificial coating to the target substrate includes:

[0043] Regulate the pattern of the photoresist layer, and through photolithography, the stress release degree of the photoresist layer in different thickness regions is different, so as to realize the stress release of the graphene;

[0044] During the stress release process of the graphene, natural fracture occurs in the region without photoresist protection in the photoresist layer, so that the graphene is completely transferred to the sidewall of the stepped substrate with a silicon dioxide layer.

[0045] A method for fabricating a vertical sub-1nm gate length field effect transistor provided by the present invention, depositing a contact metal of a two-dimensional material on a two-dimensional thin film channel to complete the fabrication of the transistor, includes:

[0046] Depositing metal titanium or palladium or chromium or gold or bismuth on the two-dimensional thin film channel to construct a contact metal and complete the fabrication of the transistor.

[0047] A vertical sub-1nm gate length field effect transistor and a fabrication method provided by the present invention realize further reduction of the transistor size by adopting a vertical graphene gate with a sub-1nm size, maintain compatibility with existing processes, and have the potential for large-scale manufacturing at the same time. This design can not only increase the transistor density but also be fabricated on a large scale, providing a feasible path for advanced process chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0049] Figure 1 It is a schematic structural diagram of a vertical sub-1nm gate length field effect transistor provided by the present invention.

[0050] Figure 2 It is a schematic diagram of the manufacturing process of a single-gate vertical sub-1nm transistor provided by the present invention.

[0051] Figure 3 It is a schematic diagram of the manufacturing process of a double-gate vertical sub-1nm transistor provided by the present invention.

[0052] Figure 4 It is a schematic diagram of the manufacturing process of a double-gate or even multi-gate vertical sub-1nm transistor provided by the present invention.

[0053] Figure 5 It is a light microscope photograph provided by the present invention.

[0054] Figure 6 It is an electrical test curve of a single-gate embodiment provided by the present invention.

[0055] Figure 7 It is an electrical test curve of a double-gate embodiment provided by the present invention.

[0056] Reference numerals: 101: stepped substrate; 102: graphene gate; 103: low dielectric constant dielectric layer; 104: high dielectric constant dielectric layer; 105: two-dimensional thin film channel; 106: contact metal. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0057] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts fall within the scope of protection of the present invention.

[0058] The following will describe a vertical sub-1nm gate-length field-effect transistor of the present invention in conjunction with Figure 1 which includes:

[0059] a stepped substrate 101, a graphene gate 102, a low dielectric constant dielectric layer 103, a high dielectric constant dielectric layer 104, a two-dimensional thin film channel 105, and a contact metal 106;

[0060] The stepped substrate 101 has a stepped structure. By using the stepped substrate 101 as a support layer for the graphene gate 102, the graphene in the graphene gate 02 adheres to the sidewall of the stepped substrate 101.

[0061] The low dielectric constant dielectric layer 103 meshes with the stepped structure of the stepped substrate 101 as a backfill step to fill the stepped structure of the stepped substrate 101.

[0062] The high dielectric constant dielectric layer 104 is provided on top of the low dielectric constant dielectric layer 103 as a gate dielectric layer.

[0063] The two-dimensional thin film channel 105 is provided on top of the high dielectric constant dielectric layer 104, and the contact metal 106 is provided on the two-dimensional thin film channel 105 to form an electrical connection with the two-dimensional thin film channel 105.

[0064] In the present invention, the stepped substrate 101 serves as a gate support layer and has a smooth surface, including a stepped sidewall and a horizontal portion, and is usually an insulating material such as SiO 2 . The vertical graphene gate 102 serves as a gate, and its thickness is at the sub-1nm level. The gate length of sub-1nm is achieved by defining the gate using the thickness of graphene. The low dielectric constant dielectric layer 103 serves as a backfill step and completely fills the stepped structure. The stepped low dielectric constant dielectric layer 103 is usually the same medium. The high dielectric constant dielectric layer 104 serves as a gate dielectric layer and usually uses a high dielectric material such as HfO 2 , ZrO 2 , Al 2 O 3. The two-dimensional thin film channel 105 is horizontally arranged and uses a two-dimensional thin film or an oxide semiconductor with semiconductor characteristics. The contact metal 106 is used to form an electrical connection with the two-dimensional thin film channel 105 and can be a metal or a conductive non-metal.

[0065] Among them, the graphene gate 102 serves as the gate, with a thickness of sub-1 nm. The vertical graphene is transferred to the sidewall of the stepped substrate 101 by a wet transfer method;

[0066] On the sidewall of the stepped substrate 101, lithographic patterning is performed so that the graphene has a specific structure.

[0067] For the transfer of the graphene gate 102, the vertical graphene is transferred to the sidewall of the stepped substrate 101 by a wet transfer method, and a special stress release process is adopted to ensure that the graphene is vertically attached to the stepped sidewall without damage. For lithographic patterning, the vertical graphene gate 102 needs to be lithographically patterned after transfer to complete the appropriate structural area.

[0068] In addition, a seed layer is formed on the graphene surface. By means of angled deposition, a seed layer such as SiO 2 , Al 2 O 3 is formed on the surface of the vertical graphene gate 102 to facilitate the subsequent formation of other materials.

[0069] After the low dielectric constant dielectric layer 103 backfills the stepped structure of the stepped substrate 101, chemical mechanical polishing is used to polish the area below the joint of the low dielectric constant dielectric layer 103 and the stepped structure to obtain a smooth vertical graphene surface.

[0070] In the present invention, the graphene is cut by chemical mechanical polishing, and after obtaining a smooth surface, it is convenient for the formation of the high dielectric constant dielectric layer 104.

[0071] See Figure 2 , the present invention also discloses a method for fabricating a vertical sub-1 nm gate length field effect transistor, including:

[0072] Refer to Figure 2 a, etching a stepped substrate through a deep silicon etching device;

[0073] Refer to Figure 2 b, generating an initial silicon dioxide layer on the surface of the stepped structure through a thermal oxidation device;

[0074] Refer to Figure 2 c, removing the initial silicon dioxide layer using a buffered oxide etchant to obtain a smooth silicon surface;

[0075] Refer to Figure 2d. A smooth first silicon dioxide layer is formed on the smooth silicon surface by an inductively coupled plasma enhanced chemical vapor deposition device, where the first silicon dioxide layer is the substrate silicon dioxide layer;

[0076] Reference Figure 2 e. Transfer the graphene to the sidewall of the stepped substrate with a silicon dioxide layer by wet transfer and pattern it;

[0077] Reference Figure 2 f and Figure 2 g. Deposit the graphene contact metal by photolithography, generate a seed layer on the graphene surface by angled deposition, and generate a second silicon dioxide layer on the seed layer surface by an inductively coupled plasma enhanced chemical vapor deposition device;

[0078] Reference Figure 2 h. Grind by chemical mechanical polishing below the junction of the first silicon dioxide layer and the second silicon dioxide layer to obtain smooth vertical graphene and a flat wafer interface;

[0079] Reference Figure 2 i and Figure 2 j. Generate a high-k dielectric layer on the smooth vertical graphene surface and construct a two-dimensional thin film channel on the top of the high-k dielectric layer;

[0080] Reference Figure 2 k. Deposit the contact metal of the two-dimensional material on the two-dimensional thin film channel to complete the preparation of the transistor.

[0081] Specifically, the stepped substrate is etched to 500 nm by a silicon deep etching device.

[0082] Use a thermal oxidation device to generate a silicon dioxide layer of about 350 nm on the stepped surface. The thermal oxidation device can make the underlying silicon surface smooth, so the surface smoothing is completed using thermal oxidation technology.

[0083] During the process of removing the initial silicon dioxide layer with a buffered oxide etchant to obtain a smooth silicon surface, the initial silicon dioxide layer on the stepped structure surface is rinsed with a BOE solution, the initial silicon dioxide layer is oxidized and etched, and a smooth silicon surface is obtained after removing the initial silicon dioxide layer.

[0084] Generate a smooth silicon dioxide dielectric by using ICP-PECVD to form an insulating silicon dioxide layer on the stepped surface. In this embodiment, 400 nm of SiO 2 .

[0085] Among them, ICP-PECVD (Inductively Coupled Plasma - Plasma Enhanced Chemical Vapor Deposition) is a technology used for depositing high-quality thin films in semiconductor manufacturing and other microelectronic applications. This technology combines the advantages of Plasma Enhanced Chemical Vapor Deposition (PECVD) and Inductively Coupled Plasma (ICP), enabling high-quality and high-density thin film deposition at relatively low temperatures.

[0086] Compared with traditional thermal CVD, ICP-PECVD can deposit thin films at lower temperatures, which helps protect temperature-sensitive substrate materials and allows for a wider range of material choices. By using a radio frequency (RF) power source to generate an inductively coupled plasma, ICP-PECVD can produce a high-density plasma, thereby increasing the reaction rate and the quality of the thin film. ICP-PECVD can provide better film thickness uniformity and compositional consistency, which are crucial for the production of high-performance microelectronic devices. Due to the activation effect of the plasma, ICP-PECVD typically has a higher deposition rate than traditional PECVD. For substrates with complex topologies, such as high aspect ratio features, ICP-PECVD can provide good step coverage capabilities, ensuring that all surfaces are uniformly covered with the thin film. The ICP-PECVD system can be adjusted according to different process requirements, such as changing parameters like power, pressure, gas mixture, etc., to meet different types of thin film deposition requirements.

[0087] A typical ICP-PECVD process flow includes:

[0088] 1. Preparation stage

[0089] Loading the substrate: Place the substrate to be processed into the reaction chamber, ensuring that the substrate is well-fixed and its surface is clean and free of contamination.

[0090] Evacuating the chamber: Close the reaction chamber and use a vacuum pump to reduce the pressure inside the chamber to the desired low vacuum state, usually in millitorr (mTorr) or lower.

[0091] 2. Pretreatment (optional)

[0092] Substrate preheating: If necessary, the substrate can be preheated first to remove moisture or other impurities adsorbed on the surface. This helps improve the quality and adhesion of the thin film.

[0093] Plasma cleaning: Sometimes, a plasma generated by oxygen or other gases is used to clean the substrate surface, further improving the thin film quality.

[0094] 3. Process parameter setting

[0095] Set the temperature: Adjust the substrate heater to bring the substrate to the specified working temperature, which is crucial for ensuring uniform thin film deposition.

[0096] Regulate the gas flow: Introduce an appropriate amount of reactive gases (such as silane, ammonia, etc.) through a mass flow controller. These gases will undergo chemical reactions under the action of plasma.

[0097] Set the RF power: Apply an appropriate RF power to the inductively coupled coil to generate a sufficient plasma density. The ICP source can provide a higher plasma density than traditional PECVD, thus promoting more efficient reactions.

[0098] 4. Plasma generation and deposition

[0099] Start the plasma: Turn on the RF power supply to activate the inductively coupled plasma. At this time, the reactive gases are dissociated into active species, which undergo chemical reactions on the substrate to form the desired thin film.

[0100] Monitor the process: Use tools such as an optical emission spectrometer (OES) and a mass spectrometer to monitor the state of the plasma and the thin film formation in real time, ensuring a stable deposition process.

[0101] 5. End stage

[0102] Turn off the plasma: When the predetermined deposition time or film thickness is reached, turn off the RF power supply to terminate plasma generation.

[0103] Cool the substrate: Let the substrate cool naturally or adopt forced cooling measures to reduce its temperature to a safe level.

[0104] Restore atmospheric pressure: Slowly fill the reaction chamber with an inert gas (such as nitrogen) until the atmospheric pressure is restored.

[0105] Unload the substrate: Open the reaction chamber and remove the substrate on which the thin film has been deposited.

[0106] 6. Inspection and analysis

[0107] Check the thin film properties: Use various characterization techniques (such as scanning electron microscopy SEM, X-ray diffraction XRD, ellipsometer, etc.) to evaluate the thickness, composition, structure, and other physical properties of the thin film to ensure compliance with the expected standards.

[0108] Transfer the graphene to the sidewall of the stepped substrate with a silica layer by wet transfer and pattern it, including:

[0109] Transfer the graphene to the sidewall of the stepped substrate with a silica layer by wet transfer;

[0110] Vertically attach graphene to the sidewall of the step by a set stress release method;

[0111] Perform photolithographic patterning on the graphene on the sidewall of the step so that the graphene has a specific structure.

[0112] Among them, transferring graphene to the sidewall of the step with a silicon dioxide layer by a wet transfer method includes:

[0113] Coat a polymer support layer on the surface of the graphene;

[0114] Continue to coat a photoresist layer on the surface of the graphene with the polymer support layer;

[0115] Pattern the photoresist layer to form a stress transfer area without photoresist and a stress protection area with photoresist, and construct a composite sacrificial coating;

[0116] Transfer the graphene with the composite sacrificial coating to the target substrate;

[0117] Among them, the target substrate is the sidewall of the step with a silicon dioxide layer.

[0118] Regulate the pattern of the photoresist layer, and through photolithography, make the stress release degree of the photoresist layer in different thickness regions different, so as to realize the stress release of graphene;

[0119] During the stress release process of graphene, natural fracture occurs in the area without photoresist protection in the photoresist layer, so that graphene is completely transferred on the sidewall of the step with a silicon dioxide layer.

[0120] In the present invention, the deposition of graphene in contact with metal is completed by photolithography. It can usually be metal and other conductive non-metals, highly doped p-type and n-type silicon, germanium semiconductors, flexible electrode materials, etc. For this embodiment, it is 5nm / 30nm of metal Ti / Pd. Deposit a silicon dioxide seed layer at an angle, and then complete 1.5um of SiO 2 layer by ICP-PECVD. After that, perform an annealing process at 250°C for more than 1 hour.

[0121] Generate a high dielectric constant dielectric layer, usually HfO 2 、ZrO 2 、Al 2 O 3 For this embodiment, it is 15nm of HfO 2 And complete the hole etching of the gate.

[0122] Deposit the contact metal of the two-dimensional material on the two-dimensional thin film channel to complete the preparation of the transistor, including:

[0123] Deposit metal titanium, palladium, chromium, gold, or bismuth on the two-dimensional thin film channel to construct a contact metal and complete the preparation of the transistor.

[0124] Specifically, the contact metal deposited on the two-dimensional material can generally be metals and other conductive non-metals, highly doped p-type and n-type silicon, germanium semiconductors, flexible electrode materials, etc. For this embodiment, it is 5 nm / 30 nm of metal Ti / Pd.

[0125] In another embodiment, referring to Figure 3 , when preparing the stepped substrate, etch the steps into a denser structure, so that a double-gate transistor can be realized. Other steps are the same as those in the previous embodiment.

[0126] In yet another embodiment, referring to Figure 4 , when transferring graphene, a method of transferring graphene multiple times and separating it with a dielectric layer is adopted to complete the multi-gate structure (see Figure 4 l- Figure 4 n), and other steps are the same as those in the previous embodiment.

[0127] After experiments, referring to Figure 5 shows the optical microscope photos of several different embodiments. Figure 5 a and 5b respectively show the optical microscope images of the graphene gate on the left and right sidewalls. Figure 5 c shows the optical microscope image of the double-gate transistor. All embodiments have obvious characteristics.

[0128] To verify the effects of the embodiments of the present invention, the fabricated devices were tested. See Figure 6 , which is the transfer characteristic curve (I ds -V g ) of the vertical sub-1 nm single-gate transistor fabricated in the example of the present invention. The figure shows the transfer characteristic curves at V ds = 0.01, 0.1, and 1 V respectively. The gate voltage is scanned from -6 V to 6 V. The devices shown in the embodiments have typical saturation characteristics and obvious curve characteristics of sub-1 nm transistors.

[0129] In addition, Figure 7 shows the transfer characteristic curve (I ds -V g ) of the vertical sub-1 nm double-gate transistor. Figure 7 The left figure of Figure 7 shows the device state diagram when the second gate is floating, and the right figure of

[0130] shows the transfer characteristic curves of the device when different voltages are applied to the second gate. It can be seen that the device has obvious characteristics modulated by the double gate.The core of the present invention lies in a monolayer or few-layer vertical graphene with a thickness less than 1 nm as the gate. Different from traditional transistors, the present invention uses vertical structure graphene as the gate and adopts special step wet transfer process, low dielectric constant backfilling process, and chemical mechanical polishing process to complete the preparation of the entire gate. In addition, silicon oxide is used as a low dielectric constant insulating layer to reduce the gate-drain and gate-source capacitances; a two-dimensional film is used as the conductive channel and covered on the high dielectric constant insulating layer, thereby completing the entire single-gate or double-gate vertical sub-1 nm gate length and planar two-dimensional film field effect transistor.

[0131] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative labor.

[0132] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course also by hardware. Based on this understanding, the above technical solution, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a vertical sub-1nm gate length field effect transistor, used for preparing a vertical sub-1nm gate length field effect transistor, characterized in that: include: Etching a step base by using a silicon deep etching device; Generating an initial silicon dioxide layer on the surface of the step structure by a thermal oxidation device; A buffered oxide etchant is used to remove the initial silicon dioxide layer to obtain a smooth silicon surface; Generating a first silicon dioxide layer on the silicon surface by using an inductively coupled plasma enhanced chemical vapor deposition device, wherein the first silicon dioxide layer is a base silicon dioxide layer; Transferring graphene onto the sidewall of a stepped substrate having a silicon dioxide layer by wet transfer and patterning the graphene; The graphene contact metal is deposited by photolithography, and a seed layer is generated on the graphene surface by angle deposition, and a second silicon dioxide layer is generated on the seed layer surface by inductively coupled plasma enhanced chemical vapor deposition equipment; Grinding below the junction of the first silicon dioxide layer and the second silicon dioxide layer by chemical mechanical polishing to obtain vertical graphene and a flat wafer interface; A high dielectric constant dielectric layer is generated on the wafer surface above the vertical graphene, and a two-dimensional thin film channel is constructed on the top of the high dielectric constant dielectric layer; A contact metal of two-dimensional material is deposited on the two-dimensional thin film channel to complete the preparation of the transistor.

2. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: The method of removing the initial silicon dioxide layer by using a buffered oxide etchant to obtain a smooth silicon surface comprises: The initial silicon dioxide layer on the surface of the step structure is washed with a BOE solution, the initial silicon dioxide layer is oxidized and etched, and the silicon surface is obtained after the initial silicon dioxide layer is removed.

3. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: The method of transferring graphene to the sidewall of a step substrate having a silicon dioxide layer by wet transfer and patterning the graphene comprises: Transferring graphene to the step sidewall with the silicon dioxide layer by wet transfer; The graphene is vertically attached to the side wall of the step through a set stress release method; Photolithography patterning is performed on the graphene on the sidewall of the step so that the graphene has a specific structure.

4. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: The step of transferring the graphene to the step sidewall having the silicon dioxide layer by wet transfer comprises: Coating a polymer support layer on the surface of graphene; Continue coating a photoresist layer on the surface of the graphene with the polymer support layer; The photoresist layer is patterned to form a stress transfer area without photoresist and a stress protection area with photoresist, so as to construct a composite sacrificial coating; transferring the graphene with the composite sacrificial coating onto a target substrate; The target substrate is a step sidewall having a silicon dioxide layer.

5. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 4, characterized in that: The step of transferring the graphene with the composite sacrificial coating to a target substrate comprises: The pattern of the photoresist layer is adjusted, and the stress release degree of the photoresist layer in different thickness areas is different through photolithography, so as to achieve stress release of graphene; During the graphene stress release process, natural fracture occurs in the area of ​​the photoresist layer without photoresist protection, allowing the graphene to be completely transferred on the step sidewall with the silicon dioxide layer.

6. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: The step of depositing a contact metal of a two-dimensional material on a two-dimensional thin film channel to complete the preparation of a transistor includes: Metal titanium, palladium, chromium, gold or bismuth is deposited on the two-dimensional thin film channel to construct contact metal and complete the transistor preparation.

7. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 1, characterized in that: The transistor comprises: Step substrate, graphene gate, low dielectric constant dielectric layer, high dielectric constant dielectric layer, two-dimensional thin film channel and contact metal; The step substrate has a step structure, and the step substrate is used as a support layer of the graphene grid, so that the graphene in the graphene grid is attached to the side wall of the step substrate; The low dielectric constant dielectric layer acts as a backfill step and meshes with the step structure of the step base to fill the step structure of the step base; The high dielectric constant dielectric layer is arranged on top of the low dielectric constant dielectric layer as a gate dielectric layer; The two-dimensional thin film channel is arranged on the top of the high dielectric constant dielectric layer, and the contact metal is arranged on the two-dimensional thin film channel to form an electrical connection with the two-dimensional thin film channel.

8. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 7, characterized in that: The step base includes a side wall and a horizontal portion, and both the side wall and the horizontal portion are provided with an insulating material.

9. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 7, characterized in that: The graphene gate is used as a gate electrode, and has a thickness of sub-1 nm. The vertical graphene is transferred to the sidewall of the step substrate by wet transfer; The sidewall of the step substrate is patterned by photolithography so that the graphene has a target structure.

10. The method for preparing a vertical sub-1 nm gate length field effect transistor according to claim 7, characterized in that: After the low dielectric constant dielectric layer backfills the step structure of the step substrate, the low dielectric constant dielectric layer and the step structure are ground and polished below the junction by chemical mechanical polishing to obtain a vertical graphene surface.

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