Semiconductor device

Abstract

The present invention discloses a semiconductor device, aiming to reduce the on-state loss and optimize the device performance. The device includes arranged cell structures, and the cell structure includes: a drift layer formed on a substrate; a fin structure protruding from the substrate, which is composed of stacked regions of different conductive types; a recess is formed between adjacent fins; the gate wraps the fin through a dielectric layer and isolates it, and the fin is laterally sandwiched between the recesses, and the depth of the recess reaches the carrier expansion layer; the longitudinal spacing between adjacent recesses is ≤ 1 μm; source / emitter and drain contact regions are respectively formed on both sides of the substrate. The width of the lateral recess is smaller than the width of the recess at the interruption of the longitudinal source / emitter contact region. By interrupting the gate in the source contact region, the present invention weakens the JFET effect and achieves low on-state loss and performance improvement.

Description

Technical Field

[0001] The present invention relates to the field of power semiconductor devices. Power semiconductor devices can withstand blocking voltages of several hundred volts and can thus be implemented as a vertical structure. The semiconductor wafer is based on semiconductor materials such as silicon, silicon carbide, or gallium nitride. The present invention presents a novel structure that allows the device to have low state losses, high cell packing density, and reduced electric field stress on the gate oxide. Background Art

[0002] Medium-voltage power semiconductor devices can be implemented through planar and recessed MOS cell designs (such as IGBT and MOSFET designs). These devices have a gate contact that is electrically isolated from the rest of the transistor structure by a suitable dielectric material (such as silicon dioxide) for controlling the device and switching it from the blocking state to the conducting state and vice versa. They are typically manufactured using a layer structure that is arranged between the source and the drain on the other side. An N-doped drift layer is arranged between the drain and the source. On the source side, a P-doped base layer is in direct contact with the source electrode. An N-doped source region is embedded in the base layer and contacts the source electrode through an opening.

[0003] The recessed cell concept is typically used to reduce the on-resistance, increase the packing density, and broaden the channel width to optimize the device and achieve a better technology curve. However, due to the high electric field at the bottom corners of the recess, the blocking ability of the recessed structure is low. In addition, the increased capacitance results in poor controllability and high switching losses, and a high short-circuit current is expected due to the high cell density in the recessed design. Therefore, many designs for optimizing the device structure have been proposed in the prior art, with particular attention paid to the area between the active MOS cells. The advantage is to reduce the on-loss by reducing the distance between the recesses. IGBTs and MOSFETs (Si and SiC) have addressed these device optimization problems. Such as the following prior art documents:

[0004] [1] EP 3227924 B1 Power Semiconductor Device;

[0005] [2] Proc. ISPSD 2023 Proposal of Vertical-channel Fin-SiC MOSFET toward Future Device Scaling;

[0006] [3] GB 2587645 A Semiconductor Device having a gate electrode formedin a trench structure Semiconductor device with a gate formed in a recess structure;

[0007] [4] US 0216331 Semiconductor Device and Method for Designing Thereof Semiconductor device and its design method.

[0008] In [2], a silicon carbide trench etched double-injected MOS (SiC TED MOS) was proposed, in which three channel types were proposed to increase channel mobility and improve R ON A. Basically, the current flows horizontally in the same way as the planar cell concept, but some advantages of the trench cell concept are added. The disadvantage of this design is that a longer channel length is required, which reduces the on-current. Therefore, this cell requires a large area, and the JFET region must be carefully taken care of.

[0009] In [1], a silicon carbide trench field effect transistor device with a double gate was proposed, in which the current flows vertically. The semiconductor is arranged in a plurality of vertical field effect transistor cells, including a body region surrounded by a gate layer, and the distance between two sides is 1 μm or less. In this design, the current flows vertically, but due to the obvious JFET effect, electrons are horizontally transferred before reaching the drain contact, which increases the on-resistance. Summary of the Invention

[0010] To solve the above problems, the present invention provides a semiconductor device with low on-conduction loss, stable gate characteristics, improved blocking ability, and good controllability.

[0011] To achieve the above object, a semiconductor device designed by the present invention includes a plurality of arranged cells, and the cells include:

[0012] Drift layer, formed by a substrate of the first conductivity type;

[0013] Fin structure, arranged on the first main side of the substrate and protruding along the y direction, disposed above the semiconductor surface, and successively stacked from top to bottom by a first conductivity type region, a second conductivity type body region, and a first conductivity type carrier expansion layer region;

[0014] A recess is formed between two adjacent fin structures;

[0015] A gate, which is coated outside the fin structure through a gate dielectric layer and isolated from the fin structure, wherein each fin structure is laterally sandwiched between two recesses in the x direction, and the depth of the recesses is greater than or equal to the position where the first-conductivity-type carrier extension layer region is located; the distance between two longitudinally adjacent recesses in the z direction is less than or equal to 1 μm;

[0016] A contact region formed on the first major side of the substrate and connected to the source or emitter electrode of the semiconductor device;

[0017] A contact region formed on the second major side of the substrate and connected to the drain of the semiconductor device.

[0018] The width between two laterally adjacent recesses in the x direction is d1, d1 is in the sub-micron or micron range, and the recesses are interrupted in the z direction at the contact region of the source or emitter electrode, and the interrupted width is d2, and the width d1 < the width d2.

[0019] Furthermore, the semiconductor device includes a second-conductivity-type blocking region, and the second-conductivity-type blocking region is implanted at the bottom of the recess and is floating;

[0020] Of course, the second-conductivity-type blocking region can also be implanted at the bottom of the recess and is in electrical contact. The electrical contact means that the second-conductivity-type blocking region is electrically connected to the contact region of the source or emitter electrode. The electrical contact of the second-conductivity-type blocking region is formed by etching the middle part of the recess, thereby defining the potential of the second-conductivity-type blocking region.

[0021] Another solution is that the gate dielectric layer coating the fin structure includes a recess top dielectric layer, a fin structure top dielectric layer, and a fin structure side dielectric layer, and the thicknesses of the recess top dielectric layer, the fin structure top dielectric layer, and the fin structure side dielectric layer are different.

[0022] At the same time, according to needs, the gate dielectric layer extends to the contact region of the source or emitter electrode and overlaps with the contact region of the source or emitter electrode in the y direction, or does not extend to the contact region of the source or emitter electrode.

[0023] In some different embodiments, the unit is arranged in a hexagonal shape. The semiconductor device designed by the present invention has a three-dimensional layout structure of a region with a vertical channel, that is, the described fin structure, which is surrounded by gate electrodes and recesses. Although the distance between the recesses is in the range of 1 μm or less, resulting in a significantly larger JFET effect. However, the gate is interrupted in the region of the source contact arrangement, and the distance between the two gates in this region is larger, thus significantly weakening the JFET effect. Therefore, such a semiconductor device not only has the advantage of low conduction loss brought about by reducing the recesses, but also avoids the disadvantage of an increase in on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a top view of Embodiment 1.

[0025] Figure 2 is a three-dimensional view of Embodiment 1.

[0026] Figure 3 is a top view of Embodiment 2.

[0027] Figure 4 is Figure 3 the cross-sectional view A-A in

[0028] Figure 5 is an enlarged view of the fin structure.

[0029] Figure 6 is a schematic structural diagram of Embodiment 3.

[0030] Figure 7 is a top view of the prior art. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0031] The preferred embodiments of the present invention will be described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are only for explaining and illustrating the present invention, and are not used to limit the present invention.

[0032] Embodiment 1.

[0033] As Figure 1 shown, the semiconductor device described in this embodiment includes a semiconductor having layers of different conductivity types, and these layers are arranged between a source 1 on one side and a drain 2 on the other side. The substrate of the first conductivity type forms a drift layer 3. By selectively etching the substrate to a certain depth to form recesses 5, a fin structure 4 with a micron or sub-micron scale protruding above the substrate is formed between two adjacent recesses 5. Naturally, multiple fin structures 4 will be formed between multiple recesses 5. Figure 1 One of the embodiments of the present invention is presented, but it is not the preferred embodiment for implementing the present invention. Its layout is similar to as Figure 7The prior art shown. A recess 5 is provided around the vertical field effect transistor unit to form a plurality of fin structures 4.

[0034] The fin structure 4 includes, from top to bottom: a first conductivity type region 6 (N+ source), a second conductivity type body region 7 (P+ body), and a first conductivity type carrier extension layer region 8 (N+ CSL). The first conductivity type region 6 is a highly doped region, and the first conductivity type carrier extension layer region 8 is also a highly doped region, and the doping concentration of the first conductivity type carrier extension layer region 8 is higher than that of the drift layer 3. At the same time, the outside of the fin structure 4 is coated with the dielectric layer of the gate 11.

[0035] The function of the first conductivity type carrier extension layer region 8 is to conduct electrons to the region without the JFET effect. The gate dielectric layer 9 is connected to the gate 11 electrode of the device through a layer of conductive material (such as highly doped polysilicon). By modulating the voltage applied to the gate 11 electrode, a vertical MOS channel can be formed in the fin structure 4, so that the semiconductor device can be switched from the blocking state to the conductive state, and vice versa.

[0036] At the same time, as Figure 2 shown, the height of the fin structure 4 in the y direction is defined by the etching depth on the substrate. In this embodiment, the upper surface 5-1 of the recess 5 is lower than the lower surface 8-1 of the first conductivity type carrier extension layer region 8.

[0037] The distance between two adjacent recesses 5, that is, the maximum width of the fin structure 4 is d1. Reducing the width d1 can increase the density of the recesses 5, thereby improving the device performance.

[0038] The fin structures 4 are arranged in the x direction at a micron or sub-micron level pitch. At the same time, the recesses 5 are blocked by the contact regions of the source 1 or the emitter in the z direction to form an interruption 1-1, forming a region with a larger distance between the recesses 5. The width of the interruption 1-1 is d2, and the size of the width d2 is less than or equal to 1 μm, and generally the width d2 is much larger than the width d1.

[0039] When the width of the fin structure 4 is small, that is, when the width d1 is small, there will be a large JFET effect, so the electron path will deflect, as Figure 1 shown in the electron flow path deflecting in the z direction. In the y direction, as Figure 2As shown, electrons first flow in the z direction through the first conductive type region 6, i.e., the N+ source region, then vertically through the second conductive type body region 7, i.e., the P+ body region, towards the first conductive type carrier spread layer region 8, i.e., the N+ CSL region, and then turn back and flow along the first conductive type carrier spread layer region 8 in the z direction (opposite to the first z direction) until the electrons reach a region where the JFET effect is extremely low or non-existent. That is, a region where the distance between the recesses 5 is relatively large, such as Figure 2 shown, and return to below the region where the source electrode 1 contact 10-1 is arranged. In this way, the electrons can longitudinally flow in the y direction towards the drain 2 again.

[0040] The advantage of this structure is that the electric field at the bottom of the recess 5 is relatively low, which means that during the turn-off operation, the oxide forming the gate dielectric layer 9 will not be affected by excessive electric fields.

[0041] In addition, in some embodiments, a second conductive type blocking region 10 (P+ blocking) can be arranged below the recess 5. By setting an extra highly doped blocking layer, the static and dynamic electric fields experienced by the gate dielectric layer 9 can be further reduced, especially high electric fields. At the same time, majority carriers do not flow around the second conductive type blocking region 10.

[0042] In an optimal embodiment, the second conductive type blocking region 10 is floating, that is, electrically isolated from the source electrode 1. In other embodiments, it can be in electrical connection contact with the source electrode 1 of the semiconductor device.

[0043] Embodiment 2.

[0044] As Figures 3 - 5 shown, the semiconductor device described in this embodiment is a preferred embodiment of the present invention. As Figure 3 shown, the semiconductor device described in this embodiment is slightly different from the semiconductor device disclosed in Figure 1 when viewed from the top view, but the two concepts are the same. Among them, the second conductive type blocking region 10 has a contact 10-1, and the contact 10-1 is made by etching the middle position of the recess 5. Through the contact 10-1, the potential of the second conductive type blocking region 10 can be controlled. The source electrode 1 and the contact 10-1 of the second conductive type blocking region 10 are arranged in an alternating and spaced manner, so the corresponding fin structures 4 also form an alternating layout.

[0045] At the same time, in Figure 3Also shown is the path of the electron current, starting from the source 1, under the action of the gate 11, flowing through the vertical channel composed of the first-conductivity-type region 6 and the second-conductivity-type body region 7 in the longitudinal y direction, flowing to the first-conductivity-type carrier expansion layer region 8, and then flowing horizontally in the z direction on the first-conductivity-type carrier expansion layer 8 until the electrons reach a region without JFET effect, which is located below the source 1 on the other side of Figure 3 the other side of the source 1 in

[0046] such as Figure 4 、 Figure 5 shown, a second-conductivity-type blocking region 10 is provided at the bottom of the recess 5. And the thickness of the gate dielectric layer 9 surrounding the fin structure 4 corresponding to different surfaces of the fin structure 4 can be set according to the needs of actual applications, that is, there is no limitation on this thickness. However, in some embodiments, the thickness of the gate dielectric layer 9 of the fin structure 4 corresponding to different surfaces of the fin structure 4 is not the same, that is, such as Figure 5 shown at the Ox1 position at the bottom of the recess 5, the Ox2 position at the top of the fin structure 4, and the Gox position on the side of the fin structure 4, preferably Ox1≠Ox2≠Gox.

[0047] Embodiment 3.

[0048] such as Figure 6 shown, the semiconductor device described in this embodiment is a multi-unit arrangement structure composed of hexagonal transistor units 12, and the gate 11 can be located in the recess 5 forming the fin structure 4. Multiple fin structures 4 connect the source 1 contact regions to each other.

[0049] In the description of the present invention, it should be noted that the xyz axes are all the directions marked in the drawings. The orientation or positional relationship indicated by the terms "vertical", "upper", "lower", "horizontal", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0050] In the description of the present invention, it should also be noted that, unless otherwise clearly specified and defined, the terms "set", "install", "connected", "connection" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances. Finally, it should be noted that the above are only the preferred embodiments of the present invention and are not used to limit the present invention. Although the present invention has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device comprising a plurality of arranged units, wherein the units include: A drift layer formed by a first conductive type substrate; Features: The fin structure is arranged on the first main side of the substrate and protrudes along the y direction, and is disposed above the semiconductor surface. The fin structure is composed of a stack of a first conductive type region, a second conductive type body region, and a first conductive type carrier expansion layer region from top to bottom; A depression is formed between two adjacent fin structures; A gate is coated on the outside of the fin structure through a gate dielectric layer and isolated from the fin structure, wherein each fin structure is laterally sandwiched between two recesses in the x direction, the depth of the recess is greater than or equal to the depth of the first conductive type carrier extension layer region; and the distance between two longitudinally adjacent recesses in the z direction is less than or equal to 1 μm; a contact region formed on the first main side of the substrate and connected to a source or emitter electrode of the semiconductor device; a contact region formed on the second main side of the substrate and connected to a drain of the semiconductor device; The width between two laterally adjacent recesses in the x direction is d1, d1 is in the submicron or micron range, and the recesses interrupt the contact area of ​​the source or emitter electrode in the z direction, the width of the interruption is d2, and width d1<width d2.

2. The semiconductor device according to claim 1, wherein: A second conductive type blocking region is included. The second conductive type blocking region is implanted at the bottom of the recess and is floating.

3. The semiconductor device according to claim 1, wherein: A second conductive type blocking region is included. The second conductive type blocking region is implanted in the bottom of the recess and is in electrical contact.

4. The semiconductor device according to claim 3, wherein: The second conductivity type blocking region is electrically connected to the contact region of the source or emitter electrode.

5. The semiconductor device according to claim 4, wherein: An electrical contact of the second conductive type blocking region is formed by etching the gate and the middle portion of the recess.

6. The semiconductor device according to claim 1, wherein: The gate dielectric layer covering the fin structure includes a recessed top dielectric layer, a fin structure top dielectric layer and a fin structure side dielectric layer, and the thicknesses of the recessed top dielectric layer, the fin structure top dielectric layer and the fin structure side dielectric layer are different.

7. The semiconductor device according to claim 6, wherein: The gate dielectric layer extends to the contact region of the source or emitter electrode and overlaps with the source or emitter electrode contact region in the y direction, or does not extend to the source or emitter electrode contact region.

8. The semiconductor device according to claim 1, wherein: The cells are arranged in a hexagonal shape.

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