Semiconductor structure and preparation method thereof

Abstract

The invention relates to a semiconductor structure and a preparation method thereof. The semiconductor structure comprises a substrate; the base comprises a substrate and an epitaxial layer which are stacked; the main junction is positioned in the epitaxial layer; at least one field limiting ring located in the epitaxial layer; the junction termination extension region is located in the epitaxial layer; the junction termination expansion region and the field limiting ring have an overlapping region; the cut-off ring is located in the epitaxial layer; wherein the surfaces of one sides, far away from the substrate, of the main junction, the field limiting ring, the cut-off ring and the junction termination extension region are flush with the surface, far away from the substrate, of the epitaxial layer; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction pointing to the main junction along the substrate; the field oxide layer is at least located on the sides, away from the substrate, of the epitaxial layer, the junction termination extension region and the cut-off ring; the field plates are respectively positioned on one sides, far away from the substrate, of the main junction and the field oxide layer; wherein the doping types of the substrate and the cut-off ring are the same, and the doping types of the main junction, the field limiting ring and the junction termination expansion region are the same. The semiconductor structure has a high withstand voltage level.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] High-voltage vertical conductive metal oxide semiconductor field effect transistor devices (VDMOSFET) have high voltage resistance requirements. Currently, single terminal junctions such as multi-zone junction terminal extension or field limiting ring structure are generally used to improve the breakdown voltage of VDMOSFET. However, due to the limited number of partitions in the device, the concentration mutation between different regions can easily introduce new electric field spikes, resulting in the surface electric field efficiency being much lower than the ideal terminal; the field limiting ring structure requires a large number of rings and a long terminal length, which increases the terminal area, making the design difficult and the manufacturing cost high. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a preparation method thereof that can improve the breakdown voltage of the device.

[0004] In a first aspect, the present application provides a semiconductor structure, comprising:

[0005] A substrate; the substrate comprises a stacked substrate and an epitaxial layer;

[0006] a main junction located in the epitaxial layer;

[0007] at least one field limiting ring located in the epitaxial layer;

[0008] A junction terminal extension region is located in the epitaxial layer; the junction terminal extension region and the field limiting ring have an overlapping area;

[0009] A cut-off ring is located in the epitaxial layer; wherein the surfaces of the main junction, the field limiting ring, the cut-off ring and the junction terminal extension region on one side away from the substrate are flush with the surface of the epitaxial layer away from the substrate; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction along the substrate pointing to the main junction;

[0010] A field oxide layer, at least located on a side of the epitaxial layer, the junction terminal extension region and the cut-off ring respectively away from the substrate;

[0011] Field plates are respectively located on the side of the main junction and the field oxide layer away from the substrate; wherein the base and the cut-off ring have the same doping type, and the main junction, the field limiting ring, and the junction terminal extension region have the same doping type.

[0012] In one of the embodiments, the ion doping concentration of the overlapping area between the junction termination extension region and the field limiting ring is equal to the sum of the ion doping concentration of the junction termination extension region and the ion doping concentration of the field limiting ring.

[0013] In one embodiment, the ion doping concentration of the junction termination extension region is lower than the ion doping concentration of the field limiting ring.

[0014] In one embodiment, the ion doping concentration of the field limiting ring outside the overlap region is the same as the ion doping concentration of the main junction.

[0015] In one embodiment, the main junction, the field limiting ring and the cut-off ring have the same depth, and the depth of the junction terminal extension region is smaller than the depth of the field limiting ring.

[0016] In one embodiment, the semiconductor structure further comprises:

[0017] A cell region is located in the epitaxial layer, and the cell region is spaced apart from the main junction, the field limiting ring, and the cut-off ring along the first direction;

[0018] A gate electrode, located on a surface of the cell region that is away from the substrate;

[0019] A source electrode, located on a surface of the cell region away from the substrate, and spaced apart from the gate electrode along the first direction;

[0020] The drain electrode is located on a surface of the substrate away from the cell region.

[0021] In one embodiment, the semiconductor structure further comprises:

[0022] A first passivation oxide layer is located on the exposed surfaces of the gate electrode, the source electrode, the field plate and the field oxide layer;

[0023] The second passivation oxide layer is located on the exposed surface of the drain electrode.

[0024] In a second aspect, the present application provides a method for preparing a semiconductor structure, the method comprising:

[0025] Providing a substrate; the substrate comprises a substrate and an epitaxial layer;

[0026] A main junction, at least one field limiting ring, a junction terminal extension region and a cut-off ring are formed in the epitaxial layer; wherein the surfaces of the main junction, the field limiting ring, the cut-off ring and the junction terminal extension region on one side away from the substrate are flush with the surface of the epitaxial layer on one side away from the substrate; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction along the substrate pointing to the main junction; the junction terminal extension region and the field limiting ring have an overlapping area;

[0027] A field oxide layer is formed at least on one side of the epitaxial layer, the junction terminal extension region and the cut-off ring respectively away from the substrate, wherein the field oxide layer exposes a portion of the upper surface of the main junction;

[0028] forming a field plate on a surface of the main junction and the field oxide layer away from the substrate;

[0029] The substrate and the cut-off ring have the same doping type, and the main junction, the field limiting ring, and the junction terminal extension region have the same doping type.

[0030] In one embodiment, forming a main junction, at least one field limiting ring, a junction terminal extension region and a cut-off ring in the epitaxial layer comprises:

[0031] Performing a first ion implantation on the epitaxial layer to form the cut-off ring; the ion type of the first ion implantation is a first doping type;

[0032] Performing a second ion implantation on the epitaxial layer to form the main junctions and the field limiting rings arranged at intervals along the first direction;

[0033] A third ion implantation is performed on the epitaxial layer to form the junction terminal extension region; the type of the second ion implantation is the same as the ion type of the third ion implantation, which is a second doping type; the first doping type is opposite to the second doping type.

[0034] In one embodiment, the ion concentration of the second ion implantation is greater than the ion concentration of the third ion implantation.

[0035] In the above semiconductor structure and preparation method thereof, the semiconductor structure includes a substrate, a main junction, at least one field limiting ring, a junction terminal extension region, a cut-off ring, a field oxide layer and a field plate, wherein the substrate includes a stacked substrate and an epitaxial layer; the main junction is located in the epitaxial layer; at least one field limiting ring is located in the epitaxial layer; the junction terminal extension region is located in the epitaxial layer; the junction terminal extension region and the field limiting ring have an overlapping region; the cut-off ring is located in the epitaxial layer; wherein the main junction, the field limiting ring, the cut-off ring and the junction terminal extension region are located away from the substrate. The side surface is flush with the surface of the epitaxial layer away from the substrate; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along the first direction, and the first direction is perpendicular to the direction along the substrate pointing to the main junction; the field oxide layer is at least located on the side of the epitaxial layer, the junction terminal extension area and the cut-off ring away from the substrate; the field plate is located on the side of the main junction and the field oxide layer away from the substrate; wherein the substrate and the cut-off ring have the same doping type, and the main junction, the field limiting ring and the junction terminal extension area have the same doping type. The main junction, at least one field limiting ring, the junction terminal extension area, the cut-off ring, the field oxide layer and the field plate constitute a composite junction terminal structure. When a reverse bias voltage is applied to the semiconductor structure, the induced negative charge on the field plate interacts with the charge of the opposite polarity of the semiconductor depletion region, so that the semiconductor surface depletion region is widened, thereby improving the withstand voltage level of the device. The introduction of the junction terminal extension area and the field limiting ring is equivalent to adding a voltage divider at the edge of the device to avoid excessive concentration of the electric field. In addition, the junction terminal extension area and the field limiting ring have an overlapping area, and the field limiting rings are connected through the junction terminal extension area, so that when the reverse withstand voltage is applied, the main junction depletion layer expands faster toward the field limiting ring, and the doped area between the field limiting rings can be quickly depleted. Each field limiting ring is connected to the main junction in advance, so that the field limiting ring can share the main junction electric field faster and better, optimize the electric field distribution in the drift region, and improve the device withstand voltage. Furthermore, when the thickness of the field oxide layer is not enough, an inversion layer will be formed in the drift region under the field oxide layer. The inversion layer will provide a conductive channel between the terminal rings, reduce the device breakdown voltage, and set a cutoff ring to avoid the formation of an inversion channel and ensure the stability of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a schematic cross-sectional structural diagram of a semiconductor structure provided in an embodiment;

[0038] Figure 2is a schematic flow chart of a method for preparing a semiconductor structure provided in an embodiment;

[0039] Figure 3 The present invention is a flow chart of a method for preparing a semiconductor structure provided in an embodiment, wherein a first main junction, at least one field limiting ring, a junction terminal extension region and a cut-off ring are formed in an epitaxial layer. DETAILED DESCRIPTION

[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0046] In one embodiment, Figure 1 As shown, the present application provides a semiconductor structure, including a substrate 100 , a main junction 200 , at least one field limiting ring 300 , a junction terminal extension region 400 , a stop ring 500 , a field oxide layer 600 and a field plate 700 .

[0047] The base 100 includes a substrate 110 and an epitaxial layer 120, a main junction 200, a field limiting ring 300, a junction terminal extension region 400 and a stop ring 500 are respectively arranged in the epitaxial layer 120, and a surface of the main junction 200, the field limiting ring 300, the stop ring 500 and the junction terminal extension region 400 away from the substrate 110 is flush with a surface of the epitaxial layer 120 away from the substrate 110. The main junction 200, the field limiting ring 300 and the stop ring 500 are arranged at intervals along a first direction, and the first direction is perpendicular to a direction along the substrate 110 pointing to the main junction 200, that is, Figure 1 The OY direction in the junction terminal extension region 400 and the field limiting ring 300 have an overlapping area. The field oxide layer 600 is at least located on the side of the epitaxial layer 120, the junction terminal extension region 400 and the cut-off ring 500 that are respectively away from the substrate 110, exposing a portion of the surface of the main junction 200. The material of the field oxide layer 600 can be one or more of silicon oxide, silicon oxycarbide, silicon oxynitride, etc. The field plate 700 is respectively located on the side of the main junction 200 and the field oxide layer 600 that are away from the substrate 110, and the field plate 700 extends from the side surface of the main junction 200 that is away from the substrate 110 to the side surface of the field oxide layer 600 that is away from the substrate 110. The shape of the field plate 700 can be stepped or sloped, and the material of the field plate 700 can be metal or polysilicon, etc. The substrate 100 and the cut-off ring 500 have the same doping type, and the main junction 200, the field limiting ring 300, and the junction terminal extension region 400 have the same doping type. Exemplarily, the substrate 100 and the cut-off ring 500 have N-type doping types, and the main junction 200, the field limiting ring 300, and the junction terminal extension region 400 have P-type doping types.

[0048] In the embodiment of the present application, the semiconductor structure includes a substrate 100, a main junction 200, at least one field limiting ring 300, a junction terminal extension region 400, a cut-off ring 500, a field oxide layer 600 and a field plate 700. The main junction 200, at least one field limiting ring 300, a junction terminal extension region 400, a cut-off ring 500, a field oxide layer 600 and a field plate 700 constitute a composite junction terminal structure. When a reverse bias voltage is applied to the semiconductor structure, the induced negative charge on the field plate 700 interacts with the charge of the opposite polarity of the semiconductor depletion region, so that the semiconductor surface depletion region is widened, thereby improving the withstand voltage level of the device. The introduction of the junction terminal extension region 400 and the field limiting ring 300 is equivalent to adding a voltage divider at the edge of the device to prevent the electric field from being too concentrated. In addition, the junction terminal extension region 400 and the field limiting ring 300 have an overlapped area, and the field limiting rings 300 are connected through the junction terminal extension region 400, so that during reverse withstand voltage, the depletion layer of the main junction 200 expands faster toward the field limiting ring 300, and the doped region between the field limiting rings 300 can be quickly depleted. Each field limiting ring 300 is connected to the main junction 200 in advance, so that the field limiting ring 300 can share the main junction 200 electric field faster and better, optimize the electric field distribution in the drift region, and improve the device withstand voltage. Further, when the thickness of the field oxide layer 600 is not enough, an inversion layer will be formed in the drift region under the field oxide layer 600, and the inversion layer will provide a conductive channel between the terminal rings, reducing the device breakdown voltage. The cut-off ring 500 can avoid the formation of an inversion channel and ensure the stability of the device.

[0049] In one embodiment, the ion doping concentration of the overlapping area of ​​the junction terminal extension region 400 and the field limiting ring 300 is equal to the sum of the ion doping concentration of the junction terminal extension region 400 and the ion doping concentration of the field limiting ring 300. In this way, without changing the terminal area, the tolerance range of the terminal ion implantation concentration error is improved, and the influence of the implanted ion diffusion on the device terminal is avoided to the greatest extent.

[0050] In one embodiment, the ion doping concentration of the junction terminal extension region 400 is lower than the ion doping concentration of the field limiting ring 300. That is, a lower doped junction terminal extension region 400 is introduced in the edge region of the field limiting ring 300, so that the depletion layer of the main junction 200 can be expanded to the field limiting ring 300 more quickly during reverse withstand voltage, so that the doping region between the field limiting rings 300 can be quickly depleted, and each field limiting ring 300 is connected to the main junction 200 in advance, so that the field limiting ring 300 can better share the electric field of the main junction 200 and improve the electric field distribution.

[0051] In one embodiment, the ion doping concentration of the portion of the field limiting ring 300 outside the overlap region is the same as the ion doping concentration of the main junction 200 .

[0052] In one embodiment, the main junction 200, the field limiting ring 300 and the cut-off ring 500 have the same depth, and the depth of the junction terminal extension region 400 is less than the depth of the field limiting ring 300. The depth of the field limiting ring 300 is the same as the depth of the main junction 200, which can ensure the synergy between the two in terms of electric field distribution and depletion layer extension, thereby improving the overall performance of the device. The depth of the cut-off ring 500 is the same as the depth of the main junction 200, which helps to maintain the electric field distribution and depletion layer state inside the device, thereby ensuring the stability and reliability of the device. The depth of the junction terminal extension region 400 is less than that of the field limiting ring 300, which can make the electric field more evenly distributed in the junction terminal extension region 400, avoiding excessive concentration of the electric field and causing early failure of the device. In addition, since the depth of the junction terminal extension region 400 is shallow, its depletion layer is more easily completely depleted, and the field limiting ring 300 can be connected more quickly, thereby improving the breakdown voltage of the device.

[0053] In one embodiment, the semiconductor structure further includes a cell region, a gate electrode, a source electrode and a drain electrode. The cell region is located in the epitaxial layer, and the cell region is spaced apart from the main junction, the field limiting ring and the cutoff ring along the first direction. The cell region includes a doped P body region and an N well region. The cell region is surrounded by a composite junction terminal structure consisting of a main junction, a field limiting ring, a cutoff ring and a junction terminal extension region. The gate electrode is located on a side surface of the cell region away from the substrate, the source electrode is located on a side surface of the cell region away from the substrate, and is spaced apart from the gate electrode along the first direction, and the drain electrode is located on a side surface of the substrate away from the cell region.

[0054] In one embodiment, the semiconductor structure further includes a first passivation oxide layer and a second passivation oxide layer. The first passivation oxide layer is located on the exposed surfaces of the gate electrode, the source electrode, the field plate and the field oxide layer, and the second passivation oxide layer is located on the exposed surface of the drain electrode. The first passivation oxide layer and the second passivation oxide layer play an insulating role.

[0055] In one embodiment, Figure 2 As shown, the present application also provides a method for preparing a semiconductor structure, including steps S210-S240.

[0056] S210, providing a substrate, where the substrate includes a substrate and an epitaxial layer.

[0057] The epitaxial layer 120 may be grown on the substrate 110 by an epitaxial process.

[0058] S220, forming a first main junction, at least one field limiting ring, a junction terminal extension region and a cutoff ring in the epitaxial layer.

[0059] The main junction 200, at least one field limiting ring 300, a junction termination extension region 400 and a stop ring 500 may be formed in the epitaxial layer 120 by a doping process. The surfaces of the main junction 200, the field limiting ring 300, the stop ring 500 and the junction termination extension region 400 away from the substrate 110 are flush with the surface of the epitaxial layer 120 away from the substrate 110. The main junction 200, the field limiting ring 300 and the stop ring 500 are arranged at intervals along a first direction, and the first direction is perpendicular to the direction pointing to the main junction 200 along the substrate 110. The junction termination extension region 400 and the field limiting ring 300 have an overlapping area.

[0060] S230, forming a field oxide layer at least on one side of the epitaxial layer, the junction terminal extension region and the cut-off ring respectively away from the substrate, wherein the field oxide layer exposes a portion of the upper surface of the main junction.

[0061] The field oxide layer 600 may be formed on the sides of the epitaxial layer 120 , the junction termination extension region 400 , and the stop ring 500 away from the substrate 110 by a deposition process.

[0062] S240, forming a field plate on a surface of the main junction and the field oxide layer that is away from the substrate.

[0063] The field plate 700 may be formed on a surface of the main junction 200 and the field oxide layer 600 away from the substrate 110 by a deposition process.

[0064] The substrate 100 and the cut-off ring 500 have the same doping type, and the main junction 200 , the field limiting ring 300 , and the junction terminal extension region 400 have the same doping type.

[0065] In the embodiment of the present application, a substrate 100 including a substrate 110 and an epitaxial layer 120 is provided, a main junction 200, at least one field limiting ring 300, a junction terminal extension region 400 and a cut-off ring 500 are formed in the epitaxial layer 120, a field oxide layer 600 is formed at least on the side of the epitaxial layer 120, the junction terminal extension region 400 and the cut-off ring 500 away from the substrate 110, and a field plate 700 is formed on the surface of the main junction 200 and the field oxide layer 600 away from the substrate 110, so as to form a semiconductor structure. Among them, the main junction 200, at least one field limiting ring 300, the junction terminal extension region 400, the cut-off ring 500, the field oxide layer 600 and the field plate 700 constitute a composite junction terminal structure. When a reverse bias voltage is applied to the semiconductor structure, the induced negative charge on the field plate 700 interacts with the charge of the opposite polarity of the semiconductor depletion region, so that the semiconductor surface depletion region is widened, thereby improving the withstand voltage level of the device. The introduction of the junction terminal extension region 400 and the field limiting ring 300 is equivalent to adding a voltage divider at the edge of the device to avoid excessive concentration of the electric field. In addition, the junction terminal extension region 400 and the field limiting ring 300 have an overlapping area, and the field limiting rings 300 are connected through the junction terminal extension region 400, so that when the reverse withstand voltage is applied, the depletion layer of the main junction 200 expands faster toward the field limiting ring 300, and the doping area between the field limiting rings 300 can be quickly depleted. Each field limiting ring 300 is connected to the main junction 200 in advance, so that the field limiting ring 300 can share the main junction 200 electric field faster and better, optimize the electric field distribution in the drift region, and improve the device withstand voltage. Further, when the thickness of the field oxide layer 600 is not enough, an inversion layer will be formed in the drift region under the field oxide layer 600, and the inversion layer will provide a conductive channel between the terminal rings, reduce the device breakdown voltage, and set the cut-off ring 500 to avoid the formation of an inversion channel and ensure the stability of the device.

[0066] In one embodiment, Figure 3 As shown, a first main junction, at least one field limiting ring, a junction terminal extension region and a cut-off ring are formed in the epitaxial layer, including S310-S330.

[0067] S310, performing a first ion implantation on the epitaxial layer to form a cutoff ring.

[0068] The ion type of the first ion implantation is a first doping type. Exemplarily, the first doping type is N type.

[0069] S320, performing a second ion implantation on the epitaxial layer to form main junctions and field limiting rings arranged at intervals along the first direction.

[0070] It can be understood that the ion doping concentrations of the main junction 200 and the field limiting ring 300 are the same. The area of ​​the second ion implantation is different from the area of ​​the first ion implantation.

[0071] S330, performing a third ion implantation on the epitaxial layer to form a junction terminal extension region.

[0072] The area of ​​the third ion implantation is between the main junction 200 and the cutoff ring 500 that have been formed, including the area where the field limiting ring 300 has been formed. The type of the second ion implantation is the same as the ion type of the third ion implantation, which is the second doping type. The first doping type is opposite to the second doping type. Exemplarily, the second doping type is P-type. The ion concentration of the second ion implantation is greater than the ion concentration of the third ion implantation. It can be understood that the ion doping concentration of the junction terminal extension region 400 is less than the ion doping concentration of the main junction 200 and the field limiting ring 300.

[0073] In the embodiment, a first ion implantation is performed on the epitaxial layer 120 to form a cut-off ring 500, and a second ion implantation is performed on the epitaxial layer 120 to form a main junction 200 and a field limiting ring 300 arranged at intervals along a first direction, thereby saving process flow. Furthermore, a third ion implantation is performed on the epitaxial layer 120 to form a junction terminal extension region 400, and the process is simple.

[0074] It should be understood that, although the steps in the above-mentioned flowcharts are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, there is no strict order restriction on the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0075] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0076] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0077] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; The base comprises a substrate and an epitaxial layer which are stacked; a main junction located in the epitaxial layer; at least one field limiting ring located in the epitaxial layer; A junction terminal extension region is located in the epitaxial layer; the junction terminal extension region and the field limiting ring have an overlapping area; A cut-off ring is located in the epitaxial layer; wherein the surfaces of the main junction, the field limiting ring, the cut-off ring and the junction terminal extension region on one side away from the substrate are flush with the surface of the epitaxial layer away from the substrate; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction along the substrate pointing to the main junction; A field oxide layer, at least located on a side of the epitaxial layer, the junction terminal extension region and the cut-off ring respectively away from the substrate; Field plates are respectively located on the side of the main junction and the field oxide layer away from the substrate; wherein the base and the cut-off ring have the same doping type, and the main junction, the field limiting ring, and the junction terminal extension region have the same doping type.

2. The semiconductor structure according to claim 1, characterized in that: The ion doping concentration of the overlapping region of the junction termination extension region and the field limiting ring is equal to the sum of the ion doping concentration of the junction termination extension region and the ion doping concentration of the field limiting ring.

3. The semiconductor structure according to claim 1, characterized in that: The ion doping concentration of the junction termination extension region is lower than the ion doping concentration of the field limiting ring.

4. The semiconductor structure according to claim 1, characterized in that: The ion doping concentration of the field limiting ring outside the overlapped region is the same as the ion doping concentration of the main junction.

5. The semiconductor structure according to claim 1, characterized in that: The main junction, the field limiting ring and the cut-off ring have the same depth, and the depth of the junction terminal extension region is less than the depth of the field limiting ring.

6. The semiconductor structure according to claim 1, characterized in that The semiconductor structure further comprises: A cell region is located in the epitaxial layer, and the cell region is spaced apart from the main junction, the field limiting ring, and the cut-off ring along the first direction; A gate electrode, located on a surface of the cell region that is away from the substrate; A source electrode, located on a surface of the cell region away from the substrate, and spaced apart from the gate electrode along the first direction; The drain electrode is located on a surface of the substrate away from the cell region.

7. The semiconductor structure according to claim 6, characterized in that: The semiconductor structure further comprises: A first passivation oxide layer is located on the exposed surfaces of the gate electrode, the source electrode, the field plate and the field oxide layer; The second passivation oxide layer is located on the exposed surface of the drain electrode.

8. A method for preparing a semiconductor structure, characterized in that: The method comprises: Providing a substrate; the substrate comprises a substrate and an epitaxial layer; A main junction, at least one field limiting ring, a junction terminal extension region and a cut-off ring are formed in the epitaxial layer; wherein the surfaces of the main junction, the field limiting ring, the cut-off ring and the junction terminal extension region on one side away from the substrate are flush with the surface of the epitaxial layer on one side away from the substrate; the main junction, the field limiting ring and the cut-off ring are arranged at intervals along a first direction, and the first direction is perpendicular to a direction along the substrate pointing to the main junction; the junction terminal extension region and the field limiting ring have an overlapping area; A field oxide layer is formed at least on one side of the epitaxial layer, the junction terminal extension region and the cut-off ring respectively away from the substrate, wherein the field oxide layer exposes a portion of the upper surface of the main junction; forming a field plate on a surface of the main junction and the field oxide layer away from the substrate; The substrate and the cut-off ring have the same doping type, and the main junction, the field limiting ring, and the junction terminal extension region have the same doping type.

9. The method according to claim 8, characterized in that The forming of the first main junction, at least one field limiting ring, a junction terminal extension region and a cut-off ring in the epitaxial layer comprises: Performing a first ion implantation on the epitaxial layer to form the cut-off ring; the ion type of the first ion implantation is a first doping type; Performing a second ion implantation on the epitaxial layer to form the main junctions and the field limiting rings arranged at intervals along the first direction; A third ion implantation is performed on the epitaxial layer to form the junction terminal extension region; the type of the second ion implantation is the same as the ion type of the third ion implantation, which is a second doping type; the first doping type is opposite to the second doping type.

10. The method according to claim 9, characterized in that The ion concentration of the second ion implantation is greater than the ion concentration of the third ion implantation.

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