Lateral super-junction silicon carbide device modulated by local medium
By introducing local dielectric regions into the silicon carbide active layer, the problems of increased on-resistance of the transverse superjunction silicon carbide power device and low gate dielectric reliability are solved, and higher breakdown voltage and lower on-resistance are achieved, improving the performance and reliability of the device.
Patent Information
- Application Number
- CN202411825638.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-12
- Publication Date
- 2025-03-18
AI Technical Summary
While the existing transverse superjunction silicon carbide power devices increase the breakdown voltage, the on-resistance increases, and the critical field strength of conventional gate dielectrics is low, resulting in a reduced device reliability.
The local dielectric region is introduced in the silicon carbide active layer as a gate dielectric layer to improve gate control capability and reliability, and the electric field distribution of the drift region is modulated through the dielectric region, the doping concentration is optimized to increase the breakdown voltage and reduce the on-resistance.
Through local dielectric modulation technology, the breakdown voltage of the device is significantly improved, the specific on-resistance is reduced, and the performance and reliability of the device are improved.
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Figure CN119653839A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of semiconductor power devices, in particular to a local dielectric modulated lateral super junction silicon carbide device. Background Art
[0002] Power semiconductor devices are the core components of power integrated circuits. The development of modern power electronics technology requires power devices to have superior high voltage, high speed, and low power consumption performance. Compared with traditional power devices, silicon carbide power devices have a higher critical breakdown electric field and can achieve the same or even higher withstand voltage with a smaller device size and thinner epitaxial layer. At the same time, due to the high thermal conductivity and strong radiation resistance of silicon carbide materials, they are more suitable for the preparation of high temperature resistant power devices, making silicon carbide power devices perform well in high temperature and high pressure fields.
[0003] There is a 2.5-power constraint relationship between the specific on-resistance and the breakdown voltage in lateral silicon carbide power devices. When the breakdown voltage of the device is increased, the specific on-resistance will also increase. The 1.3-power relationship between the specific on-resistance and the breakdown voltage in superjunction technology breaks the 2.5-power relationship in conventional devices, which can alleviate the contradiction between the specific on-resistance and the withstand voltage. In lateral superjunction silicon carbide power devices, the opposite charges in the P-type semiconductor column and the N-type semiconductor column contained in the drift region deplete each other, which can optimize the electric field and increase the doping concentration of the drift region, thereby optimizing the breakdown voltage and on-resistance. However, the charge imbalance phenomenon in lateral superjunction silicon carbide power devices limits the performance improvement. In addition, conventional lateral superjunction silicon carbide power devices use silicon dioxide as the gate dielectric, which has a low critical field strength and will break down prematurely, reducing device reliability. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a local dielectric modulated lateral super junction silicon carbide device in view of the deficiencies of the above-mentioned prior art. The local dielectric modulated lateral super junction silicon carbide device introduces a local dielectric region in the silicon carbide active layer. On the one hand, it serves as a gate dielectric layer to improve the gate control capability and gate reliability. On the other hand, it can alleviate the charge imbalance phenomenon of the super junction, optimize the electric field distribution and doping concentration in the drift region, thereby increasing the breakdown voltage and reducing the specific on-resistance.
[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is:
[0006] A local dielectric modulated lateral superjunction silicon carbide device comprises a semiconductor substrate, a buried oxide layer, a silicon carbide active layer and a metal layer which are arranged in sequence from bottom to top.
[0007] The silicon carbide active layer includes a super junction structure, a semiconductor drain region, a semiconductor well region and a dielectric region.
[0008] The super junction structure comprises a small width portion and a large width portion coaxially arranged along the length direction of the silicon carbide active layer; wherein the width of the small width portion is smaller than the width of the large width portion.
[0009] The semiconductor drain region is disposed outside the large width portion.
[0010] The semiconductor well region is disposed at the outer center of the small width.
[0011] The dielectric region is disposed on both sides of the narrow width portion and the semiconductor well region and on the top of the narrow width portion.
[0012] The metal layer includes source metal, drain metal and gate metal; wherein the source metal is arranged directly above the semiconductor well region; the drain metal is arranged directly above the semiconductor drain region; and the gate metal is arranged on the surface of the dielectric region directly above the small width.
[0013] The dielectric region includes a central dielectric region and two side dielectric regions; wherein the central dielectric region is located at the top of the small width portion; the two side dielectric regions are symmetrically arranged on both sides of the small width portion and the semiconductor well region; the length of each side dielectric region is equal to the sum of the lengths of the semiconductor well region and the small width portion; the length of each side dielectric region in contact with the small width portion is not greater than two-thirds of the length of the super junction structure.
[0014] Each side dielectric region is a rectangular cross-sectional structure with equal width, and the width of the small width portion of the super junction structure from the semiconductor well region to the semiconductor drain region is equal.
[0015] Each side dielectric region has a stepped cross-sectional structure and forms a stepped fit with the small width portion; at this time, the width of each side dielectric region from the semiconductor well region to the semiconductor drain region decreases in a step-like manner; the width of the small width portion of the super junction structure increases in a step-like manner from the semiconductor well region to the semiconductor drain region.
[0016] Each side dielectric region has a right-angled trapezoidal cross-section structure and forms an inclined surface with the small-width portion; at this time, the width of each side dielectric region from the semiconductor well region to the semiconductor drain region is linearly reduced; the width of the small-width portion of the super junction structure increases linearly from the semiconductor well region to the semiconductor drain region.
[0017] Each side dielectric region also forms an inclined surface with the semiconductor well region; the width of the semiconductor well region also increases linearly toward the direction of the semiconductor drain region.
[0018] The silicon carbide active layer also includes a semiconductor body contact region and a semiconductor source region arranged in parallel on the surface of the semiconductor well region; wherein the semiconductor source region faces the super junction structure; and the source metal is in contact with the semiconductor body contact region and the semiconductor source region.
[0019] The super junction structure includes P-type silicon carbide and N-type silicon carbide arranged symmetrically about a device symmetry line X; wherein the device symmetry line X is along the length direction of the device; and the doping concentration of the P-type silicon carbide is greater than or equal to the doping concentration of the N-type silicon carbide.
[0020] The thickness of the silicon carbide active layer is 1 to 5 microns.
[0021] The dielectric region adopts an insulating material with a high dielectric constant, which is any one of hafnium oxide, zirconium oxide, titanium dioxide, strontium titanate, titanium barium strontium oxide and lead zirconate titanate.
[0022] The present invention has the following beneficial effects:
[0023] 1. The top and both sides of the device conduction channel of the present invention are surrounded by a high dielectric constant medium, which increases the gate capacitance, reduces the device turn-on voltage, and significantly reduces the quantum tunneling effect of the gate dielectric layer, thereby effectively improving the gate leakage current. While maintaining a low turn-on voltage, it reduces the leakage current and gate dielectric breakdown problems, significantly improving the performance and reliability of the device.
[0024] 2. The present invention modulates the device surface electric field and assists in depleting the superjunction drift region by covering the surface and both sides of the smaller width portion of the silicon carbide active layer with a high dielectric constant medium, which is beneficial to increasing the breakdown voltage of the device, increasing the doping concentration of the drift region, and further reducing the on-resistance of the device.
[0025] 3. The superjunction structure of the present invention changes the width distribution of P and N-type silicon carbide by adding a dielectric region, so the width of the superjunction structure near the semiconductor well region is smaller than the width near the semiconductor drain region. The superjunction structure improves the breakdown voltage by charge compensation between P-type silicon carbide and N-type silicon carbide, modulates the charge compensation and electric field distribution in drift, optimizes the doping concentration in the drift region, significantly reduces the conduction loss, and thus improves the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 This is a schematic diagram of the three-dimensional structure of a local dielectric modulated lateral super junction silicon carbide device in Example 1 of the present invention.
[0027] Figure 2 This is a top view of the surface of the silicon carbide active layer in Example 1 of the present invention.
[0028] Figure 3 for Figure 1 Longitudinal section along line AA' in the drift zone.
[0029] Figure 4 for Figure 1 Longitudinal section along line BB' in the drift zone.
[0030] Figure 5 for Figure 1 A longitudinal cross-sectional view along the gate dielectric CC' line in FIG.
[0031] Figure 6 This is a top view of the surface of the silicon carbide active layer in Example 2 of the present invention.
[0032] Figure 7 This is a top view of the surface of the silicon carbide active layer in Example 3 of the present invention.
[0033] Description of the numbers in the figure:
[0034] 1. Semiconductor substrate; 2. Buried oxide layer; 3. Silicon carbide active layer; 4. Semiconductor drain region; 5. Semiconductor well region; 6. Semiconductor body contact region; 7. Semiconductor source region; 8. Source metal; 9. Dielectric region; 10. P-type silicon carbide; 11. N-type silicon carbide; 12. Gate metal; 13. Drain metal. DETAILED DESCRIPTION
[0035] In the description of the present invention, it should be understood that the terms "left side", "right side", "upper part", "lower part" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. "First", "second" and the like do not indicate the importance of the components, and therefore cannot be understood as limiting the present invention. The specific dimensions used in this embodiment are only for illustrating the technical solution, and do not limit the scope of protection of the present invention.
[0036] The present invention will be further described in detail below with reference to the accompanying drawings and three specific preferred embodiments.
[0037] Example 1
[0038] like Figure 1 As shown, a local dielectric modulated lateral super junction silicon carbide device includes a semiconductor substrate 1, a buried oxide layer 2, a silicon carbide active layer 3 and a metal layer arranged in sequence from bottom to top.
[0039] The thickness of the silicon carbide active layer is preferably 1 to 5 microns.
[0040] like Figures 2 to 5 As shown, the silicon carbide active layer includes a super junction structure, a semiconductor drain region 4 , a semiconductor well region 5 , a semiconductor body contact region 6 , a semiconductor source region 7 and a dielectric region 9 .
[0041] The super junction structure includes P-type silicon carbide 10 and N-type silicon carbide 11 arranged symmetrically about a device symmetry line X; wherein the device symmetry line X is along the device length direction; and the doping concentration of the P-type silicon carbide is greater than or equal to the doping concentration of the N-type silicon carbide.
[0042] Furthermore, the super junction structure includes a small width portion and a large width portion coaxially arranged along the length direction of the silicon carbide active layer, wherein the width of the small width portion is smaller than the width of the large width portion. That is, both the P-type silicon carbide 10 and the N-type silicon carbide 11 have a small width portion and a large width portion.
[0043] The semiconductor drain region is disposed outside the large width portion.
[0044] The semiconductor well region is disposed at the outer center of the small width.
[0045] The semiconductor body contact region and the semiconductor source region are arranged in parallel on the surface of the semiconductor well region; wherein the semiconductor source region faces the super junction structure.
[0046] The dielectric region is arranged on both sides of the small width portion and the semiconductor well region and on the top of the small width portion. The dielectric region preferably uses an insulating material with a high dielectric constant, and is further preferably any one of hafnium oxide, zirconium oxide, titanium dioxide, strontium titanate, barium strontium titanium oxide and lead zirconate titanate.
[0047] The dielectric region includes a central dielectric region and two side dielectric regions; wherein the central dielectric region is located at the top of the small width portion; the two side dielectric regions are symmetrically arranged on both sides of the small width portion and the semiconductor well region; the length of each side dielectric region is equal to the sum of the lengths of the semiconductor well region and the small width portion; the length of each side dielectric region in contact with the small width portion is not greater than two-thirds of the length of the super junction structure.
[0048] In the present embodiment 1, each side dielectric region is a rectangular cross-sectional structure with equal width, and the width of the small width portion of the super junction structure from the semiconductor well region to the semiconductor drain region is equal.
[0049] In this embodiment 1, the shapes of the P-type silicon carbide 10 (also called the P-type semiconductor column) and the N-type silicon carbide 11 (also called the N-type semiconductor column) and the dielectric region 9 are designed accordingly, and the width of the P-type and N-type silicon carbide is changed by changing the width of the dielectric region 9. Since the width of the P-type and N-type silicon carbide changes more widely, the charge imbalance phenomenon of the mutual depletion of the P-type semiconductor column and the N-type semiconductor column is further improved, and the electric field and doping concentration of the drift region are further optimized.
[0050] The metal layer includes source metal 8, gate metal 12 and drain metal 13. The source metal is arranged in contact with the semiconductor body contact region and the semiconductor source region; the drain metal is arranged directly above the semiconductor drain region; and the gate metal is arranged on the surface of the dielectric region directly above the small width.
[0051] A method for preparing a local dielectric modulated lateral super junction silicon carbide device comprises the following steps.
[0052] Step a: Select a silicon carbide on insulator substrate with appropriate thickness and concentration, including a semiconductor substrate 1 and a buried oxide layer 2 located above the semiconductor substrate 1 , and a silicon carbide active layer 3 located above the buried oxide layer 2 .
[0053] Step b: P-type impurities are implanted into the silicon carbide active layer 3 by an ion implantation process to form P-type silicon carbide 10. The silicon carbide active layer 3 is divided into P-type silicon carbide 10 and N-type silicon carbide 11. The P-type silicon carbide 10 and the N-type silicon carbide 11 form a super junction structure.
[0054] Step c: implanting P-type impurities into the silicon carbide active layer 3 by an ion implantation process to form a P-type well region, ie, a semiconductor well region 5 .
[0055] Step d: In the P-type well region located outside, P-type impurities are preferably implanted by an ion implantation process to form a semiconductor body contact region 6 .
[0056] Step e: In the P-type well region located inside the semiconductor body contact region 6, N-type impurities are preferably implanted by an ion implantation process to form an N-type semiconductor source region 7; in addition, at the end of the super junction structure away from the P-type well region, N-type impurities are preferably implanted by an ion implantation process to form a semiconductor drain region 4.
[0057] Step f: On the silicon carbide active layer 3 located on both sides of the P-type well region, a dry etching process is preferably used to form a local groove, and the length of the local groove needs to be greater than the length of the P-type well region.
[0058] Step g: depositing dielectric material in the local groove and using chemical mechanical polishing to planarize the surface, and retaining a dielectric layer of a certain thickness on the surface of the silicon carbide active layer 3.
[0059] Step h: Etching the dielectric layer, retaining only the surface dielectric layer corresponding to the local groove, and etching contact holes in the source and drain regions at the same time.
[0060] Step i: deposit source metal 8 and drain metal 12 at the contact hole position, and deposit metal on the dielectric region 9 to form a gate metal sheet 13.
[0061] Example 2
[0062] This embodiment provides a local dielectric modulated lateral superjunction silicon carbide device, the basic structure of which is similar to Figure 1 , the differences and improvements are: Figure 6 As shown, each side dielectric region has a stepped cross-sectional structure and forms a stepped fit with the small width portion; at this time, the width of each side dielectric region from the semiconductor well region to the semiconductor drain region is reduced in a step-like manner; the width of the small width portion of the super junction structure from the semiconductor well region to the semiconductor drain region is increased in a step-like manner.
[0063] In terms of process, it is only necessary to use a step-type mask when etching a local groove to realize the step-type groove, and the other process steps remain unchanged.
[0064] In this embodiment, the shapes of the P-type silicon carbide 10, the N-type silicon carbide 11 and the dielectric region 9 are designed accordingly, and the step-wise change in the width of the dielectric region 9 is used to achieve the step-wise change in the width of the P-type and N-type silicon carbides. This can not only improve the charge imbalance phenomenon of the mutual depletion of the P-type and N-type silicon carbide, but also optimize the surface electric field distribution by forming an electric field peak, thereby improving the breakdown voltage of the device.
[0065] Example 3
[0066] This embodiment provides a local dielectric modulated lateral superjunction silicon carbide device, whose basic structure is the same as that of embodiment 1, except that: Figure 7 As shown, each side dielectric region is a right-angle trapezoidal cross-section structure, and forms an inclined surface with the small width portion, semiconductor well region, semiconductor body contact region and semiconductor source region of the super junction structure; at this time, the width of each side dielectric region from the semiconductor well region to the semiconductor drain region is linearly reduced; the width of the small width portion of the super junction structure from the semiconductor well region to the semiconductor drain region is linearly increased. The widths of the semiconductor well region, semiconductor body contact region and semiconductor source region also increase linearly toward the direction of the semiconductor drain region.
[0067] In terms of process, it is only necessary to use a ladder-shaped mask to realize the ladder-shaped groove when etching the local groove, and the other process steps remain unchanged.
[0068] The present invention improves the gate leakage current problem and reduces the device turn-on voltage by replacing the commonly used silicon oxide gate dielectric with a high dielectric constant dielectric. At the same time, a local dielectric is used to introduce a new electric field peak in the drift region, modulate the electric field distribution, and improve the charge imbalance effect of the lateral superjunction structure, optimize the drift region concentration and reduce the on-resistance of the device, thereby improving the device performance and reliability.
[0069] The preferred embodiments of the present invention are described in detail above; however, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, various equivalent transformations can be made to the technical solutions of the present invention, and these equivalent transformations all belong to the protection scope of the present invention.
Claims
1. A local dielectric modulated lateral superjunction silicon carbide device, characterized in that: It includes a semiconductor substrate, a buried oxide layer, a silicon carbide active layer and a metal layer which are arranged in sequence from bottom to top; The silicon carbide active layer includes a super junction structure, a semiconductor drain region, a semiconductor well region and a dielectric region; The super junction structure comprises a small width portion and a large width portion coaxially arranged along the length direction of the silicon carbide active layer; wherein the width of the small width portion is smaller than the width of the large width portion; The semiconductor drain region is arranged outside the large width portion; The semiconductor well region is arranged at the outer center of the small width; The dielectric region is arranged on both sides of the small width portion and the semiconductor well region and on the top of the small width portion; The metal layer includes source metal, drain metal and gate metal; wherein the source metal is arranged directly above the semiconductor well region; the drain metal is arranged directly above the semiconductor drain region; and the gate metal is arranged on the surface of the dielectric region directly above the small width.
2. The local dielectric modulated lateral superjunction silicon carbide device according to claim 1, characterized in that: The dielectric region includes a central dielectric region and two side dielectric regions; wherein the central dielectric region is located at the top of the small width portion; the two side dielectric regions are symmetrically arranged on both sides of the small width portion and the semiconductor well region; the length of each side dielectric region is equal to the sum of the lengths of the semiconductor well region and the small width portion; the length of each side dielectric region in contact with the small width portion is not greater than two-thirds of the length of the super junction structure.
3. The local dielectric modulated lateral superjunction silicon carbide device according to claim 2, characterized in that: Each side dielectric region is a rectangular cross-sectional structure with equal width, and the width of the small width portion of the super junction structure from the semiconductor well region to the semiconductor drain region is equal.
4. The local dielectric modulated lateral superjunction silicon carbide device according to claim 2, characterized in that: Each side dielectric region has a stepped cross-sectional structure and forms a stepped fit with the small width portion; at this time, the width of each side dielectric region from the semiconductor well region to the semiconductor drain region decreases in a step-like manner; the width of the small width portion of the super junction structure increases in a step-like manner from the semiconductor well region to the semiconductor drain region.
5. The local dielectric modulated lateral superjunction silicon carbide device according to claim 2, characterized in that: Each side dielectric region has a right-angled trapezoidal cross-section structure and forms an inclined surface with the small-width portion; at this time, the width of each side dielectric region from the semiconductor well region to the semiconductor drain region is linearly reduced; the width of the small-width portion of the super junction structure increases linearly from the semiconductor well region to the semiconductor drain region.
6. The local dielectric modulated lateral superjunction silicon carbide device according to claim 5, characterized in that: Each side dielectric region also forms an inclined surface with the semiconductor well region; the width of the semiconductor well region also increases linearly toward the direction of the semiconductor drain region.
7. The local dielectric modulated lateral superjunction silicon carbide device according to claim 1, characterized in that: The silicon carbide active layer also includes a semiconductor body contact region and a semiconductor source region arranged in parallel on the surface of the semiconductor well region; wherein the semiconductor source region faces the super junction structure; and the source metal is in contact with the semiconductor body contact region and the semiconductor source region.
8. The local dielectric modulated lateral superjunction silicon carbide device according to claim 1, characterized in that: The super junction structure includes P-type silicon carbide and N-type silicon carbide arranged symmetrically about a device symmetry line X; wherein the device symmetry line X is along the length direction of the device; and the doping concentration of the P-type silicon carbide is greater than or equal to the doping concentration of the N-type silicon carbide.
9. The local dielectric modulated lateral superjunction silicon carbide device according to claim 1, characterized in that: The thickness of the silicon carbide active layer is 1 to 5 microns.
10. The local dielectric modulated lateral superjunction silicon carbide device according to claim 1, characterized in that: The dielectric region adopts an insulating material with a high dielectric constant, which is any one of hafnium oxide, zirconium oxide, titanium dioxide, strontium titanate, titanium barium strontium oxide and lead zirconate titanate.