Method of manufacturing a semiconductor structure and semiconductor structure

Abstract

Embodiments of the present application provide a manufacturing method of a semiconductor structure and a semiconductor structure, relating to the technical field of semiconductor manufacturing. The manufacturing method of the semiconductor structure includes: providing a substrate; wherein, the substrate includes a substrate and at least two gate structures spaced apart on the substrate; the gate structures protrude from the surface of the substrate; the spacing distance between the projections of two adjacent gate structures on the substrate is a first distance; forming a polymer layer on the gate structures to obtain a transition gate structure; wherein, the spacing distance between the projections of two adjacent transition gate structures on the substrate is a second distance; the second distance is less than the first distance; based on the second distance, forming a sigma trench in the substrate. Through the embodiments of the present application, the adjustment of the top size of the sigma trench is realized by controlling the thickness of the polymer layer, the adjustment difficulty of the critical dimension of the sigma trench is reduced, and the adjustment ability of the critical dimension of the sigma trench is improved.

Description

Technical Field

[0001] The embodiments in the present application relate to the field of semiconductor manufacturing technology, and particularly to a manufacturing method of a semiconductor structure and a semiconductor structure. Background Art

[0002] In the semiconductor device manufacturing process, especially for technology nodes of 28 nm and below, preparing sigma trenches is a key step in constructing high-performance devices. Specifically, due to the special geometric shape of sigma trenches which helps optimize the movement of carriers, during the process of manufacturing Complementary Metal Oxide Semiconductor (CMOS) devices, sigma trenches are often used to introduce stress engineering to improve the drive current of P-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET), thereby improving the overall electrical performance of CMOS devices.

[0003] Sigma trenches are usually formed between N-type MOSFETs and P-type MOSFETs. Due to the relatively special cross-sectional shape of sigma trenches, the process of preparing sigma trenches is relatively complex, and the dimensional accuracy requirements for trench dimensions are also relatively high. Among the multiple dimensions of sigma trenches, the top dimension of sigma trenches has an important impact on the isolation effect between different components, as well as the overall electrical performance, manufacturing yield, stability and reliability of the device, and is a key dimension in the preparation of sigma trenches.

[0004] However, the existing methods for preparing sigma trenches have a weak ability to adjust the top dimension of sigma trenches and are difficult to meet the preparation requirements of sigma trenches. Summary of the Invention

[0005] In view of this, multiple embodiments of the present application provide a manufacturing method of a semiconductor structure and a semiconductor structure to improve the ability to adjust the top dimension of sigma trenches.

[0006] In one aspect, an embodiment of the present application provides a manufacturing method of a semiconductor structure, the method including: providing a substrate; wherein, the substrate includes a substrate and at least two gate structures spaced apart on the substrate; the gate structures protrude from the surface of the substrate; the distance between the projections of two adjacent gate structures on the substrate is a first distance; forming a polymer layer on the gate structures to obtain a transition gate structure; wherein, the distance between the projections of two adjacent transition gate structures on the substrate is a second distance; the second distance is less than the first distance; based on the second distance, forming sigma trenches in the substrate.

[0007] Optionally, the step of forming a polymer layer on the gate structure to obtain a transition gate structure includes: depositing a polymer film on the surface of the substrate and the surface of the gate structure; etching the polymer film to form the polymer layer and obtain the transition gate structure.

[0008] Optionally, the step of depositing a polymer film on the gate structure includes: depositing the polymer film on the surface of the substrate and the surface of the gate structure by chemical vapor deposition according to specified deposition parameters; wherein, the thickness of the polymer film falls within the range of 1 nm to 5 nm.

[0009] Optionally, the specified deposition parameters include a specified deposition bias power, a specified deposition time, and a specified main reaction gas; wherein, the specified deposition bias power is not greater than 50 W; the specified main reaction gas includes methyl fluoride and oxygen; the polymer film formed based on the specified main reaction gas includes carbon, fluorine, hydrogen, and silicon elements.

[0010] Optionally, the step of etching the polymer film to form the polymer layer and obtain the transition gate structure includes: physically dry-etching the polymer film according to specified etching parameters to form the polymer layer and obtain the transition gate structure.

[0011] Optionally, the specified etching parameters include a specified etching bias power and a specified etching gas; wherein, the specified etching bias power falls within the range of 50 W to 250 W; the specified etching gas includes oxygen and argon.

[0012] Optionally, the gate structure includes a gate portion and a sidewall portion; the polymer layer includes a sidewall protection layer formed on the surface of the sidewall portion and a gate protection layer formed on the exposed surface of the gate portion.

[0013] Optionally, along the normal direction of the substrate, the sidewall protection layer has an upper edge away from the substrate and a lower edge close to the substrate; the distance between the projection of the lower edge on the substrate and the center of the projection of the gate structure on the substrate is a third distance; the distance between the projection of the upper edge on the substrate and the center of the projection of the gate structure on the substrate is a fourth distance; the fourth distance is less than the third distance; as the specified etching bias power increases, the difference between the third distance and the fourth distance decreases.

[0014] Optionally, the step of forming a sigma trench in the substrate based on the second distance includes: dry-etching the substrate based on the second distance to obtain a preliminary trench; wherein, the width of the preliminary trench is equal to the second distance; wet-etching the preliminary trench to obtain the sigma trench.

[0015] In another aspect, an embodiment of the present application provides a semiconductor structure, which is manufactured according to the manufacturing method of the semiconductor structure in the above embodiment.

[0016] In multiple embodiments provided by the present application, by forming a polymer layer on at least two gate structures disposed at intervals on a substrate, at least two transition gate structures are obtained. Among them, the interval distance between the projections of two adjacent gate structures on the substrate is a first distance; the interval distance between the projections of two adjacent transition gate structures on the substrate is a second distance; the second distance is less than the first distance. Then, based on the second distance, a sigma trench is formed in the substrate. The unexpected effects achieved include: by changing the thickness of the polymer layer, the interval distance between the transition gate structures is changed, so that the adjustment of the top size of the sigma trench is realized by controlling the thickness of the polymer layer, the adjustment difficulty of the critical dimension of the sigma trench is reduced, and the adjustment ability of the critical dimension of the sigma trench is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for describing the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0018] Figure 1 Schematic diagram of forming a preliminary trench in a substrate provided by the related art.

[0019] Figure 2 Schematic diagram of obtaining a sigma trench based on the preliminary trench provided by the related art.

[0020] Figure 3 Flow chart of the manufacturing method of the semiconductor structure provided by an embodiment of the present application.

[0021] Figure 4 Schematic diagram of the structure of a substrate provided by an embodiment of the present application.

[0022] Figure 5 Flow chart of the step of forming a polymer layer on a gate structure to obtain a transition gate structure provided by an embodiment of the present application.

[0023] Figure 6 Schematic diagram of depositing a polymer film on the surface of a substrate and the surface of a gate structure provided by an embodiment of the present application.

[0024] Figure 7Schematic diagram of etching a polymer film according to an embodiment of the present application to form a polymer layer and obtain a transition gate structure.

[0025] Figure 8 Flow schematic diagram of the step of forming a sigma trench in a substrate based on a second distance according to an embodiment of the present application.

[0026] Figure 9 Schematic diagram of dry-etching a substrate based on a second distance to obtain a preliminary trench according to an embodiment of the present application.

[0027] Figure 10 Schematic diagram of wet-etching the preliminary trench to obtain a sigma trench according to an embodiment of the present application.

[0028] Description of structure labels

[0029] 100, substrate; 110, base substrate; 111, wafer; 112, isolation layer; 120, gate structure; 121, gate portion; 122, sidewall portion; 130, transition gate structure; 131, polymer film; 132, polymer layer; 140, preliminary trench; 150, sigma trench. Detailed implementation manners

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0031] The accompanying drawings provided in the embodiments of the present application only illustrate the basic concept of the present application in a schematic manner. Only the components related to the present application are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The forms, quantities, and proportions of the components in actual implementation may change, and the layout form of the components may also be more complex.

[0032] In the description of the embodiments of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", "center", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be construed as a limitation to the present application. The terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of the described features.

[0033] Silicon-germanium (SiGe) epitaxial technology is a semiconductor material preparation process mainly applied to the manufacturing of high-performance integrated circuit devices. Through methods such as chemical vapor deposition or molecular beam epitaxy, one or more layers of silicon-germanium alloy materials are epitaxially grown on a silicon substrate to utilize the physical properties of the silicon-germanium alloy to improve the electron mobility of PMOS components in CMOS devices, thereby enhancing the overall speed and performance of CMOS devices.

[0034] As the integrated circuit technology node continues to shrink, in order to achieve performance improvement of small-size devices, researchers have further optimized the silicon-germanium epitaxial technology. For example, for technology nodes of 28nm and below, a technology of etching sigma trenches in the silicon-germanium epitaxial layer or the silicon substrate has been developed to improve the chip integration density while maintaining good electrical performance of the device, so as to integrate a larger number of devices on a smaller chip area.

[0035] Please refer to Figure 1 and Figure 2 . Taking the preparation of sigma trenches in a silicon substrate as an example, the preparation process and trench size control of sigma trenches in related technologies are briefly introduced.

[0036] Since the cross-sectional shape of the sigma trench is relatively special and it is difficult to prepare it by one etching, in related technologies, the sigma trench is usually prepared in the substrate by two etching steps. Specifically, first, a preliminary trench 140 is formed between the gate structures 120 arranged at intervals on the substrate 110 by plasma dry etching. The cross-sectional shape of the preliminary trench 140 can be U-shaped or bowl-shaped. Subsequently, the preliminary trench 140 can be etched by wet etching with tetramethylammonium hydroxide as the wet etching solution to obtain a large-bottom cut sigma trench 150 with a width at the bottom of the trench significantly larger than the width of the opening at the top of the trench.

[0037] To control the cross-sectional shape of the sigma trench, precise control of multiple dimensions such as the top dimension, bottom dimension, and depth dimension of the sigma trench is required. Among them, the top dimension, that is, the width of the opening at the top of the trench CD2 has a greater impact on the device performance and is the key dimension for the preparation of the sigma trench. CD2 is determined based on the distance CD1 between the projections of adjacent gate structures on the substrate, that is, CD2 is equal to CD1. In Figure 1 , the gate structure 120 includes a gate portion 121 and a sidewall portion 122. As can be seen from Figure 1 , CD1 is determined based on the distance Pitch between the projections of the gate portion 121 on the substrate 110, the width CD3 of the gate portion 121, and the thickness CD4 of the sidewall portion 122, that is, CD1 is the difference between Pitch and twice the sum of CD3 and CD4.

[0038] Since Pitch and CD3 are critical dimensions in the CMOS device design process and are often determined and difficult to change before the sigma trench is fabricated, in related technologies, the top dimension of the sigma trench is typically controlled by CD4, that is, the top dimension of the sigma trench can be adjusted by changing the thickness of the sidewall portion. However, the value of CD4 has an important impact on the leakage performance of CMOS devices, and adjusting the top dimension of the sigma trench by changing the value of CD4 may lead to a decrease in the leakage performance of the device. In addition, the sidewall portion is mainly formed by laterally etching the nitride layer deposited on the surface of the gate portion using a dry etching process, and the nitride layer is deposited by a high-temperature furnace tube process with high density and weak ability to be laterally etched. Therefore, limited by the difficulty of changing the value of CD4 and the difficulty of controlling the lateral etching of the nitride layer, the ability of the sigma trench fabrication method adopted in related technologies to adjust the top dimension of the sigma trench is weak and difficult to meet the fabrication requirements of sigma trenches with different top dimensions.

[0039] Therefore, it is necessary to provide a manufacturing method of a semiconductor structure. By forming a polymer layer on at least two gate structures spaced apart on a substrate, at least two transition gate structures are obtained, such that the spacing distance between the projections of two adjacent transition gate structures on the substrate is less than the spacing distance between the projections of two adjacent gate structures on the substrate. Changing the thickness of the polymer layer can change the spacing distance between the transition gate structures, so that the adjustment of the top dimension of the sigma trench can be achieved by controlling the thickness of the polymer layer, thereby reducing the difficulty of adjusting the critical dimensions of the sigma trench and improving the ability to adjust the critical dimensions of the sigma trench.

[0040] Please refer to Figures 3 to 10 This application provides a manufacturing method of a semiconductor structure. The manufacturing method of the semiconductor structure may include the following steps.

[0041] S110: Provide a substrate.

[0042] Please refer to Figure 4 The substrate 100 may include a substrate 110 and at least two gate structures 120 spaced apart on the substrate 110.

[0043] In this embodiment, the substrate 110 can serve as the support for transistors and other semiconductor components. Specifically, the substrate 110 can include a substrate 111 and an isolation layer 112. The substrate 111 can be composed of semiconductor materials, insulating materials, conductive materials, or any combination thereof. For example, the substrate 111 can be made of materials such as silicon (Si), silicon germanium (SiGe), silicon germanium carbide (SiGeC), silicon carbide (SiC), etc. The substrate 111 can be a single-layer structure or a multi-layer structure. In this embodiment, considering factors such as the integrated dielectric loss requirements, manufacturing processes, and manufacturing costs, a silicon wafer is used as the substrate 111. The isolation layer 112 can be used to isolate the electric field between the gate structure 120 and the substrate 110 in the MOSFET, so as to reduce the interference and leakage of carriers. Specifically, the material of the isolation layer 112 can be selected from insulating materials such as silicon nitride or silicon oxide, and the embodiments of this specification do not specifically limit the material of the isolation layer 112.

[0044] In this embodiment, the gate structure 120 can protrude from the surface of the substrate 110. Specifically, the gate structure 120 can include a gate portion 121 and a sidewall portion 122. Among them, the gate portion 121 can include a gate dielectric layer for reducing gate leakage current, a gate electrode for conducting electricity and adjusting the transistor threshold voltage, a contact layer for realizing electrical contact between the gate and the external circuit, and a gate cap for protecting the gate electrode. The top surface of the gate portion 121 can be the arc surface of the gate cap. The sidewall portion 122 can be used to define the position of the lightly doped drain (LDD) region, control the short-channel effect, and form isolation between multiple gate electrodes. The material of the sidewall portion 122 can be silicon nitride (SiN) or silicon dioxide (SiO2).

[0045] Taking the material of the sidewall portion 122 as SiN as an example, the sidewall portion 122 can be manufactured through the following process: after forming at least two gate portions 121 spaced apart from each other on the surface of the isolation layer 112 in the substrate 110, depositing a SiN layer on the surface of the isolation layer 112 and the surface of the gate portion 121, and then performing dry etching on the SiN layer in the etching main chamber to remove the SiN layer covering the surface of the isolation layer 112, so as to form the sidewall portion 122 covering a part of the top surface and the side surface of the gate portion 121.

[0046] In this embodiment, the spacing distance between the projections of two adjacent gate structures 120 on the substrate 110 is the first distance D1. Specifically, the sidewall portions 122 of two adjacent gate structures 120 have opposite surfaces. Correspondingly, the spacing distance between the projections of two adjacent gate structures 120 on the substrate 110 can be the distance between the projections of the opposite surfaces of the sidewall portions 122 of two adjacent gate structures 120 on the substrate 110.

[0047] S120: Form a polymer layer on the gate structure to obtain a transition gate structure.

[0048] Since the top dimension of the sigma trench 150 is equal to the spacing distance between the projections of two adjacent gate structures 120 on the substrate 110, to improve the adjustment ability of the top dimension of the sigma trench 150, a polymer layer 132 with variable thickness can be formed on the gate structure 120 to obtain a transition gate structure 130 including the polymer layer 132, so that the spacing distance between the projections of two adjacent transition gate structures 130 on the substrate 110 can be changed by changing the thickness of the polymer layer 132, and then the top dimension of the sigma trench 150 can be changed.

[0049] Please refer to Figures 5 to 7 .. Forming a polymer layer 132 on the gate structure 120 to obtain a transition gate structure 130 may include the following steps.

[0050] S121: Deposit a polymer film on the surface of the substrate and the surface of the gate structure.

[0051] Please refer to Figure 6 .. To improve the control ability of the thickness of the polymer layer 132 and also provide protection to the gate part 121 and the sidewall part 122 during subsequent fabrication processes, a polymer film 131 that wraps the entire gate structure 120 can be deposited on the surface of the substrate 110 and the surface of the gate structure 120.

[0052] In this embodiment, the step of depositing the polymer film 131 on the surface of the substrate 110 and the surface of the gate structure 120 may include: depositing the polymer film 131 on the surface of the substrate 110 and the surface of the gate structure 120 by chemical vapor deposition according to specified deposition parameters. Among them, the surface of the gate structure 120 may include the exposed surface of the gate part 121 and the surface of the sidewall part 122. The exposed surface of the gate part 121 may be the top surface of the part of the gate part 121 that is not covered by the sidewall part 122.

[0053] To reduce the damage to the gate structure 120 during the subsequent etching of the polymer film 131 to form the polymer layer 132, in this embodiment, the thickness of the polymer film 131 may fall within the range of 1 nm to 5 nm. For example, the thickness of the polymer film 131 may be 1 nm, 2 nm, 3 nm, 4 nm, 5 nm.

[0054] To improve the control accuracy of polymer particle deposition, in this embodiment, the specified deposition parameters may include specifying a deposition bias power, a deposition time, and a main reaction gas. Specifically, the specified deposition bias power can be used to control the deposition direction and deposition speed of polymer particles, the specified deposition time can be used to control the thickness of the polymer film 131, and the specified main reaction gas can be used to control the composition of the polymer film 131.

[0055] In this embodiment, the specified deposition bias power may not be greater than 50 W. Specifically, when the deposition bias power is relatively large, the polymer particles may hit the surfaces of the gate structure 120 and the substrate 110 at a relatively high speed, bombarding the gate structure 120 and the substrate 110, and moreover, the polymer deposition may be directional, that is, the polymer particles may be concentrated on a specific position, thus possibly causing damage to the gate structure 120 and the substrate 110 at that specific position. Therefore, to reduce the damage to the gate structure 120 and the substrate 110 during the deposition process of the polymer film 131, the specified deposition bias power can be set to a lower value. For example, the specified deposition bias power can be 40 W, 42 W, 45 W, 47 W, 50 W.

[0056] In this embodiment, the specified deposition time can be determined according to the thickness of the polymer film 131. Specifically, during the process of depositing polymer particles to form the polymer film 131, the deposition bias power can be maintained at the specified deposition bias power, and the thickness of the formed polymer film 131 can be controlled by controlling the deposition time, that is, the longer the deposition time, the thicker the formed polymer film 131.

[0057] In this embodiment, the specified main reaction gas may include methyl fluoride (CH3F) and oxygen (O2). By using the main reaction gas to react with the silicon element in the substrate 100, the polymer film 131 formed based on the specified main reaction gas can include elements such as carbon (C), fluorine (F), hydrogen (H), and silicon (Si).

[0058] S122: Etch the polymer film to form a polymer layer, obtaining a transition gate structure.

[0059] Please refer to Figure 7 . Since the top size of the sigma trench 150 is determined by the spacing distance between the projections of adjacent gate structures 120 on the substrate 110, to improve the adjustment ability of the top size of the sigma trench 150, the polymer film 131 can be etched after the polymer film 131 is formed to form a polymer layer 132, obtaining a transition gate structure 130, so as to use the polymer layer 132 to adjust the spacing distance between the projections of two adjacent transition gate structures 130 on the substrate 110.

[0060] In this embodiment, the step of etching the polymer film 131 to form the polymer layer 132 and obtain the transition gate structure 130 may include: performing physical dry etching on the polymer film 131 according to specified etching parameters to form the polymer layer 132 and obtain the transition gate structure 130.

[0061] Since the polymer contains strong covalent bonds and has a high bond energy, to improve the control accuracy of etching the polymer film 131, enhance the etching effect of the polymer film 131, and make the shape of the polymer layer 132 formed by etching the polymer film 131 meet the process requirements, in this embodiment, physical dry etching can be used to etch the polymer film 131.

[0062] In this embodiment, the spacing distance between the projections of two adjacent transition gate structures 130 on the substrate 110 is the second distance D2. Specifically, the polymer layers 132 of two adjacent transition gate structures 130 have opposite surfaces. Correspondingly, the spacing distance between the projections of two adjacent transition gate structures 130 on the substrate 110 can be the distance between the projections of the opposite surfaces of the polymer layers 132 of two adjacent transition gate structures 130 on the substrate 110. The second distance D2 is less than the first distance D1.

[0063] To improve the control accuracy of etching the polymer film 131, in this embodiment, the specified etching parameters may include a specified etching bias power and a specified etching gas. Specifically, the specified etching bias power can be used to control the etching direction and etching speed of the polymer film 131, and the specified etching gas can be used to remove the polymer film 131 and enhance the etching effect of the polymer film 131.

[0064] In this embodiment, the specified etching bias power may fall within the range of 50 W to 250 W. Specifically, the greater the etching bias power, the easier it is to control the direction of the etching plasma to be perpendicular, thereby enhancing the lateral etching ability of the polymer film 131. To improve the uniformity of lateral etching of the polymer film 131, the specified etching bias power can be set to a higher value. For example, the specified deposition bias power can be 50 W, 100 W, 150 W, 200 W, 250 W.

[0065] To further enhance the uniformity of the polymer film 131 being laterally etched, the specified etching gas may include oxygen (O2) and argon (Ar). Specifically, since the atomic mass of Ar is relatively large, during the process of physical dry etching using argon, Ar atoms will bombard the polymer film 131, making the shape of the polymer layer 132 formed by etching the polymer film 131 more controllable.

[0066] In order to provide a certain degree of protection for the mask and the sidewall portion in the subsequent process steps of forming the sigma trench, in this embodiment, the polymer layer 132 may include a sidewall protection layer formed on the surface of the sidewall portion 122 and a gate protection layer formed on the exposed surface of the gate portion 121.

[0067] Ideally, the polymer film 131 can be etched uniformly laterally, that is, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 is 90°. However, it is difficult to achieve the ideal state during the actual etching process. Therefore, in this embodiment, along the normal direction of the substrate 110, the sidewall protection layer has an upper edge away from the substrate 110 and a lower edge close to the substrate 110. Among them, the distance between the projection of the lower edge on the substrate 110 and the center of the projection of the gate structure 120 on the substrate 110 is the third distance D3, and the distance between the projection of the upper edge on the substrate 110 and the center of the projection of the gate structure 120 on the substrate 110 is the fourth distance D4. Specifically, D4 is less than D3, that is, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 is an acute angle. As the specified etching bias power increases, the surface of the sidewall protection layer gradually tends to be perpendicular to the surface of the substrate 110, that is, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 gradually increases within the range of 0° to 90°, and the difference between D3 and D4 decreases. Thus, by controlling the specified etching bias power, the angle between the surface of the sidewall protection layer and the surface of the substrate 110 can be controlled to control the interval distance between the projections of the transition gate structure 130 on the substrate 110, and further control the top size of the sigma trench 150.

[0068] S130: Form a sigma trench in the substrate based on the second distance.

[0069] After the transition gate structure 130 is formed, the sigma trench 150 can be prepared based on the interval distance between the projections of two adjacent transition gate structures 130 on the substrate 110.

[0070] Please refer to Figures 8 to 10 ... Forming the sigma trench 150 in the substrate 110 based on the second distance may include the following steps.

[0071] S131: Dry-etch the substrate based on the second distance to obtain a preliminary trench.

[0072] Please refer to Figure 9。In this embodiment, the isolation layer 112 between adjacent transition gate structures 130 can be removed by a plasma dry etching method, and the substrate 111 can be etched to obtain a preliminary trench 140. Specifically, perpendicular to the direction in which the preliminary trench 140 extends into the substrate 111, the preliminary trench 140 has a width direction, and along the direction in which the preliminary trench 140 extends into the substrate 111, the width of the preliminary trench 140 in the width direction is equal, and this width can be equal to the second distance D2. The cross-sectional shape of the preliminary trench 140 can be U-shaped. The etching process parameters for obtaining the preliminary trench 140 are the same as those of the conventional etching process used in the related art, and will not be elaborated here.

[0073] S132: Remove the polymer layer.

[0074] In this embodiment, after the preliminary trench 140 is obtained, the transition semiconductor structure with the transition gate structure 130 formed on the surface of the substrate 110 can be cleaned to remove the polymer layer 132 and impurities. Specifically, the cleaning liquid used can be hydrofluoric acid or concentrated sulfuric acid.

[0075] S133: Wet-etch the preliminary trench to obtain a sigma trench.

[0076] Please refer to Figure 10 。In this embodiment, after the polymer layer 132 is removed, the preliminary trench 140 can be subjected to crystal plane selective wet etching with tetramethylammonium hydroxide to obtain a sigma trench 150 with a top size of D2. Specifically, the etching process parameters for obtaining the sigma trench 150 are the same as those of the conventional etching process used in the related art, and will not be elaborated here.

[0077] In this embodiment, the process steps of depositing a polymer film, etching the polymer film to form a polymer layer, and dry-etching the substrate to obtain a preliminary trench can all be completed in the etching main chamber. Specifically, a chamber environment stabilizing device is provided in the etching main chamber, for example, a dry pump. During the execution of the above process steps, the chamber environment stabilizing device is always working to keep the environment in the etching main chamber clean and the pressure stable. At the same time, the temperature in the etching main chamber can fall within the range of 48°C to 52°C. For example, the temperature in the etching main chamber can be 48°C, 49°C, 50°C, 51°C, 52°C. Compared with the process temperature of up to thousands of degrees Celsius during the preparation of the sidewall portion in the high-temperature furnace tube process, the process temperature for executing the above process steps is relatively low. Since multiple process steps are concentrated in the etching main chamber to be completed, the impurity contamination that may be caused by performing different process steps in different environments is reduced, the process difficulty of adjusting the key dimensions of the sigma trench is lowered, and the preparation requirements for sigma trenches with different top sizes can be met without additional machine configuration and without changing the front-end process.

[0078] An embodiment of the present application provides a semiconductor structure, which can be manufactured by the manufacturing method of the semiconductor structure described in the above embodiment.

[0079] In the embodiment of the present application, by forming a polymer layer on at least two gate structures spaced apart on a substrate, at least two transition gate structures are obtained, such that the spacing distance between the projections of two adjacent transition gate structures on the substrate is less than the spacing distance between the projections of two adjacent gate structures on the substrate. The unexpected effects achieved include: the spacing distance between the transition gate structures can be changed by changing the thickness of the polymer layer, so that the top dimension of the sigma trench can be adjusted by controlling the thickness of the polymer layer, the adjustment difficulty of the critical dimension of the sigma trench is reduced, and the adjustment ability of the critical dimension of the sigma trench is improved.

[0080] It can be understood that the specific examples in the present application are only for helping those skilled in the art to better understand the embodiments of the present application, rather than limiting the scope of the present application.

[0081] It can be understood that in various embodiments of the present application, the magnitudes of the sequence numbers of the various processes do not mean the order of execution. The order of execution of the various processes should be determined by their functions and internal logics, and should not constitute any limitation to the implementation process of the embodiments of the present application.

[0082] It can be understood that the various embodiments described in the present application can be implemented alone or in combination, and the embodiments of the present application do not limit this.

[0083] Unless otherwise specified, all technical and scientific terms used in the embodiments of the present application have the same meaning as commonly understood by those skilled in the technical field of the present application. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the related listed items. The singular forms "a", "above-mentioned", and "the" used in the embodiments of the present application are also intended to include the plural forms unless the context clearly indicates otherwise.

[0084] In several embodiments provided by the present application, it should be understood that the disclosed semiconductor structure can be implemented in other ways. For example, the embodiments of the semiconductor structure described above are only illustrative.

[0085] As described above, it is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims described above.

Claims

1. A manufacturing method of a semiconductor structure, characterized in that, The method includes: Providing a substrate; wherein, the substrate includes a substrate body and at least two gate structures disposed at intervals on the substrate body; the gate structures include gate portions and sidewall portions; the gate structures protrude from the surface of the substrate body; the distance between the projections of two adjacent gate structures on the substrate body is a first distance; Forming a polymer layer on the gate structures to obtain a transition gate structure; wherein, the distance between the projections of two adjacent transition gate structures on the substrate body is a second distance; the second distance is less than the first distance; the polymer layer includes a sidewall protection layer formed on the surface of the sidewall portion and a gate protection layer formed on the exposed surface of the gate portion; along the normal direction of the substrate body, the sidewall protection layer has an upper edge away from the substrate body and a lower edge close to the substrate body; the distance between the projection of the lower edge on the substrate body and the center of the projection of the gate structure on the substrate body is a third distance; the distance between the projection of the upper edge on the substrate body and the center of the projection of the gate structure on the substrate body is a fourth distance; the fourth distance is less than the third distance; the step of forming a polymer layer on the gate structures to obtain a transition gate structure includes: depositing a polymer film on the surface of the substrate body and the surface of the gate structures; performing physical dry etching on the polymer film according to specified etching parameters to form the polymer layer and obtain the transition gate structure; wherein, the specified etching parameters include a specified etching bias power; Forming a sigma trench in the substrate body based on the second distance.

2. The method according to claim 1, wherein The step of depositing a polymer film on the surface of the substrate body and the surface of the gate structures includes: Depositing the polymer film on the surface of the substrate body and the surface of the gate structures by chemical vapor deposition according to specified deposition parameters; wherein, the thickness of the polymer film falls within the range of 1 nm to 5 nm.

3. The method according to claim 2, wherein The specified deposition parameters include a specified deposition bias power, a specified deposition time, and a specified main reaction gas; wherein, the specified deposition bias power is not greater than 50 W; the specified main reaction gas includes methyl fluoride and oxygen; the polymer film formed based on the specified main reaction gas includes carbon, fluorine, hydrogen, and silicon elements.

4. The method according to claim 1, wherein The specified etching bias power falls within the range of 50 W to 250 W; the specified etching parameters further include a specified etching gas; the specified etching gas includes oxygen and argon.

5. The method according to claim 1, characterized in that As the specified etching bias power increases, the difference between the third distance and the fourth distance decreases.

6. The method according to claim 1, wherein The step of forming a sigma trench in the substrate body based on the second distance includes: Dry etching the substrate body based on the second distance to obtain a preliminary trench; wherein, the width of the preliminary trench is equal to the second distance; Removing the polymer layer; Wet etching the preliminary trench to obtain the sigma trench.

7. A semiconductor structure, characterized in that, The semiconductor structure is manufactured according to the manufacturing method of the semiconductor structure as described in any one of claims 1 to 6.

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