High voltage device and method of forming same

Abstract

The embodiment of the invention provides a high-voltage device and a forming method thereof. The high-voltage device comprises a diode; a junction field effect transistor adjacent to the diode and electrically coupled to the diode; the high-voltage junction boundary element is electrically connected with the diode and the junction field effect transistor, the high-voltage junction boundary element is in a ring shape, and a high-voltage area and a low-voltage area are defined inside and outside the ring shape respectively; and the first deep well surrounds the high-voltage region. The first deep well includes: a first section disposed in the high-voltage junction boundary element; and a second section disposed in the junction field effect transistor. The first section includes a well and a doped region in the well. The second section includes only the well.

Description

Technical Field

[0001] The present invention relates to high voltage devices, and more particularly to adjusting active regions to improve electric field crowding. Background Art

[0002] In most switching applications, switching efficiency depends on switching loss and switching speed. One way to supply power to the high-voltage circuit of the gate driver is to use a bootstrap circuit, which has the advantages of simplicity and low cost. The bootstrap circuit includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR), which can provide the voltage level of the high-voltage circuit.

[0003] Although existing high voltage devices have generally met their original purposes, they are not satisfactory in all aspects. For example, the breakdown voltage needs to be further improved. Therefore, there are still some problems to be overcome regarding high voltage devices and manufacturing techniques. Summary of the invention

[0004] A high voltage device includes: a diode; a junction field effect transistor adjacent to and electrically coupled to the diode; a high voltage junction boundary element electrically connecting the diode and the junction field effect transistor, wherein from a top view, the high voltage junction boundary element is annular, and defines a high voltage region and a low voltage region inside and outside the annular shape, respectively; and a first deep well surrounding the high voltage region. The first deep well includes: a first section disposed in the high voltage junction boundary element; and a second section disposed in the junction field effect transistor. The first section includes a well, and a doped region in the well. The second section includes only the well.

[0005] A method for forming a high-voltage device includes: providing a substrate; forming an epitaxial layer on the substrate; forming a first high-voltage well, a first deep well surrounding the first high-voltage well, and a second high-voltage well surrounding the first deep well in a first region of the epitaxial layer; forming a first doped region and a second doped region surrounding the first doped region in the first high-voltage well; forming a third doped region in the first deep well, wherein the third doped region surrounds the second doped region; and forming a fourth doped region in the second high-voltage well. The method for forming a high-voltage device also includes: forming a fifth doped region and a sixth doped region in a second region of the epitaxial layer, wherein the second region is laterally adjacent to the first region; extending one side of the fourth doped region outward into the third region of the epitaxial layer to form a loop, wherein the second region is located in the loop; forming a second deep well in the loop, wherein the second deep well extends along the inner side of the loop and crosses the second region; forming a seventh doped region in the second deep well, wherein the seventh doped region extends along the contour of the second deep well; and truncating the portion of the seventh doped region in the second deep well that crosses the second region. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The following will be described in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the size of various components can be arbitrarily enlarged or reduced to clearly show the features of the embodiments of the present invention.

[0007] Figure 1 is a top view of a high voltage device according to some embodiments of the present invention.

[0008] Figure 2 According to some embodiments of the present invention, Figure 1 An enlarged schematic diagram of the high-voltage device is shown.

[0009] Figure 3 is a cross-sectional schematic diagram of a high voltage device according to some embodiments of the present invention.

[0010] Figure 4 is a cross-sectional schematic diagram of a high voltage device according to some embodiments of the present invention.

[0011] [Explanation of symbols]

[0012] 10: High-voltage device

[0013] 10A: High voltage junction boundary element

[0014] 10A-1: High Voltage Area

[0015] 10A-2: Low Pressure Area

[0016] 10B: Diode

[0017] 10C: Junction Field Effect Transistor

[0018] 100: substrate

[0019] 220: buried layer

[0020] 240: buried layer

[0021] 260: buried layer

[0022] 300: epitaxial layer

[0023] 302: Trap

[0024] 320: High-pressure trap

[0025] 322: Trap

[0026] 324: Trap

[0027] 340: Deep Trap

[0028] 342: Trap

[0029] 360: High-pressure trap

[0030] 362: Trap

[0031] 380: Deep Trap

[0032] 382: Trap

[0033] 410: doping region

[0034] 420: doping area

[0035] 430: doping area

[0036] 440: doping area

[0037] 450: doping area

[0038] 460: Doping area

[0039] 470: Conductive structure

[0040] 480: Doping area

[0041] 490: Doping area

[0042] 500a: Isolation structure

[0043] 500b: Isolation structure

[0044] 500c: Isolation structure

[0045] 500d: Isolation structure

[0046] 500e: Isolation Structure

[0047] 500f: Isolation structure

[0048] 500g: Isolation structure

[0049] 500h: Isolation structure

[0050] 500i: Isolation structure

[0051] 500j: Isolation structure

[0052] 500k: Isolation structure

[0053] 600: interlayer dielectric layer

[0054] 620: Guide hole

[0055] 640: Guide hole

[0056] 660: Guide hole

[0057] 670: Guide hole

[0058] 680: Guide hole

[0059] 720:Metal layer

[0060] 740:Metal layer

[0061] 745: Helical structure

[0062] 800: Intermetallic dielectric layer

[0063] 820: Guide hole

[0064] 830:Guide hole

[0065] 840:Guide hole

[0066] 850:Guide hole

[0067] 860:Guide hole

[0068] 880:Guide hole

[0069] 920:Metal layer

[0070] 940:Metal layer

[0071] 960:Metal layer

[0072] 965: Helical structure

[0073] A-A': Line segment

[0074] B-B': Line segment

[0075] D1: Spacing

[0076] D2: Spacing

[0077] X: Area. DETAILED DESCRIPTION

[0078] The following disclosure provides many different embodiments or examples for implementing different components of the embodiments of the present invention. Specific examples of components and configurations are described below to simplify the embodiments of the present invention. Of course, these are merely examples and are not intended to limit the embodiments of the present invention. For example, the description mentions that the first component is formed on the second component, which may include an embodiment in which the first and second components are in direct contact, and may also include an embodiment in which an additional component is formed between the first and second components so that the first and second components are not in direct contact. In addition, the present invention may repeat component symbols and / or letters in various examples. Such repetition is for the purpose of simplicity and clarity, and does not itself dominate the relationship between the various embodiments and / or configurations discussed.

[0079] Furthermore, in some embodiments of the present invention, terms related to bonding and connection, such as “connection”, “interconnection”, etc., unless otherwise defined, may refer to two structures being in direct contact, or may refer to two structures not being in direct contact, with other structures disposed between the two structures.

[0080] Furthermore, spatially relative terms such as "below," "beneath," "below," "above," "above," and the like may be used herein to describe the relationship between one element or component as shown in the figures and other elements or components. These spatial terms are intended to encompass different orientations of the device in use or operation, as well as the orientations depicted in the figures. When the device is otherwise oriented (rotated 90 degrees or at other orientations), the spatially relative descriptors used herein may be interpreted in accordance with that rotated orientation.

[0081] The terms "about", "approximately", and "generally" used herein generally mean within ±20% of a given value, preferably within ±10%, and more preferably within ±5%, or within ±3%, or within ±2%, or within ±1%, or within 0.5%. The numerical values ​​given herein are approximate values, that is, in the absence of specific description of "about", "approximately", and "generally", the given numerical values ​​may still imply the meaning of "about", "approximately", and "generally".

[0082] Some embodiments of the present invention are described below, and additional steps may be provided before, during, and / or after the multiple stages described in these embodiments. Additional components may be added to the high-voltage device structure. Some of the components may be replaced or omitted in different embodiments. Although some embodiments discussed are performed in a specific order of steps, these steps may still be performed in another logical order.

[0083] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as those commonly understood by those skilled in the art. It is understood that these terms, such as those defined in general dictionaries, should be interpreted as having a meaning consistent with the background or context of the relevant technology and the present invention, and should not be interpreted in an idealized or overly formal manner unless specifically defined in the embodiments of the present invention.

[0084] In order to improve the switching efficiency, a bootstrap circuit can be incorporated into the high-voltage device, which includes a bootstrap diode (BSD), a bootstrap capacitor (BSC), and a bootstrap resistor (BSR). The key parameters of the bootstrap diode of the bootstrap circuit are the reverse recovery time, the forward conduction voltage drop, and the reverse blocking voltage. In traditional designs, the bootstrap diode is generally configured separately. The separately configured bootstrap diode is placed outside the high-voltage device and is individually connected to the high-voltage (high side) area and the low-voltage (low side) area of ​​the high-voltage device. In order to meet the requirements of the cut-off withstand voltage, the bootstrap diode must be achieved by relaxing the design rules, which results in a larger component size. Since the separately configured bootstrap diode is not integrated into the high-voltage device, it may occupy too much space and increase the cost of the additional bill of materials (BOM). Therefore, a buried bootstrap diode integrated in the high-voltage device can be used to solve the above problems. However, compared to the separate bootstrap diode, the buried bootstrap diode may generate a forward leakage current from the anode terminal to the substrate (vertical bipolar junction) during operation, while the cathode terminal does not have a bipolar junction and has no significant reverse leakage current. Therefore, an isolation component (such as a buried layer) may be further added to the buried bootstrap diode to reduce the generation of forward leakage current.

[0085] When a high-voltage device integrates a buried bootstrap diode, a junction field-effect transistor (JFET), and a high voltage junction termination (HVJT) element, the structural differences will reduce the breakdown voltage of the overall high-voltage device. Due to the integration of different structures, the overall circuit design (especially at the interface of different elements) becomes relatively complex. For example, the peripheral doping region of the high-voltage junction termination element and the drain doping region of the junction field effect transistor can be located at different positions. During the integration process, the peripheral doping region and the drain doping region need to be extended to have a curved profile to achieve the connection between the two. From the results of the hot spot analysis, the metal layer above the corner of the doping region (that is, the active region) is prone to gather too high an electric field due to the change in size, which is determined to be the main reason for the low breakdown voltage. It should be understood that the drain doping region is generally the end point where the high voltage is applied, and thus has a direct impact on the performance of the breakdown voltage. The inventors have found that the drain doping region of the junction field effect transistor can be removed to avoid electric field crowding and thus increase the breakdown voltage.

[0086] Figure 11 is a top view of a high voltage device 10 according to some embodiments of the present invention. In some embodiments, the high voltage device may generally include any number of active components and passive components. Active components include metal-oxide semiconductor (MOS) transistors, complementary metal-oxide semiconductor (CMOS) transistors, laterally diffused metal-oxide semiconductor (LDMOS) transistors, bipolar complementary metal oxide semiconductor-double diffused metal oxide semiconductor (BCD) transistors, bipolar junction transistors (BJT), planar transistors, fin field-effect transistors (FinFET), gate-all-around field-effect transistors (GAA FET), other similar devices, or combinations thereof. Passive components include metal traces, capacitors, inductors, resistors, diodes, bonding pads, or other similar structures.

[0087] Reference Figure 1, the high voltage device 10 may include a high voltage junction boundary element 10A, a diode 10B, and a junction field effect transistor 10C. The junction field effect transistor 10C may be adjacent to and electrically coupled to the diode 10B, and the high voltage junction boundary element 10A is electrically connected to the diode 10B and the junction field effect transistor 10C. The high voltage device 10 may be a configuration of lateral diffusion. In some embodiments, from a top view, the high voltage junction boundary element 10A may be designed to be annular. A high voltage region 10A-1 may be defined within the annular shape of the high voltage junction boundary element 10A, and a low voltage region 10A-2 may be defined outside the annular shape of the high voltage junction boundary element 10A. Furthermore, the diode 10B may be a bootstrap diode of a buried configuration. Integrating the high voltage junction boundary element 10A, the diode 10B, and the junction field effect transistor 10C may result in a smaller wafer area and higher reliability. For example, since the high voltage junction boundary element 10A, the diode 10B, and the junction field effect transistor 10C share the same wafer space, the overall area of ​​the high voltage device 10 can be effectively saved. In addition, the integrated configuration makes the high voltage junction boundary element 10A, the diode 10B, and the junction field effect transistor 10C electrically coupled to each other, thereby omitting wire bonding and opening formation, resulting in improved reliability.

[0088] Continue to refer to Figure 1 Although the high-voltage junction boundary element 10A is illustrated as an elliptical ring, the embodiments of the present invention are not limited thereto. For example, the high-voltage junction boundary element 10A may be a circular ring, a square ring, a rectangular ring, a triangular ring, or any suitable closed geometric ring. The ring-shaped configuration makes the integration of the high-voltage junction boundary element 10A with the diode 10B and the junction field effect transistor 10C more efficient and does not occupy additional wafer area. The high-voltage junction boundary element 10A physically and electrically separates the high-voltage region 10A-1 and the low-voltage region 10A-2. The high-voltage region 10A-1 can accommodate components operating at a high-voltage level, while the low-voltage region 10A-2 accommodates components operating at a low-voltage level. In general, "high voltage" refers to a voltage above 300V, such as between 300V and 1200V, between 300V and 750V, or between 750V and 1200V. "Low voltage" generally refers to a voltage below 20 V, such as between 1 V and 20 V, between 1 V and 10 V, or between 10 V and 20 V. In a specific embodiment of the present invention, the high voltage region 10A-1 and the low voltage region 10A-2 operate at voltages of 600 V and 15 V, respectively.

[0089] Reference Figure 1, the range of the diode 10B may span across the anode terminal of the first conductivity type and the cathode terminal of the second conductivity type, wherein the first conductivity type is different from the second conductivity type. In the following embodiments, the first conductivity type and the second conductivity type may represent P-type and N-type, respectively. The first conductivity type (P-type) and the second conductivity type (N-type) may be doped with appropriate dopants (or impurities) respectively. P-type dopants may include boron (B), indium (In), aluminum (Al), and gallium (Ga), while N-type dopants may include phosphorus (P) and arsenic (As). As mentioned previously, in order to avoid forward leakage current generated from the anode terminal to the substrate (vertical bipolar junction), a buried layer may be added, for example, to suppress the leakage current of the substrate to less than 1%. As a result, the device architecture coupled with the diode 10B and the junction field effect transistor 10C can withstand a reverse blocking voltage of 650V and a forward current of 17mA. In addition, the recovery time required for the diode 10B to change from the on state to the off state may be between 10 nsec and 50 nsec.

[0090] Continue to refer to Figure 1 , the junction field effect transistor 10C may include a junction below the gate active region, which can apply an electric field as a gate terminal. The junction field effect transistor 10C can be designed to be a depletion mode (normally open and conducting state at a gate voltage of 0V), or can be designed to be an enhancement mode (normally off state at a gate voltage of 0V). During the operation of the junction field effect transistor 10C, current flows from the source terminal through the region below the gate terminal to the drain terminal. It should be understood that the operation of the junction field effect transistor 10C is opposite to the operation of the metal-oxide semiconductor field-effect transistor (MOSFET). For example, as the gate voltage of the junction field effect transistor 10C increases, the depletion region diffuses to clamp the conduction path to suppress the current. In the case of not integrating with the high-voltage junction boundary element 10A and the junction field effect transistor 10C, the junction field effect transistor 10C may have a circular design, such as having a drain center circle, and a gate ring, a source ring, and a body ring surrounding the drain center circle in sequence. Such a design can avoid the sharp edge effect, which can cause component failure. In addition, the circular design can also make the electric field distribution more uniform.

[0091] Figure 2 According to some embodiments of the present invention, Figure 1 A magnified schematic diagram of the marked area X. Figure 3is a schematic cross-sectional view of a high voltage device 10 according to some embodiments of the present invention. Figure 4 is a schematic cross-sectional view of a high voltage device 10 according to some embodiments of the present invention. It should be noted that: Figure 3 for Figure 2 The cross-sectional view obtained by the line segment A-A' is shown in FIG. Figure 4 for Figure 2 For simplicity, Figure 2 Only the layout of the high voltage junction boundary element 10A, the diode 10B, and all active regions (eg, doped regions) in the junction field effect transistor 10C are shown. Line segment AA' crosses the diode 10B and the junction field effect transistor 10C, while line segment BB' crosses the high voltage junction boundary element 10A.

[0092] Reference Figures 2 to 4 The high voltage device 10 may include a substrate 100, a buried layer 220, a buried layer 240, a buried layer 260, an epitaxial layer 300, a conductive structure 470, an isolation structure 500a, an isolation structure 500b, an isolation structure 500c, an isolation structure 500d, an isolation structure 500e, an isolation structure 500f, an isolation structure 500g, an isolation structure 500h, an isolation structure 500i, an isolation structure 500j, an isolation structure 500k, an interlayer dielectric (ILD) layer 600, a guide hole 620, a guide hole 640, a guide hole 660, a guide hole 670, a guide hole 680, a metal layer 720, a metal layer 740, an inter-metal dielectric (ILD) layer 600, and a conductive layer 470. dielectric, IMD) layer 800, guide via 820, guide via 830, guide via 840, guide via 850, guide via 860, guide via 880, metal layer 920, metal layer 940, and metal layer 960.

[0093] In some embodiments, epitaxial layer 300 may include well 302, high voltage well 320, deep well 340, high voltage well 360, deep well 380, and doped region 460. High voltage well 320 may include well 322 and well 324. Deep well 340 may include well 342. High voltage well 360 may include well 362 and doped region 450. Deep well 380 may include well 382. Well 322 may include doped region 410. Well 324 may include doped region 420. Well 342 may include doped region 430. Well 362 may include doped region 440. Well 302 may include doped region 480. Well 382 may include doped region 490. It is worth noting that substrate 100, epitaxial layer 300, interlayer dielectric layer 600, and intermetallic dielectric layer 800 may be arranged across high voltage junction boundary element 10A, diode 10B, and junction field effect transistor 10C.

[0094] Reference Figure 2, the high voltage junction boundary element 10A may include a doped region 440, a doped region 450, a conductive structure 470, and a doped region 490. The diode 10B may include a doped region 410, a doped region 420, a doped region 430, and a doped region 440. The junction field effect transistor 10C may include a doped region 460 and a doped region 480. It is worth noting that the doped region 420 surrounds the doped region 410, the doped region 430 surrounds the doped region 420, and the doped region 440 surrounds the doped region 430. Furthermore, one side of the doped region 440 extends outward to form a loop. In other words, the doped region 440 crosses the high voltage junction boundary element 10A and the diode 10B, and is in direct contact with the low voltage region 10A-2.

[0095] In a conventional circuit, the doped region 490 crosses the high voltage junction boundary element 10A and the junction field effect transistor 10C, and is adjacent to the high voltage region 10A-1. According to the circuit design specification, the doped region 490 in the section of the high voltage junction boundary element 10A (e.g., the peripheral doped region) needs to be separated from the conductive structure 470 by a distance D1 in the horizontal direction, and the doped region 490 in the section of the junction field effect transistor 10C (e.g., the drain doped region) needs to be separated from the doped region 480 by a distance D2 in the horizontal direction. Since the positions of the conductive structure 470 and the doped region 480 are different, and the distance D1 is different from the distance D2, the section of the doped region 490 in the high voltage junction boundary element 10A and the section in the junction field effect transistor 10C cannot be aligned. As mentioned previously, the doped region 490 needs to have a curved profile to connect the section in the high voltage junction boundary element 10A and the section in the junction field effect transistor 10C. However, according to the results of the hot spot analysis, the corners of the doped region 490 and the corresponding metal layer 960 above are prone to gather too high an electric field, resulting in a decrease in the breakdown voltage. Generally speaking, due to reliability considerations, the overall breakdown voltage of the device needs to be about 20% higher than the predetermined operating voltage. The inventors found that even if the corner profile is designed to have a larger radius of curvature to alleviate the concentration of the electric field, it is still insufficient to improve the breakdown voltage.

[0096] According to some embodiments of the present invention, the doped region 490 may be removed from the junction field effect transistor 10C to avoid electric field crowding. The doped region 490 may be removed from the junction field effect transistor 10C so that the curved contour may be omitted. For illustrative purposes, the portion of the doped region 490 removed is indicated by a dashed line (eg, Figure 2 Even if the loop of the original doped region 490 is cut off in the section of the junction field effect transistor 10C, the deep well 380 (as shown) can be used to Figure 3 to Figure 4More specifically, the deep well 380 is used to establish an electrical connection between the two ends of the doped region 490 that are cut off. When the electric field crowding is effectively alleviated, the overall breakdown voltage of the high voltage device 10 can be increased.

[0097] Reference Figure 3 to Figure 4 The substrate 100 may be, for example, a wafer or a die, but the present invention is not limited thereto. In some embodiments, the substrate 100 may be a semiconductor substrate, such as a silicon (Si) substrate. In addition, in some embodiments, the semiconductor substrate may also be: an elemental semiconductor, including germanium (Ge); a compound semiconductor, including gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); an alloy semiconductor, including silicon germanium (SiGe) alloy, gallium arsenide phosphide (GaAsP) alloy, aluminum indium arsenide (AlInAs) alloy, aluminum gallium arsenide (AlGaAs) alloy, gallium indium arsenide (GaAs) alloy, and / or indium antimonide (InSb) alloy. arsenide (GaInAs) alloy, gallium indium phosphide (GaInP) alloy, and / or gallium indium arsenide phosphide (GaInAsP) alloy, or a combination thereof.

[0098] In other embodiments, the substrate 100 may also be a semiconductor on insulator (SOI) substrate. The semiconductor on insulator substrate may include a base plate, a buried oxide (BOX) layer disposed on the base plate, and a semiconductor layer disposed on the buried oxide layer. In a specific embodiment of the present invention, the substrate 100 may be a first conductivity type (P type) with a doping concentration between 1×1014 cm-3 and 3×1014 cm-3.

[0099] In other embodiments, the substrate 100 may include an isolation structure (not shown) to define the active region and electrically isolate the active region components in or on the substrate 100, but the embodiments of the present invention are not limited thereto. The isolation structure may include a deep trench isolation (DTI) structure, a shallow trench isolation (STI) structure, or a local oxidation of silicon (LOCOS) structure. In some embodiments, forming the isolation structure may include, for example, forming an insulating layer on the substrate 100, selectively etching the insulating layer and the substrate 100 to form a trench extending from the top surface of the substrate 100 to a position in the substrate 100, wherein the trench is located between adjacent active regions. Next, forming the isolation structure may include growing a liner rich in nitrogen (such as silicon oxynitride (SiON) or other similar materials) along the trench, and then filling the trench with an insulating material (such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride, or other similar materials) by a deposition process. Afterwards, an annealing process is performed on the insulating material in the trench, and a planarization process (such as chemical mechanical polishing (CMP)) is performed on the substrate 100 to remove excess insulating material so that the insulating material in the trench is flush with the top surface of the substrate 100 .

[0100] Continue to refer to Figure 3 to Figure 4 , an epitaxial layer 300 is formed on the substrate 100. According to some embodiments of the present invention, the epitaxial layer 300 may have a second conductivity type (N type), and its doping concentration is between 1.13×1015cm-3 and 2.30×1015cm-3. In a specific embodiment of the present invention, the substrate 100 and the epitaxial layer 300 may have different conductivity types, and the doping concentration of the substrate 100 is less than the doping concentration of the epitaxial layer 300. The material of the epitaxial layer 300 may include silicon, silicon germanium, silicon carbide, other similar materials, or a combination thereof. The thickness of the epitaxial layer 300 may be between 3μm and 7μm. The epitaxial layer 300 may be formed by an epitaxial process, and its epitaxial process may include metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), molecular beam epitaxy (MBE), other suitable methods, or a combination thereof.

[0101] Reference Figure 3 to Figure 4 , the high voltage device 10 includes a buried layer 220, a buried layer 240, and a buried layer 260 disposed in a substrate 100. In some embodiments, the buried layer 220, the buried layer 240, and the buried layer 260 may be located in a diode 10B, a junction field effect transistor 10C, and a high voltage junction boundary element 10A, respectively. The buried layer 220 may directly contact a high voltage well 320 and a deep well 340 of an epitaxial layer 300, and the buried layer 240 and the buried layer 260 may directly contact the epitaxial layer 300. According to some embodiments of the present invention, the buried layer 220 helps to reduce the leakage current from the anode end of the diode 10B to the substrate 100, the buried layer 240 may increase the channel space of the junction field effect transistor 10C to withstand a higher current, and the buried layer 260 may form an N-type substrate of the high voltage region 10A-1. It is worth noting that a larger channel space will require a higher pinch-off voltage to close the channel. The buried layer 220, the buried layer 240, and the buried layer 260 have a second conductivity type (N type). The doping concentration of the buried layer 220, the buried layer 240, and the buried layer 260 may be between 6.4×1016cm-3 and 9.6×1016cm-3. The vertical dimensions of the buried layer 220, the buried layer 240, and the buried layer 260 may be between 1 μm and 2 μm. The lateral dimensions of the buried layer 220 may cross the high voltage well 320 and the deep well 340 of the epitaxial layer 300. The lateral dimensions of the buried layer 240 may be similar to the lateral dimensions of the well 302. The lateral dimensions of the buried layer 260 may cross the entire high voltage region 10A-1.

[0102] The method for forming the buried layer 220, the buried layer 240, and the buried layer 260 may include, before forming the epitaxial layer 300, ion implanting N-type dopants (such as phosphorus or arsenic) into the substrate 100, performing a heat treatment to drive the implanted ions into the substrate 100, and then forming the epitaxial layer 300 on the substrate 100. In some embodiments, since the epitaxial layer 300 is formed under high temperature conditions, the implanted ions will diffuse into the epitaxial layer 300. Figure 3 to Figure 4 As shown, the buried layer 220, the buried layer 240, and the buried layer 260 are located near the interface between the substrate 100 and the epitaxial layer 300, and have a portion in the substrate 100 and another portion in the epitaxial layer 300. In other words, the buried layer 220, the buried layer 240, and the buried layer 260 may extend upward from the interface between the substrate 100 and the epitaxial layer 300.

[0103] Continue to refer to Figure 3 to Figure 4, a high-voltage well 320, a deep well 340, a high-voltage well 360, and a deep well 380 may be formed in the epitaxial layer 300. In some embodiments, the high-voltage well 320 and the deep well 340 may be located in the diode 10B, the high-voltage well 360 may be located in the high-voltage junction boundary element 10A and the diode 10B, and the deep well 380 may be located in the high-voltage junction boundary element 10A and the junction field effect transistor 10C. It should be understood that, from the top view, the deep well 340 surrounds the high-voltage well 320, so the deep well 340 in the cross-sectional schematic diagram is arranged on both sides of the high-voltage well 320. Similarly, from the top view, the high-voltage well 360 surrounds the deep well 340, so the high-voltage well 360 in the cross-sectional schematic diagram is arranged on both sides of the periphery of the deep well 340. The high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380 may extend vertically from the upper surface of the epitaxial layer 300 to the interface between the epitaxial layer 300 and the substrate 100, or to the interface between the epitaxial layer 300 and the buried layer 220. According to some embodiments of the present invention, the high-voltage well 320 and the high-voltage well 360 may be of the first conductivity type (P type), and the deep well 340 and the deep well 380 may be of the second conductivity type (N type). Since the high-voltage well 320 of the first conductivity type is surrounded by the deep well 340 of the second conductivity type, and the deep well 340 is surrounded by the high-voltage well 360 of the first conductivity type, a parasitic bipolar (PNP) junction is formed.

[0104] The high voltage well 320, the deep well 340, the high voltage well 360, and the deep well 380 may be formed by, for example, ion implantation and / or diffusion processes. In alternative embodiments, instead of using ion implantation and / or diffusion processes, the high voltage well 320, the deep well 340, the high voltage well 360, and the deep well 380 may be doped in situ during the growth of the epitaxial layer 300. In other embodiments, both in situ and implantation doping may be used together.

[0105] In some embodiments, the high voltage well 320 may be located above the buried layer 220. More specifically, the high voltage well 320 may be in direct contact with the buried layer 220 in the vertical direction. The doping concentration of the high voltage well 320 may be between 1.6×1016cm-3 and 2.4×1016cm-3. As mentioned previously, the high voltage well 320 may include a well 322 and a well 324. It should be understood that from the top view, the well 324 surrounds the well 322, so the well 324 in the cross-sectional schematic diagram is disposed on both sides of the well 322.

[0106] In some embodiments, the deep well 340 may laterally surround the high-voltage well 320 and may be partially located above the buried layer 220. More specifically, the deep well 340 may be in direct contact with the buried layer 220 in the vertical direction, and the deep well 340 may be between the high-voltage well 320 and the high-voltage well 360 in the horizontal direction. The doping concentration of the deep well 340 may be between 3.6×1016cm-3 and 5.4×1016cm-3. As mentioned previously, the deep well 340 may include a well 342. It should be understood that, from the top view, the well 342 surrounds the well 324, so the well 342 in the cross-sectional schematic diagram is disposed on both sides of the periphery of the well 324.

[0107] In some embodiments, the high voltage well 360 may laterally surround the deep well 340. Furthermore, the high voltage well 360 may cross the high voltage junction boundary element 10A and the diode 10B. The doping concentration of the high voltage well 360 may be between 1.6×1016cm-3 and 2.4×1016cm-3. As mentioned previously, the high voltage well 360 may include a well 362. It should be understood that from the top view, the well 362 surrounds the well 342, so the well 362 of the cross-sectional schematic diagram is disposed on both sides of the periphery of the well 342.

[0108] In some embodiments, the deep well 380 may traverse the high voltage junction boundary element 10A and the junction field effect transistor 10C. From a top view, the deep well 380 may be a loop that laterally surrounds and directly contacts the high voltage region 10A-1. The doping concentration of the deep well 380 may be between 3.6×1016cm-3 and 5.4×1016cm-3. As previously mentioned, the deep well 380 may include a well 382. More specifically, the deep well 380 includes the well 382 and the doped region 490 in the well 382 in the section of the high voltage junction boundary element 10A, while the deep well 380 includes only the well 382 in the section of the junction field effect transistor 10C.

[0109] Reference Figure 3 , a well 302 may be formed in the epitaxial layer 300. In some embodiments, the well 302 may be located in the junction field effect transistor 10C. The well 302 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300 and may overlap the buried layer 240. The well 302 may be of the first conductivity type (P-type). According to some embodiments of the present invention, the well 302 may define the size of the channel region of the junction field effect transistor 10C. The doping concentration of the well 302 may be between 9.6×1017cm-3 and 1.4×1018cm-3. The thickness of the well 302 may be between 0.2μm and 0.6μm. The lateral size of the well 302 may be between 18μm and 22μm. The method of forming the well 302 may be similar to the method of forming the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated here.

[0110] Reference Figure 3 , a well 322 and a well 324 may be provided in the high-voltage well 320. The well 322 and the well 324 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. In the present embodiment, the well 322 and the well 324 are laterally spaced apart from each other. According to some embodiments of the present invention, the well 322 may be of the second conductivity type (N type), and the well 324 may be of the first conductivity type (P type). The formation method of the well 322 and the well 324 may be similar to the formation method of the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated here.

[0111] In some embodiments, the well 322 may overlap the buried layer 220. According to some embodiments of the present invention, the well 322 may constitute a second conductivity type (N-type) semiconductor layer of the diode 10B. The doping concentration of the well 322 may be between 4.5×1016cm-3 and 6.8×1016cm-3. The thickness of the well 322 may be between 1 μm and 2 μm.

[0112] In some embodiments, the well 324 may overlap the buried layer 220. According to some embodiments of the present invention, the well 324 may constitute a first conductivity type (P-type) semiconductor layer of the diode 10B. The doping concentration of the well 324 may be between 3.6×1016cm-3 and 5.4×1016cm-3. The thickness of the well 324 may be between 1 μm and 2 μm.

[0113] Continue to refer to Figure 3 , a well 342 may be provided in the deep well 340. The well 342 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300, and may partially overlap with the buried layer 220. The well 342 may be of the second conductivity type (N-type). According to some embodiments of the present invention, the well 342 may enhance the isolation effect of the deep well 340 in the horizontal direction. The doping concentration of the well 342 may be between 4.5×1016cm-3 and 6.8×1016cm-3. The thickness of the well 342 may be between 1μm and 2μm. The method for forming the well 342 may be similar to the method for forming the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated here.

[0114] Reference Figure 3 to Figure 4, a well 362 and a doped region 450 may be provided in the high-voltage well 360. The well 362 and the doped region 450 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. In the present embodiment, the well 362 and the doped region 450 are laterally spaced apart from each other. According to some embodiments of the present invention, the well 362 and the doped region 450 may both be of the first conductivity type (P type). The formation method of the well 362 and the doped region 450 may be similar to the formation method of the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated herein.

[0115] In some embodiments, the well 362 may traverse the high voltage junction boundary element 10A and the diode 10B. According to some embodiments of the present invention, the well 362 may reduce the series resistance of the high voltage well 360. The doping concentration of the well 362 may be between 3.6×1016cm-3 and 5.4×1016cm-3. The thickness of the well 362 may be between 1 μm and 2 μm.

[0116] In some embodiments, the doped region 450 may be one of the annular components of the high voltage junction boundary element 10A. According to some embodiments of the present invention, the doped region 450 and the doped region 440 may be a common ground terminal of the high voltage junction boundary element 10A. The doping concentration of the doped region 450 may be between 1.1×1020 cm-3 and 1.7×1020 cm-3. The thickness of the doped region 450 may be between 0.18 μm and 0.22 μm.

[0117] Continue to refer to Figure 3 to Figure 4 , a well 382 may be provided in the deep well 380. The well 382 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The well 382 may be of the second conductivity type (N type). According to some embodiments of the present invention, the well 382 may reduce the series resistance of the deep well 380. The doping concentration of the well 382 may be between 4.5×1016cm-3 and 6.8×1016cm-3. The thickness of the well 382 may be between 1μm and 2μm. The method for forming the well 382 may be similar to the method for forming the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated here.

[0118] Referring to FIGS. 2 and 3 , a doped region 410 may be provided in the well 322. The doped region 410 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 410 may be of the second conductivity type (N-type). According to some embodiments of the present invention, the doped region 410 may serve as the cathode terminal of the diode 10B and may be electrically coupled to the junction field effect transistor 10C through the metal layer 920. The doping concentration of the doped region 410 may be between 4.0×1020 cm-3 and 6.0×1020 cm-3. The thickness of the doped region 410 may be between 0.09 μm and 0.11 μm. The method of forming the doped region 410 may be similar to the method of forming the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated herein.

[0119] Continuing to refer to FIGS. 2 and 3 , a doped region 420 may be provided in the well 324. The doped region 420 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. As previously mentioned, the doped region 420 surrounds the doped region 410. The doped region 420 may be of the first conductivity type (P-type). According to some embodiments of the present invention, the doped region 420 may serve as the anode terminal of the diode 10B. The doping concentration of the doped region 420 may be between 1.1×1020 cm-3 and 1.7×1020 cm-3. The thickness of the doped region 420 may be between 0.18 μm and 0.22 μm. The method of forming the doped region 420 may be similar to the method of forming the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated herein.

[0120] Referring to FIGS. 2 and 3 , a doped region 430 may be provided in the well 342. The doped region 430 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. As previously mentioned, the doped region 430 surrounds the doped region 420. The doped region 430 may be of the second conductivity type (N-type). According to some embodiments of the present invention, the doped region 430 may also serve as the anode terminal of the diode 10B and may be electrically connected to the doped region 420 through the metal layer 720. The doping concentration of the doped region 430 may be between 4.0×1020 cm-3 and 6.0×1020 cm-3. The thickness of the doped region 430 may be between 0.09 μm and 0.11 μm. The method of forming the doped region 430 may be similar to the method of forming the high voltage well 320, the deep well 340, the high voltage well 360, and the deep well 380, and the details thereof will not be repeated herein.

[0121] Reference Figures 2 to 4, a doped region 440 may be provided in the well 362. The doped region 440 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. As previously mentioned, the doped region 440 surrounds the doped region 430 and crosses the high-voltage junction boundary element 10A and the diode 10B. The doped region 440 may be of the first conductivity type (P-type). According to some embodiments of the present invention, since the doped region 440, the well 362, the high-voltage well 360, and the substrate 100 are all of the first conductivity type (P-type), the high-voltage device 10 may be electrically grounded from the top or from the bottom, and the doped region 440 may serve as the main body of the substrate end. The doping concentration of the doped region 440 may be between 1.1×1020cm-3 and 1.7×1020cm-3. The thickness of the doped region 440 may be between 0.18μm and 0.22μm. The method of forming the doped region 440 may be similar to the method of forming the high-voltage well 320 , the deep well 340 , the high-voltage well 360 , and the deep well 380 , and the details thereof will not be repeated herein.

[0122] Referring to FIGS. 2 and 3 , a doped region 460 may be provided in the epitaxial layer 300 . The doped region 460 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300 . The doped region 460 may be of the second conductivity type (N-type). According to some embodiments of the present invention, the doped region 460 may serve as a source terminal of the junction field effect transistor 10C and may be electrically coupled to the diode 10B through the metal layer 920 . Since the source terminal is of the second conductivity type (N-type), the junction field effect transistor 10C may be of the second conductivity type (N-type). The doping concentration of the doped region 460 may be between 4.0×1020 cm-3 and 6.0×1020 cm-3. The thickness of the doped region 460 may be between 0.09 μm and 0.11 μm. The method of forming the doped region 460 may be similar to the method of forming the high-voltage well 320 , the deep well 340 , the high-voltage well 360 , and the deep well 380 , and the details thereof will not be repeated herein.

[0123] Reference Figure 2 and Figure 4 , a conductive structure 470 may be disposed on the epitaxial layer 300. The conductive structure 470 may extend horizontally from the high voltage well 360 to the epitaxial layer 300. The conductive structure 470 is another ring-shaped component of the high voltage junction boundary element 10A. According to some embodiments of the present invention, the conductive structure 470 may modulate the electric field below it. The thickness of the conductive structure 470 may be between 3.5 μm and 4.0 μm.

[0124] The material of the conductive structure 470 may include amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides (such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), or other similar materials), metal silicides (such as nickel silicide (NiSi), cobalt silicide (CoSi), tantalum silicon nitride (TaSiN), or other similar materials), metal carbides (such as tantalum carbide (TaC), tantalum carbonitride (TaCN), or other similar materials), metal oxides, and metals. The metal may include cobalt (Co), ruthenium (Ru), aluminum (Al), palladium (Pd), platinum (Pt), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silver (Ag), gold (Au), nickel (Ni), manganese (Mn), zirconium (Zr), other similar materials, combinations thereof, or multiple layers thereof. The conductive structure 470 may be formed by physical vapor deposition (PVD), atomic layer deposition, plating, other suitable processes, or combinations thereof.

[0125] Referring to FIGS. 2 and 3 , a doped region 480 may be provided in the well 302. The doped region 480 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. The doped region 480 may be of the first conductivity type (P-type). According to some embodiments of the present invention, the doped region 480 may serve as a gate terminal of the junction field effect transistor 10C. The doping concentration of the doped region 480 may be between 1.1×1020 cm-3 and 1.7×1020 cm-3. The thickness of the doped region 480 may be between 0.18 μm and 0.22 μm. The method for forming the doped region 480 may be similar to the method for forming the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated herein.

[0126] Reference Figure 2 and Figure 4, a doped region 490 may be provided in the well 382. The doped region 490 may extend vertically from the upper surface of the epitaxial layer 300 into the epitaxial layer 300. As mentioned previously, the original loop of the doped region 490 is cut off in the section of the junction field effect transistor 10C, and only the section of the doped region 490 in the high-voltage junction boundary element 10A is retained. The doped region 490 may be of the second conductivity type (N-type). According to some embodiments of the present invention, the doped region 490 may reduce the contact resistance of the deep well 380. The doping concentration of the doped region 490 may be between 4.0×1020cm-3 and 6.0×1020cm-3. The thickness of the doped region 490 may be between 0.09μm and 0.11μm. The method for forming the doped region 490 may be similar to the method for forming the high-voltage well 320, the deep well 340, the high-voltage well 360, and the deep well 380, and the details thereof will not be repeated here.

[0127] Reference Figure 3 to Figure 4 , isolation structures 500a, 500b, 500c, 500d, 500e, 500f, 500g, 500h, 500i, 500j, and 500k may be formed on the epitaxial layer 300. Specifically, since the manufacturing process thereof involves high temperature treatment, the isolation structures 500a, 500b, 500c, 500d, 500e, 500f, 500g, 500h, 500i, 500j, and 500k are partially embedded in the epitaxial layer 300. According to some embodiments of the present invention, isolation structure 500a, isolation structure 500b, isolation structure 500c, isolation structure 500d, isolation structure 500e, isolation structure 500f, isolation structure 500g, isolation structure 500h, isolation structure 500i, isolation structure 500j, and isolation structure 500k may be drift oxide (DOX) to isolate various conductive components to prevent electrical short circuit in the high-voltage device 10 during operation.

[0128] like Figure 3As shown, the doped region 440 may be laterally located between the isolation structure 500a and the isolation structure 500b in the section of the diode 10B. The isolation structure 500b may laterally isolate the doped region 440 from the doped region 430. The doped region 430 may be laterally located between the isolation structure 500b and the isolation structure 500c. The doped region 420 may be laterally located between the isolation structure 500c and the isolation structure 500d. The doped region 410 may be laterally surrounded by the isolation structure 500d. It is worth noting that, from the top view, the isolation structure 500c surrounds the isolation structure 500d, the isolation structure 500b surrounds the isolation structure 500c, and the isolation structure 500a surrounds the isolation structure 500b. The doped region 460 of the junction field effect transistor 10C may be laterally located between the isolation structure 500a and the isolation structure 500e. The isolation structure 500e may laterally isolate the doped region 460 from the doped region 480. The doped region 480 may be laterally located between the isolation structure 500e and the isolation structure 500f. In a conventional arrangement, the isolation structure 500f should be located between the doped region 480 and the doped region 490. Since the loop of the doped region 490 is interrupted in the section of the junction field effect transistor 10C, the isolation structure 500f extends across the entire deep well 380.

[0129] like Figure 4 As shown, the doped region 440 may be laterally located between the isolation structure 500g and the isolation structure 500h in the section of the high-voltage junction boundary element 10A. The isolation structure 500h may laterally isolate the doped region 440 from the doped region 450. The doped region 450 may be laterally located between the isolation structure 500h and the isolation structure 500i. The isolation structure 500i may laterally isolate the doped region 450 from the conductive structure 470. The conductive structure 470 may be laterally located between the isolation structure 500i and the isolation structure 500j. The isolation structure 500j may laterally isolate the conductive structure 470 from the doped region 490 in the section of the high-voltage junction boundary element 10A. As previously mentioned, the doped region 490 has a spacing D1 between the section of the high-voltage junction boundary element 10A and the conductive structure 470. The doped region 490 may laterally be located between the isolation structure 500j and the isolation structure 500k in the section of the high-voltage junction boundary element 10A.

[0130] In some embodiments, the isolation structures 500a, 500b, 500c, 500d, 500e, 500f, 500g, 500h, 500i, 500j, and 500k may be formed by silicon oxide (SiO), which may be silicon local oxidation isolation structures formed by thermal oxidation. In other embodiments, the isolation structures 500a, 500b, 500c, 500d, 500e, 500f, 500g, 500h, 500i, 500j, and 500k may be shallow trench isolation structures formed by etching, oxidation, and deposition processes.

[0131] Reference Figure 3 to Figure 4 After forming the isolation structures 500a, 500b, 500c, 500d, 500e, 500f, 500g, 500h, 500i, 500j, and 500k, an interlayer dielectric layer 600 may be formed on the epitaxial layer 300. In some embodiments, the interlayer dielectric layer 600 may cover the epitaxial layer 300, the conductive structure 470, the isolation structures 500a, 500b, 500c, 500d, 500e, 500f, 500g, 500h, 500i, 500j, and 500k. In addition to providing mechanical protection and insulation to the components below, the interlayer dielectric layer 600 may also isolate conductive materials at different levels. The material of the interlayer dielectric layer 600 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon oxynitrocarbide (SiOxNyC1-xy, where x and y are in the range of 0 to 1), tetraethoxysilane (tetra ethyl ortho silicate, TEOS), undoped silicate glass, doped silicon oxide (such as boron-doped phospho-silicate glass (BPSG), fused silica glass (FSG), phospho-silicate glass (PSG), boron-doped silicate glass (BSG), or other similar materials), low dielectric constant (low-k) dielectric material, or other suitable dielectric materials.

[0132] The thickness of the interlayer dielectric layer 600 may be between 1000 μm and 1200 μm. The interlayer dielectric layer 600 may be formed by spin-on coating, chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), flowable chemical vapor deposition (FCVD), sub-atmospheric chemical vapor deposition (SACVD), other similar methods, or a combination thereof. Then, the interlayer dielectric layer 600 may be subjected to a planarization process (such as chemical mechanical polishing) to make the interlayer dielectric layer 600 have a flat top surface.

[0133] Continue to refer to Figure 3 to Figure 4 , guide holes 620, guide holes 640, guide holes 660, guide holes 670, and guide holes 680 may be formed to pass through the interlayer dielectric layer 600. The guide holes 620, guide holes 640, guide holes 660, guide holes 670, and guide holes 680 may respectively physically contact the doped regions 420, the doped regions 430, the doped regions 440, the doped regions 450, and the doped regions 490. In addition, metal layers 720 and metal layers 740 may be formed on the interlayer dielectric layer 600. In some embodiments, the metal layer 720 is electrically coupled to the doped regions 420 and the doped regions 430 through the guide holes 620 and the guide holes 640, respectively, and the metal layer 740 is electrically coupled to the doped regions 440, the doped regions 450, and the doped regions 490 through the guide holes 660, the guide holes 670, and the guide holes 680, respectively. According to some embodiments of the present invention, metal layer 720 can be used as the anode terminal of diode 10B, and metal layer 740 can be used as the electrical ground of diode 10B. In addition, metal layer 740 can be used as a high-voltage power supply contact of high-voltage area 10A-1 in the section of high-voltage junction boundary element 10A. Via 620, via 640, via 660, via 670, via 680, metal layer 720, and metal layer 740 can be integrally formed and thus include the same material.

[0134] In some embodiments, the metal layer 740 may further include a spiral structure 745. The spiral structure 745 may be located above the isolation structure 500j. From the top view, the spiral structure 745 may be one of the ring-shaped components of the high-voltage junction boundary element 10A and extend in a spiral form. According to some embodiments of the present invention, the spiral structure 745 may serve as a plurality of field plates to manipulate the surface electric field of the semiconductor layer below. The width of each field plate component may be between 4 μm and 5 μm.

[0135] In some embodiments, the materials and forming methods of the guide holes 620, guide holes 640, guide holes 660, guide holes 670, guide holes 680, metal layer 720, and metal layer 740 may be similar to the materials and forming methods of the conductive structure 470, and the details will not be repeated here. First, openings may be formed in the interlayer dielectric layer 600 to correspond to the doped regions 420, doped regions 430, doped regions 440, doped regions 450, and doped regions 490. Then, the above materials may be blanket deposited on the interlayer dielectric layer 600 by the above-mentioned suitable deposition process. In addition to being formed on the surface of the interlayer dielectric layer 600, the above materials are also filled into the openings to form the guide holes 620, guide holes 640, guide holes 660, guide holes 670, and guide holes 680. The metal layer 720 and the metal layer 740 (including the spiral structure 745) may be formed by patterning the deposited film layer by a photolithography process followed by an etching process. The photolithography process may include applying photoresist, soft baking, exposure, post-exposure baking, development, other similar methods, or a combination thereof. The etching process may include dry etching, wet etching, other similar methods, or a combination thereof. The thickness of the metal layer 720 and the metal layer 740 (including the spiral structure 745) may be between 0.4 μm and 0.5 μm.

[0136] Reference Figure 3 to Figure 4 , an intermetallic dielectric layer 800 may be formed on the interlayer dielectric layer 600. In some embodiments, the intermetallic dielectric layer 800 may cover the interlayer dielectric layer 600, the metal layer 720, and the metal layer 740. According to some embodiments of the present invention, in addition to providing mechanical protection and electrical insulation for the underlying structure, the intermetallic dielectric layer 800 may also separate different levels of conductive materials. The thickness of the intermetallic dielectric layer 800 may be between 500 μm and 700 μm. The material and formation method of the intermetallic dielectric layer 800 may be similar to the material and formation method of the interlayer dielectric layer 600, and the details will not be repeated here.

[0137] Continue to refer to Figure 3 to Figure 4, guide holes 820, guide holes 830, guide holes 840, guide holes 850, guide holes 860, and guide holes 880 may be formed through the intermetallic dielectric layer 800. It is worth noting that guide holes 820, guide holes 840, and guide holes 860 further penetrate the interlayer dielectric layer 600 to physically contact the doped regions 410, 460, and 480, respectively. Guide holes 830, guide holes 850, and guide holes 880 physically contact the metal layer 740. In addition, metal layers 920, metal layers 940, and metal layers 960 may be formed on the intermetallic dielectric layer 800. In some embodiments, metal layer 920 is electrically coupled to doped region 410 and doped region 460 through via 820 and via 840, respectively, metal layer 940 is electrically coupled to doped region 480 through via 860, and metal layer 960 corresponds to via 660, via 670, and via 680 through via 830, via 850, and via 880, respectively.

[0138] According to some embodiments of the present invention, metal layer 920 can serve as the cathode terminal of diode 10B and be electrically coupled to junction field effect transistor 10C, metal layer 940 can serve as the gate terminal of junction field effect transistor 10C, and metal layer 960 can serve as the high voltage contact of high voltage junction boundary element 10A. The thickness of metal layer 920, metal layer 940, and metal layer 960 can be between 0.8 μm and 3.0 μm. In addition, metal layer 960 can further include a spiral structure 965. Spiral structure 965 can be located above spiral structure 745. The features of spiral structure 965 can be similar to those shown in spiral structure 745, and the details will not be repeated here. Since the design rules of spiral structure 965 are different from the design rules of spiral structure 745, the optimized spiral structure 965 can have a different number of turns (or the number of field plate components). Furthermore, the pitch of the spiral structure 745 may be between 0.5um and 0.8um, while the pitch of the spiral structure 965 is different from the spiral structure 745 according to different thicknesses. The materials and formation methods of the guide holes 820, guide holes 830, guide holes 840, guide holes 850, guide holes 860, guide holes 880, metal layers 920, metal layers 940, and metal layers 960 (including the spiral structure 965) may be similar to the materials and formation methods of the guide holes 620, guide holes 640, guide holes 660, guide holes 670, guide holes 680, metal layers 720, and metal layers 740, and the details thereof will not be repeated herein.

[0139] The high-voltage device of the present invention integrates a high-voltage junction boundary element, a buried bootstrap diode with an isolation component, and a junction field effect transistor. However, the difference in structure makes the overall circuit design relatively complicated, thereby reducing the breakdown voltage of the high-voltage device. For example, when two active areas need to be extended to have a curved profile to connect into a loop, the metal layer above the corner of the loop is prone to accumulate excessive electric fields due to the change in size, thereby reducing the breakdown voltage. The high-voltage device of the present invention removes the section where the loop needs to have a corner to avoid electric field crowding. Even if a part of the loop is cut off, the conduction of the loop can be maintained by other components (such as a well). When the electric field crowding is effectively alleviated, the overall breakdown voltage of the high-voltage device can be improved.

[0140] The features of several embodiments are summarized above so that those skilled in the art can better understand the concepts of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equivalent structures do not deviate from the spirit and scope of the present invention, and various changes, substitutions and replacements can be made without violating the spirit and scope of the present invention.

Claims

1. A high-voltage device, characterized in that: include: A diode; a junction field effect transistor adjacent to the diode and electrically coupled to the diode; a high-voltage junction boundary element, electrically connected to the diode and the junction field effect transistor, the high-voltage junction boundary element being in a ring shape, defining a high-voltage region and a low-voltage region inside and outside the ring shape, respectively; and A first deep well, surrounding the high-voltage region, comprising: a first section disposed in the high-voltage junction boundary element, wherein the first section includes a well and a doped region in the well; and A second section is disposed in the junction field effect transistor, wherein the second section only includes the well.

2. The high voltage device according to claim 1, characterized in that: Also includes: a substrate, disposed across the high-voltage junction boundary element, the diode, and the junction field effect transistor, and having a first conductivity type; as well as An epitaxial layer is disposed across the high voltage junction boundary element, the diode, and the junction field effect transistor and on the substrate, wherein the epitaxial layer has a second conductivity type different from the first conductivity type.

3. The high voltage device according to claim 2, characterized in that: The first deep well is disposed in the epitaxial layer and has the second conductivity type.

4. The high voltage device according to claim 2, characterized in that: The diode further comprises: a first high-voltage well, disposed in the epitaxial layer and having the first conductivity type; a second deep well disposed in the epitaxial layer and laterally surrounding the first high-voltage well and having the second conductivity type; and A second high-voltage well is disposed in the epitaxial layer and laterally surrounds the second deep well and has the first conductivity type.

5. The high voltage device according to claim 4, characterized in that: The diode further includes a first buried layer disposed in the substrate, wherein the first buried layer directly contacts the first high-voltage well and the second deep well.

6. The high voltage device according to claim 4, characterized in that: The first high-voltage well includes a first doped region and a second doped region, the second deep well includes a third doped region, and the second high-voltage well includes a fourth doped region.

7. The high voltage device according to claim 6, characterized in that: The second doping region surrounds the first doping region, the third doping region surrounds the second doping region, and the fourth doping region surrounds the third doping region.

8. The high voltage device according to claim 7, characterized in that: The junction field effect transistor further comprises: a fifth doped region, disposed in the epitaxial layer and having the second conductivity type; a sixth doped region, disposed in the epitaxial layer and having the first conductivity type; and A second buried layer is disposed in the substrate and below the sixth doped region.

9. The high voltage device according to claim 8, characterized in that: Also includes: an interlayer dielectric layer disposed on the epitaxial layer; A first metal layer and a second metal layer are disposed on the interlayer dielectric layer; an intermetallic dielectric layer, covering the interlayer dielectric layer, the first metal layer, and the second metal layer; as well as A third metal layer and a fourth metal layer are disposed on the intermetallic dielectric layer.

10. The high voltage device according to claim 9, characterized in that The first metal layer is electrically coupled to the second doping region and the third doping region through a first guide hole and a second guide hole, respectively.

11. The high voltage device according to claim 9, characterized in that: The second metal layer is electrically coupled to the fourth doped region through a third guide hole.

12. The high voltage device according to claim 9, characterized in that: The third metal layer is electrically coupled to the first doped region and the fifth doped region through a fourth guide hole and a fifth guide hole, respectively.

13. The high voltage device according to claim 9, characterized in that: The fourth metal layer is electrically coupled to the sixth doped region through a sixth via.

14. A method for forming a high-voltage device, characterized in that: include: providing a substrate; forming an epitaxial layer on the substrate; forming a first high-voltage well, a first deep well surrounding the first high-voltage well, and a second high-voltage well surrounding the first deep well in a first region of the epitaxial layer; forming a first doped region and a second doped region surrounding the first doped region in the first high-voltage well; forming a third doped region in the first deep well, wherein the third doped region surrounds the second doped region; forming a fourth doped region in the second high-voltage well; forming a fifth doped region and a sixth doped region in a second region of the epitaxial layer, wherein the second region laterally adjoins the first region; Extending one side of the fourth doped region outward into a third region of the epitaxial layer to form a loop, wherein the second region is located within the loop; forming a second deep well in the loop, the second deep well extending along the inner side of the loop and crossing the second region; forming a seventh doped region in the second deep well, wherein the seventh doped region extends along a contour of the second deep well; as well as A portion of the seventh doped region in the second deep well that crosses the second region is cut off.

15. The method for forming a high voltage device according to claim 14, characterized in that: The first region, the second region, and the third region respectively define a diode, a junction field effect transistor, and a high-voltage junction boundary element.

16. The method for forming a high voltage device according to claim 14, characterized in that: The method also includes forming a first buried layer and a second buried layer in the substrate, wherein the first buried layer and the second buried layer extend into the first region and the second region of the epitaxial layer respectively.

17. The method for forming a high voltage device according to claim 14, characterized in that: The method also includes forming an eighth doped region and a conductive structure between the loop in the third region and the second deep well.

18. The method for forming a high-voltage device according to claim 17, characterized in that: There is a first distance between the conductive structure and the seventh doping region.

19. The method for forming a high voltage device according to claim 18, characterized in that: Before the portion of the seventh doping region crossing the second region is cut off, a second distance exists between the sixth doping region and the portion of the seventh doping region crossing the second region, and the second distance is different from the first distance.

20. The method for forming a high voltage device according to claim 17, characterized in that: The first doped region of the first region and the fifth doped region of the second region are electrically coupled through a metal layer.

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