Quantum dot-nanowire avalanche diode single-photon detector and preparation method thereof

Abstract

The invention relates to an avalanche diode single-photon detector and a preparation method thereof, in particular to a quantum dot-nanowire avalanche diode single-photon detector and a preparation method thereof, and solves the problems that an existing single-photon detector is low in detection efficiency and the preparation difficulty is large and the improvement effect is limited when an existing method is adopted for improvement. The detector comprises a detector N + substrate, a plurality of quantum dot-nanowire units, a passivation layer, a P-type electrode and an N-type electrode, wherein the quantum dot-nanowire units are arranged on the upper surface of the detector N + substrate at intervals; each quantum dot-nanowire unit comprises a semiconductor nanowire, a porous nanomaterial layer and a quantum dot material layer; the semiconductor nanowire comprises a heavily doped N + layer, an undoped I-type layer and a heavily doped P + layer; the porous nano material layer covers the semiconductor nanowire; the quantum dot material layer covers the porous nano material layer; the passivation layer is filled between the quantum dot-nanowire units; the P-type electrode grows on the top of the quantum dot-nanowire unit; and the N-type electrode grows on the upper surface of the detector N + substrate.

Description

Technical Field

[0001] The invention relates to an avalanche diode single-photon detector and a preparation method thereof, and in particular to a quantum dot-nanowire avalanche diode single-photon detector and a preparation method thereof. Background Art

[0002] Single-photon detectors have extremely high sensitivity at the photon scale and play an important role in the development of cutting-edge fields such as quantum communications, biomedicine, and remote sensing. Avalanche diode single-photon detection arrays are an important type of single-photon detector. Compared with other single-photon detectors such as photomultiplier tubes and superconducting single-photon detectors, they have the advantages of high integration, low power consumption, and a wide range of application scenarios. The photon detection efficiency of single-photon avalanche diodes is limited by the photon absorption efficiency of photon absorbing materials. The existing Si, SiGe, and III-V group single-photon avalanche diodes have a single response band and low photon absorption efficiency, which limits the further improvement of the performance of avalanche diode single-photon detectors.

[0003] The existing methods to improve the photon absorption efficiency are to integrate a microlens structure on the light-incoming surface of the avalanche diode single-photon detector or to introduce a distributed Bragg reflector structure inside it. The two methods are as follows:

[0004] (1) Integrate a microlens structure on the light-incoming surface of the detector. The principle of this method is to utilize the deflection and convergence effect of the microlens structure integrated on the light-incoming surface of the detector to converge the light to the active area of ​​the detector, thereby increasing the absorption rate of the incident light. The disadvantage of this method is that the deflection and convergence effect of the microlens structure on light not only depends on the size and structure design, but also the final presentation effect of the microlens structure morphology is also affected by the photolithography mask preparation and etching process. It is difficult to strictly control the morphology of the microlens structure, resulting in not only high preparation costs but also lower-than-expected focusing effects. In addition, since the microlens units are isolated from each other, their filling factor in the entire detector chip is low, which has limited effect on improving the photon absorption efficiency, and thus has little effect on improving the photon detection efficiency of the detector.

[0005] (2) Introducing a distributed Bragg reflector structure inside the detector. The principle of this method is to use the distributed Bragg reflector structure introduced inside the detector to increase the peak value of the photon absorption rate and the in-band flatness of broadband light absorption. The disadvantage of this method is that the specific composition of the distributed Bragg reflector structure involves the stacking of multiple layers of thin film materials with different refractive indices, and it is difficult to find the optimal solution for the material thickness design, and thus the effect on improving the photon absorption efficiency is also limited; in addition, the introduction of a distributed Bragg reflector structure will increase the number of detector preparation steps, increase the difficulty and complexity of the process, and result in a high preparation cost.

[0006] In summary, developing an avalanche diode single-photon detector that is easy to prepare, has low preparation cost, and high photon detection efficiency is an issue that needs to be urgently addressed. Summary of the invention

[0007] The purpose of the present invention is to solve the technical problems that the existing avalanche diode single-photon detector has low photon detection efficiency, and when the existing method is used to improve its photon detection efficiency, its preparation difficulty is increased, the preparation cost is increased, and the effect on improving the photon detection efficiency is limited, and to provide a quantum dot-nanowire avalanche diode single-photon detector and a preparation method thereof.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] A quantum dot-nanowire avalanche diode single photon detector, which is special in that:

[0010] Including detector N + The substrate and the spacer are arranged on the detector N + A plurality of quantum dot-nanowire units on the upper surface of the substrate, further comprising a passivation layer, a P-type electrode and an N-type electrode;

[0011] Each of the quantum dot-nanowire units comprises a semiconductor nanowire, a porous nanomaterial layer and a quantum dot material layer;

[0012] The semiconductor nanowire includes heavily doped N + layer, undoped I-type layer, and heavily doped P + layer; the heavily doped N + The layer is epitaxially grown on the detector N + On the upper surface of the substrate, its shape is a cone with a larger bottom and a smaller top; the undoped I-type layer is epitaxially grown on the heavily doped N + The outer surface of the layer is heavily doped with N + layer, and its lower end surface is connected to the detector N + There is a gap between the upper surface of the substrate, and the distance size of the gap meets the following conditions: the undoped I-type layer and the detector N + The heavily doped P + The layer is epitaxially grown on the outer surface of the undoped I-type layer, covering the undoped I-type layer, and its lower end surface is adjacent to the detector N + There is a gap between the upper surfaces of the substrate, and the distance size of the gap meets the following conditions: + Layer and detector N + The substrates are electrically isolated from each other;

[0013] The porous nanomaterial layer grows on the outer surface of the semiconductor nanowires to cover the semiconductor nanowires; the quantum dot material layer is coated on the outer surface of the porous nanomaterial layer to cover the porous nanomaterial layer; the quantum dot material layer is used to absorb photons; the porous nanomaterial layer is used to absorb photogenerated excitons and realize separation of electrons and holes; the semiconductor nanowires are used to realize photogenerated carrier multiplication;

[0014] The passivation layer fills the gaps between the quantum dot-nanowire units and the outer circle surrounding all the quantum dot-nanowire units; the upper surface of the passivation layer is parallel to the detector N + The upper surface of the substrate, and the top of the quantum dot-nanowire unit extends out of the upper surface of the passivation layer;

[0015] The P-type electrode is grown on the outer surface of the portion of each quantum dot-nanowire unit extending from the upper surface of the passivation layer, and its lower surface is coplanar with the upper surface of the passivation layer, covering the upper surface of the passivation layer and the outer surface of the portion of each quantum dot-nanowire unit extending from the upper surface of the passivation layer;

[0016] The N-type electrode is grown on the detector N + On the upper surface of the substrate and located outside the outer contour of the passivation layer.

[0017] Furthermore, the detector N + The substrate is a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer;

[0018] The heavily doped N + The doping concentration range is 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer;

[0019] The heavily doped P + The doping concentration range is 5×10 17 cm -3 Up to 1×10 20 cm -3 P-type semiconductor layer.

[0020] Furthermore, the height of the top of the quantum dot-nanowire unit protruding from the upper surface of the passivation layer is greater than or equal to 10 nm and less than or equal to 1 μm.

[0021] Furthermore, the detector N + The materials of the substrate and the semiconductor nanowires are silicon, germanium or III-V group semiconductor materials;

[0022] The material of the porous nanomaterial layer is a two-dimensional material;

[0023] The material of the quantum dot material layer is lead sulfide, indium phosphide, cadmium selenide or indium arsenide;

[0024] The material of the passivation layer is benzocyclobutene, SU-8 resin or spin-on glass;

[0025] The P-type electrode is made of a transparent conductive film;

[0026] The material of the N-type electrode is a metal material or a laminated material of multiple metals.

[0027] Furthermore, in order to simplify the process, the heavily doped P + The lower end surface of the layer and the detector N + The distance between the upper surface of the substrate is greater than the distance between the lower end surface of the undoped I-type layer and the detector N + The distance between the upper surfaces of the substrate.

[0028] At the same time, the present invention also provides a method for preparing the above quantum dot-nanowire avalanche diode single-photon detector, which is special in that it includes the following steps:

[0029] Step 1: Prepare the detector N according to the size and material requirements of the quantum dot-nanowire avalanche diode single photon detector to be prepared. + substrate;

[0030] Step 2: The detector N prepared in step 1 + On the substrate surface, gold nanoparticles were aerosol deposited as epitaxial growth of heavily doped N + When gold nanoparticles are deposited by aerosol, the concentration of gold nanoparticles in the aerosol is determined according to the quantum dot-nanowire avalanche diode single-photon detector to be prepared. + The number of quantum dot-nanowire units arranged and spaced per unit area on the upper surface of the substrate is determined;

[0031] Step 3: Detector N on which gold nanoparticles were aerosol-deposited in step 2 + On the substrate surface, epitaxial growth of heavily doped N + layer, and the detector N is spaced and arranged + There are multiple heavily doped N-doped nanostructures on the upper surface of the substrate. + layer;

[0032] Step 4: The heavily doped N + On the outer surface of the layer, an undoped I-type layer is epitaxially grown to obtain an intermittent arrangement grown on the detector N +The multiple outer surfaces on the upper surface of the substrate are covered with a heavily doped N-type layer without doping I-type layer. + layer;

[0033] Step 5: The heavily doped N-type layer obtained in step 4 is covered with an undoped I-type layer on each of the outer surfaces. + On the outer surface of each undoped I-type layer corresponding to the layer, a heavily doped P + layer, and the detector N is spaced and arranged + a plurality of semiconductor nanowire prototypes on the upper surface of the substrate;

[0034] Step 6: The heavily doped P corresponding to each of the semiconductor nanowire prototypes obtained in step 5 + On the outer surface of the layer, a photoresist is spin-coated; then a plasma ashing process is used to remove the heavily doped P + The outer surface of the layer is connected to the detector N + The distance between the substrate and the surface is equal to the heavily doped P required in the quantum dot-nanowire avalanche diode single photon detector to be prepared. + The lower end surface of the layer and the detector N + The photoresist coated on the substrate is removed from the area above the lower end contour line formed by the points spaced apart from each other on the upper surface of the substrate; then, a metal plating process is used to deposit metal on the entire outer surface of the semiconductor nanowire prototype on which the photoresist is retained on the outer surface of the lower end; finally, a stripping process is used to remove the photoresist and the metal deposited on the outer surface of the photoresist, thereby obtaining the nanowires arranged at intervals and grown on the detector N + A plurality of semiconductor nanowire prototypes with a metal mask deposited on the outer surfaces of the upper ends of the substrate;

[0035] Step 7: Using a semiconductor wet etching process, the exposed heavily doped P + The undoped I-type layer and its corresponding position are removed to prevent heavy doping of P + layer and undoped I-type layer, with detector N + The substrate is electrically connected to eliminate the leakage path; then the metal wet etching process is used to remove the metal mask deposited on the outer surface of the upper end of each semiconductor nanowire prototype, and the semiconductor nanowires grown on the detector N are obtained. + a plurality of semiconductor nanowires on an upper surface of a substrate;

[0036] Step 8: growing a porous nanomaterial layer on the outer surface of each of the semiconductor nanowires obtained in step 7 to cover each of the semiconductor nanowires;

[0037] Step 9: Coating a quantum dot material layer on the outer surface of the porous nanomaterial layer corresponding to each of the semiconductor nanowires whose porous nanomaterial layer has been grown on the outer surface in step 8, so as to cover each of the porous nanomaterial layers, so as to obtain a spaced arrangement arranged on the detector N + a plurality of quantum dot-nanowire units on the upper surface of the substrate;

[0038] Step 10: The gaps between the quantum dot-nanowire units obtained in step 9 and the outer circle of positions surrounding all the quantum dot-nanowire units are filled with a passivation material, and heat-treated to form a thermosetting polymer, i.e., a passivation layer;

[0039] Step 11: removing the excess passivation material on the passivation layer formed in step 10 by an etching process to expose the top of each quantum dot-nanowire unit obtained in step 9; then growing a P-type electrode on the outer surface of the protruding portion of the top of each quantum dot-nanowire unit that protrudes from the upper surface of the passivation layer;

[0040] Step 12: In step 11, on the outer surface of the protruding portion of the top of each quantum dot-nanowire unit protruding from the upper surface of the passivation layer, grow the detector N of each quantum dot-nanowire unit where the P-type electrode is located. + An N-type electrode is grown on the upper surface of the substrate, outside the outer contour of the passivation layer formed in step 10, to complete the preparation of the quantum dot-nanowire avalanche diode single-photon detector.

[0041] Furthermore, in step 3, the epitaxial growth of heavily doped N + When the undoped I-type layer is epitaxially grown in step 4, and when the heavily doped P-type layer is epitaxially grown in step 5, + When the layers are grown, chemical vapor deposition or molecular beam epitaxy is used.

[0042] Furthermore, when the porous nanomaterial layer is grown in step 8, the growth method is pulsed laser deposition, chemical vapor deposition or electrolytic corrosion.

[0043] Furthermore, when coating the quantum dot material layer in step 9, the coating is performed by spin coating or spray coating.

[0044] Furthermore, when the P-type electrode is grown in step 11, the growth method is magnetron sputtering;

[0045] When the N-type electrode is grown in step 12, the growth method is magnetron sputtering, electron beam evaporation or conductive silver paste coating.

[0046] The beneficial effects of the present invention are:

[0047] (1) The quantum dot-nanowire avalanche diode single-photon detector of the present invention integrates semiconductor nanowires with a quantum dot material layer, coats the quantum dot material layer on the outer surface of a porous nanomaterial layer grown on the outer surface of the semiconductor nanowire, designs quantum dot materials as photon absorption materials to cover the nanowire PIN avalanche diode in three dimensions, utilizes the quantum dot material layer as a photosensitive layer to efficiently capture incident photons and generate photogenerated carriers, and the nanowire avalanche diode operates in Geiger mode, where carriers collide and ionize under high electric field conditions to form a current that can be detected; the present invention breaks through the limitation that the quantum dot material layer in conventional single-photon detectors can only cover a certain plane of the device, greatly increases the effective area of ​​the photon absorption layer, and expands the effective incident photon angle. degree, increases the field of view of the detector, improves the photon absorption efficiency, and thus can greatly improve the photon detection efficiency of the single-photon detector; in the preparation process of the quantum dot-nanowire avalanche diode single-photon detector of the present invention, a simple liquid phase processing technology can be used to uniformly coat the quantum dot material on a large area on the outer surface of the porous nanomaterial layer grown on the outer surface of the semiconductor nanowire, without being restricted by lattice mismatch, showing excellent material compatibility, easy preparation, easy control of process parameters, and low preparation cost; therefore, the present invention solves the technical problems that the existing avalanche diode single-photon detector has a low photon detection efficiency, and when the existing method is used to improve its photon detection efficiency, its preparation difficulty is increased, the preparation cost is increased, and the effect on improving the photon detection efficiency is limited.

[0048] (2) In the quantum dot-nanowire avalanche diode single-photon detector of the present invention, quantum dot materials are used as photon absorption materials. The quantum confinement effect of quantum dots is utilized. By adjusting the size and material of the quantum dots, the band gap of the material can be precisely controlled, thereby achieving flexible spectral response. Simple liquid phase processing techniques such as spin coating and spray coating are used instead of epitaxial material growth to uniformly coat the quantum dot material over a large area on the outer surface of the porous nanomaterial layer grown on the outer surface of the semiconductor nanowires, so that the quantum dots are integrated with the carrier avalanche multiplication structure, thereby improving the flexibility of the device structure design. Vertical semiconductor nanowires are used to realize photogenerated carrier multiplication. Since each semiconductor nanowire can undergo avalanche multiplication independently, the dark count and after-pulse effects of the single-photon detector can be effectively suppressed.

[0049] (3) The quantum dot-nanowire avalanche diode single-photon detector of the present invention effectively reduces the area per unit pixel on the basis of improving the photon detection efficiency, which is beneficial to reducing the pixel center distance and the total area of ​​a single chip. Compared with the existing single-photon detector, in order to improve the sensitivity of a single pixel, the diameter of a single pixel of the single-photon avalanche diode is made to reach tens of microns, which limits the spatial resolution and array scale of the detector and increases the chip production cost. The present invention increases the upper limit of the single-photon detector array scale.

[0050] (4) In the quantum dot-nanowire avalanche diode single-photon detector of the present invention, the avalanche is confined within the quantum dot-nanowire unit, which effectively suppresses the crosstalk between different pixels of the single-photon detector and reduces the detector noise. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 It is a schematic structural diagram of an embodiment of a quantum dot-nanowire avalanche diode single photon detector of the present invention;

[0052] Figure 2 It is a flow chart of an embodiment of a method for preparing a quantum dot-nanowire avalanche diode single-photon detector of the present invention.

[0053] The descriptions of the numbers in the figure are as follows:

[0054] 1-Detector N + Substrate, 2-N-type electrode, 3-semiconductor nanowire, 31-heavily doped N + layer, 32-undoped I-type layer, 33-heavily doped P + layer, 4-porous nanomaterial layer, 5-quantum dot material layer, 6-passivation layer, 7-P-type electrode. DETAILED DESCRIPTION

[0055] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0056] See also Figure 1 The present invention provides a quantum dot-nanowire avalanche diode single-photon detector, comprising a detector N + Substrate 1, arranged at intervals on detector N + The plurality of quantum dot-nanowire units on the upper surface of the substrate 1 also include a passivation layer 6, a P-type electrode 7 and an N-type electrode 2. The detector N + Substrate 1 refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer.

[0057] Each of the quantum dot-nanowire units comprises a semiconductor nanowire 3, a porous nanomaterial layer 4 and a quantum dot material layer 5. The semiconductor nanowire 3 comprises a heavily doped N + layer 31, undoped I-type layer 32, and heavily doped P + Layer 33: The heavily doped N + Layer 31 generally refers to a doping concentration in the range of 5×10 17 cm -3 Up to 1×10 20 cm -3N-type semiconductor layer; the heavily doped P + Layer 33 usually refers to a doping concentration in the range of 5×10 17 cm -3 Up to 1×10 20 cm -3 P-type semiconductor layer; the heavily doped N + Layer 31 is epitaxially grown on the detector N + On the upper surface of the substrate 1, its shape is a cone with a larger bottom and a smaller top. The above-mentioned undoped I-type layer 32 is epitaxially grown on the heavily doped N + On the outer surface of layer 31, N + Layer 31 covers the lower end surface of the detector N + There is a gap between the upper surface of the substrate 1, and the distance size of the gap meets the following conditions: the undoped I-type layer 32 and the detector N + The substrate 1 is electrically isolated from the substrate 1; the heavily doped P + The layer 33 is epitaxially grown on the outer surface of the undoped I-type layer 32, covering the undoped I-type layer 32, and its lower end surface is adjacent to the detector N + There is a gap between the upper surfaces of the substrate 1, and the distance size of the gap meets the following conditions: + Layer 33 and detector N + The substrate 1 is electrically isolated from the substrate 1. In order to simplify the process, the heavily doped P + The lower end surface of layer 33 and detector N + The distance between the upper surface of the substrate 1 is greater than the distance between the lower end surface of the undoped I-type layer 32 and the detector N + The distance between the upper surfaces of the substrate 1. The above detector N + The materials of the substrate 1 and the semiconductor nanowires 3 are not limited to silicon, germanium or III-V semiconductor materials. In this embodiment, the detector N + The substrate 1 is made of silicon material, and the semiconductor nanowire 3 is made of indium phosphide (InP) material. The porous nanomaterial layer 4 is grown on the outer surface of the semiconductor nanowire 3 to cover the semiconductor nanowire 3; the material of the porous nanomaterial layer 4 includes but is not limited to surface defect materials and loosely structured two-dimensional materials; in this embodiment, the porous nanomaterial layer 4 is made of porous graphene material. The quantum dot material layer 5 is coated on the outer surface of the porous nanomaterial layer 4 to cover the porous nanomaterial layer 4; the material of the quantum dot material layer 5 includes but is not limited to lead sulfide, indium phosphide, cadmium selenide or indium arsenide; in this embodiment, the quantum dot material layer 5 is made of indium arsenide (InAs). The quantum dot material layer 5 is used to absorb photons; the porous nanomaterial layer 4 is used to absorb photogenerated excitons and realize the separation of electrons and holes; the semiconductor nanowire 3 is used to realize photogenerated carrier multiplication.

[0058] The passivation layer 6 fills the gaps between the quantum dot-nanowire units and the outer circle surrounding all the quantum dot-nanowire units; the upper surface of the passivation layer 6 is parallel to the detector N + The upper surface of the substrate 1, and the top of the quantum dot-nanowire unit extends out of the upper surface of the passivation layer 6. Preferably, the height of the top of the quantum dot-nanowire unit extending out of the upper surface of the passivation layer 6 is greater than or equal to 10nm and less than or equal to 1μm. The material of the passivation layer 6 includes but is not limited to benzocyclobutene (BCB), SU-8 resin or spin-on glass. In this embodiment, the passivation layer 6 is made of spin-on glass material.

[0059] The P-type electrode 7 is grown on the outer surface of the portion extending from the top of each quantum dot-nanowire unit to the upper surface of the passivation layer 6, and its lower surface is coplanar with the upper surface of the passivation layer 6, covering the upper surface of the passivation layer 6 and the outer surface of the portion extending from the top of each quantum dot-nanowire unit to the upper surface of the passivation layer 6. The material of the P-type electrode 7 includes but is not limited to transparent conductive films such as ITO; in this embodiment, the P-type electrode 7 is a transparent conductive film made of ITO material.

[0060] The N-type electrode 2 is grown on the detector N + On the upper surface of the substrate 1, and outside the outer contour of the passivation layer 6. The material of the N-type electrode 2 includes but is not limited to metal materials such as gold, aluminum, titanium, nickel, or a laminated material of multiple metals; in this embodiment, the N-type electrode 2 uses (titanium / gold laminated) Ti / Au laminated material.

[0061] In addition, the present invention also provides a method for preparing the above quantum dot-nanowire avalanche diode single photon detector, see Figure 2 , including the following steps:

[0062] Step 1: Prepare the detector N according to the size and material requirements of the quantum dot-nanowire avalanche diode single photon detector to be prepared. + Substrate 1;

[0063] Step 2: The detector N prepared in step 1 + On the upper surface of substrate 1, gold nanoparticles are aerosol-deposited as epitaxial growth of heavily doped N + When the gold nanoparticles are deposited by aerosol, the concentration of the gold nanoparticles in the aerosol is determined according to the quantum dot-nanowire avalanche diode single-photon detector to be prepared, and the detector N is required + The number of quantum dot-nanowire units arranged and spaced apart per unit area on the upper surface of the substrate 1 is determined;

[0064] Step 3: Detector N on which gold nanoparticles were aerosol-deposited in step 2 + On the upper surface of substrate 1, epitaxial growth of heavily doped N+ Layer 31, the growth method includes but is not limited to chemical vapor deposition method or molecular beam epitaxy method, etc., to obtain a spaced arrangement and growth on the detector N + There are multiple heavily doped N + Layer 31;

[0065] Step 4: The heavily doped N + On the outer surface of the layer 31, an undoped I-type layer 32 is epitaxially grown, and the growth method includes but is not limited to chemical vapor deposition or molecular beam epitaxy, etc., to obtain a layer 32 that is arranged at intervals and grown on the detector N + The multiple outer surfaces of the upper surface of the substrate 1 are covered by the undoped I-type layer 32. + Layer 31;

[0066] Step 5: The heavily doped N-type layers obtained in step 4 are covered with the undoped I-type layer 32. + On the outer surface of each undoped I-type layer 32 corresponding to layer 31, heavily doped P + Layer 33, the growth method includes but is not limited to chemical vapor deposition method or molecular beam epitaxy method, etc., to obtain a spaced arrangement and growth on the detector N + A plurality of semiconductor nanowire prototypes on the upper surface of substrate 1;

[0067] Step 6: The heavily doped P corresponding to each of the semiconductor nanowire prototypes obtained in step 5 + On the outer surface of layer 33, a photoresist is spin-coated; then, a plasma ashing process is used to remove the heavily doped P + The outer surface of layer 33 is connected to the detector N + The distance between the upper surface of the substrate 1 is equal to the heavily doped P required in the quantum dot-nanowire avalanche diode single photon detector to be prepared. + The lower end surface of layer 33 and detector N + The above-mentioned photoresist coated by spin coating is removed from the area above the lower end contour line formed by the points spaced apart from each other on the upper surface of the substrate 1; then, a metal plating process is used to deposit metal on the entire outer surface of the semiconductor nanowire prototype on which the photoresist is retained on the outer surface of the lower end; finally, a stripping process is used to remove the photoresist and the metal deposited on the outer surface of the photoresist, thereby obtaining the semiconductor nanowires arranged and grown on the detector N at intervals. + A plurality of semiconductor nanowire prototypes with metal masks deposited on the outer surfaces of the upper ends of the substrate 1;

[0068] Step 7: Using a semiconductor wet etching process, the exposed heavily doped P +The layer 33 and the undoped I-type layer 32 at the corresponding position inside it are removed to prevent heavy doping of P + layer 33 and the undoped I-type layer 32, and the detector N + The substrate 1 is electrically connected to eliminate the leakage path; then the metal mask deposited on the outer surface of the upper end of each semiconductor nanowire prototype is removed by a metal wet etching process to obtain a semiconductor nanowire arranged and grown on the detector N + A plurality of semiconductor nanowires 3 on the upper surface of the substrate 1;

[0069] Step 8: growing a porous nanomaterial layer 4 on the outer surface of each of the semiconductor nanowires 3 obtained in step 7 to cover each of the semiconductor nanowires 3; the growth method includes but is not limited to pulsed laser deposition, chemical vapor deposition or electrolytic corrosion, etc.;

[0070] Step 9: Coating the quantum dot material layer 5 on the outer surface of the porous nanomaterial layer 4 corresponding to each of the semiconductor nanowires 3 on the outer surface of which the porous nanomaterial layer 4 is grown in step 8, so as to cover each of the porous nanomaterial layers 4, and the coating method includes but is not limited to spin coating, spray coating, etc., to obtain a spaced arrangement arranged in the detector N + A plurality of quantum dot-nanowire units on the upper surface of substrate 1;

[0071] Step 10: The gaps between the quantum dot-nanowire units obtained in step 9 and the outer circle surrounding all the quantum dot-nanowire units are filled with a passivation material, and the passivation material is heat-treated to form a thermosetting polymer, i.e., a passivation layer 6 is formed;

[0072] Step 11: removing the excess passivation material on the passivation layer 6 formed in step 10 by an etching process to expose the top of each of the quantum dot-nanowire units obtained in step 9; then growing a P-type electrode 7 on the outer surface of the protruding portion of the passivation layer 6 on the top of each quantum dot-nanowire unit, wherein the growth method includes but is not limited to a magnetron sputtering method, etc.;

[0073] Step 12: In step 11, on the outer surface of the protruding portion of the passivation layer 6 on the top of each quantum dot-nanowire unit, the detector N of each quantum dot-nanowire unit where the P-type electrode 7 is located is grown. + On the upper surface of the substrate 1, an N-type electrode 2 is grown at an outer position of the outer contour of the above-mentioned passivation layer 6 formed in step 10, and its growth method includes but is not limited to magnetron sputtering, electron beam evaporation or conductive silver paste coating, etc.; the preparation of the quantum dot-nanowire avalanche diode single-photon detector is completed.

[0074] In summary, the quantum dot-nanowire avalanche diode single-photon detector of the present invention effectively reduces the unit pixel area on the basis of improving the photon detection efficiency, which is beneficial to reducing the pixel center distance and the total area of ​​a single chip, and improves the upper limit of the single-photon detector array scale. And when the preparation method of the quantum dot-nanowire avalanche diode single-photon detector of the present invention is used to prepare the quantum dot-nanowire avalanche diode single-photon detector, the preparation process is simple, the process parameters are easy to control, and the preparation cost is low.

Claims

1. A quantum dot-nanowire avalanche diode single-photon detector, characterized in that: Including detector N + The substrate (1) is arranged at intervals on the detector N + A plurality of quantum dot-nanowire units on the upper surface of a substrate (1), further comprising a passivation layer (6), a P-type electrode (7) and an N-type electrode (2); Each of the quantum dot-nanowire units comprises a semiconductor nanowire (3), a porous nanomaterial layer (4) and a quantum dot material layer (5); The semiconductor nanowire (3) comprises heavily doped N + layer (31), an undoped I-type layer (32), and a heavily doped P + layer (33); the heavily doped N + The layer (31) is epitaxially grown on the detector N + On the upper surface of the substrate (1), the outer shape is a cone with a larger bottom and a smaller top; the undoped I-type layer (32) is epitaxially grown on the heavily doped N + On the outer surface of layer (31), N + The layer (31) covers the lower end surface of the detector N + A gap is left between the upper surfaces of the substrate (1), and the distance dimension of the gap meets the following conditions: the undoped I-type layer (32) and the detector N + The substrates (1) are electrically isolated from each other; the heavily doped P + The layer (33) is epitaxially grown on the outer surface of the undoped I-type layer (32) to cover the undoped I-type layer (32), and its lower end surface is in contact with the detector N + There is a gap between the upper surfaces of the substrate (1), and the distance size of the gap meets the following conditions: + Layer (33) and detector N + The substrates (1) are electrically isolated from each other; The porous nanomaterial layer (4) is grown on the outer surface of the semiconductor nanowire (3) to cover the semiconductor nanowire (3); the quantum dot material layer (5) is coated on the outer surface of the porous nanomaterial layer (4) to cover the porous nanomaterial layer (4); the quantum dot material layer (5) is used to absorb photons; the porous nanomaterial layer (4) is used to absorb photogenerated excitons and achieve separation of electrons and holes; the semiconductor nanowire (3) is used to achieve photogenerated carrier multiplication; The passivation layer (6) fills the gaps between the quantum dot-nanowire units and the outer circle surrounding all the quantum dot-nanowire units; The upper surface of the passivation layer (6) is parallel to the detector N + The upper surface of the substrate (1), and the top of the quantum dot-nanowire unit extends out of the upper surface of the passivation layer (6); The P-type electrode (7) is grown on the outer surface of the portion of each quantum dot-nanowire unit extending from the upper surface of the passivation layer (6), and its lower surface is coplanar with the upper surface of the passivation layer (6), covering the upper surface of the passivation layer (6) and the outer surface of the portion of each quantum dot-nanowire unit extending from the upper surface of the passivation layer (6); The N-type electrode (2) is grown on the detector N + The passivation layer (6) is located on the upper surface of the substrate (1) and outside the outer contour of the passivation layer (6).

2. The quantum dot-nanowire avalanche diode single photon detector according to claim 1, characterized in that: The detector N + Substrate (1) refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; The heavily doped N + Layer (31) refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; The heavily doped P + Layer (33) refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 P-type semiconductor layer.

3. The quantum dot-nanowire avalanche diode single photon detector according to claim 1, characterized in that: The height of the top of the quantum dot-nanowire unit protruding from the upper surface of the passivation layer (6) is greater than or equal to 10 nm and less than or equal to 1 μm.

4. The quantum dot-nanowire avalanche diode single photon detector according to any one of claims 1 to 3, characterized in that: The detector N + The materials of the substrate (1) and the semiconductor nanowires (3) are silicon, germanium or III-V group semiconductor materials; The material of the porous nanomaterial layer (4) is a two-dimensional material; The material of the quantum dot material layer (5) is lead sulfide, indium phosphide, cadmium selenide or indium arsenide; The material of the passivation layer (6) is benzocyclobutene, SU-8 resin or spin-on glass; The P-type electrode (7) is made of a transparent conductive film; The material of the N-type electrode (2) is a metal material or a laminated material of multiple metals.

5. The quantum dot-nanowire avalanche diode single photon detector according to claim 4, characterized in that: The heavily doped P + The lower end surface of layer (33) and detector N + The distance between the upper surface of the substrate (1) is greater than the distance between the lower end surface of the undoped I-type layer (32) and the detector N + The distance between the upper surfaces of the substrate (1).

6. A method for preparing a quantum dot-nanowire avalanche diode single-photon detector, characterized in that: The following steps are involved: Step 1: Prepare the detector N according to the size and material requirements of the quantum dot-nanowire avalanche diode single photon detector to be prepared. + Substrate (1); Step 2: The detector N prepared in step 1 + On the upper surface of the substrate (1), gold nanoparticles are aerosol-deposited as epitaxially grown heavily doped N + When the gold nanoparticles are deposited by aerosol, the concentration of the gold nanoparticles in the aerosol is determined according to the quantum dot-nanowire avalanche diode single-photon detector to be prepared, requiring the detector N + The number of quantum dot-nanowire units arranged and spaced apart per unit area on the upper surface of the substrate (1) is determined; Step 3: Detector N on which gold nanoparticles were aerosol-deposited in step 2 + On the upper surface of the substrate (1), epitaxially grown heavily doped N + layer (31), and the detector N is arranged at intervals. + A plurality of heavily doped N-doped nanostructured nanostructures having a large bottom and a small top are formed on the upper surface of the substrate (1). + Layer (31); Step 4: The heavily doped N + On the outer surface of the layer (31), an undoped I-type layer (32) is epitaxially grown to obtain a spaced arrangement and growth on the detector N + A plurality of outer surfaces on the upper surface of the substrate (1) are covered with a heavily doped N-type layer (32) without doping. + Layer (31); Step 5: The heavily doped N-type substrates obtained in step 4 are each covered with an undoped I-type layer (32). + On the outer surface of each undoped I-type layer (32) corresponding to the layer (31), a heavily doped P + layer (33), and the detector N is arranged at intervals. + A plurality of semiconductor nanowire prototypes on the upper surface of a substrate (1); Step 6: The heavily doped P corresponding to each of the semiconductor nanowire prototypes obtained in step 5 + Spin-coating a photoresist on the outer surface of the layer (33); Then, a plasma ashing process is used to remove the heavily doped P + The outer surface of the layer (33) is connected to the detector N + The distance between the upper surface of the substrate (1) is equal to the heavily doped P required in the quantum dot-nanowire avalanche diode single photon detector to be prepared. + The lower end surface of layer (33) and detector N + The photoresist coated on the upper surface of the substrate (1) is removed from the area above the lower end contour line formed by the points spaced apart from each other; a metal plating process is then used to deposit metal on the entire outer surface of the semiconductor nanowire prototype on which the photoresist is retained on the outer surface of the lower end; and a stripping process is finally used to remove the photoresist and the metal deposited on the outer surface of the photoresist, thereby obtaining the semiconductor nanowires arranged and grown on the detector N at intervals. + A plurality of semiconductor nanowire prototypes with metal masks deposited on the upper outer surfaces of the upper surface of the substrate (1); Step 7: Using a semiconductor wet etching process, the exposed heavily doped P + The layer (33) and the undoped I-type layer (32) at the corresponding position inside it are removed to prevent heavy doping of P + layer (33) and an undoped I-type layer (32), and a detector N + The substrate (1) is electrically connected to eliminate the leakage path; then the metal mask deposited on the outer surface of the upper end of each semiconductor nanowire prototype is removed by a metal wet etching process to obtain a semiconductor nanowire arranged and grown on the detector N + A plurality of semiconductor nanowires (3) on the upper surface of the substrate (1); Step 8: growing a porous nanomaterial layer (4) on the outer surface of each semiconductor nanowire (3) obtained in step 7 to cover each semiconductor nanowire (3); Step 9: Coating a quantum dot material layer (5) on the outer surface of the porous nanomaterial layer (4) corresponding to each of the semiconductor nanowires (3) on which the porous nanomaterial layer (4) is grown in step 8, so as to cover each of the porous nanomaterial layers (4) to obtain a spaced arrangement arranged on the detector N + A plurality of quantum dot-nanowire units on the upper surface of a substrate (1); Step 10: The gaps between the quantum dot-nanowire units obtained in step 9 and the outer circle of positions surrounding all the quantum dot-nanowire units are filled with a passivation material, and the passivation material is heat-treated to form a thermosetting polymer, i.e., a passivation layer (6); Step 11: removing the excess passivation material on the passivation layer (6) formed in step 10 by an etching process to expose the top of each quantum dot-nanowire unit obtained in step 9; then growing a P-type electrode (7) on the outer surface of the protruding portion of the top of each quantum dot-nanowire unit that protrudes from the upper surface of the passivation layer (6); Step 12: In step 11, on the outer surface of the protruding portion of the passivation layer (6) on the top of each quantum dot-nanowire unit, the detector N of each quantum dot-nanowire unit where the P-type electrode (7) is located is grown. + An N-type electrode (2) is grown on the upper surface of the substrate (1) at a position outside the outer contour of the passivation layer (6) formed in step 10, thereby completing the preparation of the quantum dot-nanowire avalanche diode single-photon detector.

7. The method for preparing a quantum dot-nanowire avalanche diode single photon detector according to claim 6, characterized in that: In step 3, epitaxial growth of heavily doped N + When the undoped I-type layer (31) is formed, when the undoped I-type layer (32) is epitaxially grown in step 4, and when the heavily doped P-type layer (31) is epitaxially grown in step 5, + When the layer (33) is grown, the growth method adopts chemical vapor deposition method or molecular beam epitaxy method.

8. The method for preparing a quantum dot-nanowire avalanche diode single photon detector according to claim 7, characterized in that: When the porous nanomaterial layer (4) is grown in step 8, the growth method is pulsed laser deposition, chemical vapor deposition or electrolytic corrosion.

9. The method for preparing a quantum dot-nanowire avalanche diode single photon detector according to claim 8, characterized in that: When coating the quantum dot material layer (5) in step 9, the coating is performed by spin coating or spray coating.

10. The method for preparing a quantum dot-nanowire avalanche diode single photon detector according to claim 9, characterized in that: When the P-type electrode (7) is grown in step 11, the growth method is magnetron sputtering; When the N-type electrode (2) is grown in step 12, the growth method is magnetron sputtering, electron beam evaporation or conductive silver paste coating.

Images