Quantum dot-vertical line type avalanche diode single-photon detector and preparation method thereof

Abstract

The invention relates to an avalanche diode single-photon detector and a preparation method thereof, in particular to a quantum dot-vertical line type avalanche diode single-photon detector and a preparation method thereof, and solves the problems that an existing single-photon detector is low in detection efficiency, and when an existing method is adopted for improvement, the preparation difficulty is large, the cost is high, and the effect is limited. The detector comprises a detector N + substrate, a back electrode growing on the lower surface of the detector N + substrate, a plurality of quantum dot-vertical line units arranged on the upper surface of the detector N + substrate at intervals in an array mode, a passivation layer and a front electrode. Each quantum dot-vertical line unit comprises a semiconductor vertical line structure, a porous nano material layer and a quantum dot material layer; the semiconductor vertical line structure grows on the upper surface of the detector N + substrate; the porous nanometer material layer covers the semiconductor vertical line structure; the quantum dot material layer covers the porous nano material layer; the passivation layer is filled between the quantum dot-vertical line units; and the front electrode grows on the part, extending out of the passivation layer, of the quantum dot-vertical line unit.

Description

Technical Field

[0001] The invention relates to an avalanche diode single-photon detector and a preparation method thereof, and in particular to a quantum dot-vertical line avalanche diode single-photon detector and a preparation method thereof. Background Art

[0002] Single-photon detectors have extremely high sensitivity at the photon scale and play an important role in the development of cutting-edge fields such as quantum communications, biomedicine, and remote sensing. Avalanche diode single-photon detection arrays are an important type of single-photon detector. Compared with other single-photon detectors such as photomultiplier tubes and superconducting single-photon detectors, they have the advantages of high integration, low power consumption, and a wide range of application scenarios. The photon detection efficiency of single-photon avalanche diodes is limited by the photon absorption efficiency of photon absorbing materials. The existing Si, SiGe, and III-V group single-photon avalanche diodes have a single response band and low photon absorption efficiency, which limits the further improvement of the performance of avalanche diode single-photon detectors.

[0003] The existing methods to improve the photon absorption efficiency are to integrate a microlens structure on the light-incoming surface of the avalanche diode single-photon detector or to introduce a distributed Bragg reflector structure inside it. The two methods are as follows:

[0004] (1) Integrate a microlens structure on the light-incoming surface of the detector. The principle of this method is to utilize the deflection and convergence effect of the microlens structure integrated on the light-incoming surface of the detector to converge the light to the active area of ​​the detector, thereby increasing the absorption rate of the incident light. The disadvantage of this method is that the deflection and convergence effect of the microlens structure on light not only depends on the size and structure design, but also the final presentation effect of the microlens structure morphology is also affected by the photolithography mask preparation and etching process. It is difficult to strictly control the morphology of the microlens structure, resulting in not only high preparation costs but also lower-than-expected focusing effects. In addition, since the microlens units are isolated from each other, their filling factor in the entire detector chip is low, which has limited effect on improving the photon absorption efficiency, and thus has little effect on improving the photon detection efficiency of the detector.

[0005] (2) Introducing a distributed Bragg reflector structure inside the detector. The principle of this method is to use the distributed Bragg reflector structure introduced inside the detector to increase the peak value of the photon absorption rate and the in-band flatness of broadband light absorption. The disadvantage of this method is that the specific composition of the distributed Bragg reflector structure involves the stacking of multiple layers of thin film materials with different refractive indices, and it is difficult to find the optimal solution for the material thickness design, and thus the effect on improving the photon absorption efficiency is also limited; in addition, the introduction of a distributed Bragg reflector structure will increase the number of detector preparation steps, increase the difficulty and complexity of the process, and result in a high preparation cost.

[0006] In summary, developing an avalanche diode single-photon detector that is easy to prepare, has low preparation cost, and has high photon detection efficiency is an issue that needs to be urgently addressed. Summary of the invention

[0007] The purpose of the present invention is to solve the technical problems that the existing avalanche diode single-photon detector has low photon detection efficiency, and when the existing method is used to improve its photon detection efficiency, its preparation difficulty is increased, the preparation cost is increased, and the effect on improving the photon detection efficiency is limited, and to provide a quantum dot-vertical line avalanche diode single-photon detector and a preparation method thereof.

[0008] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0009] A quantum dot-vertical linear avalanche diode single photon detector, which is special in that:

[0010] Including detector N + Substrate, grown on detector N + The back electrode and array of the lower surface of the substrate are arranged at intervals on the detector N + a plurality of quantum dot-vertical line units on the upper surface of the substrate, further comprising a passivation layer and a front electrode;

[0011] Each of the quantum dot-vertical line units comprises a semiconductor vertical line structure, a porous nanomaterial layer and a quantum dot material layer;

[0012] The semiconductor vertical line structure is grown on the detector N + On the upper surface of the substrate, there are heavily doped N + layer, undoped I-type layer, lightly doped P - Layer and heavily doped P + layer; the porous nano material layer is grown on the outer surface of the semiconductor vertical line structure to cover the semiconductor vertical line structure; the quantum dot material layer is coated on the outer surface of the porous nano material layer to cover the porous nano material layer; the quantum dot material layer is used to absorb photons; the porous nano material layer is used to absorb photogenerated excitons and realize the separation of electrons and holes; the semiconductor vertical line structure is used to realize the multiplication of photogenerated carriers;

[0013] The passivation layer fills the gaps between the quantum dot-vertical line units and the outer circle surrounding all the quantum dot-vertical line units; the upper surface of the passivation layer is parallel to the detector N + The upper surface of the substrate is higher than the heavily doped P + The lower surface of the layer, the top of the quantum dot-vertical line unit protrudes out of the upper surface of the passivation layer;

[0014] The front electrode is grown on the outer surface of the protruding portion of the top of each quantum dot-vertical line unit that protrudes from the upper surface of the passivation layer, and its lower surface is coplanar with the upper surface of the passivation layer, covering the upper surface of the passivation layer and the outer surface of the protruding portion of the top of each quantum dot-vertical line unit that protrudes from the upper surface of the passivation layer.

[0015] Furthermore, the detector N + The substrate is a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer;

[0016] The heavily doped N + The doping concentration range is 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; the lightly doped P - The doping concentration range is 1×10 15 cm -3 Up to 5×10 16 cm -3 P-type semiconductor layer; the heavily doped P + The doping concentration range is 5×10 17 cm -3 Up to 1×10 20 cm -3 A P-type semiconductor layer;

[0017] The radial dimension of the horizontal cross section of the semiconductor vertical line structure is greater than or equal to 10 nm and less than or equal to 10 μm.

[0018] Furthermore, the height of the top of the quantum dot-vertical line unit protruding from the upper surface of the passivation layer is greater than or equal to 10 nm and less than or equal to 1 μm.

[0019] Furthermore, the detector N + The materials of the substrate and the semiconductor vertical line structure are silicon, germanium or III-V group semiconductor materials;

[0020] The material of the porous nanomaterial layer is a two-dimensional material;

[0021] The material of the quantum dot material layer is lead sulfide, indium phosphide, cadmium selenide or indium arsenide;

[0022] The material of the passivation layer is benzocyclobutene, SU-8 resin or spin-on glass.

[0023] Furthermore, the front electrode is made of a transparent conductive film;

[0024] The material of the back electrode is a metal material or a laminated material of multiple metals.

[0025] At the same time, the present invention also provides a method for preparing the above quantum dot-vertical linear avalanche diode single-photon detector, which is special in that it includes the following steps:

[0026] Step 1: Prepare the detector N according to the size and material requirements of the quantum dot-vertical linear avalanche diode single photon detector to be prepared. + substrate;

[0027] Step 2: The detector N prepared in step 1 + On the upper surface of the substrate, heavily doped N + layer, undoped I-type layer, lightly doped P - Layer and heavily doped P + layer;

[0028] Step 3: After growing heavily doped P on the upper surface in step 2 + Layer detector N + On the lower surface of the substrate, a back electrode is grown;

[0029] Step 4: After the back electrode is grown in step 3, the heavily doped P + On the upper surface of the layer, the semiconductor vertical line structure area is delineated by photolithography and etched. During etching, the heavily doped P grown in step 2 + Starting from the top surface of the layer, from top to bottom, the heavily doped P + Layer, lightly doped P - layer, undoped I-type layer, heavily doped N + layer until it reaches detector N + The upper surface of the substrate is etched to obtain an array of spaced arrays grown on the detector N + a plurality of semiconductor vertical line structures on the upper surface of the substrate;

[0030] Step 5: growing a porous nanomaterial layer on the outer surface of each of the semiconductor vertical line structures etched in step 4 to cover each of the semiconductor vertical line structures;

[0031] Step 6: On the outer surface of the porous nanomaterial layer corresponding to each of the semiconductor vertical line structures on which the porous nanomaterial layer has been grown in step 5, a quantum dot material layer is coated to cover the porous nanomaterial layer, so as to obtain an array of spaced arrangement arranged on the detector N + a plurality of quantum dot-vertical line units on the upper surface of the substrate;

[0032] Step 7: The gaps between the quantum dot-vertical line units obtained in step 6 and the outer circle of positions surrounding all the quantum dot-vertical line units are filled with a passivation material, and the passivation material is heat-treated to form a thermosetting polymer, i.e., a passivation layer;

[0033] Step 8: Use an etching process to remove excess passivation material on the passivation layer formed in step 7 to expose the top of each quantum dot-vertical line unit obtained in step 6; then grow a front electrode on the outer surface of the protruding portion of the passivation layer on the top of each quantum dot-vertical line unit; complete the preparation of the quantum dot-vertical line avalanche diode single-photon detector.

[0034] Further, in step 2, the detector N prepared in step 1 + On the upper surface of the substrate, heavily doped N + layer, undoped I-type layer, lightly doped P - Layer and heavily doped P + When the layer is grown, the growth method adopts chemical vapor deposition method or molecular beam epitaxy method.

[0035] Furthermore, when the porous nanomaterial layer is grown in step 5, the growth method is pulsed laser deposition, chemical vapor deposition or electrolytic corrosion.

[0036] Furthermore, when coating the quantum dot material layer in step 6, the coating is performed by spin coating or spray coating.

[0037] Furthermore, when growing the back electrode in step 3, the growth method is magnetron sputtering or electron beam evaporation;

[0038] When growing the front electrode in step 8, the growth method is magnetron sputtering.

[0039] The beneficial effects of the present invention are:

[0040] (1) The quantum dot-vertical line avalanche diode single-photon detector of the present invention integrates a semiconductor vertical line structure with a quantum dot material layer, and coats the quantum dot material layer on the outer surface of a porous nanomaterial layer grown on the outer surface of the semiconductor vertical line structure. The quantum dot material is designed as a photon absorption material to three-dimensionally cover the vertical line PIN avalanche diode, and the quantum dot material layer is used as a photosensitive layer to efficiently capture incident photons and generate photogenerated carriers. The vertical line avalanche diode operates in Geiger mode, and carriers are collisionally ionized under high electric field conditions to form a current that can be detected. The present invention breaks through the limitation that the quantum dot material layer in conventional single-photon detectors can only cover a certain plane of the device, greatly increases the effective area of ​​the photon absorption layer, and expands the effective incident light The quantum dot-vertical line avalanche diode single-photon detector of the present invention can increase the field of view of the detector and improve the photon absorption efficiency, thereby greatly improving the photon detection efficiency of the single-photon detector; in the preparation process of the quantum dot-vertical line avalanche diode single-photon detector of the present invention, the quantum dot material can be uniformly coated on a large area on the outer surface of the porous nanomaterial layer grown on the outer surface of the semiconductor vertical line structure by a simple liquid phase processing technology, which is not restricted by lattice mismatch, shows excellent material compatibility, is easy to prepare, the process parameters are easy to control, and the preparation cost is low; therefore, the present invention solves the technical problems that the existing avalanche diode single-photon detector has low photon detection efficiency, and when the existing method is used to improve its photon detection efficiency, its preparation difficulty is increased, the preparation cost is increased, and the effect on improving the photon detection efficiency is limited.

[0041] (2) In the quantum dot-vertical line avalanche diode single-photon detector of the present invention, quantum dot materials are used as photon absorption materials. The quantum confinement effect of quantum dots is utilized. By adjusting the size and material of quantum dots, the band gap of the material can be precisely controlled, thereby achieving flexible spectral response. Simple liquid phase processing techniques such as spin coating and spray coating are used instead of epitaxial material growth to uniformly coat the quantum dot material over a large area on the outer surface of a porous nanomaterial layer grown on the outer surface of a semiconductor vertical line structure. The quantum dots are integrated with a carrier avalanche multiplication structure, thereby improving the flexibility of device structure design. A vertical semiconductor vertical line structure is used to achieve photogenerated carrier multiplication. Since each semiconductor vertical line structure can undergo avalanche multiplication independently, the dark count and after-pulse effects of the single-photon detector can be effectively suppressed.

[0042] (3) The quantum dot-vertical line avalanche diode single-photon detector of the present invention effectively reduces the area per unit pixel on the basis of improving the photon detection efficiency, which is beneficial to reducing the pixel center distance and the total area of ​​a single chip. Compared with the existing single-photon detector, in order to improve the sensitivity of a single pixel, the diameter of a single pixel of the single-photon avalanche diode is made to reach tens of microns, which limits the spatial resolution and array scale of the detector and increases the chip production cost. The present invention increases the upper limit of the single-photon detector array scale. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 It is a schematic structural diagram of an embodiment of a quantum dot-vertical linear avalanche diode single photon detector of the present invention;

[0044] Figure 2 It is a flow chart of an embodiment of a method for preparing a quantum dot-vertical linear avalanche diode single-photon detector of the present invention.

[0045] The descriptions of the numbers in the figure are as follows:

[0046] 1-Detector N + Substrate, 2-back electrode, 3-semiconductor vertical line structure, 31-heavily doped N + layer, 32-undoped I-type layer, 33-lightly doped P - Layer, 34-heavily doped P + layer, 4-porous nanomaterial layer, 5-quantum dot material layer, 6-passivation layer, 7-front electrode. DETAILED DESCRIPTION

[0047] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] See also Figure 1 The present invention provides a quantum dot-vertical linear avalanche diode single-photon detector, comprising a detector N + Substrate 1, grown on detector N + The back electrode 2 on the lower surface of the substrate 1 is arranged in an array at intervals on the detector N + The plurality of quantum dot-vertical line units on the upper surface of the substrate 1 also include a passivation layer 6 and a front electrode 7. The detector N + Substrate 1 usually refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer.

[0049] Each of the quantum dot-vertical line units comprises a semiconductor vertical line structure 3, a porous nanomaterial layer 4 and a quantum dot material layer 5. The semiconductor vertical line structure 3 is grown on the detector N + The upper surface of the substrate 1 includes heavily doped N + Layer 31, undoped I-type layer 32, lightly doped P - Layer 33 and heavily doped P + Layer 34: the heavily doped N + Layer 31 generally refers to a doping concentration in the range of 5×10 17 cm -3 Up to 1×1020 cm -3 N-type semiconductor layer; the lightly doped P - Layer 33 usually refers to a doping concentration in the range of 1×10 15 cm -3 Up to 5×10 16 cm -3 P-type semiconductor layer; the heavily doped P + Layer 34 generally refers to a doping concentration in the range of 5×10 17 cm -3 Up to 1×10 20 cm -3 The radial dimension of the horizontal cross section of the semiconductor vertical line structure 3 is greater than or equal to 10nm and less than or equal to 10μm; the detector N + The materials of the substrate 1 and the semiconductor vertical line structure 3 are not limited to silicon, germanium or III-V semiconductor materials. In this embodiment, the detector N + The substrate 1 is made of indium phosphide (InP) material, and the semiconductor vertical line structure 3 is made of indium phosphide (InP) material. The porous nano material layer 4 is grown on the outer surface of the semiconductor vertical line structure 3 to cover the semiconductor vertical line structure 3; the material of the porous nano material layer 4 includes but is not limited to surface defect materials and loosely structured two-dimensional materials; in this embodiment, the porous nano material layer 4 is made of porous graphene material. The quantum dot material layer 5 is coated on the outer surface of the porous nano material layer 4 to cover the porous nano material layer 4; the material of the quantum dot material layer 5 includes but is not limited to lead sulfide, indium phosphide, cadmium selenide or indium arsenide; in this embodiment, the quantum dot material layer 5 is made of indium arsenide (InAs) material. The quantum dot material layer 5 is used to absorb photons, the porous nano material layer 4 is used to absorb photogenerated excitons and realize the separation of electrons and holes, and the semiconductor vertical line structure 3 is used to realize photogenerated carrier multiplication.

[0050] The passivation layer 6 fills the gaps between the quantum dot-vertical line units and the outer circle surrounding all the quantum dot-vertical line units; the upper surface of the passivation layer 6 is parallel to the detector N + The upper surface of substrate 1 is higher than the heavily doped P + The top of the quantum dot-vertical line unit protrudes from the upper surface of the passivation layer 6. Preferably, the height of the top of the quantum dot-vertical line unit protruding from the upper surface of the passivation layer 6 is generally greater than or equal to 10 nm and less than or equal to 1 μm. The material of the passivation layer 6 includes but is not limited to benzocyclobutene (BCB), SU-8 resin or spin-on glass. In this embodiment, the passivation layer 6 is made of spin-on glass material.

[0051] The front electrode 7 is grown on the outer surface of the portion extending from the top of each quantum dot-vertical line unit to the upper surface of the passivation layer 6, and its lower surface is coplanar with the upper surface of the passivation layer 6, covering the upper surface of the passivation layer 6 and the outer surface of the portion extending from the top of each quantum dot-vertical line unit to the upper surface of the passivation layer 6. The material of the back electrode 2 includes but is not limited to metal materials such as gold, aluminum, titanium, nickel, or a laminated material of multiple metals; in this embodiment, the back electrode 2 uses a titanium / gold laminate (Ti / Au laminate) material. The material of the front electrode 7 includes but is not limited to a transparent conductive film such as ITO; in this embodiment, the front electrode 7 uses a transparent conductive film of ITO material.

[0052] In addition, the present invention also provides a method for preparing the above quantum dot-vertical linear avalanche diode single photon detector, see Figure 2 , including the following steps:

[0053] Step 1: Prepare the detector N according to the size and material requirements of the quantum dot-vertical linear avalanche diode single photon detector to be prepared. + Substrate 1;

[0054] Step 2: The detector N prepared in step 1 + On the upper surface of substrate 1, heavily doped N + Layer 31, undoped I-type layer 32, lightly doped P - Layer 33 and heavily doped P + Layer 34; its growth method includes but is not limited to chemical vapor deposition method, molecular beam epitaxy method, etc.;

[0055] Step 3: After growing heavily doped P on the upper surface in step 2 + Detector N of layer 34 + On the lower surface of the substrate 1, a back electrode 2 is grown; its growth method includes but is not limited to magnetron sputtering method, electron beam evaporation method, etc.;

[0056] Step 4: After the back electrode 2 is grown in step 3, the heavily doped P + On the upper surface of layer 34, the semiconductor vertical line structure 3 region is delineated by photolithography and etched. During etching, the heavily doped P grown in step 2 is + Starting from the upper surface of layer 34, from top to bottom, the heavily doped P + Layer 34, lightly doped P - Layer 33, undoped I-type layer 32, heavily doped N + Layer 31, until it reaches detector N + The upper surface of substrate 1 is etched to obtain an array of spaced arrangement grown on detector N + A plurality of semiconductor vertical line structures 3 on the upper surface of the substrate 1;

[0057] Step 5: growing a porous nanomaterial layer 4 on the outer surface of each of the semiconductor vertical line structures 3 etched in step 4 to cover each of the semiconductor vertical line structures 3; the growing method includes but is not limited to pulsed laser deposition, chemical vapor deposition, electrolytic corrosion, etc.;

[0058] Step 6: Coat the outer surface of the porous nanomaterial layer 4 corresponding to each of the semiconductor vertical line structures 3 on which the porous nanomaterial layer 4 is grown in step 5, so as to cover the porous nanomaterial layer 4, and obtain an array of spaced arrangement arranged in the detector N. + A plurality of quantum dot-vertical line units on the upper surface of the substrate 1; when coating the quantum dot material layer 5, the coating method includes but is not limited to spin coating, spray coating, etc.;

[0059] Step 7: The gaps between the quantum dot-vertical line units obtained in step 6 and the outer circle of positions surrounding all the quantum dot-vertical line units are filled with a passivation material, and the passivation material is heat-treated to form a thermosetting polymer, i.e., a passivation layer 6 is formed;

[0060] Step 8: Use an etching process to remove excess passivation material on the passivation layer 6 formed in step 7 to expose the top of each of the quantum dot-vertical line units obtained in step 6; then grow a front electrode 7 on the outer surface of the protruding portion of the passivation layer 6 on the top of each quantum dot-vertical line unit; when growing the front electrode 7, its growth method includes but is not limited to magnetron sputtering, etc.; complete the preparation of the quantum dot-vertical line avalanche diode single-photon detector.

[0061] In summary, the quantum dot-vertical linear avalanche diode single-photon detector of the present invention effectively reduces the unit pixel area on the basis of improving the photon detection efficiency, which is beneficial to reducing the pixel center distance and the total area of ​​a single chip, and improves the upper limit of the single-photon detector array scale. And when the preparation method of the quantum dot-vertical linear avalanche diode single-photon detector of the present invention is adopted, when preparing the quantum dot-vertical linear avalanche diode single-photon detector, the preparation process is simple, the process parameters are easy to control, and the preparation cost is low.

Claims

1. A quantum dot-vertical line avalanche diode single photon detector, characterized in that: Including detector N + Substrate (1), grown on detector N + The back electrode (2) on the lower surface of the substrate (1) is arranged in an array at intervals on the detector N + A plurality of quantum dot-vertical line units on the upper surface of a substrate (1), further comprising a passivation layer (6) and a front electrode (7); Each of the quantum dot-vertical line units comprises a semiconductor vertical line structure (3), a porous nanomaterial layer (4) and a quantum dot material layer (5); The semiconductor vertical line structure (3) is grown on the detector N + On the upper surface of the substrate (1), there are heavily doped N + layer (31), an undoped I-type layer (32), a lightly doped P - layer (33) and heavily doped P + The porous nanomaterial layer (34) is grown on the outer surface of the semiconductor vertical line structure (3) to cover the semiconductor vertical line structure (3); the quantum dot material layer (5) is coated on the outer surface of the porous nanomaterial layer (4) to cover the porous nanomaterial layer (4); the quantum dot material layer (5) is used to absorb photons; the porous nanomaterial layer (4) is used to absorb photogenerated excitons and realize separation of electrons and holes; the semiconductor vertical line structure (3) is used to realize photogenerated carrier multiplication; The passivation layer (6) fills the gaps between the quantum dot-vertical line units and the outer circle surrounding all the quantum dot-vertical line units; The upper surface of the passivation layer (6) is parallel to the detector N + The upper surface of the substrate (1) is higher than the heavily doped P + The lower surface of the layer (34), the top of the quantum dot-vertical line unit extends out of the upper surface of the passivation layer (6); The front electrode (7) is grown on the outer surface of the portion of the top of each quantum dot-vertical line unit extending out from the upper surface of the passivation layer (6), and its lower surface is coplanar with the upper surface of the passivation layer (6), covering the upper surface of the passivation layer (6) and the outer surface of the portion of the top of each quantum dot-vertical line unit extending out from the upper surface of the passivation layer (6).

2. The quantum dot-vertical line avalanche diode single photon detector according to claim 1, characterized in that: The detector N + Substrate (1) refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; The heavily doped N + Layer (31) refers to a doping concentration range of 5×10 17 cm -3 Up to 1×10 20 cm -3 N-type semiconductor layer; the lightly doped P - Layer (33) refers to a doping concentration range of 1×10 15 cm -3 Up to 5×10 16 cm -3 P-type semiconductor layer; the heavily doped P + Layer (34) refers to a doping concentration in the range of 5×10 17 cm -3 Up to 1×10 20 cm -3 A P-type semiconductor layer; The radial dimension of the horizontal cross section of the semiconductor vertical line structure (3) is greater than or equal to 10 nm and less than or equal to 10 μm.

3. The quantum dot-vertical line avalanche diode single photon detector according to claim 1, characterized in that: The height of the top of the quantum dot-vertical line unit protruding from the upper surface of the passivation layer (6) is greater than or equal to 10 nm and less than or equal to 1 μm.

4. The quantum dot-vertical line avalanche diode single photon detector according to any one of claims 1 to 3, characterized in that: The detector N + The materials of the substrate (1) and the semiconductor vertical line structure (3) are silicon, germanium or III-V group semiconductor materials; The material of the porous nanomaterial layer (4) is a two-dimensional material; The material of the quantum dot material layer (5) is lead sulfide, indium phosphide, cadmium selenide or indium arsenide; The material of the passivation layer (6) is benzocyclobutene, SU-8 resin or spin-on glass.

5. The quantum dot-vertical line avalanche diode single photon detector according to claim 4, characterized in that: The front electrode (7) is made of a transparent conductive film; The material of the back electrode (2) is a metal material or a laminated material of multiple metals.

6. A method for preparing a quantum dot-vertical linear avalanche diode single-photon detector, characterized in that: The following steps are involved: Step 1: Prepare the detector N according to the size and material requirements of the quantum dot-vertical linear avalanche diode single photon detector to be prepared. + Substrate (1); Step 2: The detector N prepared in step 1 + On the upper surface of the substrate (1), heavily doped N + layer (31), an undoped I-type layer (32), a lightly doped P - layer (33) and heavily doped P + Layer (34); Step 3: After growing heavily doped P on the upper surface in step 2 + Detector N of layer (34) + A back electrode (2) is grown on the lower surface of the substrate (1); Step 4: After the back electrode (2) is grown in step 3, the heavily doped P + On the upper surface of the layer (34), the semiconductor vertical line structure (3) region is delineated by photolithography and then etched. During the etching, the heavily doped P grown in step 2 is + Starting from the upper surface of layer (34), from top to bottom, the heavily doped P + Layer (34), lightly doped P - layer (33), an undoped I-type layer (32), a heavily doped N + Layer (31) until it reaches detector N + The upper surface of the substrate (1) is etched to obtain an array of spaced-apart structures grown on the detector N + A plurality of semiconductor vertical line structures (3) on the upper surface of the substrate (1); Step 5: growing a porous nanomaterial layer (4) on the outer surface of each semiconductor vertical line structure (3) obtained by etching in step 4, so as to cover each semiconductor vertical line structure (3); Step 6: Coating a quantum dot material layer (5) on the outer surface of the porous nano material layer (4) corresponding to each of the semiconductor vertical line structures (3) on which the porous nano material layer (4) is grown in step 5, so as to cover the porous nano material layer (4) and obtain an array of spaced arrangement arranged on the detector N + A plurality of quantum dot-vertical line units on the upper surface of a substrate (1); Step 7: The gaps between the quantum dot-vertical line units obtained in step 6 and the outer circle of positions surrounding all the quantum dot-vertical line units are filled with a passivation material, and the passivation material is heat-treated to form a thermosetting polymer, i.e., a passivation layer (6) is formed; Step 8: Using an etching process to remove the excess passivation material on the passivation layer (6) formed in step 7 to expose the top of each quantum dot-vertical line unit obtained in step 6; then growing a front electrode (7) on the outer surface of the protruding portion of the passivation layer (6) on the top of each quantum dot-vertical line unit; completing the preparation of the quantum dot-vertical line avalanche diode single-photon detector.

7. The method for preparing the quantum dot-vertical linear avalanche diode single photon detector according to claim 6, characterized in that: In step 2, the detector N prepared in step 1 + On the upper surface of the substrate (1), heavily doped N + layer (31), an undoped I-type layer (32), a lightly doped P - layer (33) and heavily doped P + When the layer (34) is grown, the growth method adopts chemical vapor deposition method or molecular beam epitaxy method.

8. The method for preparing the quantum dot-vertical linear avalanche diode single photon detector according to claim 7, characterized in that: When the porous nano material layer (4) is grown in step 5, the growth method is pulsed laser deposition, chemical vapor deposition or electrolytic corrosion.

9. The method for preparing the quantum dot-vertical linear avalanche diode single photon detector according to claim 8, characterized in that: When coating the quantum dot material layer (5) in step 6, the coating is performed by spin coating or spray coating.

10. The method for preparing the quantum dot-vertical linear avalanche diode single photon detector according to claim 9, characterized in that: When growing the back electrode (2) in step 3, the growth method is magnetron sputtering or electron beam evaporation; When the front electrode (7) is grown in step 8, the growth method is magnetron sputtering.

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