Chip packaging structure and preparation method of chip packaging structure

Abstract

The invention relates to a chip packaging structure and a preparation method of the chip packaging structure, and relates to the technical field of chip packaging, the chip packaging structure comprises a substrate, a supporting glue layer, an induction chip, a wiring layer, a processing chip, a plastic package body and a first conductive column, the processing chip is attached to the wiring layer and is connected to a second bonding pad, and the first conductive column is connected to the plastic package body. According to the utility model, the electrical connection with the sensing chip is realized, the sensing chip and the processing chip can be directly stacked, the processing chip can be directly connected with the wiring layer, and the wiring layer can be directly connected with the sensing chip through the step groove, so that rewiring outside the plastic package body is not needed, the transmission path between the chips is reduced, and the cost is reduced. The transmission speed is improved, and the chip performance is further improved. And moreover, the step groove is arranged, so that the binding force among the wiring layer, the plastic package body and the sensing chip is also improved, and warping layering is avoided.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and more specifically, to a chip packaging structure and a method for preparing the chip packaging structure. Background Art

[0002] The types and structures of sensor chips are constantly updated, and sensor chips such as charge coupled devices (CCD), CMOS chips, and contact image sensors (CIS) have been developed. Generally, in practical applications, sensor chips need to be packaged to form sensor devices for use. Usually, the photosensitive chip and the processor chip need to be packaged together to meet the high performance of the sensor chip and achieve miniaturization. The packaged products are small in size, superior in product performance, and fast in signal processing speed. The products are mainly used in miniaturized and thin graphics processing terminal products.

[0003] The inventors have discovered through research that the stacked structure formed by the sensor chip and the processing chip in the prior art usually requires rewiring on the outside of the plastic package. Both the sensor chip and the processing chip are connected to the external wiring layer through conductive columns. This results in a longer transmission path between the sensor chip and the processing chip, which is prone to processing delays and is not conducive to improving device performance. Summary of the invention

[0004] The purpose of the present application is to provide a chip packaging structure and a method for preparing the chip packaging structure, which can form stacked chips and can reduce the transmission path between chips, increase the transmission speed, and thereby improve chip performance.

[0005] In order to achieve the above object, the present invention is implemented by the following scheme: In a first aspect, the present invention provides a chip packaging structure, comprising: substrate; A supporting adhesive layer, the supporting adhesive layer is disposed on the substrate and is provided with a sensing groove; A sensing chip, wherein the sensing chip is arranged on the supporting adhesive layer, and a sensing area and an electrical bump are arranged on the front side of the sensing chip, the electrical bump is bonded to the supporting adhesive layer, and the sensing area is correspondingly bonded to the sensing groove; A wiring layer, the wiring layer is arranged on the back side of the sensing chip and is electrically connected to the electrical bump, and a first pad and a second pad are arranged on the wiring layer; a processing chip mounted on the wiring layer and connected to the second pad; A plastic package, the plastic package being disposed on the wiring layer and covering the processing chip; A first conductive column, wherein the first conductive column is embedded in the plastic package and connected to the first pad, and the first conductive column is spaced apart from the processing chip and exposed from the plastic package; Wherein, a step groove is arranged on the back side of the sensing chip, the step groove exposes the electrical bump, and the wiring layer extends to the side wall and the bottom wall of the step groove.

[0006] In an optional embodiment, the step groove has a first step and a second step, the distance between the first step and the substrate is greater than the distance between the second step and the substrate, the second step is also provided with an opening exposing the electrical bump, the wiring layer covers the first step and the second step, and extends into the opening to electrically contact the electrical bump.

[0007] In an optional embodiment, the second pad is disposed on the back side of the sensing chip and is spaced apart from the step groove, and the first pad is disposed on the first step and / or the second step so that the first conductive column is bonded to the first step and / or the second step.

[0008] In an optional embodiment, the first conductive pillar is disposed on at least two sides of the sensing chip, and one end of the first conductive pillar is connected to the first step.

[0009] In an optional implementation manner, a solder ball is further disposed at one end of the first conductive column that is exposed from the plastic package body.

[0010] In an optional embodiment, the wiring layer includes a first dielectric layer, a conductive layer and a second dielectric layer, the first dielectric layer is arranged on the back side of the sensing chip, the conductive layer is arranged on the first dielectric layer and is electrically contacted with the electrical bump, the second dielectric layer is arranged on the first dielectric layer and covers the conductive layer, and the first pad and the second pad are both arranged on the second dielectric layer and connected to the conductive layer.

[0011] In an optional embodiment, the second pad is disposed on the first step, the processing chip is flip-chip bonded to the back of the sensing chip, and a second conductive column is disposed at an edge of the processing chip, the second conductive column is embedded in the plastic package and connected to the second pad.

[0012] In an optional embodiment, the first pad is disposed on the back side of the sensing chip and is spaced apart from the step groove, and the first conductive column is embedded in the plastic package and connected to the first pad.

[0013] In an optional embodiment, an adhesive layer is further provided in an area of ​​the back side of the sensing chip where the step groove is not provided, and the processing chip is fixed to the back side of the sensing chip through the adhesive layer.

[0014] In an optional embodiment, a third conductive column is further provided at the edge of the processing chip, a third pad is provided on the wiring layer on the second step, and the third conductive column is embedded in the plastic package and connected to the third pad.

[0015] In an optional embodiment, a support column is provided on the wiring layer on the first step and / or the second step, and the support column extends in a direction away from the substrate and is gap-matched with a surface of the processing chip on one side close to the substrate.

[0016] In an optional embodiment, a protective column is further provided on the wiring layer on the first step and / or the second step, the protective column extends in a direction away from the substrate and is located outside the processing chip, and the protective column is gap-matched with the side wall of the processing chip.

[0017] In a second aspect, the present invention provides a method for preparing a chip packaging structure, which is used to prepare the chip packaging structure as described in the above embodiment, and the preparation method comprises: providing a substrate; forming a supporting adhesive layer on the substrate, and forming a sensing groove on the supporting adhesive layer; A wafer is attached to the supporting adhesive layer, wherein the wafer includes a plurality of sensing chips, a sensing area and an electrical bump are provided on the front of the sensing chip, the electrical bump is bonded to the supporting adhesive layer, and the sensing area is correspondingly bonded to the sensing groove; Etching the wafer and forming a step groove on the back side of the sensor chip, wherein the step groove exposes the electrical bump; forming a wiring layer on the wafer, wherein the wiring layer extends to the side wall and the bottom wall of the step groove, and a first pad and a second pad are disposed on the wiring layer; mounting a processing chip on the wiring layer, wherein the processing chip is connected to the second pad; forming a plastic package on the wiring layer, wherein the plastic package covers the processing chip; A first conductive column is formed in the plastic package, wherein the first conductive column is connected to the first pad, and the first conductive column is spaced apart from the processing chip and exposed from the plastic package.

[0018] Through the above technical scheme, the chip packaging structure and preparation method provided by the embodiment of the present invention form a supporting glue layer on the substrate, the supporting glue layer is provided with a sensing groove, and the sensing chip is arranged on the supporting glue layer, and the sensing area corresponds to the sensing groove, and the electrical bump is bonded to the supporting glue block downward, and the back of the sensing chip is formed with a step groove, and the step groove can expose the electrical bump. In addition, a wiring layer is also provided on the back of the sensing chip, and the wiring layer extends to the side wall and bottom wall of the step groove, and electrically contacts the electrical bump to achieve electrical connection with the sensing chip, and the first conductive column is embedded in the plastic package and connected to the first pad on the wiring layer, so as to achieve electrical connection with the wiring layer. The processing chip is mounted on the wiring layer and connected to the second pad to achieve electrical connection with the sensing chip. Compared with the prior art, the embodiment of the present invention can directly stack the sensing chip and the processing chip, and the processing chip can be directly connected to the wiring layer, and the wiring layer can be directly connected to the sensing chip through the step groove, so there is no need to rewire outside the plastic package, which reduces the transmission path between the chips, improves the transmission speed, and thus improves the chip performance. In addition, the step groove setting also improves the bonding strength between the wiring layer, the plastic package and the sensor chip, avoiding warping and delamination.

[0019] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A front view of a chip packaging structure provided in the first embodiment of the present application; Figure 2 A top view of the chip packaging structure provided in the first embodiment of the present application; Figures 3 to 9 A process flow chart of a method for preparing a chip packaging structure provided in the first embodiment of the present application; Fig.10 A front view of a chip packaging structure provided in the second embodiment of the present application; Fig.11 A top view of a chip packaging structure provided in a second embodiment of the present application; Fig.12 A schematic diagram of a chip packaging structure provided in the third embodiment of the present application; Fig.13A schematic diagram of a chip packaging structure provided in the fourth embodiment of the present application.

[0022] icon: 100-chip packaging structure; 110-substrate; 120-supporting adhesive layer; 121-sensing groove; 130-sensing chip; 131-sensing area; 132-electrical bump; 133-adhesive layer; 140-wiring layer; 141-first dielectric layer; 142-conductive layer; 143-second dielectric layer; 150-processing chip; 151-second solder pad; 152-second conductive column; 153-third conductive column; 154-support column; 155-protective column; 156-third solder pad; 160-plastic package; 170-first conductive column; 171-first solder pad; 172-solder ball; 180-step groove; 181-first step; 182-second step. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the technical scheme in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0024] In the description of this application, it should be noted that the terms "inside", "outside", etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship in which the product of the application is usually placed when in use, which is only for the convenience of describing this application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application. In addition, the terms "first", "second", etc. are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0025] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "disposed" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0026] As disclosed in the background technology, the sensing packaging structure in the prior art usually requires re-wiring on the outside of the plastic package, and the sensor chip and the processing chip are both connected to the external wiring layer through conductive pillars. This results in a long transmission path between the sensor chip and the processing chip passing through the conductive pillars twice, which is prone to processing delays and is not conducive to improving device performance.

[0027] Furthermore, the wiring layer and the plastic package in the prior art are in planar contact, resulting in poor bonding between the two, and the plastic package or wafer is prone to warping, which in turn leads to delamination between the wiring layer and the plastic package, affecting the stability of the device structure. In addition, the stacking structure of the processing chip and the sensing chip in the prior art has poor structural stability.

[0028] In order to solve the above problems, the embodiments of the present invention provide a novel chip packaging structure and a method for preparing the chip packaging structure. It should be noted that the features in the embodiments of the present application can be combined with each other without conflict.

[0029] First embodiment See also Figure 1 and Figure 2 The chip packaging structure 100 provided in the embodiment of the present invention can form stacked chips, and can reduce the transmission path between chips, improve the transmission speed, and thus improve the chip performance.

[0030] The chip packaging structure 100 provided in the embodiment of the present invention includes a substrate 110, a supporting adhesive layer 120, a sensing chip 130, a wiring layer 140, a processing chip 150, a plastic package 160 and a first conductive column 170. The supporting adhesive layer 120 is arranged on the substrate 110 and is provided with a sensing groove 121. The sensing chip 130 is arranged on the supporting adhesive layer 120, and the front side of the sensing chip 130 is provided with a sensing area 131 and an electrical bump 132. The electrical bump 132 is bonded to the supporting adhesive layer 120, and the sensing area 131 is correspondingly bonded to the sensing groove 121. The wiring layer 140 is arranged on the back side of the sensing chip 130 and is bonded to the electrical bump 131. 2 is electrically connected, and a first pad 171 and a second pad 151 are provided on the wiring layer 140; the processing chip 150 is mounted on the wiring layer 140 and connected to the second pad 151; the plastic package 160 is provided on the wiring layer 140 and covers the processing chip 150; the first conductive column 170 is embedded in the plastic package 160 and connected to the first pad 171, and the first conductive column 170 is spaced from the processing chip 150 and exposed from the plastic package 160; wherein a step groove 180 is provided on the back of the sensing chip 130, the step groove 180 exposes the electrical bump 132, and the wiring layer 140 extends to the side wall and the bottom wall of the step groove 180.

[0031] In this embodiment, the substrate 110 may be glass, silicon, a polymer composite material or a metal material. The sensing chip 130 may be an image sensor chip, and its sensing area 131 corresponds to the sensing groove 121 on the supporting glue layer 120. In this case, the substrate 110 needs to be made of a transparent material. Alternatively, the sensing chip 130 may also be a gyroscope, a capacitive sensing chip 130, etc., and in this case, the substrate 110 may be made of an opaque material. Among them, the supporting glue layer 120 may be a thermosetting glue layer, using a polymer composite material such as epoxy resin, polyimide, benzocyclobutene, etc. The supporting glue layer 120 can fix the wafer, and multiple sensing chips 130 can be distributed on the wafer. The embodiment of the present invention can directly stack the sensing chip 130 and the processing chip 150, and the processing chip 150 can be directly connected to the wiring layer 140. The wiring layer 140 can be directly connected to the sensing chip 130 through the step groove setting, so there is no need to rewire outside the plastic package 160, which reduces the transmission path between the chips, improves the transmission speed, and thus improves the chip performance. Furthermore, the step groove arrangement also improves the bonding strength among the wiring layer 140 , the plastic package 160 and the sensor chip 130 , thereby preventing warping and delamination.

[0032] In this embodiment, the step groove 180 has a first step 181 and a second step 182, the distance between the first step 181 and the substrate 110 is greater than the distance between the second step 182 and the substrate 110, and the second step 182 is also provided with an opening to expose the electrical bump 132, and the wiring layer 140 covers the first step 181 and the second step 182, and extends into the opening to electrically contact the electrical bump 132. Specifically, the first step 181 and the second step 182 can be formed by two slotting processes, and the slot sizes in the two slottings are different, so that the first step 181 and the second step 182 arranged in a staggered manner can be formed. At the same time, the second step 182 can continue to be slotted to expose the electrical bump 132, so as to ensure that the wiring layer 140 is laid on the first step 181 and the second step 182, and is in electrical contact with the electrical bump 132. Among them, the setting of the first step 181 and the second step 182 adopts two slotting processes of different sizes, which reduces the difficulty of slotting and ensures the slotting accuracy. At the same time, the staggered arrangement between the first step 181 and the second step 182 and the distribution of the wiring layer 140 on the first step 181 and the second step 182 can further increase the contact area between the plastic package 160, the wiring layer 140 and the sensor chip 130, thereby enhancing the bonding strength of the three and avoiding warping and stratification of the plastic package 160 or the wafer.

[0033] In this embodiment, the second pad 151 is arranged on the wiring layer 140 on the back of the sensing chip 130 and is spaced from the step groove 180. The first pad 171 is arranged on the first step 181 and / or the second step 182 so that the first conductive column 170 is bonded to the first step 181 and / or the second step 182. Preferably, the first pad 171 is arranged on the first step 181 so that the first conductive column 170 can be bonded to the first step 181. Among them, a convex mesa is formed in the middle of the back of the sensing chip 130, and the step groove is arranged at the edge of the convex mesa. The convex mesa is the ungrooved area on the back of the sensing chip 130, and the processing chip 150 is arranged on the convex mesa. And the horizontal size of the processing chip 150 is less than or equal to the horizontal size of the convex mesa, so that the density of the processing chip 150 can be improved, for example, multiple processing chips 150 can be arranged. In addition, by bonding the first conductive column 170 to the relatively high first step 181, the transmission path between the wiring layer 140 and the outside can be further shortened.

[0034] In this embodiment, the first conductive pillars 170 are disposed on at least two sides of the sensing chip 130, and one end of the first conductive pillars 170 is bonded to the first step 181. Specifically, the first conductive pillars 170 can be disposed around the sensing chip 130 and are arranged in a rectangular shape around the convex surface. A solder ball 172 is also disposed on one end of each first conductive pillar 170 exposed from the plastic package 160, so as to achieve connection with an external circuit board.

[0035] In this embodiment, the wiring layer 140 includes a first dielectric layer 141, a conductive layer 142, and a second dielectric layer 143. The first dielectric layer 141 is arranged on the back of the sensing chip 130, the conductive layer 142 is arranged on the first dielectric layer 141, and is in electrical contact with the electrical bump 132, the second dielectric layer 143 is arranged on the first dielectric layer 141, and covers the conductive layer 142, and the first pad 171 and the second pad 151 are both arranged on the second dielectric layer 143 and connected to the conductive layer 142. Specifically, the first dielectric layer 141 and the second dielectric layer 143 are both dielectric materials, such as polymer composite materials such as epoxy resin, polyimide, and benzocyclobutene. At the same time, the conductive layer 142 can be a conductive metal layer, such as a copper layer, which has a better conductive effect.

[0036] This embodiment also provides a method for preparing a chip packaging structure 100, which is used to prepare the aforementioned chip packaging structure 100. The preparation method comprises the following steps: S1: Provide a substrate 110.

[0037] Specifically, a wafer can be first taken for use, and then a substrate 110 can be taken. The substrate 110 can also be a carrier. The substrate 110 can be made of glass, silicon, polymer composite materials, metal and other materials. The substrate 110 can be determined according to the specific type of the sensor chip 130. When the sensor chip 130 is an image sensor chip, it is necessary to ensure that the substrate 110 meets the transparent characteristics. If the sensor chip 130 is other sensor chips, such as a gyroscope or a capacitive sensor chip 130, the substrate 110 can also be made of opaque materials.

[0038] S2 : forming a supporting adhesive layer 120 on the substrate 110 , and forming a sensing groove 121 on the supporting adhesive layer 120 .

[0039] See also Figure 3 Specifically, a liquid adhesive layer may be firstly coated on the surface of the substrate 110 by a coating machine in a spin coating manner, and then soft-baked on a hot plate to form a film to form a supporting adhesive layer 120, and then a sensing groove 121 may be formed on the supporting adhesive layer 120 by an etching process. The sensing groove 121 penetrates the supporting adhesive layer 120 and partially exposes the substrate 110.

[0040] S3: placing the wafer on the supporting adhesive layer 120 .

[0041] See also Figure 4 , wherein the wafer includes a plurality of sensing chips 130, and the front of the sensing chip 130 is provided with a sensing area 131 and an electrical bump 132, the electrical bump 132 is bonded to the supporting glue layer 120, and the sensing area 131 is correspondingly bonded to the sensing groove 121. Specifically, the electrical bump 132 is located on at least two sides of the sensing area 131. When mounting the wafer, the sensing area 131 of the sensing chip 130 can be aligned with the sensing groove 121 through an alignment process, and the electrical bump 132 can be bonded to the supporting glue layer 120 on both sides of the sensing groove 121. The supporting glue layer 120 can be used to fix the wafer, and finally the supporting glue layer 120 is cured by baking.

[0042] S4 : etching the wafer and forming a step groove 180 on the back side of the sensor chip 130 .

[0043] See also Figure 5, wherein the step groove 180 exposes the electrical bump 132. The etching of the step groove 180 can be divided into three etching processes. First, the back of the wafer is etched using plasma etching technology (using plasma dry etching with a mixture of O2 and SF6) or chemical etching technology (using a mixed agent such as phosphoric acid, acetic acid, hydrogen chloride, sulfuric acid, etc. for etching), or the back of the wafer is thinned by grinding, first etching to form the first step 181, then etching again to form the second step 182, and finally etching to expose the electrical bump 132 of the wafer. Among them, the groove width of the first step 181 is greater than the groove width of the second step 182. After three etchings, the electrical bump 132 of the wafer can be exposed.

[0044] S5: forming a wiring layer 140 on the wafer.

[0045] See also Figure 6 , wherein the wiring layer 140 extends to the side wall and the bottom wall of the step groove 180, and the wiring layer 140 is provided with a first pad 171 and a second pad 151. Specifically, after etching the back side of the wafer, the first dielectric layer 141 can be coated on the back side of the wafer by a spin coating process, and then the first dielectric layer 141 is covered with a photomask, and a pattern layer opening is formed by an exposure and development process, and then a conductive layer 142 is formed by electroplating by an electroplating process, and finally a second dielectric layer 143 is formed by a spin coating process again. The first dielectric layer 141 and the second dielectric layer 143 can both be polymer composite materials such as epoxy resin, polyimide, and benzocyclobutene. Finally, the second dielectric layer 143 is covered with a photomask again, and then a pattern layer opening is formed by an exposure and development process, and then a metal pad is formed by electroplating in the pattern layer opening by an electroplating process, thereby forming a first pad 171 and a second pad 151, wherein the first pad 171 is located on the first step 181, and the second pad 151 is located on the convex surface of the back side of the wafer.

[0046] S6 : Mounting the processing chip 150 on the wiring layer 140 .

[0047] See also Figure 7 , wherein the processing chip 150 is connected to the second pad 151. Specifically, the processing chip 150 is mounted on the wiring layer 140 using a flip-chip process, and the bumps of the processing chip 150 are correspondingly connected to the second pad 151, and then fixed by reflow soldering to complete the stacking, thereby achieving electrical connection between the processing chip 150 and the wiring layer 140.

[0048] S7 : forming a plastic package 160 on the wiring layer 140 .

[0049] See also Figure 8, wherein the plastic package 160 covers the processing chip 150. Specifically, the plastic package 160 can be prepared on the wiring layer 140 by using a plastic package process, and the plastic package 160 can play the role of a protective layer. The plastic package material can be a polymer composite material such as epoxy resin, polyimide, benzocyclobutene, etc.

[0050] S8: forming a first conductive column 170 in the plastic package body 160 .

[0051] See also Fig. 9 , wherein the first conductive column 170 is connected to the first pad 171, and the first conductive column 170 is spaced apart from the processing chip 150 and exposed to the plastic package 160. Specifically, the plasma etching technology or the laser opening technology can be used again to open a hole in the plastic package 160, and the first pad 171 on the first step 181 is exposed, and then the metal is filled by electroplating to form the first conductive column 170, and then the metal layer is formed on the first conductive column 170 by electroplating, and finally the ball is implanted to form the solder ball 172 on the first conductive column 170. The metal layer can be a nickel-vanadium layer or a titanium-nickel-vanadium layer, and the material of the solder ball 172 can be SnAg or SnAgCu. Finally, a single product is formed by a cutting process.

[0052] In summary, the chip packaging structure 100 and the preparation method thereof provided by the embodiment of the present invention form a supporting glue layer 120 on a substrate 110, the supporting glue layer 120 is provided with a sensing groove 121, and the sensing chip 130 is provided on the supporting glue layer 120, and the sensing area 131 corresponds to the sensing groove 121, and the electrical bump 132 is bonded downward to the supporting glue block, and a step groove 180 is formed on the back of the sensing chip 130, and the step groove 180 can expose the electrical bump 132. In addition, a wiring layer 140 is also provided on the back of the sensing chip 130, and the wiring layer 140 extends to the side wall and the bottom wall of the step groove 180, and is electrically in contact with the electrical bump 132, so as to realize the electrical connection with the sensing chip 130, and the first conductive column 170 is embedded in the plastic package 160, and is connected to the first pad 171 on the wiring layer 140, so as to realize the electrical connection with the wiring layer 140. The processing chip 150 is mounted on the wiring layer 140 and connected to the second pad 151, thereby realizing electrical connection with the sensing chip 130. Compared with the prior art, the embodiment of the present invention can directly stack the sensing chip 130 and the processing chip 150, and the processing chip 150 can be directly connected to the wiring layer 140. The wiring layer 140 can be directly connected to the sensing chip 130 through the step groove setting, so there is no need to rewire outside the plastic package 160, which reduces the transmission path between chips, improves the transmission speed, and thus improves the chip performance. In addition, the step groove setting also improves the bonding force between the wiring layer 140, the plastic package 160 and the sensing chip 130, avoiding warping and delamination.

[0053] Second embodiment See also Fig.10 and Fig.11 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the first embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the first embodiment.

[0054] In this embodiment, the chip packaging structure 100 includes a substrate 110, a supporting glue layer 120, a sensing chip 130, a wiring layer 140, a processing chip 150, a plastic package 160 and a first conductive column 170. The supporting glue layer 120 is arranged on the substrate 110 and is provided with a sensing groove 121; the sensing chip 130 is arranged on the supporting glue layer 120, and the front side of the sensing chip 130 is provided with a sensing area 131 and an electrical bump 132, the electrical bump 132 is bonded to the supporting glue layer 120, and the sensing area 131 is correspondingly bonded to the sensing groove 121; the wiring layer 140 is arranged on the back side of the sensing chip 130 and is electrically connected to the electrical bump 132. The processing chip 150 is mounted on the wiring layer 140 and connected to the second pad 151; the plastic package 160 is arranged on the wiring layer 140 and covers the processing chip 150; the first conductive column 170 is embedded in the plastic package 160 and connected to the first pad 171, and the first conductive column 170 is spaced apart from the processing chip 150 and exposed to the plastic package 160; wherein a step groove 180 is arranged on the back side of the sensing chip 130, the step groove 180 exposes the electrical bump 132, and the wiring layer 140 extends to the side wall and bottom wall of the step groove 180.

[0055] In this embodiment, the step groove 180 has a first step 181 and a second step 182, the distance between the first step 181 and the substrate 110 is greater than the distance between the second step 182 and the substrate 110, and the second step 182 is also provided with an opening to expose the electrical bump 132, and the wiring layer 140 covers the first step 181 and the second step 182, and extends into the opening to electrically contact the electrical bump 132. The second pad 151 is provided on the first step 181, the processing chip 150 is attached to the back of the sensing chip 130, and the edge of the processing chip 150 is provided with a second conductive column 152, which is embedded in the plastic package 160 and connected to the second pad 151.

[0056] In this embodiment, a convex platform is formed in the middle of the back side of the sensor chip 130, and the step groove is arranged at the edge of the convex platform. The horizontal width of the processing chip 150 is greater than the horizontal width of the convex platform, and the edge of the processing chip 150 extends out of the edge of the convex platform. The second conductive column 152 is located outside the edge of the convex platform and is connected to the second pad 151.

[0057] In this embodiment, the first pad 171 is disposed on the back of the sensing chip 130 and is spaced apart from the step groove 180. The first conductive column 170 is embedded in the plastic package 160 and connected to the first pad 171. Specifically, the first pad 171 is spaced apart from the mounting area of ​​the processing chip 150. By arranging the first pad 171 on the boss surface, the distance of the first conductive column 170 can be further shortened, thereby shortening the transmission path between the wiring layer 140 and the external circuit, and improving the performance.

[0058] Furthermore, an adhesive layer 133 is also provided in the area on the back of the sensing chip 130 where the step groove 180 is not provided, and the processing chip 150 is flip-chip fixed to the back of the sensing chip 130 through the adhesive layer 133. Specifically, the adhesive layer 133 is coated on the mounting area of ​​the convex surface and is a non-conductive material. The front of the processing chip 150 can be fixed to the convex surface through the adhesive layer 133 to achieve fixation. What is particularly important is that the fixing effect of the adhesive layer 133 on the processing chip 150 can make the welding performance between the second conductive column 152 and the second pad 151 of the processing chip 150 better during welding, thereby avoiding desoldering or cracking at the welding point (conventional flip-chip direct welding has no fixing effect and is prone to desoldering or cracking).

[0059] It should be noted that in this embodiment, the processing chip 150 is connected to the second pad 151 through the second conductive column 152, and the second pad 151 is located on the first step 181, so that the second conductive column 152 not only plays an electrical connection role, but also can enhance the edge capillary effect, so that the plastic encapsulation material can be filled into the gap between the processing chip 150 and the first step 181, ensuring the filling and fixing effect of the plastic encapsulation body 160. In addition, the plastic encapsulation material is filled between the edge of the processing chip 150 and the first step 181, which can further enhance the bonding force between the plastic encapsulation body 160 and the processing chip 150, thereby further ensuring the stability and reliability of the structure.

[0060] Third embodiment See also Fig.12 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the second embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the second embodiment.

[0061] In this embodiment, a third conductive column 153 is further provided at the edge of the processing chip 150, a third pad 156 is provided on the wiring layer 140 on the second step 182, and the third conductive column 153 is embedded in the plastic package 160 and connected to the third pad 156. Specifically, the third conductive column 153 is electrically connected to the third pad 156, so that the electrical connection effect between the processing chip 150 and the wiring layer 140 is better, and the third conductive column 153 can also play a structural support role, thereby improving the structural stability.

[0062] Further, a support column 154 is provided on the wiring layer 140 on the first step 181 and / or the second step 182, and the support column 154 extends in a direction away from the substrate 110 and is gapped with the surface of the processing chip 150 on one side close to the substrate 110. Specifically, a support column 154 is provided on the wiring layer 140 of the second step 182, and the support column 154 extends toward the front edge of the processing chip 150 and is gapped with the front of the processing chip 150. By providing the support column 154, the processing chip 150 can be positioned for mounting in the actual mounting process, and the capillary action of the support column 154 can further ensure the filling effect of the plastic encapsulation material and improve the stability of the overall structure. Furthermore, by setting up multiple support columns 154, a blocking wall structure can be formed around the edge of the sensing chip 130, and the support columns 154 are made of metal material, which can block external photoelectric signals (such as visible light) and prevent external signals from causing adverse interference to the sensing area (with the setting of the step groove 180, the thinning of the sensing chip 130 will cause the photoelectric signal to enter or exit from the thinning part, thereby affecting the normal function of the sensing area 131), thereby improving the performance of the sensing chip 130.

[0063] Of course, in other preferred embodiments of the present invention, the support column 154 may also be disposed on the first step 181 .

[0064] Fourth embodiment See also Fig.13 This embodiment provides a chip packaging structure 100, whose basic structure, principle and technical effects are the same as those of the second embodiment. For the sake of brief description, for parts not mentioned in this embodiment, reference may be made to the corresponding contents in the second embodiment.

[0065] In this embodiment, a protective column 155 is further provided on the wiring layer 140 on the first step 181 and / or the second step 182. The protective column 155 extends in a direction away from the substrate 110 and is located outside the processing chip 150. The protective column 155 is matched with the sidewall gap of the processing chip 150. Specifically, a protective column 155 is provided on the wiring layer 140 of the first step 181. The protective column 155 extends upward and does not pass through the plastic package 160. The height of the protective column 155 relative to the first step 181 is greater than the height of the back of the processing chip 150 relative to the first step 181, so that the protective column 155 can protrude from the back of the processing chip 150.

[0066] In this embodiment, a support column 154 may be further provided on the wiring layer 140 of the first step 181 . The support column 154 extends upward and is gap-matched with the front surface of the processing chip 150 .

[0067] It should be noted that, in this embodiment, by providing the support column 154, the processing chip 150 can be positioned during the actual mounting process, and the capillary action of the support column 154 can further ensure the filling effect of the plastic packaging material and improve the stability of the overall structure. At the same time, by providing the protective column 155, on the one hand, the capillary action of the plastic packaging material can be further improved to ensure the filling effect, and on the other hand, it can protect the processing chip 150 and the second conductive column 152 to avoid the mold flow impact causing the second conductive column 152 and the second pad 151 to shift. At the same time, when mounting the processing chip 150, the protective column 155 can also play a preliminary positioning role, so that the processing chip 150 can be positioned quickly and accurately. Furthermore, multiple protective columns 155 can form a wall structure, which can be arranged around the sensing area, and the protective columns 155 are also made of metal materials, which can block external photoelectric signals (such as visible light) and prevent external signals from causing adverse interference to the sensing area (with the setting of the step groove 180, the thinning of the sensing chip 130 will cause the photoelectric signal to enter or exit from the thinning part, thereby affecting the normal function of the sensing area 131), thereby improving the performance of the sensing chip 130.

[0068] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging structure, characterized in that: include: substrate; A supporting adhesive layer, the supporting adhesive layer is disposed on the substrate and is provided with a sensing groove; A sensing chip, wherein the sensing chip is arranged on the supporting adhesive layer, and a sensing area and an electrical bump are arranged on the front side of the sensing chip, the electrical bump is bonded to the supporting adhesive layer, and the sensing area is correspondingly bonded to the sensing groove; A wiring layer, the wiring layer is arranged on the back side of the sensing chip and is electrically connected to the electrical bump, and a first pad and a second pad are arranged on the wiring layer; a processing chip mounted on the wiring layer and connected to the second pad; A plastic package, the plastic package being disposed on the wiring layer and covering the processing chip; A first conductive column, wherein the first conductive column is embedded in the plastic package and connected to the first pad, and the first conductive column is spaced apart from the processing chip and exposed from the plastic package; Wherein, a step groove is arranged at the edge of the back side of the sensing chip, the step groove exposes the electrical bump, and the wiring layer extends to the side wall and the bottom wall of the step groove.

2. The chip packaging structure according to claim 1, characterized in that: The step groove has a first step and a second step, the distance between the first step and the substrate is greater than the distance between the second step and the substrate, and the second step is also provided with an opening exposing the electrical bump, the wiring layer covers the first step and the second step, and extends into the opening to electrically contact the electrical bump.

3. The chip packaging structure according to claim 2, characterized in that: The second pad is disposed on the wiring layer on the back side of the sensing chip and is spaced apart from the step groove, and the first pad is disposed on the first step and / or the second step so that the first conductive column is bonded to the first step and / or the second step.

4. The chip packaging structure according to claim 3, characterized in that: The first conductive pillar is disposed on at least two sides of the sensing chip, and one end of the first conductive pillar is connected to the first step.

5. The chip packaging structure according to claim 2, characterized in that: A solder ball is also disposed on one end of the first conductive column exposed from the plastic package body.

6. The chip packaging structure according to claim 2, characterized in that: The wiring layer includes a first dielectric layer, a conductive layer, and a second dielectric layer. The first dielectric layer is arranged on the back side of the sensing chip. The conductive layer is arranged on the first dielectric layer and is in electrical contact with the electrical bump. The second dielectric layer is arranged on the first dielectric layer and covers the conductive layer. The first pad and the second pad are both arranged on the second dielectric layer and are connected to the conductive layer.

7. The chip packaging structure according to claim 2, characterized in that: The second pad is arranged on the first step, the processing chip is flip-chip mounted on the back of the sensing chip, and a second conductive column is arranged on the edge of the processing chip. The second conductive column is embedded in the plastic package and connected to the second pad.

8. The chip packaging structure according to claim 7, characterized in that: The first pad is arranged on the back side of the sensing chip and is spaced apart from the step groove. The first conductive column is embedded in the plastic package and connected to the first pad.

9. The chip packaging structure according to claim 8, characterized in that: An adhesive layer is also provided in the area of ​​the back side of the sensing chip where no step groove is provided, and the processing chip is fixed to the back side of the sensing chip through the adhesive layer.

10. The chip packaging structure according to claim 7, characterized in that: A third conductive column is also arranged at the edge of the processing chip, a third pad is arranged on the wiring layer on the second step, and the third conductive column is embedded in the plastic package and connected to the third pad.

11. The chip packaging structure according to claim 7, characterized in that: A support column is provided on the wiring layer on the first step and / or the second step. The support column extends in a direction away from the substrate and is gap-matched with a surface of the processing chip on one side close to the substrate.

12. The chip packaging structure according to claim 11, characterized in that: A protection column is also provided on the wiring layer on the first step and / or the second step. The protection column extends in a direction away from the substrate and is located outside the processing chip. The protection column is gap-matched with the sidewall of the processing chip.

13. A method for preparing a chip packaging structure, used for preparing the chip packaging structure as claimed in claim 1, characterized in that: The preparation method comprises: providing a substrate; forming a supporting adhesive layer on the substrate, and forming a sensing groove on the supporting adhesive layer; A wafer is attached to the supporting adhesive layer, wherein the wafer includes a plurality of sensing chips, a sensing area and an electrical bump are provided on the front of the sensing chip, the electrical bump is bonded to the supporting adhesive layer, and the sensing area is correspondingly bonded to the sensing groove; Etching the wafer and forming a step groove on the back side of the sensor chip, wherein the step groove exposes the electrical bump; forming a wiring layer on the wafer, wherein the wiring layer extends to the side wall and the bottom wall of the step groove, and a first pad and a second pad are disposed on the wiring layer; mounting a processing chip on the wiring layer, wherein the processing chip is connected to the second pad; forming a plastic package on the wiring layer, wherein the plastic package covers the processing chip; A first conductive column is formed in the plastic package, wherein the first conductive column is connected to the first pad, and the first conductive column is spaced apart from the processing chip and exposed from the plastic package.

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