A method for manufacturing a superlattice infrared detector chip

Abstract

The invention provides a method for manufacturing a superlattice infrared detector chip, belonging to the technical field of infrared detector manufacturing. The invention solves the problem that the current solution for removing a hard mask does not take into account the fluctuation of the precision of the lithography process when removing the hard mask, resulting in low product performance or low product yield. The invention comprises the following steps: hard mask film formation: growing a hard mask of a certain thickness on the surface of a wafer of a superlattice material; upper electrode table photolithography; hard mask etching: using photoresist as a mask and adopting ICP technology to etch the hard mask to obtain an upper electrode table mask pattern; upper electrode table degumming and cleaning; lower electrode table photolithography: using photoresist as a mask for a lower electrode table area and adopting photolithography technology to manufacture a lower electrode table area; table ICP etching; table wet etching; lower electrode table degumming and cleaning; passivation layer film formation; passivation layer opening; gold electrode manufacturing. The invention is applied to the preparation of a superlattice infrared detector chip.

Description

Technical Field

[0001] The invention provides a method for manufacturing a superlattice infrared detector chip, belonging to the technical field of infrared detector manufacturing. Background Art

[0002] With the popularity of small-sized, high-aspect-ratio infrared detectors, the necessity of using hard masks to make infrared detector mesas is becoming increasingly strong. However, when removing the hard mask, although the side walls are protected by photoresist, the alignment accuracy of the photolithography process is limited, which will inevitably cause etching damage to the side walls of the upper electrode mesas, resulting in a decrease in the performance of the infrared detector, or the mesas hard mask will not be completely removed, causing abnormal climbing of the lower electrode and causing a short circuit, resulting in product scrapping. This problem needs to be solved urgently.

[0003] The problems existing in the existing infrared detector manufacturing process are described in detail below.

[0004] like Figure 1 As shown, the ideal process flow is:

[0005] 1) Photolithography process: exposure, development, and etching are performed, and photoresist 2 is used to protect the side wall of the mesa 3 from being damaged by over-etching, thereby obtaining the structure shown in FIG. (1a);

[0006] 2) Etching process: Use RIE (Reactive Ion Etching) to remove the hard mask 1 above the mesa 3 to obtain the structure shown in Figure (1b);

[0007] 3) Cleaning process: remove the photoresist 2 on the side wall of the mesa 3 to obtain the mesa 3 as shown in Figure (1c).

[0008] However, due to the limitation of photolithography alignment accuracy, Figure 2 As shown, the actual situation is as follows:

[0009] 1) In some locations, the photoresist 2 overflows the side wall of the table 3 and covers the table 3, while in some locations, the side wall of the table 3 is not protected by the photoresist 2 and is exposed, as shown in Figure (2a);

[0010] 2) Etching process: RIE etching is used to remove the hard mask 1 on the mesa 3, and part of the photoresist 2 and the hard mask 1 are not removed, as shown in FIG. (2b);

[0011] 3) Cleaning process: remove the photoresist 2 on the sidewall of the mesa 3. It can be seen that when the boundary of the photoresist 2 exceeds the sidewall, part of the photoresist 2 will protect the mesa 3, and the hard mask 1 cannot be removed completely. When the boundary of the photoresist 2 is shorter than the sidewall, part of the sidewall position is not properly protected and will still be affected by etching, and the leakage current will increase. As shown in Figure (2c), there will be some residual hard mask 4 on the mesa 3, and when etching the photoresist 2, it will cause the sidewall etching defect 5 of the mesa 3.

[0012] If the hard mask 1 on the mesa 3 is not removed completely, it will affect the slope of the lower electrode. The main purpose of removing the hard mask 1 is to ensure that the slope of the lower electrode is normal. Figure 3 As shown, the details are as follows:

[0013] 1) Deposition, photolithography and etching of hard mask 1 to obtain the structure shown in Figure (3a);

[0014] 2) ICP etching to obtain the structure shown in Figure (3b);

[0015] 3) Wet etching: In order to ensure the side wall morphology of the upper electrode table 3, wet etching will be performed for 30~60s to remove the dangling bonds on the side wall surface. Due to the severe side etching of wet etching, this will cause the hard mask 1 to protrude from the table 3. The effect is shown in Figure (3c):

[0016] 4) Removing the hard mask 1: Since the photoresist 2 protects the sidewall of the mesa 3, part of the hard mask 1 cannot be removed, resulting in a residual hard mask 4 as shown in FIG. (3d);

[0017] 5) The residual hard mask 4 will cause the gold electrode 8 at the lower electrode position to climb abnormally, the lower electrode to break abnormally, and the product to be scrapped, as shown in Figure (3e). Summary of the invention

[0018] The current solution for removing the hard mask does not take into account the fluctuation in the accuracy of the lithography process when removing the hard mask, resulting in abnormal climbing of the gold electrode at some lower electrode mesas and over-engraving of the side walls at some upper electrode mesas, which increases the leakage current and reduces the product performance. In order to solve the above technical problems, the present invention proposes a method for manufacturing a superlattice infrared detector chip.

[0019] The technical solution adopted by the present invention is: a method for manufacturing a superlattice infrared detector chip, comprising the following steps:

[0020] S1.1: Hard mask film formation: grow a hard mask of a set thickness on the surface of the wafer of superlattice material;

[0021] S1.2: Photolithography of upper electrode mesa: The upper electrode mesa region is fabricated on the hard mask using photolithography technology;

[0022] S1.3: Hard mask etching: Using photoresist as a mask, ICP technology is used to etch the hard mask to obtain the upper electrode table mask pattern;

[0023] S1.4: Degumming and cleaning of the upper electrode surface;

[0024] S1.5: Photolithography of the lower electrode mesa: Photoresist is used as a mask for the lower electrode mesa region, and the lower electrode mesa region is produced by photolithography technology;

[0025] S1.6: Terrane ICP etching: ICP technology is used to etch the hard mask to obtain the upper electrode terrace pattern and the lower electrode terrace pattern;

[0026] S1.7: Mesa wet etching: wet etching the upper and lower electrodes to remove the side wall dangling bonds;

[0027] S1.8: Degumming and cleaning of the lower electrode table;

[0028] S1.9: Passivation layer film formation;

[0029] S1.10: Opening of passivation layer;

[0030] S1.11: Fabrication of gold electrodes.

[0031] Furthermore, the material of the hard mask in step S1.1 is SiO2 or Si3N4 material.

[0032] Furthermore, step S1.2 specifically includes: placing the wafer with the hard mask grown thereon into a plasma glue coating machine without a metal cover to remove surface impurities; then coating with adhesive; and then spinning, exposing, developing, vertically coating, and removing residual photoresist at the edge of the image.

[0033] Furthermore, in step S1.7, a mixed solution of phosphoric acid, citric acid and hydrogen peroxide is used to corrode the superlattice material.

[0034] Furthermore, step S1.11 specifically includes: using negative photoresist L300 to perform gold electrode lithography, then using electron beam evaporation technology to evaporate Ti / Pt / Au metal, placing the wafer with the evaporated metal in acetone, waiting for a period of time, using acetone to blow off the surface of the material to complete metal stripping; after the metal is stripped clean, wash the wafer with anhydrous ethanol and deionized water in turn, and blow dry with nitrogen, and the preparation of the unit detector chip is officially completed.

[0035] A method for manufacturing a superlattice infrared detector chip comprises the following steps:

[0036] S2.1: Hard mask film formation: growing a hard mask of a certain thickness on the surface of the wafer of superlattice material;

[0037] S2.2: mesa lithography: using photolithography technology to make the upper electrode mesa region and the lower electrode mesa region on the hard mask;

[0038] S2.3: Hard mask etching: using photoresist as a mask, the hard mask is etched using ICP technology to obtain the upper electrode mesa mask pattern and the lower electrode mesa mask pattern;

[0039] S2.4: degumming and cleaning;

[0040] S2.5: Terrane ICP etching: ICP technology is used to etch the hard mask to obtain the upper electrode terrace pattern and the lower electrode terrace pattern;

[0041] S2.6: Mesa wet etching: wet etching the upper and lower electrodes to remove the side wall dangling bonds;

[0042] S2.7: removing the bottom electrode mesa hard mask;

[0043] S2.8: degumming and cleaning;

[0044] S2.9: Passivation layer film formation;

[0045] S2.10: Opening of passivation layer;

[0046] S2.11: Fabrication of gold electrodes.

[0047] Furthermore, the material of the hard mask in step S2.1 is SiO2 or Si3N4 material.

[0048] Furthermore, the degumming and cleaning steps in steps S2.4 and S2.8 are as follows: first, the wafer is placed in an acetone water bath and heated for 10-20 minutes to remove the photoresist on the surface of the wafer, and then the wafer surface is cleaned with anhydrous ethanol and deionized water in turn.

[0049] Furthermore, in step S2.7, the lower electrode mesa hard mask is removed by photolithography technology and ICP technology.

[0050] Furthermore, in step S2.7, the hard mask of the lower electrode mesa is removed by using a photolithography mask, and the exposure position of the photolithography mask only covers the lower electrode mesa.

[0051] The beneficial effects of the present invention compared with the prior art are as follows:

[0052] 1) Improve the abnormal climbing of the gold electrode at the lower electrode position to avoid the lower electrode breaking, product scrapping, and improve product yield;

[0053] 2) Perfectly protect the side wall of the upper electrode mesa to prevent the side wall of the upper electrode mesa from being over-etched during the RIE hard mask removal process, thereby reducing leakage current and improving device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] The present invention will be further described below in conjunction with the accompanying drawings:

[0055] Figure 1 A flow chart for obtaining the mesa structure through an ideal process;

[0056] Figure 2 A flow chart of the table structure obtained through the actual process;

[0057] Figure 3 is a schematic diagram of the electrode structure obtained through the actual process;

[0058] Figure 4 Process flow chart for existing detector chips;

[0059] Figure 5 This is a process flow chart of Example 1 of the present invention;

[0060] Figure 6 It is a schematic diagram of the structure of the existing photolithography Mask;

[0061] Figure 7 Schematic diagram of the structure of the modified photolithography Mask in Example 2 of the present invention;

[0062] Figure 8 Schematic diagram of the lower electrode structure obtained by Example 1 and Example 2 of the present invention;

[0063] Fig. 9 Schematic diagram of the upper electrode structure obtained by Example 1 and Example 2 of the present invention;

[0064] In the figure: 1 is a hard mask, 2 is a photoresist, 3 is a mesa, 4 is a residual hard mask, 5 is a sidewall etching defect, 7 is an indium column, 8 is a gold electrode, 9 is an upper electrode mesa region, 10 is a lower electrode mesa region, 11 is a substrate, 12 is a lower contact layer, 13 is an absorption region, 14 is an upper contact layer, and 15 is a passivation layer. DETAILED DESCRIPTION

[0065] like Figure 4 The figure shows the process flow of manufacturing the existing detector chip, and the specific implementation steps are as follows:

[0066] S10: Hard mask 1 film formation: Use plasma enhanced chemical vapor deposition (PECVD) process to grow SiO2 of a certain thickness on the wafer surface of the superlattice material as hard mask 1 for subsequent etching of the mesa 3. The thickness of SiO2 depends on the etching depth required by the device and the etching ratio of the mask to the material by different ICP gas combinations. Usually, 200-300nm is added to the required thickness to prevent over-etching.

[0067] S20: table photolithography: put the wafer with SiO2 growth into a plasma glue coater without a metal cover to remove impurities attached to the surface; put it into HMDS to coat the adhesive to increase the adhesion between the material surface and the photoresist 2 to avoid the phenomenon of no glue sticking during the glue spinning process; use the glue spinner to spread the glue, the first version uses positive glue AZ6130, the glue thickness is 1.5-2μm, put it on the heating plate, 95℃, pre-bake for 10min to remove moisture on the wafer surface; exposure, the time is set according to the glue thickness; put the wafer into a tetramethylammonium hydroxide solution with a concentration of 2.38% for development; blow dry with nitrogen after development, put it on the heating plate, select temperature points between 95℃-110℃ for gradient hardening, each for 10min, and finally harden at 120℃ for 20-30min; put it into a plasma glue coater with a metal cover to remove the residual photoresist 2 at the edge of the pattern.

[0068] S30: Etching of hard mask 1: Using photoresist 2 as a mask, using inductively coupled plasma (ICP) technology, SiO2 is etched to form a mesa 3 pattern. The process gas is 5 sccm of chlorine, 12 sccm of methane, and 5 sccm of argon. The vacuum degree is 5 mTorr, the temperature of substrate 11 is 200°C, the ICP power is 600W, and the RF power is 35W.

[0069] S40: Degumming and cleaning: first place the wafer in an acetone water bath and heat it for 10-20 minutes to remove the photoresist 2 on the surface of the wafer, and then use anhydrous ethanol and deionized water to clean the surface of the wafer in turn.

[0070] S50: Terrane ICP etching: Using ICP dry etching technology, the upper electrode and lower electrode terraces are etched using SiO2 as a hard mask 1.

[0071] S60: Mesa wet etching: The superlattice material is etched using a mixed solution of phosphoric acid / citric acid / hydrogen peroxide (H3PO4 / C6H8O7 / H2O2).

[0072] S70: Photolithography to remove the hard mask 1: Photolithography technology is used to remove the remaining hard mask 1 on the upper electrode table and the lower electrode table, and the parameters are consistent with the parameters of step S20.

[0073] S80: Hard mask 1 etching: ICP technology is used to remove the remaining hard mask 1 on the upper electrode table and the lower electrode table, and the parameters are consistent with the parameters of step S30.

[0074] S90: Glue removal and cleaning: the same as step S40.

[0075] S100: Formation of the passivation layer 15: After the etching of the mesa 3 is completed, 30-60 nm silicon oxide is deposited by an atomic layer deposition (ALD) method, and 100-300 nm silicon oxide is deposited by a plasma enhanced chemical vapor deposition process as a composite passivation film.

[0076] S200: Opening holes in the passivation layer 15: Performing composite passivation film opening photolithography to leave the area where the hole needs to be opened, and covering the other areas with photoresist 2, with the same parameters as the mesa photolithography in step S20, and then etching the SiO2 hard mask 1 using ICP technology.

[0077] S300: Preparation of gold electrode 8: Use negative photoresist L300 to perform gold electrode 8 photolithography, then use electron beam evaporation technology to evaporate Ti / Pt / Au metal with thickness of 50 / 50 / 300nm respectively, put the wafer with evaporated metal into acetone, generally wait for 1~2 hours, use acetone spray gun or syringe to blow off the surface of the material to complete metal stripping; after the metal is stripped clean, clean the wafer with anhydrous ethanol and deionized water in turn, blow dry with nitrogen, and the preparation of the unit detector chip is officially completed.

[0078] like Figure 5-9 As shown, based on the above existing process, the present invention takes into account the different requirements of the lower electrode mesa region 10 and the upper electrode mesa region 9 and proposes a method for manufacturing a superlattice infrared detector chip.

[0079] The specific differences between the requirements of the lower electrode mesa region 10 and the upper electrode mesa region 9 are as follows:

[0080] 1) The gold electrode 8 in the lower electrode mesa region 10 needs to climb, but the gold electrode 8 in the upper electrode mesa region 9 does not need to climb;

[0081] 2) The upper electrode mesa region 9 is expected to have a good sidewall morphology of the mesa 3 to minimize possible leakage current, while the lower electrode mesa region 10 is mainly to ensure the height of the indium pillar 7 is consistent to facilitate flip-chip interconnection between the lower electrode and the readout circuit ROIC.

[0082] Therefore, in view of the different requirements of the lower electrode mesa region 10 and the upper electrode mesa region 9, two methods are provided in this embodiment, and the two methods are respectively described below.

[0083] Example 1

[0084] The upper electrode mesa region 9 uses SiO2, Si3N4 or the like as the hard mask 1, and the lower electrode mesa region 10 uses photoresist as the mask, so that the step of removing the hard mask 1 in the existing process can be skipped. The specific process flow of this embodiment is as follows Figure 5 As shown, the specific implementation steps are as follows:

[0085] S1.1: Hard mask 1 film formation: SiO2, Si3N4, etc. are used as the hard mask 1 of the upper electrode mesa region 9, and the specific implementation method is the same as step S10 of the existing process;

[0086] S1.2: Photolithography of the upper electrode table: the specific implementation method is the same as step S20 of the existing process;

[0087] S1.3: etching of the hard mask 1: the specific implementation method is the same as step S30 of the existing process;

[0088] S1.4: Glue removal and cleaning: The specific implementation method is the same as step S40 of the existing process;

[0089] S1.5: Photolithography of the lower electrode mesa: using the photoresist 2 as a mask for the lower electrode mesa region 10, photolithography of the lower electrode mesa is performed by photolithography technology, and the specific implementation method is the same as step S20 of the existing process;

[0090] S1.6: mesa ICP etching: the specific implementation method is the same as step S50 of the existing process;

[0091] S1.7: mesa wet etching: the specific implementation method is the same as step S60 of the existing process;

[0092] S1.8: Degumming and cleaning of the lower electrode table: the specific implementation method is the same as step S40 of the existing process;

[0093] S1.9: forming the passivation layer 15: the specific implementation method is the same as step S100 of the existing process;

[0094] S1.10: opening a hole in the passivation layer 15: the specific implementation method is the same as step S200 of the existing process;

[0095] S1.11: Preparation of gold electrode 8: The specific implementation method is the same as step S300 of the existing process.

[0096] Embodiment 2:

[0097] The hard mask 1 is used in both the upper electrode mesa region 9 and the lower electrode mesa region 10, but only the hard mask 1 in the lower electrode mesa region 10 is removed to ensure that the gold electrode 8 in the lower electrode mesa region 10 climbs. The hard mask 1 in the upper electrode mesa region 9 is retained to ensure that the side wall of the upper electrode mesa will not be damaged by over-etching. The specific implementation steps are as follows Figure 4 The existing processes shown are consistent, and only differ in the part of removing the hard mask 1. The specific implementation steps are as follows:

[0098] S2.1: Hard mask 1 film formation: SiO2, Si3N4 or the like is used as the hard mask 1 of the upper electrode mesa region 9, and the specific implementation method is the same as step S10 of the existing process;

[0099] S2.2: mesa photolithography: the specific implementation method is the same as step S20 of the existing process;

[0100] S2.3: etching of the hard mask 1: the specific implementation method is the same as step S30 of the existing process;

[0101] S2.4: Glue removal and cleaning: The specific implementation method is the same as step S40 of the existing process;

[0102] S2.5: mesa ICP etching: the specific implementation method is the same as step S50 of the existing process;

[0103] S2.6: mesa wet etching: the specific implementation method is the same as step S60 of the existing process;

[0104] S2.7: removing the hard mask 1 in the lower electrode mesa region 10: the specific implementation method is the same as steps S70 and S80 of the prior art process;

[0105] S2.8: Glue removal and cleaning: The specific implementation method is the same as step S40 of the existing process;

[0106] S2.9: forming the passivation layer 15: the specific implementation method is the same as step S100 of the existing process;

[0107] S2.10: opening a hole in the passivation layer 15: the specific implementation method is the same as step S200 of the existing process;

[0108] S2.11: Preparation of gold electrode 8: The specific implementation method is the same as step S300 of the existing process.

[0109] In this embodiment, in order to remove only the hard mask 1 in the lower electrode mesa region 10, the shape of the photolithography Mask is improved. The shape of the old photolithography Mask is as follows: Figure 6 As shown, a positive photoresist such as AZ6130 can be used to remove the hard mask 1. The black area is the exposure position, that is, the position where the hard mask 1 needs to be removed. The hard mask 1 needs to be removed from both the upper electrode mesa region 9 and the lower electrode mesa region 10.

[0110] Modified lithography mask such as Figure 7 As shown, only the hard mask 1 in the lower electrode mesa region 10 can be removed.

[0111] The technical solutions of embodiments 1 and 2 of the present invention can achieve the following effects: Figure 8 and 9 As shown, there is no hard mask 1 at the lower electrode mesa, and the hard mask 1 is retained at the upper electrode mesa, which can ensure that the gold electrode 8 at the lower electrode position climbs smoothly and the side wall morphology of the upper electrode mesa is intact without over-engraving damage.

[0112] For infrared detectors with a high aspect ratio that must use a hard mask, based on current photolithography process conditions, the technical solution of the present invention can solve the problem of removing the hard mask 1 with high quality.

[0113] Compared with the existing process, the present invention does not increase the process steps, but can simultaneously solve the problems of the gold electrode 8 climbing at the position of the lower electrode table and the over-engraving of the side wall of the upper electrode table.

[0114] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for manufacturing a superlattice infrared detector chip, characterized in that: The following steps are involved: S1.1: Hard mask film formation: grow a hard mask of a set thickness on the surface of the wafer of superlattice material; S1.2: Photolithography of upper electrode mesa: The upper electrode mesa region is fabricated on the hard mask using photolithography technology; S1.3: Hard mask etching: Using photoresist as a mask, ICP technology is used to etch the hard mask to obtain the upper electrode table mask pattern; S1.4: Degumming and cleaning of the upper electrode surface; S1.5: Photolithography of the lower electrode mesa: Photoresist is used as a mask for the lower electrode mesa region, and the lower electrode mesa region is produced by photolithography technology; S1.6: Terrane ICP etching: ICP technology is used to etch the hard mask to obtain the upper electrode terrace pattern and the lower electrode terrace pattern; S1.7: Mesa wet etching: wet etching the upper and lower electrodes to remove the side wall dangling bonds; S1.8: Degumming and cleaning of the lower electrode surface; S1.9: Passivation layer film formation; S1.10: Opening of passivation layer; S1.11: Fabrication of gold electrodes.

2. The method for manufacturing a superlattice infrared detector chip according to claim 1, characterized in that: The material of the hard mask in step S1.1 is SiO2 or Si3N4.

3. The method for manufacturing a superlattice infrared detector chip according to claim 2, characterized in that: Step S1.2 specifically includes: placing the wafer with the hard mask grown on it into a plasma glue coating machine without a metal cover to remove surface impurities; then coating with adhesive; and then spinning, exposing, developing, vertically coating, and removing residual photoresist at the edge of the image.

4. The method for manufacturing a superlattice infrared detector chip according to claim 1, characterized in that: In step S1.7, a mixed solution of phosphoric acid, citric acid and hydrogen peroxide is used to corrode the superlattice material.

5. The method for manufacturing a superlattice infrared detector chip according to claim 1, characterized in that: Step S1.11 specifically includes: using negative photoresist L300 to perform gold electrode lithography, then using electron beam evaporation technology to evaporate Ti / Pt / Au metal, placing the wafer with evaporated metal in acetone, waiting for a period of time, using acetone to blow off the surface of the material to complete metal stripping; after the metal is stripped clean, wash the wafer with anhydrous ethanol and deionized water in turn, blow dry with nitrogen, and the preparation of the unit detector chip is officially completed.

6. A method for manufacturing a superlattice infrared detector chip, characterized in that: The following steps are involved: S2.1: Hard mask film formation: growing a hard mask of a certain thickness on the surface of the wafer of superlattice material; S2.2: mesa lithography: using photolithography technology to make the upper electrode mesa region and the lower electrode mesa region on the hard mask; S2.3: Hard mask etching: using photoresist as a mask, the hard mask is etched using ICP technology to obtain the upper electrode mesa mask pattern and the lower electrode mesa mask pattern; S2.4: degumming and cleaning; S2.5: Terrane ICP etching: ICP technology is used to etch the hard mask to obtain the upper electrode terrace pattern and the lower electrode terrace pattern; S2.6: Mesa wet etching: wet etching the upper and lower electrodes to remove the side wall dangling bonds; S2.7: removing the bottom electrode mesa hard mask; S2.8: degumming and cleaning; S2.9: Passivation layer film formation; S2.10: Opening of passivation layer; S2.11: Fabrication of gold electrodes.

7. The method for manufacturing a superlattice infrared detector chip according to claim 6, characterized in that: The material of the hard mask in step S2.1 is SiO2 or Si3N4.

8. The method for manufacturing a superlattice infrared detector chip according to claim 6, characterized in that: The degumming and cleaning steps in steps S2.4 and S2.8 are as follows: first, place the wafer in an acetone water bath and heat it for 10-20 minutes to remove the photoresist on the surface of the wafer, and then use anhydrous ethanol and deionized water to clean the surface of the wafer in turn.

9. The method for manufacturing a superlattice infrared detector chip according to claim 6, characterized in that: In step S2.7, the hard mask of the lower electrode mesa is removed by photolithography technology and ICP technology.

10. The method for manufacturing a superlattice infrared detector chip according to claim 9, characterized in that: In step S2.7, the hard mask of the lower electrode mesa is removed by photolithography Mask, and the exposure position of the photolithography Mask only covers the lower electrode mesa.

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