Method for preparing heterojunction cell by tubular PECVD (Plasma Enhanced Chemical Vapor Deposition) and heterojunction cell

Abstract

The invention relates to a method for preparing a heterojunction cell through tubular PECVD (plasma enhanced chemical vapor deposition) and the heterojunction cell, and belongs to the technical field of solar cells. Comprising the following steps: depositing intrinsic amorphous silicon layers on the front surface and the back surface of a crystalline silicon substrate by using tubular PECVD (Plasma Enhanced Chemical Vapor Deposition); repairing the front intrinsic amorphous silicon layer by using tubular PECVD (Plasma Enhanced Chemical Vapor Deposition), and preparing an N-type doped layer on the front surface of the repaired front intrinsic amorphous silicon layer; repairing the back intrinsic amorphous silicon layer by using tubular PECVD (Plasma Enhanced Chemical Vapor Deposition), and preparing a P-type doped layer on the back of the repaired back intrinsic amorphous silicon layer; and a front transparent conductive film layer and a front metal electrode as well as a back transparent conductive film layer and a back metal electrode are prepared on the front surface of the N-type doped layer and the back surface of the P-type doped layer respectively. According to the method, the damaged intrinsic amorphous silicon exposed in the atmosphere can be effectively repaired when the tubular PECVD is used for preparing the heterojunction cell, so that the passivation performance and hole / electron transmission of the cell are improved, and the photoelectric conversion efficiency of the heterojunction cell is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a method for preparing a heterojunction cell by tubular PECVD and a heterojunction cell. Background Art

[0002] In the global energy transformation, photovoltaic cells have become an important development direction due to their green and renewable characteristics. Heterojunction cells have attracted much attention among crystalline silicon photovoltaics and stacked cells due to their advantages such as high photoelectric conversion efficiency, low temperature manufacturing, low temperature coefficient and high bifaciality. Their conversion efficiency has reached 27.3%, setting a record for single-cell crystalline silicon cells. With the continuous maturity of technology and the improvement of the industrial chain, the manufacturing cost of heterojunction cells will be further reduced, and the market competitiveness will be greatly improved.

[0003] In the existing photovoltaic field, the investment cost of heterojunction batteries is about 300 million yuan / GW, of which the investment cost of PECVD is about 150-200 million yuan / GW, accounting for about 50% of the investment cost. In recent years, domestic photovoltaic equipment manufacturers such as Maxsun and JEC have focused on the research and development of PECVD equipment, which has greatly reduced the investment cost of heterojunction batteries, and their research and development focus is on plate-type PECVD. This style of PECVD has the advantages of good deposition rate quality and excellent uniformity, but it also has disadvantages such as low output, large footprint, and high investment cost. Compared with other battery technologies, equipment cost is still a major factor restricting the large-scale industrialization and promotion of heterojunction.

[0004] Tubular PECVD can effectively solve the problems of high equipment cost, large floor space and low output of plate PECVD. However, in the preparation process of tubular PECVD, each cavity is independently dispersed. In the preparation process of heterojunction battery, the preparation of intrinsic amorphous silicon layer and doping layer needs to be completed in different cavities. After the preparation of intrinsic amorphous silicon is completed, before the preparation of doping layer, because the intrinsic amorphous silicon layer and doping layer cavity are independently in the atmospheric environment, the intrinsic amorphous silicon layer inevitably needs to be exposed to atmospheric conditions for 2-3 minutes. Exposure to oxygen in the air will damage the prepared intrinsic amorphous silicon layer, causing the microstructure factor and hydrogen content of the intrinsic amorphous silicon layer to be damaged, thereby affecting the preparation of the doping layer. The damage of the intrinsic amorphous silicon layer not only affects the final passivation performance of the battery, resulting in a decrease in the open circuit voltage of the battery, but also affects the transmission of holes / electrons, resulting in a decrease in the filling factor of the battery, darkening the PL, and ultimately affecting the photoelectric conversion efficiency of the battery.

[0005] Therefore, in the process of preparing heterojunction batteries using tubular PECVD, how to repair the successfully prepared intrinsic amorphous silicon layer is an urgent problem that technical personnel in this field need to solve. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a heterojunction battery by tubular PECVD and a heterojunction battery. The technical solution of the present invention is as follows:

[0007] The present invention provides a method for preparing a heterojunction battery by tubular PECVD, which comprises:

[0008] S1, selecting a single crystal silicon wafer, texturing the single crystal silicon wafer to form a pyramid structure as a crystalline silicon substrate;

[0009] S2, depositing a front intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate using a tubular PECVD;

[0010] S3, using tubular PECVD to repair the front intrinsic amorphous silicon layer, and preparing an N-type doping layer on the front side of the repaired front intrinsic amorphous silicon layer, wherein pure hydrogen or a mixture of hydrogen and a carbon-containing compound is used to repair the front intrinsic amorphous silicon layer, and the carbon-containing compound is carbon dioxide or methane;

[0011] S4, depositing a back intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate using a tubular PECVD;

[0012] S5, using tubular PECVD to repair the back intrinsic amorphous silicon layer, and preparing a P-type doping layer on the back of the repaired back intrinsic amorphous silicon layer, wherein the back intrinsic amorphous silicon layer is repaired using pure hydrogen or a mixture of hydrogen and a carbon-containing compound, and the carbon-containing compound is carbon dioxide or methane;

[0013] S6, preparing a front transparent conductive thin film layer and a back transparent conductive thin film layer on the front side of the N-type doped layer and the back side of the P-type doped layer respectively;

[0014] S7, preparing a front metal electrode and a back metal electrode on the front side of the front transparent conductive film layer and on the back side of the back transparent conductive film layer, respectively.

[0015] Optionally, the single crystal silicon wafer is an N-type single crystal silicon wafer with a thickness of 40-160 um.

[0016] Optionally, the size of the pyramid structure velvet surface is 0.5-10um.

[0017] Optionally, when S2 and S4 are implemented, the flow rate of silane is controlled at 600-2500sccm, the dilution ratio of hydrogen to silane is 5-100:1, the thickness of the front intrinsic amorphous silicon layer and the back intrinsic amorphous silicon layer are both controlled at 4-9nm, the microstructure factor is 20%-70%, and the hydrogen content is 18%-60%.

[0018] Optionally, when S3 is repairing the front intrinsic amorphous silicon layer and S5 is repairing the back intrinsic amorphous silicon layer, the hydrogen flow rate is 500-40000sccm, the tubular PECVD power is controlled at 400-3000W, the pressure is controlled at 500-3000mtor, the ratio of hydrogen to carbon-containing compounds is 10:1-100:1, the processing time is controlled at 20s-120s, and the temperature is controlled at 100-210°C.

[0019] Optionally, the N-type doped layer is N-type amorphous silicon, N-type microcrystalline silicon or N-type microcrystalline silicon oxide;

[0020] For N-type amorphous silicon, the dilution ratio of hydrogen to silane is 5-20:1, the doping ratio of phosphine to silane is 3%-5%, and the thickness is 5-9nm;

[0021] For N-type microcrystalline silicon, the dilution ratio of hydrogen to silane is 100-400:1, the doping ratio of phosphine to silane is 3%-5%, and the thickness is 10-15nm;

[0022] For N-type microcrystalline silicon oxide, the dilution ratio of hydrogen to silane is 100-400:1, the doping ratio of phosphine to silane is 3%-5%, the ratio of carbon dioxide to silane is 0.5-1.5:1, and the thickness is 10-20nm.

[0023] Optionally, the P-type doped layer is P-type amorphous silicon or P-type microcrystalline silicon;

[0024] For P-type amorphous silicon, the ratio of hydrogen to silane is 5-20:1, the doping ratio of borane to silane is 2%-4%, and the thickness is 9-15nm;

[0025] For P-type microcrystalline silicon, the ratio of hydrogen to silane is 250-400:1, the doping ratio of borane to silane is 0.2%-0.5%, and the thickness is 25-35nm.

[0026] Optionally, the front transparent conductive film layer and the back transparent conductive film layer are both made of one or any combination of ITO, IWO, and AZO, and have a thickness of 90-120 nm.

[0027] Optionally, the number of main grids of the front metal electrode and the back metal electrode is 0-28, the number of fine grids is 40-160, and the fine grid line width is 15-60 μm.

[0028] The present invention also provides a heterojunction battery, which is prepared by using the above-mentioned method for preparing a heterojunction battery by tubular PECVD.

[0029] All the above optional technical solutions can be combined arbitrarily, and the present invention does not provide detailed descriptions of the structures after the combinations.

[0030] By means of the above scheme, the beneficial effects of the present invention are as follows:

[0031] By using tubular PECVD to repair the front intrinsic amorphous silicon layer and preparing an N-type doped layer on the front of the repaired front intrinsic amorphous silicon layer, and by using tubular PECVD to repair the back intrinsic amorphous silicon layer and preparing a P-type doped layer on the back of the repaired back intrinsic amorphous silicon layer, the intrinsic amorphous silicon that is damaged when exposed to the atmosphere during the preparation of heterojunction cells by tubular PECVD can be effectively repaired, thereby improving the passivation performance and hole / electron transmission of the cell, and improving the photoelectric conversion efficiency of the heterojunction cell. This method is of great significance to improving the performance of heterojunction cells and provides new ideas and directions for mass production research of heterojunction cells.

[0032] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention and implement it according to the contents of the specification, the following is a detailed description of the preferred embodiments of the present invention in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flow chart of the method for preparing heterojunction batteries by tubular PECVD provided in an embodiment of the present invention.

[0034] Figure 2 It is a schematic diagram of the composition structure of a heterojunction battery prepared by the method for preparing a heterojunction battery by tubular PECVD provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The specific implementation of the present invention is further described in detail below in conjunction with the accompanying drawings and examples. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0036] like Figure 1 As shown, the method for preparing heterojunction batteries by tubular PECVD provided in an embodiment of the present invention comprises:

[0037] S1, selecting a single crystal silicon wafer, texturing the single crystal silicon wafer to form a pyramid structure as a crystalline silicon substrate.

[0038] In a specific implementation, the single crystal silicon wafer is an N-type single crystal silicon wafer with a thickness of 40-160 um. The pyramid structure is prepared by using KOH and a texturing additive, and the size of the texturing surface is 0.5-10 um.

[0039] S2, using tubular PECVD to deposit a front intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate.

[0040] Specifically, the front intrinsic amorphous silicon layer is a composite structure. During preparation, the flow rate of silane is controlled at 600-2500sccm, the dilution ratio of hydrogen to silane is 5-100:1, the thickness of the front intrinsic amorphous silicon layer is controlled at 4-9nm, the microstructure factor is 20%-70%, and the hydrogen content is 18%-60%.

[0041] S3, using tubular PECVD to repair the front intrinsic amorphous silicon layer, and preparing an N-type doping layer on the front side of the repaired front intrinsic amorphous silicon layer, wherein pure hydrogen or a mixture of hydrogen and a carbon-containing compound is used to repair the front intrinsic amorphous silicon layer, and the carbon-containing compound is carbon dioxide or methane.

[0042] Specifically, due to the use of tubular PECVD, after the preparation of the front intrinsic amorphous silicon layer is completed and before the preparation of the doped layer, the front intrinsic amorphous silicon layer and the doped layer cavity are independently in the atmospheric environment, so the front intrinsic amorphous silicon layer inevitably needs to be exposed to atmospheric conditions for 2-3 minutes, and the oxygen in the air will damage the prepared front intrinsic amorphous silicon layer. Therefore, the embodiment of the present invention uses tubular PECVD to repair the front intrinsic amorphous silicon layer, and prepares the N-type doped layer on the basis of the repaired front intrinsic amorphous silicon layer.

[0043] In a specific embodiment, when the S3 is repairing the front intrinsic amorphous silicon layer, the flow rate of hydrogen is 500-40000sccm, the power of the tubular PECVD is controlled at 400-3000W, the pressure is controlled at 500-3000mtor, the ratio of hydrogen to carbon-containing compounds is 10:1-100:1, the processing time is controlled at 20s-120s, and the temperature is controlled at 100-210°C. The microstructure factor and hydrogen content of the front intrinsic amorphous silicon layer can be repaired by using this repair method, and the damaged front intrinsic amorphous silicon layer can be well repaired.

[0044] During the repair process, due to the use of tubular PECVD, it can be applied to the preparation on the graphite boat. During the preparation process, only an appropriate amount of gas needs to be introduced to complete the repair. No specific equipment and gas environment (nitrogen, argon, etc.) are required, which can greatly reduce the investment cost.

[0045] Furthermore, the N-type doped layer in the embodiment of the present invention is prepared on the basis of amorphous silicon repair. The N-type doped layer can be N-type amorphous silicon, N-type microcrystalline silicon or N-type microcrystalline silicon oxide; for N-type amorphous silicon, the dilution ratio of hydrogen to silane is 5-20:1, the doping ratio of phosphine to silane is 3%-5%, and the thickness is 5-9nm; for N-type microcrystalline silicon, the dilution ratio of hydrogen to silane is 100-400:1, the doping ratio of phosphine to silane is 3%-5%, and the thickness is 10-15nm; for N-type microcrystalline silicon oxide, the dilution ratio of hydrogen to silane is 100-400:1, the doping ratio of phosphine to silane is 3%-5%, and the ratio of carbon dioxide to silane is 0.5-1.5:1, and the thickness is 10-20nm.

[0046] S4, depositing a back intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate using tubular PECVD.

[0047] Specifically, the back intrinsic amorphous silicon layer is a composite structure. During preparation, the flow rate of silane is controlled at 600-2500sccm, the dilution ratio of hydrogen to silane is 5-100:1, the thickness of the back intrinsic amorphous silicon layer is controlled at 4-9nm, the microstructure factor is 20%-70%, and the hydrogen content is 18%-60%.

[0048] S5, using tubular PECVD to repair the back intrinsic amorphous silicon layer, and preparing a P-type doping layer on the back side of the repaired back intrinsic amorphous silicon layer, wherein the back intrinsic amorphous silicon layer is repaired using pure hydrogen or a mixture of hydrogen and a carbon-containing compound, and the carbon-containing compound is carbon dioxide or methane.

[0049] The repair principle in this step is the same as that in step S3 and will not be repeated here.

[0050] In a specific embodiment, when S5 repairs the back intrinsic amorphous silicon layer, the hydrogen flow rate is 500-40000sccm, the tubular PECVD power is controlled at 400-3000W, the pressure is controlled at 500-3000mtor, the ratio of hydrogen to carbon-containing compounds is 10:1-100:1, the processing time is controlled at 20s-120s, and the temperature is controlled at 100-210°C.

[0051] Furthermore, the P-type doped layer in the embodiment of the present invention is prepared on the basis of amorphous silicon repair. The P-type doped layer is P-type amorphous silicon or P-type microcrystalline silicon; for P-type amorphous silicon, the ratio of hydrogen to silane is 5-20:1, the doping ratio of borane to silane is 2%-4%, and the thickness is 9-15nm; for P-type microcrystalline silicon, the ratio of hydrogen to silane is 250-400:1, the doping ratio of borane to silane is 0.2%-0.5%, and the thickness is 25-35nm.

[0052] S6, preparing a front transparent conductive film layer and a back transparent conductive film layer on the front side of the N-type doped layer and the back side of the P-type doped layer respectively.

[0053] In a specific embodiment, the front transparent conductive film layer and the back transparent conductive film layer can be prepared by a physical chemical vapor deposition (PVD) method, or by a plasma (RPD) method. The front transparent conductive film layer and the back transparent conductive film layer are one or any combination of ITO (indium tin oxide), IWO (tungsten-doped indium oxide), and AZO (aluminum-doped zinc oxide), and are formed under the three atmospheres of argon, hydrogen, and oxygen, and the thickness is 90-120nm.

[0054] S7, preparing a front metal electrode and a back metal electrode on the front side of the front transparent conductive film layer and on the back side of the back transparent conductive film layer, respectively.

[0055] In a specific embodiment, the front metal electrode and the back metal electrode are prepared by, but not limited to, screen printing, inkjet printing, electroplating, etc. The number of main grids of the front metal electrode and the back metal electrode is 0-28, the number of fine grids is 40-160, and the fine grid line width is 15-60 μm.

[0056] The present invention also provides a heterojunction battery, which is prepared by the method for preparing a heterojunction battery by tubular PECVD as described in the above embodiment. Figure 2 As shown, it includes a crystalline silicon substrate 1, a front intrinsic amorphous silicon layer 2, an N-type doped layer 3, a front transparent conductive film layer 4 and a front metal electrode 5 which are sequentially prepared on the front side of the crystalline silicon substrate 1, and a back intrinsic amorphous silicon layer 6, a P-type doped layer 7, a back transparent conductive film layer 8 and a back metal electrode 9 which are sequentially prepared on the back side of the crystalline silicon substrate 1, wherein the N-type doped layer 3 is prepared on the front side of the repaired front intrinsic amorphous silicon layer by using tubular PECVD to repair the front intrinsic amorphous silicon layer, and the P-type doped layer 7 is prepared on the back side of the repaired back intrinsic amorphous silicon layer by using tubular PECVD to repair the back intrinsic amorphous silicon layer, and the repair uses pure hydrogen or a mixture of hydrogen and a carbon-containing compound, and the carbon-containing compound is carbon dioxide or methane.

[0057] In order to verify the beneficial effects of the method for preparing heterojunction batteries by tubular PECVD provided in the embodiments of the present invention, Comparative Example 1, Comparative Example 2, Example 1 and Example 2 are provided below.

[0058] Comparative Example 1:

[0059] The method for preparing a heterojunction battery provided in Comparative Example 1 comprises the following steps:

[0060] A. Use KOH and a texturing additive to texturing an N-type single crystal silicon wafer with a thickness of 110um and a size of 166mm*166mm to form a pyramid velvet surface, remove impurity ions and clean the surface. The velvet surface size is 3um.

[0061] B. Prepare the front intrinsic amorphous silicon layer by plate PECVD, the silane flow rate is 2000sccm, the hydrogen dilution factor is 5 times, and the thickness is 5nm; after the preparation, prepare the N-type doped microcrystalline silicon oxide film, the hydrogen dilution factor is 300 times, the doping ratio of phosphine to borane is 4%, the ratio of carbon dioxide to silane is 1:1, and the thickness is 15nm;

[0062] C. Prepare the back intrinsic amorphous silicon layer by plate PECVD, the thickness of which is 5nm; after the preparation, prepare a P-type doped microcrystalline silicon film, the thickness of which is 25nm; the process parameters of the P-type microcrystalline silicon film used are: the flow ratio of diborane and silane is 0.3%, and the dilution ratio is 300 times;

[0063] D. Prepare the front transparent conductive film layer and the back transparent conductive film layer by physical vapor deposition (PVD) method; the TCO target material used is ITO (indium tin oxide), and the thickness thereof is 100 nm;

[0064] E. The metal electrode is formed by screen printing. The number of main grids of the front metal electrode is 9, the main grid is a solder point main grid, the width is 0.1mm, the fine grid line width is 0.05mm, and the number of fine grids is 90; the number of main grids of the back silver metal electrode is 9, the width is 0.1mm, the main grid is a solder point main grid, the fine grid line width is 0.05mm, and the number of fine grids is 120;

[0065] F. Sintering makes good ohmic contact between metal and silicon;

[0066] G. Test the electrical performance of the battery.

[0067] Comparative Example 2:

[0068] The method for preparing a heterojunction battery provided in Comparative Example 2 comprises the following steps:

[0069] A. Use KOH and a texturing additive to texturing an N-type single crystal silicon wafer with a thickness of 110um and a size of 166mm*166mm to form a pyramid velvet surface, remove impurity ions and clean the surface. The velvet surface size is 3um.

[0070] B. Prepare the front intrinsic amorphous silicon layer by tubular PECVD, the silane flow rate is 2000sccm, the hydrogen dilution factor is 5 times, and the thickness is 5nm; after the preparation is completed, after exposure to the atmosphere for 3min, prepare the front N-type doped microcrystalline silicon oxide film, the hydrogen dilution factor is 300 times, the doping ratio of phosphine to borane is 4%, the ratio of carbon dioxide to silane is 1:1, and the thickness is 15nm;

[0071] C. Prepare the back intrinsic amorphous silicon layer by tubular PECVD, the thickness of which is 5nm; after the preparation is completed, after exposure to the atmosphere for 3min, prepare the back doped P-type microcrystalline silicon film, the thickness of which is 25nm; the process parameters of the P-type microcrystalline silicon film used are: the flow ratio of diborane and silane is 0.3%, and the dilution ratio is 300 times;

[0072] D. Prepare the front transparent conductive film layer and the back transparent conductive film layer by physical vapor deposition (PVD) method; the TCO target material used is ITO (indium tin oxide), and the thickness thereof is 100 nm;

[0073] E. The metal electrode is formed by screen printing. The number of main grids of the front metal electrode is 9, the main grid is a solder point main grid, the width is 0.1mm, the fine grid line width is 0.05mm, and the number of fine grids is 90; the number of main grids of the back silver metal electrode is 9, the width is 0.1mm, the main grid is a solder point main grid, the fine grid line width is 0.05mm, and the number of fine grids is 120;

[0074] F. Sintering makes good ohmic contact between metal and silicon;

[0075] G. Test the electrical performance of the battery.

[0076] Example 1

[0077] The method for preparing a heterojunction battery provided in Example 1 comprises the following steps:

[0078] A. Use KOH and a texturing additive to texturing an N-type single crystal silicon wafer with a thickness of 110um and a size of 166mm*166mm to form a pyramid velvet surface, remove impurity ions and clean the surface. The velvet surface size is 3um.

[0079] B. Prepare the front intrinsic amorphous silicon layer by tubular PECVD, the silane flow rate is 2000sccm, the hydrogen dilution factor is 5 times, and the thickness is 5nm; after the preparation is completed, after being exposed to the atmosphere for 3min, the front intrinsic amorphous silicon layer is repaired, the repair gas is hydrogen, the hydrogen flow rate is 10000sccm, the tubular PECVD power is 1500W, the pressure is 2000mtor, and the processing time is 60s; prepare an N-type doped microcrystalline silicon oxide film on the front of the repaired front intrinsic amorphous silicon layer, the hydrogen dilution factor is 300 times, the doping ratio of phosphine to borane is 4%, the ratio of carbon dioxide to silane is 1:1, and the thickness is 15nm;

[0080] C. Prepare a back intrinsic amorphous silicon layer by tubular PECVD, the thickness of which is 5nm; after preparation, after exposure to the atmosphere for 3min, repair the back intrinsic amorphous silicon layer, the repair gas used is hydrogen, the hydrogen flow rate is 10000sccm, the tubular PECVD power is 1500W, the pressure is 2000mtor, and the processing time is 30s; prepare a back doped P-type microcrystalline silicon film on the back of the repaired back intrinsic amorphous silicon layer, the thickness of which is 25nm; the process parameters of the P-type microcrystalline silicon film used are: the flow ratio of diborane and silane is 0.3%, and the dilution ratio is 300 times;

[0081] D. Prepare the front transparent conductive film layer and the back transparent conductive film layer by physical vapor deposition (PVD) method; the TCO target material used is ITO (indium tin oxide), and the thickness thereof is 100 nm;

[0082] E. The metal electrode is formed by screen printing. The number of main grids of the front metal electrode is 9, the main grid is a solder point main grid, the width is 0.1mm, the fine grid line width is 0.05mm, and the number of fine grids is 90; the number of main grids of the back silver metal electrode is 9, the width is 0.1mm, the main grid is a solder point main grid, the fine grid line width is 0.05mm, and the number of fine grids is 120;

[0083] F. Sintering makes good ohmic contact between metal and silicon;

[0084] G. Test the electrical performance of the battery.

[0085] Example 2

[0086] The method for preparing a heterojunction battery provided in Example 2 comprises the following steps:

[0087] A. Use KOH and a texturing additive to texturing N-type monocrystalline silicon wafers with a thickness of 110um and 166mm*166mm to form a pyramid velvet surface, remove impurity ions and clean the surface. The velvet surface size is 3um.

[0088] B. Prepare the front intrinsic amorphous silicon layer by tubular PECVD, the silane flow rate is 2000sccm, the hydrogen dilution multiple is 5 times, and the thickness is 5nm; after the preparation is completed, after being exposed to the atmosphere for 3min, the front intrinsic amorphous silicon layer is repaired, and the repair gas is a mixture of hydrogen and carbon-containing compounds, the hydrogen flow rate is 10000sccm, the carbon-containing compound flow rate is 600sccm, the tubular PECVD power is 1500W, the pressure is 2000mtor, and the processing time is 60s; prepare an N-type doped microcrystalline silicon oxide film on the front of the repaired front intrinsic amorphous silicon layer, the hydrogen dilution multiple is 300 times, the doping ratio of phosphine to borane is 4%, the ratio of carbon dioxide to silane is 1:1, and the thickness is 15nm;

[0089] C. Prepare a back intrinsic amorphous silicon layer by tubular PECVD, the thickness of which is 5nm; after preparation, after exposure to the atmosphere for 3min, repair the back intrinsic amorphous silicon layer, the repairing gases are hydrogen and carbon dioxide, wherein the hydrogen flow rate is 10000sccm, the carbon dioxide flow rate is 600sccm, the tubular PECVD power is 1500W, the pressure is 2000mtor, and the processing time is 30s; prepare a back doped P-type microcrystalline silicon film on the back of the repaired back intrinsic amorphous silicon layer, the thickness of which is 25nm; the process parameters of the P-type microcrystalline silicon film used are: the flow ratio of diborane and silane is 0.3%, and the dilution ratio is 300 times;

[0090] D. Prepare the front transparent conductive film layer and the back transparent conductive film layer by physical vapor deposition (PVD) method; the TCO target material used is ITO (indium tin oxide), and the thickness thereof is 100 nm;

[0091] E. The metal electrode is formed by screen printing. The number of main grids of the front metal electrode is 9, the main grid is a solder point main grid, the width is 0.1mm, the fine grid line width is 0.05mm, and the number of fine grids is 90; the number of main grids of the back silver metal electrode is 9, the width is 0.1mm, the main grid is a solder point main grid, the fine grid line width is 0.05mm, and the number of fine grids is 120;

[0092] F. Sintering makes good ohmic contact between metal and silicon;

[0093] G. Test the electrical performance of the battery.

[0094] The electrical properties of the heterojunction batteries prepared in Comparative Example 1, Comparative Example 2, Example 1 and Example 2 are compared, and the comparison results are shown in Table 1.

[0095] Table 1

[0096]

[0097] By comparing Comparative Example 1 with Comparative Example 2, it is found that after using tubular PECVD, compared with plate PECVD, the photoelectric conversion efficiency has a loss of 0.15, which is mainly caused by the damage of the intrinsic amorphous silicon layer. By adopting the methods of Example 1 and Example 2, that is, by adopting the method of repairing amorphous silicon, the photoelectric conversion efficiency of the battery is greatly improved, and the debugged photoelectric conversion efficiency can be basically the same as that of plate PECVD. Among them, the improvement of open circuit voltage Voc is due to the enhancement of intrinsic amorphous silicon passivation performance, and the improvement of FF is due to the improvement of hole / electron transmission, resulting in enhanced conductivity.

[0098] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention, and these improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A method for preparing heterojunction batteries by tubular PECVD, characterized in that: include: S1, selecting a single crystal silicon wafer, texturing the single crystal silicon wafer to form a pyramid structure as a crystalline silicon substrate; S2, depositing a front intrinsic amorphous silicon layer on the front side of the crystalline silicon substrate using a tubular PECVD; S3, using tubular PECVD to repair the front intrinsic amorphous silicon layer, and preparing an N-type doping layer on the front side of the repaired front intrinsic amorphous silicon layer, wherein pure hydrogen or a mixture of hydrogen and a carbon-containing compound is used to repair the front intrinsic amorphous silicon layer, and the carbon-containing compound is carbon dioxide or methane; S4, depositing a back intrinsic amorphous silicon layer on the back side of the crystalline silicon substrate using a tubular PECVD; S5, using tubular PECVD to repair the back intrinsic amorphous silicon layer, and preparing a P-type doping layer on the back of the repaired back intrinsic amorphous silicon layer, wherein the back intrinsic amorphous silicon layer is repaired using pure hydrogen or a mixture of hydrogen and a carbon-containing compound, and the carbon-containing compound is carbon dioxide or methane; S6, preparing a front transparent conductive thin film layer and a back transparent conductive thin film layer on the front side of the N-type doped layer and the back side of the P-type doped layer respectively; S7, preparing a front metal electrode and a back metal electrode on the front side of the front transparent conductive film layer and on the back side of the back transparent conductive film layer, respectively.

2. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: The single crystal silicon wafer is an N-type single crystal silicon wafer with a thickness of 40-160um.

3. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: The size of the pyramid structure velvet surface is 0.5-10um.

4. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: In the specific implementation of S2 and S4, the flow rate of silane is controlled at 600-2500sccm, the dilution ratio of hydrogen to silane is 5-100:1, the thickness of the front intrinsic amorphous silicon layer and the back intrinsic amorphous silicon layer are both controlled at 4-9nm, the microstructure factor is 20%-70%, and the hydrogen content is 18%-60%.

5. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: When S3 is repairing the front intrinsic amorphous silicon layer and S5 is repairing the back intrinsic amorphous silicon layer, the hydrogen flow rate is 500-40000sccm, the tubular PECVD power is controlled at 400-3000W, the pressure is controlled at 500-3000mtor, the ratio of hydrogen to carbon-containing compounds is 10:1-100:1, the processing time is controlled at 20s-120s, and the temperature is controlled at 100-210°C.

6. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: The N-type doped layer is N-type amorphous silicon, N-type microcrystalline silicon or N-type microcrystalline silicon oxide; For N-type amorphous silicon, the dilution ratio of hydrogen to silane is 5-20:1, the doping ratio of phosphine to silane is 3%-5%, and the thickness is 5-9nm; For N-type microcrystalline silicon, the dilution ratio of hydrogen to silane is 100-400:1, the doping ratio of phosphine to silane is 3%-5%, and the thickness is 10-15nm; For N-type microcrystalline silicon oxide, the dilution ratio of hydrogen to silane is 100-400:1, the doping ratio of phosphine to silane is 3%-5%, the ratio of carbon dioxide to silane is 0.5-1.5:1, and the thickness is 10-20nm.

7. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: The P-type doped layer is P-type amorphous silicon or P-type microcrystalline silicon; For P-type amorphous silicon, the ratio of hydrogen to silane is 5-20:1, the doping ratio of borane to silane is 2%-4%, and the thickness is 9-15nm; For P-type microcrystalline silicon, the ratio of hydrogen to silane is 250-400:1, the doping ratio of borane to silane is 0.2%-0.5%, and the thickness is 25-35nm.

8. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: The front transparent conductive film layer and the back transparent conductive film layer are both one or any combination of ITO, IWO, and AZO, and the thickness is 90-120nm.

9. The method for preparing heterojunction batteries by tubular PECVD according to claim 1, characterized in that: The number of main grids of the front metal electrode and the back metal electrode is 0-28, the number of fine grids is 40-160, and the width of the fine grid line is 15-60 μm.

10. A heterojunction battery, characterized in that: The battery is prepared by the method for preparing a heterojunction battery by tubular PECVD as described in any one of claims 1 to 9.

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