Display device

Abstract

A display device includes: a substrate including a plurality of pixel regions spaced apart from each other and a plurality of transmissive regions between the plurality of pixel regions, where each of the plurality of pixel regions includes a plurality of sub-pixels; and a plurality of signal lines extending along a first direction on the substrate, in which the plurality of sub-pixels include a plurality of pixel circuits, in which the plurality of signal lines overlap the plurality of pixel circuits and the plurality of signal lines do not overlap the plurality of transmission regions. Accordingly, the plurality of pixel regions and the plurality of signal lines are in the same region to reduce the size of an opaque region and increase the size of a transmissive region in the entire display device, thereby implementing a transparent display device.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0121471 filed on September 13, 2023 with the Korean Intellectual Property Office. Technical Field

[0003] The present disclosure relates to a transparent display device, and more particularly, to a transparent display device using a light emitting diode (LED). Background Art

[0004] As a display device used for a display of a computer, a television, or a cellular phone, there are an organic light emitting display device (OLED) which is a self-light emitting device and a liquid crystal display device (LCD) which requires a separate light source.

[0005] Application ranges of the display device are diverse, including personal digital assistants as well as monitors of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0006] In addition, in recent years, display devices including LEDs are receiving attention as next-generation display devices. Since LEDs are formed of inorganic materials rather than organic materials, they are excellent in reliability, making their lifespan longer than that of liquid crystal display devices or organic light-emitting display devices. In addition, LEDs have fast lighting speed, excellent luminous efficiency, and strong impact resistance, so that they are excellent in stability and can display images with high brightness. Summary of the invention

[0007] One object to be achieved by the present disclosure is to provide a transparent display device with high transmittance.

[0008] Another object to be achieved by the present disclosure is to provide a display device that maximizes the size of a transmission area.

[0009] Another object to be achieved by the present disclosure is to provide a display device in which interference between a driving transistor of a pixel area and a plurality of data lines is reduced.

[0010] Another object to be achieved by the present disclosure is to provide a display device that reduces fluctuations in voltage and driving current of a driving transistor due to a data line.

[0011] Yet another object to be achieved by the present disclosure is to provide a display device that reduces coupling between a data line and a driving transistor to improve display quality.

[0012] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above may be clearly understood by those skilled in the art from the following description.

[0013] The present disclosure provides a display device according to an independent claim. Preferred embodiments are described in the dependent claims. According to one embodiment of the present disclosure, a display device comprises: a substrate comprising a plurality of pixel regions spaced apart from each other and a plurality of transmission regions between the plurality of pixel regions; and a plurality of data lines extending along a first direction on the substrate, wherein the plurality of pixel regions overlap with the plurality of data lines, and the plurality of data lines do not overlap with the plurality of transmission regions. The first direction described herein may be a column direction. The second direction described herein may be a row direction.

[0014] In one embodiment, a display device includes: a substrate, including a pixel area and a transmission area that is more transparent than the pixel area; a first insulating layer, on the substrate; a driving transistor, on the first insulating layer in the pixel area; a signal line, overlapping the driving transistor in the pixel area; a light emitting diode, in the pixel area, the light emitting diode is electrically connected to the driving transistor; and a second insulating layer, between the signal line and the driving transistor in the pixel area, the thickness of the second insulating layer being greater than the thickness of the first insulating layer.

[0015] In one embodiment, a display device includes: a substrate in which a plurality of pixel regions arranged to be spaced apart from each other and a plurality of transmission regions arranged between the plurality of pixel regions are defined; and a plurality of wirings extending along a column direction on the substrate, wherein the plurality of pixel regions overlap with a region in which the plurality of wirings are arranged.

[0016] Additional details of example embodiments are included in the detailed description and the accompanying drawings.

[0017] According to one aspect of the present disclosure, a transparent display device with improved transmittance may be realized.

[0018] According to another aspect of the present disclosure, opaque configurations in the configuration of the display device overlap each other to maximize the size of the transmissive region in the display device. According to some embodiments, the opaque pixel region and the plurality of wirings overlap to maximize the size of the transmissive region.

[0019] According to another aspect of the present disclosure, voltage fluctuation of a driving transistor and resulting driving current fluctuation due to coupling of a data line to the driving transistor may be reduced.

[0020] According to another aspect of the present disclosure, crosstalk and brightness variation due to coupling of a data line with a driving transistor may be reduced.

[0021] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 3 is a schematic enlarged plan view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0027] Figure 4 is an enlarged plan view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure;

[0028] Figure 5 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure;

[0029] Figure 6 It is the simulation result that measures the crosstalk level according to the thickness of the insulation layer;

[0030] Figure 7 is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure;

[0031] Figure 8 is a cross-sectional view of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure;

[0032] Fig.9A is a graph obtained by measuring the voltage and driving current of the driving gate according to the data voltage in the display device according to the comparative example; and

[0033] Fig. 9B is a graph obtained by measuring a voltage of a driving gate and a driving current according to a data voltage in a display device according to another exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving the advantages and features will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0035] The shapes, sizes, ratios, angles, quantities, etc. illustrated in the drawings used to describe the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally represent the same elements throughout the specification. In addition, in the following description of the present disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "having" and "comprising" used herein are generally intended to allow the addition of other components unless the term is used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0036] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0037] When terms such as “on,” “above,” “below,” or “next” are used to describe a positional relationship between two parts, one or more parts may be located between the two parts unless the terms are used together with the terms “immediately” or “directly.”

[0038] When an element or layer is disposed “on” another element or layer, the element or layer may be directly disposed on the other element or layer, or another layer or another element may be disposed between the element or layer and the other element or layer.

[0039] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below can be the second component in the technical concept of the present disclosure.

[0040] Like reference numbers generally refer to like elements throughout the specification.

[0041] The size and thickness of each component illustrated in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0042] The features of the various embodiments of the present disclosure may be partially or entirely related or combined with each other and may be technically related and operated in various ways, and the embodiments may be implemented independently of each other or in association with each other.

[0043] Hereinafter, a display device according to exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 is a schematic diagram of a display device 100 according to an exemplary embodiment of the present disclosure. Figure 1In the figure, for the convenience of description, among the components of the display device 100, the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are shown.

[0045] Reference Figure 1 The display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0046] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 2 and 3. It is shown that one gate driver GD is disposed to be spaced apart from one side of the display panel PN, but the number of the gate drivers GD and the arrangement thereof are not limited thereto.

[0047] The data driver DD supplies data voltages to a plurality of data lines DL (eg, signal lines) according to a plurality of data control signals and image data supplied from the timing controller TC. The data driver DD converts the image data into data voltages using a reference gamma voltage and may supply the converted data voltages to the plurality of data lines DL.

[0048] The timing controller TC aligns the image data input from the outside to supply the image data to the data driver DD. The timing controller TC can generate a gate control signal and a data control signal using synchronization signals input from the outside, such as a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal. In addition, the timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0049] The display panel PN is a configuration that displays an image to a user and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL cross each other and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL at their intersections.

[0050] In the display panel PN, an active area AA and a non-active area NA may be defined.

[0051] The active area AA is an area where an image is displayed in the display device 100. In the active area AA, a plurality of sub-pixels SP constituting a plurality of pixels PX and a pixel circuit (or a plurality of pixel circuits) for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units constituting the active area AA and n sub-pixels SP form one pixel PX (for example, n=3 or n=4). In each of the plurality of sub-pixels SP, a light emitting diode 120 and a thin film transistor for driving the light emitting diode 120 may be provided. The plurality of light emitting diodes 120 of the plurality of sub-pixels SP may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light emitting display panel, each of the light emitting diodes 120 may be a light emitting diode (LED) or a micro light emitting diode (LED).

[0052] In the active area AA, a plurality of signal lines for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of signal lines include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP and a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP. The plurality of scan lines SL extend in one direction in the active area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the active area AA to be connected to the plurality of sub-pixels SP. In addition, in the active area AA, a low potential power line and a high potential power line may be further provided, but the present disclosure is not limited thereto.

[0053] The non-active area NA is an area where no image is displayed, so that the non-active area NA can be defined as an area extending from the active area AA. In one embodiment, in a plan view of the display device, the non-active area NA surrounds the active area AA. In the non-active area NA, a link line for transmitting a signal to a sub-pixel SP, a pad electrode, or a driving IC (e.g., a gate driving IC or a data driving IC) of the active area AA may be provided.

[0054] Meanwhile, the non-active area NA may be located on the rear surface of the display panel PN, that is, on a surface on which the sub-pixel SP is not disposed or may be omitted, and is not limited as shown in the drawings.

[0055] Meanwhile, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-active area NA in a gate-in-panel (GIP) manner or between a plurality of sub-pixels SP in an active area AA in a gate-in-active-area (GIA) manner.

[0056] For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards, and the display panel PN is electrically connected to the data driver DD and the timing controller TC by bonding the flexible films and the printed circuit boards to pad electrodes formed in the non-active area NA of the display panel PN.

[0057] As another example, when the gate driver GD is installed in the active area AA in a GIA manner and the side lines SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN are formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-active area NA can be minimized on the front surface of the display panel PN. Therefore, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero frame without a frame can be substantially achieved, which will refer to Figure 2A and Figure 2B Describe in more detail.

[0058] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure.

[0059] In the non-active area NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to the plurality of sub-pixels SP are provided. For example, in the non-active area NA on the front surface of the display panel PN, a first pad electrode PAD1 for transmitting signals to the plurality of sub-pixels SP is provided. In the non-active area NA on the rear surface of the display panel PN, a second pad electrode PAD2 electrically connected to a driving component (e.g., a flexible film and a printed circuit board) is provided.

[0060] In this case, even though not shown in the drawings, various signal lines (eg, scan lines SL or data lines DL) connected to the plurality of sub-pixels SP extend from the active area AA to the non-active area NA to be electrically connected to the first pad electrode PAD1.

[0061] In addition, the side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, the driving component is disposed on the rear surface of the display panel PN, and a signal transmission path is formed between the front and rear surfaces of the display panel PN to minimize the size of the non-active area NA on the front surface of the display panel PN.

[0062] In addition, refer to Figure 2B , a spliced ​​display device TD with a large screen size can be realized by connecting a plurality of display devices 100. Figure 2A As shown, when the spliced ​​display device TD is implemented using the display device 100 with a minimized frame, the seam area where the image between the display devices 100 is not displayed is minimized, so that the display quality can be improved.

[0063] For example, one pixel PX may include a plurality of sub-pixels SP and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Therefore, the distance between pixels PX between the display devices 100 is configured to be constant to minimize a seam area.

[0064] However, Figure 2A and Figure 2B It is illustrative such that the display device 100 according to an exemplary embodiment of the present disclosure may be a general display device having a bezel, but is not limited thereto.

[0065] Below, we will refer to Figures 3 to 6 The display panel PN of the display device 100 according to an exemplary embodiment of the present disclosure is described in more detail.

[0066] Figure 3 is a schematic enlarged plan view of a pixel unit of an active area of ​​a display device according to an exemplary embodiment of the present disclosure. Figure 4 is an enlarged plan view of an active area of ​​a display device according to an exemplary embodiment of the present disclosure. Figure 5 is a cross-sectional view of a sub-pixel of a display device according to an exemplary embodiment of the present disclosure. Figure 6 is a simulation result that measures the crosstalk level according to the thickness of the insulation layer. Figure 3 , for convenience of description, among a plurality of wirings, only the scan lines SL and the data lines DL are shown, and only one pixel area UPA among a plurality of pixel areas UPA and a plurality of transmission areas TA surrounding the one pixel area UPA are shown.

[0067] Reference Figure 3, in the active area AA, a pixel area UPA in which a pixel PX is formed and a plurality of transmission areas TA surrounding the pixel area UPA are formed. In one embodiment, each transmission area TA has no pixel PX and is more transparent than the pixel area UPA. In each pixel PX in the active area AA, a pixel circuit including a driving element and a light emitting diode 120 driven by the pixel circuit are formed, so that a plurality of pixel areas UPA in which the pixel PX is formed may be substantially opaque areas. In addition, a plurality of transmission areas TA in which no pixel PX is formed may be substantially transparent areas. In this case, the pixel area UPA defined by the pixel PX formed therein is an area in which light emitted from the light emitting diode 120 is displayed, so that it is also defined as a light emitting area. In addition, the pixel area UPA defined by the pixel PX formed therein is an area in which a pixel circuit including a driving element is formed, so that it can also be defined as a circuit area.

[0068] In the active area AA, a plurality of pixel areas UPA are formed. Each of the plurality of pixel areas UPA is a region in which a driving element and a light emitting diode 120 are disposed to display an image. The plurality of pixel areas UPA may be disposed to be spaced apart from each other and a plurality of transmission areas TA are disposed therebetween. For example, the plurality of pixel areas UPA may be disposed by forming a plurality of rows and a plurality of columns.

[0069] A plurality of sub-pixels SP are disposed in each of the plurality of pixel areas UPA. Each of the plurality of sub-pixels SP includes a light emitting diode 120 and a pixel circuit to emit light independently. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 that emit light of different colors. For example, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel, but the present disclosure is not limited thereto.

[0070] Hereinafter, description will be made by assuming that one pixel PX includes two first subpixels SP1, two second subpixels SP2, and two third subpixels SP3, that is, for example, two red subpixels, two green subpixels, and two blue subpixels, but the configuration of the pixel PX is not limited thereto.

[0071] Meanwhile, a pair of first sub-pixels SP1, a pair of second sub-pixels SP2, and a pair of third sub-pixels SP3 may be used as main sub-pixels SP and redundant sub-pixels SP, respectively. For example, one first sub-pixel SP1 in a pair of first sub-pixels SP1, one second sub-pixel SP2 in a pair of second sub-pixels SP2, and one third sub-pixel SP3 in a pair of third sub-pixels SP3 may be main sub-pixels SP, which are basically used when the display device 100 is driven. When displaying an image, according to one embodiment, the main sub-pixels SP may be used. In addition, the remaining first sub-pixels SP1 in a pair of first sub-pixels SP1, the remaining second sub-pixels SP2 in a pair of second sub-pixels SP2, and the remaining third sub-pixels SP3 in a pair of third sub-pixels SP3 may be redundant sub-pixels SP, so that when the main sub-pixels SP are defective, the redundant sub-pixels SP may be used to replace the main sub-pixels.

[0072] In addition, the placement order of the main sub-pixels SP can be configured to be the same as the placement order of the redundant sub-pixels SP. For example, the sub-pixels SP forming the main sub-pixel SP are arranged in the order of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In addition, the sub-pixels SP forming the redundant sub-pixel SP can also be arranged in the order of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0073] However, a pair of first subpixels SP1, a pair of second subpixels SP2, and a pair of third subpixels SP3 are not limited to the main subpixels SP and the redundant subpixels SP, but all subpixels may always be used while driving the display device 100. In addition, the placement order of the subpixels SP is not limited to the above placement order.

[0074] The pixel area UPA may overlap with the wiring (e.g., data line DL and reference line RL) extending in the column direction among the plurality of wirings. In this article, the column direction may be referred to as the first direction. The pixel area UPA is formed in an area where a plurality of opaque wirings are provided to ensure the size of the transmission area TA in the entire active area AA. Specifically, due to the configuration such as the pixel circuit and the light emitting diode 120 provided in the plurality of sub-pixels SP, the pixel area UPA provided with the plurality of sub-pixels SP has a low transmittance and is substantially an opaque area. Therefore, the plurality of sub-pixels SP of the pixel area UPA may be arranged to overlap with the opaque wiring (e.g., data line DL, reference line RL, low potential power line VSS, and high potential power line VDD) extending in the column direction. Therefore, the plurality of sub-pixels SP of the pixel area UPA are arranged to overlap with the plurality of wirings to reduce the size of the opaque area in the entire active area AA and maximize the size of the transmission area TA.

[0075] In a plan view of the display device, a plurality of sub-pixels SP disposed in one pixel area UPA may be formed to have any one of a rectangular shape and an "L" shape. For example, a first sub-pixel SP1 (e.g., a first main sub-pixel), a second sub-pixel SP2 (e.g., a second main sub-pixel), and a third sub-pixel SP3 (e.g., a third main sub-pixel) are disposed on one side (e.g., a first side) of the scan line SL and a first sub-pixel SP1 (e.g., a first redundant sub-pixel), a second sub-pixel SP2 (e.g., a second redundant sub-pixel), and a third sub-pixel SP3 (e.g., a third redundant sub-pixel) may be disposed on the other side (e.g., a second side) of the scan line SL. In one embodiment, the first main sub-pixel SP1 and the first redundant sub-pixel SP1 emit light of a first color, the second main sub-pixel SP2 and the second redundant sub-pixel SP2 emit light of a second color, and the third main sub-pixel SP3 and the third redundant sub-pixel SP3 emit light of a third color.

[0076] At each of one side and the other side of the scan line SL, the first sub-pixel SP1 is disposed in a rectangular region and the second sub-pixel SP2 is disposed in an L-shaped region surrounding two adjacent sides of the four sides of the first sub-pixel SP1. In addition, the third sub-pixel SP3 may be disposed in an L-shaped region surrounding an outer portion of the L-shaped second sub-pixel SP2. Therefore, one pixel area UPA consisting of the first sub-pixel SP1 having a rectangular shape and the second sub-pixel SP2 and the third sub-pixel SP3 having an L shape may form a rectangular shape together. In one embodiment, in a plan view of the display device, the second sub-pixel SP2 is located between the first sub-pixel SP1 and the third sub-pixel SP3.

[0077] Each of the plurality of transmission areas TA is an area in the active area AA except for the area where the plurality of wirings and the plurality of pixel areas UPA are provided. That is, each transmission area TA may be an area in the active area AA where the plurality of wirings are not provided. In other words, the transmission area TA may not be affected by any wirings, pixel circuits, and light-emitting diodes. The transmittance of the plurality of transmission areas TA is higher than the transmittance of the plurality of pixel areas UPA. Light is transmitted through the transmission area TA and the background located on the rear surface of the display device 100 is seen from the front surface of the display device 100. The plurality of transmission areas TA may be spaced apart from each other and the plurality of wirings and the plurality of pixel areas UPA are provided therebetween. The plurality of transmission areas TA may be provided to surround the plurality of pixel areas UPA. Therefore, the display device 100 according to the exemplary embodiment of the present disclosure may be implemented as a transparent display device 100 including the plurality of transmission areas TA.

[0078] Reference Figures 3 to 5, each of the plurality of sub-pixels SP includes a pixel circuit and one or more light emitting diodes 120. The pixel circuit includes a plurality of transistors T1, T2, and DT and a storage capacitor Cst for supplying a driving current to the light emitting diode 120. For example, the pixel circuit may include a first transistor T1, a second transistor T2, a driving transistor DT, and a storage capacitor Cst. In addition, the plurality of sub-pixels SP disposed in one pixel area UPA are connected to a scan line SL, a plurality of data lines DL, a reference line RL, a high potential power line VDD, and a low potential power line VSS to be supplied with various signals.

[0079] First, the substrate 110 is a component for supporting various components included in the display device 100 and may be formed of an insulating material. For example, the substrate 110 may be formed of glass or resin. In addition, the substrate 110 may be configured to include polymer or plastic or may be formed of a material having flexibility.

[0080] A light shielding layer LS is disposed in each of a plurality of sub-pixels SP on the substrate 110. The light shielding layer LS blocks light incident on a driving active layer DACT of a driving transistor DT to be described below from below the substrate 110. Light incident on the driving active layer DACT of the driving transistor DT is blocked by the light shielding layer LS to minimize leakage current.

[0081] The buffer layer 111 is disposed on the substrate 110 and the light shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 can be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is composed of a single layer or a double layer, but is not limited thereto. However, depending on the type of the substrate 110 or the type of the transistor, the buffer layer 111 may be omitted, but the present disclosure is not limited thereto.

[0082] The driving transistor DT, the first transistor T1 , and the second transistor T2 are disposed in each of the plurality of sub-pixels SP on the buffer layer 111 .

[0083] The driving transistor DT, the first transistor T1, and the second transistor T2 of each of the plurality of sub-pixels SP may be a P-type thin film transistor or an N-type thin film transistor. For example, since holes move from the source to the drain in a P-type thin film transistor, current flows from the source to the drain. Since electrons move from the source to the drain in an N-type thin film transistor, current flows from the drain to the source. Hereinafter, description will be made assuming that the driving transistor DT, the first transistor T1, and the second transistor T2 are P-type thin film transistors in which current flows from the source to the drain, but the present disclosure is not limited thereto.

[0084] First, a driving transistor DT is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The driving transistor DT is a transistor that controls a driving current supplied to the light emitting diode 120. In one pixel area UPA, the driving transistor DT of each of the plurality of sub-pixels SP may be disposed in a row along a column direction. The plurality of driving transistors DT of the plurality of sub-pixels SP may be disposed in a row while overlapping an area where the reference line RL and the data line DL are disposed.

[0085] The driving transistor DT includes a driving active layer DACT, a driving gate DGE, a driving source DSE, and a driving drain DDE.

[0086] The driving active layer DACT is disposed on the buffer layer 111. The driving active layer DACT may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0087] The gate insulating layer 112 is disposed on the driving active layer DACT. The gate insulating layer 112 is an insulating layer that insulates the driving active layer DACT from the driving gate DGE. The gate insulating layer 112 may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) of single layer or double layer, but not limited to this.

[0088] The driving gate DGE is disposed on the gate insulating layer 112. The driving gate DGE may be composed of a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0089] The first interlayer insulating layer 113a is disposed on the driving gate DGE. A contact hole is formed in the first interlayer insulating layer 113a, and the driving source electrode DSE contacts the driving active layer DACT through the contact hole. The first interlayer insulating layer 113a is an insulating layer for protecting components below the first interlayer insulating layer 113a. The first interlayer insulating layer 113a may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) of single layer or double layer, but not limited to this.

[0090] The driving source electrode DSE is disposed on the first interlayer insulating layer 113a. The driving source electrode DSE is electrically connected to the driving active layer DACT through a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the driving source electrode DSE may be electrically connected to the second transistor T2. The driving source electrode DSE may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0091] The second interlayer insulating layer 113b is disposed on the driving source electrode DSE. The second interlayer insulating layer 113b is an insulating layer for protecting components below the second interlayer insulating layer 113b. The second interlayer insulating layer 113b may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) of single layer or double layer, but not limited to this.

[0092] The first passivation layer 114a is disposed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer that protects components below the first passivation layer 114a. The first passivation layer 114a may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) of single layer or double layer, but not limited to this.

[0093] The driving drain electrode DDE is disposed on the first passivation layer 114a. The driving drain electrode DDE is electrically connected to the driving active layer DACT through a contact hole formed in the first passivation layer 114a, the first interlayer insulating layer 113a, the second interlayer insulating layer 113b, and the gate insulating layer 112. In addition, the driving drain electrode DDE may be electrically connected to the low potential power supply line VSS through a contact hole formed in the first passivation layer 114a. The driving drain electrode DDE may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0094] Next, a first transistor T1 is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The first transistor T1 is a transistor that transmits a data voltage Vdata to a driving gate DGE of a driving transistor DT and is referred to as a switching transistor. At this time, the plurality of first transistors T1 of the plurality of sub-pixels SP are disposed to overlap with the scan line SL and the protruding portion of the scan line SL in one pixel area UPA, and may be disposed in a row along a row direction. Herein, the row direction may be referred to as a second direction.

[0095] Specifically, the scan line SL extends in the row direction on the gate insulating layer 112 and may be arranged across a plurality of pixel areas UPA. At this time, the scan line SL may include portions protruding toward both sides of the scan line SL toward a plurality of sub-pixels SP in an area overlapping with the plurality of pixel areas UPA. The portion protruding toward one side of the scan line SL may include a portion extending in the column direction and a portion extending from an end of the portion extending in the column direction toward the row direction. That is, the scan line SL may further include a protruding portion including a portion protruding from the scan line SL and extending at least partially in the row direction. For example, the portion protruding from one side of the scan line SL may be formed into an L shape. In addition, the portion protruding from the other side of the scan line SL may include a portion extending in the column direction.

[0096] In addition, the first transistors T1 of the plurality of sub-pixels SP at one side of the scan line SL may be arranged in a row along a portion of the protruding portion of the scan line SL extending in the row direction. In addition, the first transistors T1 of the plurality of sub-pixels SP at the other side of the scan line SL may be arranged in a row along the scan line SL extending in the row direction. Therefore, the plurality of first transistors T1 at one side of the scan line SL are arranged in a row along the row direction on the protruding portion of the scan line SL, and the plurality of first transistors T1 at the other side of the scan line SL may be arranged in a row along the row direction on the scan line SL. The scan line SL is divided into two branches in one pixel area UPA, so that the first transistor T1 of the main sub-pixel SP and the first transistor T1 of the redundant sub-pixel SP are easily separated. Therefore, the main sub-pixel SP and the redundant sub-pixel SP are connected to different first transistors T1 to be driven.

[0097] The first transistor T1 includes a first active layer ACT1, a first gate GE1, a first source SE1, and a first drain DE1.

[0098] The first active layer ACT1 is disposed between the buffer layer 111 and the gate insulating layer 112. The first active layer ACT1 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0099] The first gate GE1 is disposed on the gate insulating layer 112. The first gate GE1 may be electrically connected to the scan line SL. For example, the first gate GE1 may be formed integrally with the scan line SL. The first gate GE1 may be composed of a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0100] The first drain electrode DE1 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The first drain electrode DE1 is electrically connected to the first active layer ACT1 through a contact hole formed in the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the first drain electrode DE1 may be electrically connected to the second gate GE2 of the second transistor T2 through the contact hole of the first interlayer insulating layer 113a. The first drain electrode DE1 may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0101] The first source electrode SE1 is disposed on the first passivation layer 114a. The first source electrode SE1 is electrically connected to the first active layer ACT1 through a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. In addition, the first source electrode SE1 may be electrically connected to the data line DL. For example, the first source electrode SE1 may be formed integrally with the data line DL. The first source electrode SE1 may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0102] Next, a second transistor T2 is disposed in each of the plurality of sub-pixels SP on the buffer layer 111. The second transistor T2 is a transistor for compensating for the threshold voltage of the driving transistor DT and is referred to as a sensing transistor. The second transistors T2 of the plurality of sub-pixels SP may be disposed in a row along a portion of the protruding portion of the scan line SL extending in the column direction. For example, the second transistors T2 of the plurality of sub-pixels SP at one side of the scan line SL are disposed to correspond to a portion of the protruding portion of the scan line SL extending in the column direction. The second transistors T2 of the plurality of sub-pixels SP at the other side of the scan line SL may be disposed to correspond to the protruding portion of the scan line SL. Therefore, the plurality of second transistors T2 disposed in one pixel area UPA may be disposed in a row along the column direction.

[0103] The second transistor T2 includes a second active layer ACT2, a second gate GE2, a second source SE2, and a second drain DE2.

[0104] The second active layer ACT2 is disposed between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon, but is not limited thereto.

[0105] At this time, the second active layers ACT2 of the plurality of adjacent sub-pixels SP may be connected to each other. For example, the second active layers ACT2 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 disposed on one side of the scan line SL are connected to each other while extending in the column direction, and are connected to the second drain electrode DE2 disposed in the first sub-pixel SP1. In addition, the second active layers ACT2 of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 disposed on the other side of the scan line SL are connected to each other while extending in the column direction, and are connected to the second drain electrode DE2 disposed in the first sub-pixel SP1. That is, the connection portion of the channel region of the second active layer ACT2 connecting the plurality of sub-pixels SP and the reference line RL is formed by the transparent material of the second active layer ACT2 instead of the opaque conductive material. Therefore, the transmittance at the outermost edge of the pixel area UPA can be improved. In addition, the connection portion of the channel region of the second active layer ACT2 connecting the plurality of sub-pixels SP and the reference line RL is formed by the material of the second active layer ACT2, so that the contact hole can be omitted and the structure of the pixel area UPA can be simplified.

[0106] The second gate GE2 is disposed between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate GE2 may be electrically connected to the scan line SL. For example, the second gate GE2 may be formed integrally with a protruding portion of the scan line SL to be electrically connected. The second gate GE2 may be composed of a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0107] The second source electrode SE2 is disposed between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 through the contact hole of the first interlayer insulating layer 113a and the gate insulating layer 112. In addition, the second source electrode SE2 is integrally formed with the driving source electrode DSE to be electrically connected to the driving source electrode DSE. The second source electrode SE2 may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0108] The second drain electrode DE2 is disposed between the first passivation layer 114a and the second passivation layer 114b. The second drain electrode DE2 is electrically connected to the second active layer ACT2 through a contact hole formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain electrode DE2 is integrally formed with the reference line RL to be electrically connected to the reference line RL. The second drain electrode DE2 may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0109] Next, a storage capacitor Cst is disposed on the gate insulating layer 112. The storage capacitor Cst stores a potential difference between the driving gate DGE and the driving source DSE of the driving transistor DT while the light emitting diode 120 emits light, so that a constant driving current can be supplied to the light emitting diode 120. The storage capacitor Cst includes a first capacitor electrode C1 electrically connected to the driving gate DGE and a second capacitor electrode C2 electrically connected to the driving source DSE. Therefore, the storage capacitor Cst can constantly maintain the voltages of the driving gate DGE and the driving source DSE.

[0110] Specifically, the first capacitor electrode C1 is disposed on the gate insulating layer 112. The first capacitor electrode C1 is integrally formed with the driving gate DGE. The second capacitor electrode C2 is disposed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 may be disposed to overlap the first interlayer insulating layer 113a therebetween. At this time, the second capacitor electrode C2 is integrally formed with the driving source electrode DSE. The first capacitor electrode C1 and the second capacitor electrode C2 may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but the present disclosure is not limited thereto.

[0111] Next, an auxiliary electrode AE ​​is disposed on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode for electrically connecting the driving source electrode DSE and the first reflective electrode RE1. The driving source electrode DSE and the first reflective electrode RE1 are electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE ​​may be composed of a single layer or multiple layers of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0112] The low potential power line VSS is disposed on the second interlayer insulating layer 113b. The low potential power line VSS is disposed along the column direction and overlaps with the plurality of pixel areas UPA. The low potential power line VSS may be electrically connected to the driving drain electrode DDE. The low potential power line VSS may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0113] The reference line RL is disposed on the first passivation layer 114a. In one embodiment, the reference line RL overlaps the driving transistor DT. The reference line RL is disposed along the column direction and overlaps the plurality of pixel areas UPA. The reference line RL is disposed adjacent to the protruding portion of the scan line SL and may be electrically connected to the plurality of second transistors T2 disposed on the protruding portion of the scan line SL. The reference line RL may be composed of a single layer or multiple layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0114] A plurality of data lines DL are disposed on the first passivation layer 114a. The plurality of data lines DL extend in a column direction and overlap with the plurality of pixel areas UPA. The plurality of data lines DL include data lines DL connected to the first transistors T1 of the plurality of first sub-pixels SP1, data lines DL connected to the first transistors T1 of the plurality of second sub-pixels SP2, and data lines DL connected to the first transistors T1 of the plurality of third sub-pixels SP3. In one embodiment, as Figure 5 As shown, each data line DL overlaps with a corresponding driving transistor DT.

[0115] Next, a second passivation layer 114b is disposed on the driving transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference line RL, and the data line DL. The second passivation layer 114b is an insulating layer that protects components below the second passivation layer 114b and may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) of single layer or double layer, but not limited to this.

[0116] The first planarization layer 115a is disposed on the second passivation layer 114b. The first planarization layer 115a may planarize the upper portion of the substrate 110 on which the plurality of transistors and the storage capacitor Cst are disposed. The first planarization layer 115a may be composed of a single layer or a double layer, and may be formed of, for example, a photoresist or an acryl-based organic material, but is not limited thereto.

[0117] Meanwhile, even though not shown in the drawings, an additional passivation layer may be further disposed on the first planarization layer 115a. For example, a passivation layer made of silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed into a single or double layer passivation layer to protect the structure below the passivation layer.

[0118] Next, a plurality of first reflective electrodes RE1 are disposed on the first planarization layer 115a. The plurality of first reflective electrodes RE1 are disposed in each of the plurality of sub-pixels SP to electrically connect the driving transistor DT and the light emitting diode 120 and reflect light emitted from the light emitting diode 120 to the outside of the display device 100. The plurality of first reflective electrodes RE1 may be disposed adjacent to the driving source electrode DSE in each of the plurality of sub-pixels SP. The plurality of first reflective electrodes RE1 may be formed of an opaque conductive material having high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but the present disclosure is not limited thereto.

[0119] The second reflective electrode RE2 and the high potential power line VDD are disposed on the first planarization layer 115a. The second reflective electrode RE2 and the high potential power line VDD are integrally formed to reflect light emitted from the light emitting diode 120 to the outside of the display device 100 while supplying a high potential power supply voltage to the light emitting diode 120. The second reflective electrodes RE2 of the plurality of sub-pixels SP are connected to each other to be integrally formed. The second reflective electrode RE2 and the high potential power line VDD extend in the column direction and overlap the light emitting diode 120. The second reflective electrode RE2 and the high potential power line VDD may be disposed to overlap with a plurality of data lines DL, a reference line RL, and a low potential power line VSS. The second reflective electrode RE2 and the high potential power line VDD may be formed of an opaque conductive material having a high reflection efficiency, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, but the present disclosure is not limited thereto.

[0120] The third passivation layer 114c is disposed on the plurality of first reflective electrodes RE1 and the second reflective electrode RE2. The third passivation layer 114c is an insulating layer that protects components below the third passivation layer 114c and may be made of silicon oxide (SiO x ) or silicon nitride (SiN x ) of single layer or double layer, but not limited to this.

[0121] The adhesive layer AD is disposed on the third passivation layer 114c. The adhesive layer AD is formed on the front surface of the substrate 110 to fix the light emitting diode 120 disposed on the adhesive layer AD. The adhesive layer AD may be formed of a photocurable adhesive material that is photocured. For example, the adhesive layer AD may be selected from any one of an adhesive polymer, an epoxy resist, a UV resin, a polyimide, an acrylate, a polyurethane, and polydimethylsiloxane (PDMS), but is not limited thereto.

[0122] A plurality of light emitting diodes 120 are disposed in each of the plurality of sub-pixels SP on the adhesive layer AD. Each light emitting diode 120 is an element that emits light by current. And each light emitting diode 120 may include a red light emitting diode 120R that emits red light, a green light emitting diode 120G that emits green light, or a blue light emitting diode 120B that emits blue light. Light of various colors including white can be realized by a combination of a plurality of light emitting diodes 120 (for example, by a combination of a red light emitting diode 120R, a green light emitting diode 120G, and a blue light emitting diode 120B). For example, each light emitting diode 120 may be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0123] The red light emitting diode 120R may be disposed in the first sub-pixel SP1, the green light emitting diode 120G may be disposed in the second sub-pixel SP2, and the blue light emitting diode 120B may be disposed in the third sub-pixel SP3. The plurality of light emitting diodes 120 disposed in one pixel area UPA may be arranged in a row along the column direction. In addition, the plurality of light emitting diodes 120 may be arranged to overlap the second reflective electrode RE2 in each of the plurality of sub-pixels SP.

[0124] Meanwhile, when the plurality of sub-pixels SP are divided into the main sub-pixels SP and the redundant sub-pixels SP as described above, the plurality of light emitting diodes 120 may also be divided into the main light emitting diodes 120 and the redundant light emitting diodes 120. For example, one of the pair of first sub-pixels SP1, one of the pair of second sub-pixels SP2, and one of the pair of third sub-pixels SP3 is the main sub-pixel SP. Therefore, the red light emitting diode 120R, the green light emitting diode 120G, and the blue light emitting diode 120B provided in each of the main sub-pixels SP may be the main light emitting diode 120. For example, the other of the pair of first sub-pixels SP1, the other of the pair of second sub-pixels SP2, and the other of the pair of third sub-pixels SP3 may be the redundant sub-pixels SP. Therefore, the red light emitting diode 120R, the green light emitting diode 120G, and the blue light emitting diode 120B provided in each of the redundant sub-pixels SP may be the redundant light emitting diode 120.

[0125] Each of the plurality of light emitting diodes 120 includes a first semiconductor layer 121 , a light emitting layer 122 , a second semiconductor layer 123 , a first electrode 124 , a second electrode 125 , and an encapsulation film 126 .

[0126] The first semiconductor layer 121 is disposed on the adhesive layer AD and the second semiconductor layer 123 is disposed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping n-type impurities and p-type impurities into a specific material. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may be layers in which n-type impurities and p-type impurities are doped into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but are not limited thereto.

[0127] The light emitting layer 122 is disposed between the first semiconductor layer 121 and the second semiconductor layer 123. The light emitting layer 122 is supplied with holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123 to emit light. The light emitting layer 122 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0128] The first electrode 124 is disposed on the first semiconductor layer 121. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121. The first electrode 124 is an electrode electrically connecting the driving transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with n-type impurities and the first electrode 124 may be a cathode. The first electrode 124 may be disposed on the top surface of the first semiconductor layer 121 exposed from the light emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be composed of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0129] The second electrode 125 is disposed on the second semiconductor layer 123. The second electrode 125 may be disposed on the top surface of the second semiconductor layer 123. The second electrode 125 is an electrode electrically connecting the high potential power line VDD and the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities and the second electrode 125 may be an anode. The second electrode 125 may be composed of a transparent conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof, but is not limited thereto.

[0130] Next, the encapsulation film 126 is provided to surround the first semiconductor layer 121, the light emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The encapsulation film 126 is formed of an insulating material to protect the first semiconductor layer 121, the light emitting layer 122, and the second semiconductor layer 123. In the encapsulation film 126, a contact hole exposing the first electrode 124 and a contact hole exposing the second electrode 125 are formed to electrically connect the first connection electrode CE1 and the second connection layer CE2 to the first electrode 124 and the second electrode 125, respectively.

[0131] At the same time, a portion of the side surface of the first semiconductor layer 121 may be exposed from the encapsulation film 126 (in other words, the portion of the side surface may not be covered by the encapsulation film 126). During the manufacturing process of the display device 100, the light emitting diode 120 manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, in the process of separating the light emitting diode 120 from the wafer, a portion of the encapsulation film 126 may be torn. For example, a portion of the encapsulation film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light emitting diode 120 is torn during the process of separating the light emitting diode 120 from the wafer. Therefore, a portion of the lower side surface of the first semiconductor layer 121 may be exposed to the outside. Even if the lower portion of the light emitting diode 120 is exposed from the encapsulation film 126, after forming the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer 121, the first connection electrode CE1 and the second connection electrode CE2 are formed. Therefore, short circuit defects can be reduced or prevented.

[0132] Next, the second planarization layer 115 b and the third planarization layer 115 c are disposed on the adhesive layer AD and the light emitting diode 120 .

[0133] The second planarization layer 115b overlaps a portion of the side surface of the plurality of light emitting diodes 120 to fix and protect the plurality of light emitting diodes 120. The torn portion of the encapsulation film 126 protecting the side surface of the first semiconductor layer 121 of the light emitting diodes 120 may be covered by the second planarization layer 115b. Thus, contact between the connection electrode and the first semiconductor layer 121 and a short circuit defect may be suppressed thereafter.

[0134] The third planarization layer 115c is formed to cover the second planarization layer 115b and the upper portion of the light emitting diode 120. A contact hole exposing the first electrode 124 of the light emitting diode 120 and a contact hole exposing the second electrode 125 are formed in the third planarization layer 115c. The first electrode 124 and the second electrode 125 of the light emitting diode 120 are exposed from the third planarization layer 115c (in other words, at least a portion of the first electrode 124 and at least a portion of the second electrode 125 may not be covered by the third planarization layer 115c), and the third planarization layer 115c is partially disposed in a region between the first electrode 124 and the second electrode 125 to reduce short circuit defects. The second planarization layer 115b and the third planarization layer 115c may be composed of a single layer or a double layer, and, for example, may be formed of a photoresist or an acrylic organic material, but the present disclosure is not limited thereto.

[0135] The first and second link electrodes CE1 and CE2 are disposed on the third planarization layer 115c.

[0136] The first connection electrode CE1 is an electrode that electrically connects the first electrode 124 of the light emitting diode 120 and the driving transistor DT. The first connection electrode CE1 is electrically connected to the first electrode 124 exposed from the third planarization layer 115c and is simultaneously electrically connected to the first reflective electrode RE1 through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, the adhesive layer AD, and the third passivation layer 114c. Therefore, the first electrode 124 and the driving source electrode DSE may be electrically connected through the first connection electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0137] The second connection electrode CE2 is an electrode that electrically connects the second electrode 125 of the light emitting diode 120 and the high potential power line VDD. The second connection electrode CE2 is electrically connected to the second electrode 125 exposed from the third planarization layer 115c. And, the second connection electrode CE2 is electrically connected to the second reflective electrode RE2 and the high potential power line VDD through a contact hole formed in the third planarization layer 115c, the second planarization layer 115b, the adhesive layer AD, and the third passivation layer 114c. Therefore, the second electrode 125 and the high potential power line VDD are electrically connected through the second connection electrode CE2.

[0138] The first connection electrode CE1 and the second electrode CE2 may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but are not limited thereto.

[0139] Meanwhile, in the drawings, the driving source DSE of the driving transistor DT is shown to be electrically connected to the first electrode 124 of the light emitting diode 120. However, the driving drain DDE of the driving transistor DT and the second electrode 125 of the light emitting diode 120 may be electrically connected according to the type of the driving transistor DT and the design of the pixel circuit.

[0140] Next, in the pixel area UPA, a bank BB is disposed on the third planarization layer 115c, the first connection electrode CE1, and the second connection electrode CE2. The bank BB may be disposed to be spaced apart from the light emitting diode 120 by a predetermined interval. The bank BB is disposed at a boundary between the plurality of sub-pixels SP and covers a portion of the first connection electrode CE1 and the second connection electrode CE2. The bank BB may be disposed to be spaced apart from the transmission area TA. The bank BB may be formed of an opaque material to reduce color mixing between the plurality of sub-pixels SP and may be formed of, for example, a black resin, but is not limited thereto.

[0141] The protective layer 116 is disposed on the first connection electrode CE1, the second connection electrode CE2 and the bank BB. The protective layer 116 is a layer for protecting the structure below the protective layer 116. The protective layer 116 may be configured as a single layer or a double layer, and may be made of, for example, benzocyclobutene (BCB), a semi-transparent epoxy resin, a photoresist, an acrylic organic material, or a silicon oxide (SiO x ) or silicon nitride (SiN x ) is formed by inorganic materials, but is not limited to this.

[0142] Meanwhile, in order to expand the size of the transmission area TA, the plurality of sub-pixels SP may be arranged to overlap with the plurality of wirings. At this time, a driving current fluctuation may occur in each of the plurality of sub-pixels SP due to some wirings. For example, the driving transistor DT and the storage capacitor Cst of each of the plurality of sub-pixels SP overlap with the data line DL to be coupled to the data line DL. Figure 5 As shown, the data line DL overlaps at least one of the driving source electrode DSE, the driving gate electrode DGE, or the driving active layer DACT. In this case, the voltage of the driving gate electrode DGE may fluctuate due to the data line to which different voltages are applied in each frame. As the voltage of the driving gate electrode DGE fluctuates, the driving current flowing through the light emitting diode 120 fluctuates, and the brightness changes due to crosstalk, thereby reducing the display quality.

[0143] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the thickness of the insulating layer is adjusted in consideration of the dielectric constant of the insulating layer disposed between the storage capacitor Cst and the driving transistor DT and the data line DL. Therefore, the voltage fluctuation of the driving gate DGE caused by the data line DL can be reduced. For example, the inorganic insulating layer disposed on the substrate 110, that is, the insulating layer such as the buffer layer 111, the gate insulating layer 112, the first interlayer insulating layer 113a and the second passivation layer 114b, can be formed to have a thickness of several thousand angstroms. However, the thickness of the first passivation layer 114a and the second interlayer insulating layer 113b, which are insulating layers disposed between the data line DL and the storage capacitor Cst, is different from the thickness of other insulating layers, which is at least several micrometers (μm). Thus, the voltage fluctuation of the driving transistor DT caused by the data line DL can be minimized. Therefore, the thickness of the insulating layer between the data line DL and the storage capacitor Cst can be greater than the thickness of the buffer layer 111, the thickness of the gate insulating layer 112, the thickness of the first interlayer insulating layer 113a, and the thickness of the second passivation layer 114b.

[0144] Reference Figure 6 , when the width of the data line DL is 1 μm, the thickness of the insulating layer can be determined by the material and dielectric constant of the insulating layer disposed under the data line DL. As the thickness of the insulating layer increases, the level of brightness variation due to crosstalk decreases. At this time, when the insulating layer is made of silicon nitride (SiN) having a dielectric constant of about 6.69 and a target crosstalk of 2%, the brightness variation level due to crosstalk is reduced. x ), the thickness of the insulating layer is formed to be about 16.55 μm or more to control the brightness variation level due to crosstalk to less than 2%. At this time, when the insulating layer is made of silicon oxide (SiO2) having a dielectric constant of about 4.3 and a target crosstalk of 2%, the thickness of the insulating layer is formed to be about 16.55 μm or more to control the brightness variation level due to crosstalk to less than 2%. x ) is formed, the thickness of the insulating layer is formed to be about 10.64 μm or more to control the brightness variation level due to crosstalk to less than 2%. Therefore, when the width of the data line DL is 1 μm, the total thickness of the first passivation layer 114a and the second interlayer insulating layer 113b is formed to be at least 10.64 μm or more to minimize the fluctuation of the voltage of the driving transistor DT and the storage capacitor Cst connected to the driving transistor DT due to the data line DL. In addition, as the width of the data line DL increases, a thicker insulating layer may be required to achieve the same level of crosstalk.

[0145] Therefore, the total thickness of the first passivation layer 114a and the second interlayer insulating layer 113b may be determined in consideration of the width of the data line DL, the dielectric constants of the first passivation layer 114a and the second interlayer insulating layer 113b, and the target crosstalk level. In addition, the driving current may be kept constant while minimizing interference between the data line DL and the driving transistor DT and the storage capacitor Cst connected to the driving transistor DT.

[0146] In the display device 100 according to an exemplary embodiment of the present disclosure, a plurality of pixel areas UPA are arranged in an area in which a plurality of wirings extending in a column direction are arranged to maximize the size of the transmission area TA. A substantially opaque pixel area UPA including a pixel circuit and a light emitting diode 120 is arranged together with an opaque wiring to reduce the size of the opaque area in the active area AA. For example, in a plan view of the display device 100, a data line DL and / or a reference line RL (as an example of an opaque wiring extending in a column direction) may be arranged to overlap with the light emitting diode 120. For example, in a cross-sectional view of the display device 100, a data line DL and / or a reference line RL may be arranged between the light emitting diode 120 and a thin film transistor (e.g., a driving transistor DT) and / or a storage capacitor Cst of a pixel circuit. Therefore, the size of the transmission area TA is maximized to improve the overall transmittance of the display device 100 and realize a transparent display device 100.

[0147] In the display device 100 according to the exemplary embodiment of the present disclosure, the voltage fluctuation of the driving transistor DT caused by the data line DL can be minimized or at least reduced. When the data line DL and the pixel area UPA are formed to overlap to ensure the size of the transmission area TA, the configuration of the data line DL and the pixel area UPA can be coupled to cause the voltage to fluctuate. For example, the data line DL overlaps the driving transistor DT and the storage capacitor Cst, so that it can be coupled to the driving transistor DT and the storage capacitor Cst, and the voltage of the driving transistor DT and the storage capacitor Cst can fluctuate, so that the brightness fluctuates, and the display quality may be reduced. Therefore, the insulating layer between the data line DL and the driving transistor DT and the storage capacitor Cst is formed to be thicker to minimize or at least reduce the influence of the data line DL. At this time, the thickness of the insulating layer can be determined in consideration of the dielectric constant of the insulating layer, the width of the data line DL, and the target crosstalk level. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the thickness of the insulating layer between the data line DL and the driving transistor DT among the plurality of insulating layers is formed to be relatively thick. Therefore, the fluctuation of the driving current caused by the data line DL is minimized or at least reduced, and the display quality can be improved.

[0148] Figure 7is an enlarged plan view of a display device according to another exemplary embodiment of the present disclosure. Figure 8 is a cross-sectional view of a sub-pixel of a display device according to another exemplary embodiment of the present disclosure. Fig.9A is a graph obtained by measuring the voltage and the driving current of the driving gate according to the data voltage in the display device according to the comparative example. Fig. 9B is a graph obtained by measuring the voltage and driving current of the driving gate according to the data voltage in the display device according to another exemplary embodiment of the present disclosure. Figure 7 and Figure 8 In the display panel PN′, only the low potential power line VSS is different from Figures 1 to 5 The display panel PN is the same as that of the previous embodiment, and other configurations are basically the same, so repeated descriptions will be omitted.

[0149] Reference Figure 7 and Figure 8 , the low potential power line VSS is arranged to overlap with the plurality of data lines DL between the second interlayer insulating layer 113b and the first passivation layer 114a. The low potential power line VSS may overlap with the region where the plurality of data lines DL are arranged. The low potential power line VSS has a relatively large width so that one low potential power line VSS overlaps with the plurality of data lines DL. The low potential power line VSS may cover the storage capacitors Cst and the driving transistors DT of the plurality of sub-pixels SP′. Only the low potential power line VSS is arranged between the second interlayer insulating layer 113b and the first passivation layer 114a, so that the low potential power line VSS may be easily formed in the remaining regions except for the region where the contact hole is arranged.

[0150] In the low potential power line VSS, an opening overlapping with the contact hole may be formed. For example, in the low potential power line VSS, an opening overlapping with the contact hole through which the first source electrode SE1 and the first active layer ACT1 are connected and the contact hole through which the driving drain electrode DDE and the driving active layer DACT are connected may be formed. The first source electrode SE1 and the driving drain electrode DDE are arranged on the low potential power line VSS, and the first active layer ACT1 and the driving active layer DACT are arranged below the low potential power line VSS. Therefore, an opening is formed in the low potential power line VSS to easily connect the structure connected to the upper and lower parts of the low potential power line VSS.

[0151] The low potential power line VSS is provided between the storage capacitor Cst and the plurality of data lines DL and between the driving transistor DT and the plurality of data lines DL to serve as a blocking film that blocks the voltage fluctuation of the driving transistor DT caused by the data lines DL. The low potential power line VSS to which a constant voltage is applied is provided between the storage capacitor Cst and the driving transistor DT and the data lines DL to suppress the coupling of the data lines DL with the storage capacitor Cst and the driving transistor DT. The low potential power line VSS is provided to at least cover the driving gate DGE of the driving transistor DT to protect the voltage DTG of the driving gate DGE from fluctuation due to the data lines DL.

[0152] Below, we will refer to Fig.9A and Fig. 9B Describe the effect of extending the low potential power supply line VSS.

[0153] Reference Fig.9A , the display device 10 according to the comparative example has a structure in which the low potential power line VSS is not provided between the data line DL and the driving transistor DT. In the display panel 10 according to the comparative example, a separate barrier film is not provided between the data line DL and the driving transistor DT, thereby confirming that the voltage DTG of the driving gate DGE fluctuates according to the voltage fluctuation of the data line DL. It is also confirmed that as the voltage DTG of the driving gate DGE fluctuates, the driving current ILED flowing through the light emitting diode 120 also fluctuates. In this case, the brightness fluctuates, and thus the display quality may be deteriorated.

[0154] Reference Fig. 9B In a display panel PN′ according to another exemplary embodiment of the present disclosure, a low potential power line VSS used as a barrier film is provided between the data line DL and the driving transistor DT and between the data line DL and the storage capacitor Cst. Therefore, even if the voltage of the data line DL fluctuates, the voltage DTG of the driving gate DGE and the driving current ILED can be kept constant. Therefore, the brightness is kept constant and the display quality can be improved.

[0155] In a display panel PN′ according to another exemplary embodiment of the present disclosure, a low potential power line VSS is formed between the data line DL and the driving transistor DT to minimize the voltage fluctuation of the driving transistor DT caused by the data line DL. The low potential power line VSS may be arranged to cover the driving transistor DT and the storage capacitor Cst under the plurality of data lines DL. The low potential power line VSS, which always maintains a constant voltage, can block the plurality of data lines DL from interfering with the driving transistor DT and the storage capacitor Cst. In this case, in the case where no insulating layer is formed between the plurality of data lines DL and the driving transistor DT and the storage capacitor Cst is thick, the voltage DTG of the driving gate DGE and the driving current ILED can be kept constant. In addition, instead of forming a separate blocking film, the size of the existing low potential power line VSS is enlarged to correspond to the area where the plurality of data lines DL are provided, so that the low potential power line VSS is used as a blocking film. In addition, the manufacturing process of the display panel PN′ can be simplified. Therefore, in a display panel PN′ according to another exemplary embodiment of the present disclosure, the low potential power line VSS is formed with an increased size so as to overlap with all the plurality of data lines DL. Therefore, the driving current ILED of the sub-pixel SP′ can be kept constant, and the reliability of the display panel PN′ is improved.

[0156] Meanwhile, in the prior art, the main light emitting diode and the redundant light emitting diode are arranged together in one sub-pixel, and the main light emitting diode and the redundant light emitting diode are connected in parallel in one pixel circuit. In this case, the first electrode and the second electrode of the main light emitting diode and the first electrode and the second electrode of the redundant light emitting diode are connected to the same node, that is, the same electrode. When a short circuit defect occurs in the light emitting diode or the pixel circuit in this structure, both the main light emitting diode and the redundant light emitting diode connected in parallel and sharing a specific electrode become dark to cause a defect. In addition, it is difficult to separate and repair only the defective light emitting diode.

[0157] In contrast, in the display panels PN and PN′ according to various exemplary embodiments of the present disclosure, as described above, a plurality of sub-pixels SP and SP′ are divided into main sub-pixels SP and SP′ including a main light emitting diode 120 and redundant sub-pixels SP and SP′ including a redundant light emitting diode 120. In addition, the main light emitting diode 120 of the main sub-pixels SP and SP′ and the redundant light emitting diode 120 of the redundant sub-pixels SP and SP′ can be driven independently. That is, a pixel circuit for driving the main light emitting diode 120 and a pixel circuit for driving the redundant light emitting diode 120 can be formed separately. For example, in the scan line SL extending in the row direction, an L-shaped protrusion is further formed. One of the first transistor T1 for driving the main light emitting diode 120 and the first transistor T1 for driving the redundant light emitting diode 120 is formed on the scan line SL and the other is formed on the L-shaped protrusion. Therefore, the first transistor T1 for driving the main light emitting diode 120 and the first transistor T1 for driving the redundant light emitting diode 120 can be formed separately. Therefore, a protrusion is further formed in the scan line SL to independently form the first transistor T1 for the main light emitting diode 120 and the first transistor T1 for the redundant light emitting diode 120 and independently drive the main light emitting diode 120 and the redundant light emitting diode 120. Therefore, in the display panels PN and PN' according to various exemplary embodiments of the present disclosure, the main light emitting diode 120 and the redundant light emitting diode 120 are connected to different pixel circuits. Therefore, a defect of a specific sub-pixel SP or SP' does not affect another sub-pixel SP or SP', and only the defective sub-pixel SP or SP' can be easily detected and repaired.

[0158] Exemplary embodiments of the present disclosure may also be described as follows:

[0159] According to one aspect of the present disclosure, a display device includes: a substrate in which a plurality of pixel regions arranged to be spaced apart from each other and a plurality of transmission regions arranged between the plurality of pixel regions are defined; and a plurality of data lines extending along a column direction on the substrate. The plurality of pixel regions overlap with a region in which the plurality of data lines are arranged.

[0160] The display device may further include a plurality of sub-pixels arranged in each of the plurality of pixel regions. The plurality of sub-pixels may include a first sub-pixel having a rectangular shape, a second sub-pixel surrounding two adjacent sides of four sides of the first sub-pixel, and a third sub-pixel surrounding an outer portion of the second sub-pixel, and the first sub-pixel, the second sub-pixel, and the third sub-pixel may form a rectangle.

[0161] The display device may further include a scan line extending in a row direction across the plurality of pixel regions on the substrate. The plurality of sub-pixels in each of the plurality of pixel regions may be formed by a first sub-pixel, a second sub-pixel, and a third sub-pixel disposed on one side of the scan line and a first sub-pixel, a second sub-pixel, and a third sub-pixel disposed on the other side (e.g., the opposite side) of the scan line.

[0162] Each of the multiple sub-pixels may also include a first transistor arranged between the multiple data lines and the substrate and electrically connected to the multiple data lines, a driving transistor arranged between the multiple data lines and the substrate and electrically connected to the first transistor, a second transistor arranged between the multiple data lines and the substrate and electrically connected to the driving transistor, a storage capacitor arranged between the multiple data lines and the substrate and electrically connected to the gate of the driving transistor, and a light emitting diode arranged on the multiple data lines and electrically connected to the driving transistor.

[0163] In one pixel region among the plurality of pixel regions, the first transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in a row along a row direction.

[0164] In a pixel area among multiple pixel areas, the scan line may include a protrusion that protrudes from the scan line and extends at least partially in the row direction, a first transistor of a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged on one side of the scan line may be arranged on the protrusion of the scan line, and a first transistor of a first sub-pixel, a second sub-pixel, and a third sub-pixel arranged on the other side of the scan line may be arranged on the scan line.

[0165] In one pixel region among the plurality of pixel regions, the second transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in a row along a column direction.

[0166] In one pixel region among the plurality of pixel regions, driving transistors of the first sub-pixel, the second sub-pixel, and the third sub-pixel may be arranged in a row along a column direction.

[0167] In one pixel region among the plurality of pixel regions, the light emitting diodes of the first sub-pixel, the second sub-pixel and the third sub-pixel may be arranged in a row along a column direction.

[0168] A plurality of data lines may be disposed on and may overlap the driving transistor and the storage capacitor.

[0169] The display device may further include a buffer layer disposed between the substrate and the driving transistor, a gate insulating layer disposed between a driving gate of the driving transistor and a driving active layer on the buffer layer, a first interlayer insulating layer covering the driving transistor, and one or more insulating layers covering the storage capacitor on the first interlayer insulating layer. The plurality of data lines may be disposed on the one or more insulating layers and the thickness of the one or more insulating layers may be greater than the thickness of the buffer layer, the thickness of the gate insulating layer, and the thickness of the first interlayer insulating layer.

[0170] The display device may further include a low potential power line disposed between the storage capacitor and the plurality of data lines. The low potential power line may overlap with a region where the plurality of data lines are disposed.

[0171] The low potential power supply line may overlap the driving transistor and the storage capacitor.

[0172] The driving active layer of the driving transistor and the first active layer of the first transistor can be set below the low potential power line, the driving drain of the driving transistor and the first source of the first transistor can be set on the low potential power line, and the low potential power line may include multiple openings, which overlap with the contact holes for connecting the driving active layer and the driving drain and the contact holes for connecting the first active layer and the first source.

[0173] According to another aspect of the present disclosure, a display device may include: a substrate including a plurality of pixel regions spaced apart from each other and a plurality of transmission regions between the plurality of pixel regions, wherein each of the plurality of pixel regions includes a plurality of sub-pixels; and a plurality of signal lines extending along a first direction on the substrate, wherein the plurality of sub-pixels include a plurality of pixel circuits, wherein the plurality of signal lines overlap with the plurality of pixel regions, and the plurality of signal lines do not overlap with the plurality of transmission regions.

[0174] Each sub-pixel may include a light emitting diode, and each of the plurality of signal lines may be disposed so as to overlap with at least one of the light emitting diodes in a plan view of the display device.

[0175] Each pixel circuit may include a thin film transistor and a storage capacitor, wherein, in a cross-sectional view of the display device, each of the plurality of signal lines may be arranged between at least one light emitting diode and at least one thin film transistor and / or storage capacitor.

[0176] The plurality of transmission regions may be disposed directly adjacent to the plurality of pixel regions.

[0177] The display device may further include: a scan line extending along a second direction across multiple pixel areas on the substrate, the second direction being different from the first direction, wherein multiple sub-pixels in each of the multiple pixel areas may include a first main sub-pixel, a second main sub-pixel, and a third main sub-pixel on a first side of the scan line and a first redundant sub-pixel, a second redundant sub-pixel, and a third redundant sub-pixel on a second side of the scan line, wherein the first main sub-pixel and the first redundant sub-pixel emit light of a first color, the second main sub-pixel and the second redundant sub-pixel emit light of a second color, and the third main sub-pixel and the third redundant sub-pixel emit light of a third color.

[0178] The plurality of signal lines may include at least one of a plurality of data lines and a plurality of reference lines.

[0179] Each of the multiple sub-pixels may also include: a first transistor, between a data line among the multiple data lines and the substrate, the first transistor is electrically connected to the data line; a driving transistor, between the data line and the substrate, the driving transistor is electrically connected to the first transistor; a second transistor, between the data line and the substrate, the second transistor is electrically connected to the driving transistor; a storage capacitor, between the data line and the substrate, the storage capacitor is electrically connected to the gate of the driving transistor; and a light emitting diode, above the data line, the light emitting diode is electrically connected to the driving transistor.

[0180] In one pixel region among the plurality of pixel regions, a first transistor of a first sub-pixel, a first transistor of a second sub-pixel, and a first transistor of a third sub-pixel may be arranged in a row along a second direction different from the first direction.

[0181] In a pixel area, a scan line may include a protruding portion protruding from the scan line in a first direction and extending at least partially in a second direction, a first transistor of a first main sub-pixel, a first transistor of a second main sub-pixel, and a first transistor of a third main sub-pixel on a first side of the scan line may be on the protruding portion of the scan line, and a first transistor of a first redundant sub-pixel, a first transistor of a second redundant sub-pixel, and a first transistor of a third redundant sub-pixel on a second side of the scan line may be on the scan line, wherein the first main sub-pixel and the first redundant sub-pixel may emit light of a first color, the second main sub-pixel and the second redundant sub-pixel may emit light of a second color, and the third main sub-pixel and the third redundant sub-pixel may emit light of a third color.

[0182] In one pixel region among the plurality of pixel regions, the second transistor of the first sub-pixel, the second transistor of the second sub-pixel, and the second transistor of the third sub-pixel may be arranged in a row along the first direction.

[0183] In one pixel region among the plurality of pixel regions, a driving transistor of a first sub-pixel, a driving transistor of a second sub-pixel, and a driving transistor of a third sub-pixel may be arranged in a row along a first direction.

[0184] In one pixel region among the plurality of pixel regions, the light emitting diode of the first sub-pixel, the light emitting diode of the second sub-pixel, and the light emitting diode of the third sub-pixel may be arranged in a row along the first direction.

[0185] A plurality of signal lines may be above and overlap the drive transistor and the storage capacitor.

[0186] The display device may also include: a buffer layer between the substrate and the driving transistor; a gate insulating layer on the buffer layer, the gate insulating layer between the driving gate of the driving transistor and the driving active layer; a first interlayer insulating layer covering the driving transistor; and one or more insulating layers covering the storage capacitor on the first interlayer insulating layer, wherein a plurality of signal lines are arranged on the one or more insulating layers, and the thickness of the one or more insulating layers may be greater than the thickness of the buffer layer, the thickness of the gate insulating layer, and the thickness of the first interlayer insulating layer.

[0187] The display device may further include: a power line between the storage capacitor and the plurality of signal lines, the power line overlapping the plurality of signal lines.

[0188] The power supply line may include or may be a low potential power supply line or a high potential power supply line.

[0189] The power supply line may overlap the driving transistor and the storage capacitor.

[0190] The driving active layer of the driving transistor and the first active layer of the first transistor may be below the power line, the driving drain of the driving transistor and the first source of the first transistor may be on the power line, and the power line may include multiple openings, and the multiple openings overlap with the contact holes for connecting the driving active layer and the driving drain and the contact holes for connecting the first active layer and the first source.

[0191] The display device may include a reference line, wherein the reference line extends along a first direction on the substrate and overlaps the plurality of pixel regions.

[0192] The reference line may not overlap with the plurality of transmissive regions.

[0193] In a plan view of the display device, the reference line may overlap with at least one light emitting diode.

[0194] In a cross-sectional view of the display device, the reference line may be disposed between at least one light emitting diode and at least one driving transistor and / or storage capacitor.

[0195] The reference line may be electrically connected to the second transistor, and the reference line may be disposed at the same height as the data line.

[0196] The reference line may be formed integrally with the second drain of the second transistor.

[0197] The multiple sub-pixels may include: a first sub-pixel having a rectangular shape in a plan view of the display device; a second sub-pixel surrounding two adjacent sides of the four sides of the first sub-pixel in the plan view; and a third sub-pixel surrounding an outer portion of the second sub-pixel in the plan view, wherein the first sub-pixel, the second sub-pixel and the third sub-pixel together form a rectangular shape.

[0198] According to another aspect of the present disclosure, a display device may include: a substrate including a pixel area and a transmissive area that is more transparent than the pixel area; a driving transistor in the pixel area; a power line above the driving transistor in the pixel area; a signal line above the power line in the pixel area; and a light emitting diode in the pixel area, the light emitting diode being electrically connected to the driving transistor.

[0199] The driving transistor may include a gate electrode, a source electrode, a drain electrode, and an active layer, and the signal line overlaps at least one of the source electrode, the gate electrode, or the active layer.

[0200] In the cross-sectional view, the signal line may be between the driving transistor and the power line, and overlap with the driving transistor and the power line.

[0201] The signal line may be a data line configured to supply a data voltage.

[0202] The display device may include: a first insulating layer on a substrate.

[0203] The display device may include: a second insulating layer between the signal line and the driving transistor.

[0204] The first insulating layer may be between the substrate and the driving transistor, or between different layers of the driving transistor, or between the driving transistor and the second insulating layer.

[0205] The thickness of the second insulating layer may be greater than the thickness of the first insulating layer.

[0206] The first insulating layer may include: at least one buffer layer between the substrate and the driving transistor; a gate insulating layer between a gate of the driving transistor and the active layer; and a first interlayer insulating layer covering the driving transistor.

[0207] The power supply line may be a low potential power supply line overlapping the signal line and the driving transistor.

[0208] The display device may further include a scan line, wherein in the pixel region, the scan line includes a first portion protruding from the scan line in a first direction and a second portion extending at least partially in a second direction different from the first direction in the pixel region.

[0209] The pixel region may include a plurality of main sub-pixels on a first side of the second portion of the scan line and a plurality of redundant sub-pixels on a second side of the second portion of the scan line.

[0210] The plurality of main sub-pixels may include a first main sub-pixel configured to emit light of a first color, a second main sub-pixel configured to emit light of a second color, and a third main sub-pixel configured to emit light of a third color, and the plurality of redundant sub-pixels may include a first redundant sub-pixel configured to emit light of the first color, a second redundant sub-pixel configured to emit light of the second color, and a third redundant sub-pixel configured to emit light of the third color, wherein each of the plurality of main sub-pixels and each of the plurality of redundant sub-pixels may include a corresponding pixel driving circuit.

[0211] According to another aspect of the present disclosure, a display device may include: a substrate, in which a plurality of pixel regions arranged to be spaced apart from each other and a plurality of transmission regions arranged between the plurality of pixel regions are defined; and a plurality of wirings extending along a column direction on the substrate, wherein the plurality of pixel regions overlap with a region where the plurality of wirings are arranged.

[0212] The wiring may include one or more of a data line, a reference line, a low potential power line, and a high potential power line.

[0213] In a plan view of the display device, at least one of the plurality of wirings may overlap with a light emitting diode and / or a thin film transistor of a pixel circuit provided in a pixel region.

[0214] In the cross-sectional view of the display device, at least one of the plurality of wirings may be provided between a light emitting diode and a thin film transistor of a pixel circuit provided in a pixel region.

[0215] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto, and the present disclosure may be implemented in a variety of different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure.

Claims

1. A display device, comprising: a substrate including a plurality of pixel regions spaced apart from each other and a plurality of transmission regions between the plurality of pixel regions, wherein each of the plurality of pixel regions includes a plurality of sub-pixels; and a plurality of signal lines extending along a first direction on the substrate, The plurality of sub-pixels include a plurality of pixel circuits, wherein the plurality of signal lines overlap with the plurality of pixel circuits, and the plurality of signal lines do not overlap with the plurality of transmission areas.

2. The display device according to claim 1, further comprising: a scan line, the scan line extending on the substrate across the plurality of pixel regions along a second direction, the second direction being different from the first direction, The plurality of sub-pixels in each of the plurality of pixel regions include a first main sub-pixel, a second main sub-pixel, and a third main sub-pixel on a first side of the scan line and a first redundant sub-pixel, a second redundant sub-pixel, and a third redundant sub-pixel on a second side of the scan line. The first main sub-pixel and the first redundant sub-pixel emit light of a first color, the second main sub-pixel and the second redundant sub-pixel emit light of a second color, and the third main sub-pixel and the third redundant sub-pixel emit light of a third color.

3. The display device according to claim 1, wherein: The plurality of signal lines include at least one of a plurality of data lines and a plurality of reference lines.

4. The display device according to claim 3, wherein: Each of the plurality of sub-pixels further comprises: a first transistor, the first transistor being between one of the plurality of data lines and the substrate, the first transistor being electrically connected to the one data line; a driving transistor, the driving transistor being between the one data line and the substrate, the driving transistor being electrically connected to the first transistor; a second transistor, the second transistor being between the one data line and the substrate, the second transistor being electrically connected to the driving transistor; a storage capacitor between the one data line and the substrate, the storage capacitor being electrically connected to a gate of the driving transistor; and A light emitting diode is disposed above the one data line and is electrically connected to the driving transistor.

5. The display device according to claim 4, wherein: In one pixel region among the plurality of pixel regions, the first transistor of a first sub-pixel, the first transistor of a second sub-pixel, and the first transistor of a third sub-pixel are arranged in a row along a second direction different from the first direction.

6. The display device according to claim 5, wherein: In the one pixel region, the scan line includes a protruding portion that protrudes from the scan line in the first direction and at least partially extends in the second direction, The first transistor of the first main sub-pixel on the first side of the scan line, the first transistor of the second main sub-pixel, and the first transistor of the third main sub-pixel are on the protruding portion of the scan line, and the first transistor of the first redundant sub-pixel on the second side of the scan line, the first transistor of the second redundant sub-pixel, and the first transistor of the third redundant sub-pixel are on the scan line, The first main sub-pixel and the first redundant sub-pixel are configured to emit light of a first color, the second main sub-pixel and the second redundant sub-pixel are configured to emit light of a second color, and the third main sub-pixel and the third redundant sub-pixel are configured to emit light of a third color.

7. The display device according to claim 4, wherein: In one pixel region among the plurality of pixel regions, the second transistor of the first sub-pixel, the second transistor of the second sub-pixel, and the second transistor of the third sub-pixel are arranged in a row along the first direction.

8. The display device according to claim 4, wherein: In one pixel region among the plurality of pixel regions, the driving transistor of the first sub-pixel, the driving transistor of the second sub-pixel, and the driving transistor of the third sub-pixel are arranged in a row along the first direction.

9. The display device according to claim 4, wherein: In one pixel area among the plurality of pixel areas, the light emitting diode of the first sub-pixel, the light emitting diode of the second sub-pixel and the light emitting diode of the third sub-pixel are arranged in a row along the first direction.

10. The display device according to claim 4, wherein: The plurality of signal lines are above and overlap the drive transistor and the storage capacitor.

11. The display device according to claim 4, further comprising: a buffer layer, the buffer layer being between the substrate and the driving transistor; a gate insulating layer, the gate insulating layer being on the buffer layer and between a driving gate and a driving active layer of the driving transistor; a first interlayer insulating layer, wherein the first interlayer insulating layer covers the driving transistor; as well as one or more insulating layers, the one or more insulating layers covering the storage capacitor on the first interlayer insulating layer, The plurality of signal lines are on the one or more insulating layers, and the thickness of the one or more insulating layers is greater than the thickness of the buffer layer, the thickness of the gate insulating layer, and the thickness of the first interlayer insulating layer.

12. The display device according to claim 4, further comprising: A power supply line is provided between the storage capacitor and the plurality of signal lines, the power supply line overlapping the plurality of signal lines.

13. The display device according to claim 12, wherein: The power line includes a low potential power line or a high potential power line.

14. The display device according to claim 12, wherein: The power supply line overlaps the driving transistor and the storage capacitor.

15. The display device according to claim 13, wherein: The driving active layer of the driving transistor and the first active layer of the first transistor are below the power line, the driving drain of the driving transistor and the first source of the first transistor are on the power line, and the power line includes a plurality of openings, and the plurality of openings overlap with contact holes for connecting the driving active layer and the driving drain and contact holes for connecting the first active layer and the first source.

16. The display device according to claim 4, wherein: The reference line is electrically connected to the second transistor, and the reference line is disposed at the same height as the data line.

17. The display device according to claim 16, wherein: The reference line is formed integrally with the second drain of the second transistor.

18. The display device according to claim 1, wherein: The plurality of sub-pixels include: a first sub-pixel having a rectangular shape in a plan view of the display device; a second sub-pixel, surrounding two adjacent sides of four sides of the first sub-pixel in the plan view; and a third sub-pixel surrounding an outer portion of the second sub-pixel in the plan view, and The first sub-pixel, the second sub-pixel and the third sub-pixel together form a rectangular shape.

19. A display device comprising: a substrate comprising a pixel region and a transmission region that is more transparent than the pixel region; a driving transistor, the driving transistor being located in the pixel region; a power supply line, the power supply line being above the driving transistor in the pixel region; a signal line, the signal line being above the power line in the pixel region; as well as A light emitting diode is provided in the pixel region and is electrically connected to the driving transistor.

20. The display device according to claim 19, wherein: In the cross-sectional view, the signal line is between the driving transistor and the power line, and overlaps with the driving transistor and the power line.

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