Substrate, manufacturing method thereof and electronic device

Abstract

The invention discloses a substrate, a manufacturing method thereof and an electronic device. The substrate comprises a substrate body, a peripheral circuit and a common electrode lead. The substrate comprises a working area, a non-working area located on the periphery of the working area and an outer contour edge. The non-working area comprises a peripheral area close to the working area; the peripheral circuit is arranged in the peripheral area; the common electrode lead is arranged along at least part of the outer contour edge of the substrate; the orthographic projection of the common electrode lead on the substrate is at least partially overlapped with the orthographic projection of the peripheral circuit on the substrate, and the common electrode lead is insulated from the peripheral circuit. According to the substrate, the width of the common electrode lead independently occupied in the non-working area can be reduced, and when the substrate is used in electronic devices such as a display device, a narrower frame can be achieved.

Description

[0001] This application is a divisional application of the Chinese invention patent application with the application date of December 19, 2017, application number 201711376371.X, and invention name “Substrate and its manufacturing method, electronic device”. Technical Field

[0002] At least one embodiment of the present disclosure relates to a substrate and a manufacturing method thereof, and an electronic device. Background Art

[0003] Usually, driving circuits and integrated circuit chips that control display operations are set or connected in the peripheral area around the display area of ​​the display. These structures occupy a large space, which will cause the display frame size to be larger. While ensuring the reliability of the fixation between the frame and the display screen, in order to maximize the proportion of the display area to the display surface, the size of the peripheral area must be compressed as much as possible to form a frame as narrow as possible. As the resolution of displays becomes larger and larger, in order to minimize the proportion of the frame in the display, various manufacturers are committed to research on narrowing the frame of the display. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a substrate, which includes: a base substrate, a peripheral circuit, and a common electrode lead. The base substrate includes a working area, a non-working area located around the working area, and an outer contour edge; the non-working area includes a peripheral area close to the working area; the peripheral circuit is arranged in the peripheral area; the common electrode lead is arranged along at least part of the outer contour edge of the base substrate; the orthographic projection of the common electrode lead on the base substrate at least partially overlaps with the orthographic projection of the peripheral circuit on the base substrate, and the common electrode lead is insulated from the peripheral circuit.

[0005] For example, the substrate provided in an embodiment of the present disclosure further includes a common electrode, and the common electrode extends from the working area to the peripheral area; the common electrode is electrically connected to the common electrode lead.

[0006] For example, the substrate provided in one embodiment of the present disclosure further includes a bridging conductive layer, which is located in the peripheral area, insulated from the peripheral circuit, extends across the peripheral circuit, and electrically connects the common electrode lead and the common electrode.

[0007] For example, in the substrate provided by one embodiment of the present disclosure, the jumper conductive layer is directly overlapped with the common electrode lead to realize electrical connection between the jumper conductive layer and the common electrode lead; the common electrode and the jumper conductive layer are integrally formed; or the common electrode and the jumper conductive layer are directly overlapped with the common electrode to realize electrical connection between the common electrode and the jumper conductive layer.

[0008] For example, in a substrate provided in an embodiment of the present disclosure, the peripheral circuit includes an external connection part, and the external connection part includes an external connection point and an external connection wire; the peripheral area includes a first area away from the working area and a second area close to the working area; the external connection point is arranged in the second area of ​​the peripheral area; the orthographic projection of the external connection point on the substrate substrate does not overlap with the orthographic projection of the common electrode lead on the substrate substrate.

[0009] For example, in a substrate provided by an embodiment of the present disclosure, the external connection point is located on a side of the common electrode lead that is close to an outer contour edge of the base substrate.

[0010] For example, the substrate provided in one embodiment of the present disclosure further includes an interlayer insulating layer, wherein the interlayer insulating layer is disposed between the peripheral circuit and the common electrode lead, covering the peripheral circuit to thereby insulate the peripheral circuit from the common electrode lead.

[0011] For example, in a substrate provided by an embodiment of the present disclosure, the interlayer insulating layer includes vias exposing external connection points of the peripheral circuit, and the external connection wires are electrically connected to the external connection points of the peripheral circuit via the vias.

[0012] For example, in the substrate provided by an embodiment of the present disclosure, the external connection wire and the common electrode lead are made of the same material and are arranged in the same layer.

[0013] For example, in a substrate provided in an embodiment of the present disclosure, the peripheral circuit includes: at least one thin film transistor, a capacitor, a peripheral circuit signal output lead and a connecting line. The thin film transistor includes a gate, a source and a drain; the capacitor includes a first plate and a second plate arranged opposite to each other, and the first plate and the gate of the thin film transistor are arranged on the same layer; the peripheral circuit signal output lead is configured to output the output signal of the peripheral circuit to the working area; the connecting line includes a first part; the second plate of the capacitor is electrically connected to the source or drain of the thin film transistor through the first part of the connecting line; the external connection point, the second plate of the capacitor, and the connecting line are arranged on the same layer.

[0014] For example, in a substrate provided in an embodiment of the present disclosure, the peripheral circuit includes a plurality of thin film transistors, and the connecting line also includes a second part and a third part, wherein two of the thin film transistors are electrically connected through the second part of the connecting line; and the third part of the connecting line electrically connects the source or drain of the thin film transistor to the signal output lead of the peripheral circuit.

[0015] At least one embodiment of the present disclosure further provides an electronic device, comprising any one of the above-mentioned substrates.

[0016] At least one embodiment of the present disclosure further provides a substrate manufacturing method, the method comprising: providing a base substrate, the base substrate having an outer contour edge and including a working area and a peripheral area outside the working area; forming a peripheral circuit in the peripheral area; and forming a common electrode lead along at least part of the outer contour edge of the base substrate. In the method, the orthographic projection of the common electrode lead on the base substrate at least partially overlaps with the orthographic projection of the peripheral circuit on the base substrate, and the common electrode lead is insulated from the peripheral circuit.

[0017] For example, the substrate manufacturing method provided by an embodiment of the present disclosure also includes: forming a bridging conductive layer, which is formed in the peripheral area and is insulated from the peripheral circuit, extends across the peripheral circuit and electrically connects the common electrode lead and the common electrode.

[0018] For example, the substrate manufacturing method provided by an embodiment of the present disclosure further includes: forming a common electrode in the working area, wherein the common electrode is electrically connected to the common electrode lead.

[0019] For example, in a substrate manufacturing method provided in an embodiment of the present disclosure, forming the peripheral circuit includes forming an external connection part of the peripheral circuit; the peripheral area includes a first area away from the working area and a second area close to the working area; the external connection part includes an external connection point and an external connection wire, the external connection point is formed in the second area of ​​the peripheral area, and the orthographic projection of the external connection point on the substrate substrate does not overlap with the orthographic projection of the common electrode lead on the substrate substrate.

[0020] For example, in a substrate manufacturing method provided in an embodiment of the present disclosure, forming the peripheral circuit includes: forming a gate metal layer pattern and forming a second metal layer pattern. Forming the gate metal layer pattern includes forming the gates of multiple thin film transistors, the first electrode plate of the capacitor, the mutual connection between the gates of the multiple thin film transistors and the peripheral circuit output leads through the same process; forming the second metal layer pattern includes forming the second electrode plate of the capacitor, the first part of the connecting line electrically connecting the second electrode plate of the capacitor to the source or drain, the second part of the connecting line electrically connecting the source or drain of the multiple thin film transistors, the third part of the connecting line electrically connecting the source or drain of the thin film transistor to the peripheral circuit signal output lead and the external connection point through the same process.

[0021] For example, the substrate manufacturing method provided in an embodiment of the present disclosure further includes: forming an interlayer insulating layer and forming a via hole in the interlayer insulating layer to expose the external connection point. The interlayer insulating layer is located between the peripheral circuit and the common electrode lead, covering the peripheral circuit so that the peripheral circuit and the common electrode lead are insulated from each other; the external connection wire is electrically connected to the external connection point via the via hole, and the external connection wire of the peripheral circuit and the common electrode lead are formed by the same process. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0023] Figure 1 is a schematic plan view of a substrate;

[0024] Figure 2 For along Figure 1 Schematic cross-sectional view of line I-I';

[0025] Figure 3 A schematic plan view of a substrate provided in one embodiment of the present disclosure;

[0026] Figure 4A For along Figure 3 A schematic cross-sectional view of the H-H' line in FIG.

[0027] Figure 4B For along Figure 3 Another cross-sectional schematic diagram of the H-H' line in FIG.

[0028] Figure 4C For along Figure 3 Another cross-sectional schematic diagram of the H-H' line in FIG.

[0029] Figure 4D For along Figure 3 Another cross-sectional schematic diagram of the H-H' line in FIG.

[0030] Figure 4E A schematic plan view of another substrate provided in one embodiment of the present disclosure;

[0031] Figure 4F For along Figure 4E A schematic cross-sectional view of the G-G' line in FIG.

[0032] Figure 4G yes Figure 4A A partially enlarged schematic diagram of a peripheral circuit in;

[0033] Figure 5AA schematic plan view of an array substrate provided in one embodiment of the present disclosure;

[0034] Figure 5B A schematic plan view of another array substrate provided in one embodiment of the present disclosure;

[0035] Figure 5C A schematic plan view of another array substrate provided in an embodiment of the present disclosure;

[0036] Figure 6 For along Figure 5A Schematic diagram of the cross section of the G-G' line;

[0037] Figure 7 A schematic diagram of a display device provided in one embodiment of the present disclosure;

[0038] Figures 8A-8L A schematic diagram of a method for manufacturing an array substrate provided in one embodiment of the present disclosure;

[0039] Figure 8M for Figure 8L A partially enlarged schematic diagram of a peripheral circuit in;

[0040] Figures 9A-9F A schematic diagram of a method for manufacturing a driving circuit of an array substrate provided in one embodiment of the present disclosure.

[0041] Reference numerals

[0042] 1001 - peripheral area; 111 - substrate; 1002 - driving circuit area; 1003 - display area; 201 - driving circuit layer; 401 - common electrode lead; 601 - cross-connection conductive layer; 701 - common electrode; 101- non-working area; 102 - peripheral area; 1021 - first area; 1022 - second area; 103 - working area; 1 - substrate; 2 - peripheral circuit layer; 3 - interlayer insulating layer; 4 - common electrode lead; 5 - flat layer; 6 - cross-connection conductive layer; 7-common electrode; 8 - pixel defining layer; 9 - external connection part; 901 - external connection point; 902 - external connection wire; 10 - substrate; 12 - outer contour edge; 13 - peripheral circuit; 14 - array element; 15 - anode; 16 - organic light-emitting layer; 11 - display device; 100 - array substrate; 301 - via hole; 903 - common electrode lead layer; 602 - conductive layer; 1301 - first part of thin film transistor; 1302 - first insulating layer; 1303 - gate metal layer; 1304 - first plate of capacitor; 1305 - gate; 1306 - peripheral circuit signal output lead; 1307 - second insulating layer; 1308 - second via hole; 1309 - second metal layer; 1310 - second plate of capacitor; 1311 - first part of connecting line; 1312 - second part of connecting line; 1313 - third part of connecting line; 20 - local. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0044] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0045] The dimensions of the drawings used in this disclosure are not strictly drawn according to the actual scale, and the number of array elements in the array substrate is not limited to the number shown in the drawings. The specific dimensions and number of each structure can be determined according to actual needs. The drawings in this disclosure are only schematic diagrams of the structures.

[0046] Organic light-emitting diode (OLED) display devices do not require backlight panels, and have wide display viewing angles, uniform image quality, fast response speed, easy colorization, and can be illuminated with a simple driving circuit. They have simple processes and can be made into flexible panels, meeting the requirements of being thin, light and short, and their application range covers panels of all sizes. However, active matrix OLED (AMOLED) display devices at this stage still have some shortcomings in some aspects. For example, compared with active matrix LCD (AMLCD) display devices, the active backplane peripheral circuit structure of AMOLED display devices occupies a relatively large area, making its frame width larger. In addition, the life of AMOLED display devices is currently lower than that of AMLCD, partly because the Joule heat in the current concentration area of ​​the peripheral circuit causes a higher temperature rise, which adversely affects the life of the OLED device near this area. Reducing the temperature rise caused by the Joule heat of the peripheral circuit usually also requires a larger area to reduce the wiring resistance of the peripheral circuit.

[0047] Figure 1 is a schematic diagram of a substrate. Figure 2 For along Figure 1 Schematic diagram of the cross section along the I-I' line. Figure 1 and Figure 2The substrate is a display substrate, which includes a base substrate 111, the base substrate 111 includes a display area 1003 and a peripheral area 1001 located around the display area 1003, and the peripheral area 1001 includes a driving circuit area 1002. A driving circuit layer 201 is arranged on the base substrate 111, and a driving circuit, such as a gate driving circuit, is arranged at the driving circuit layer 201 corresponding to the driving circuit area 1002. The substrate also includes a common electrode lead 401 arranged on the base substrate 111, which is located on a side of the driving circuit area 1002 away from the display area 1003 and extends along the outer contour edge of the base substrate 111. A first insulating layer is arranged between the common electrode lead 401 and the driving circuit layer 201 to insulate the common electrode lead 401 from the driving circuit located in the driving circuit area 1002. The substrate peripheral circuit structure also includes a bridging conductive layer 601 and a common electrode 701. The common electrode 701 is electrically connected to the common electrode lead 401 through the bridging conductive layer 601, that is, the bridging conductive layer 601 serves as a bridge for the common electrode 701 to be electrically connected to the common electrode lead 401 through the bridging conductive layer 601. The common electrode 701 extends from the display area 103 to the drive circuit area 1002 and contacts with one end of the bridging conductive layer 601 close to the display area 1003 to achieve electrical connection, and one end of the bridging conductive layer 601 away from the display area 1003 contacts with the common electrode lead 401 to achieve electrical connection.

[0048] exist Figure 1 and Figure 2 In the display substrate shown, the common electrode lead occupies a certain width (i.e., not shared with other circuit structures) around the display area, i.e., occupies a certain area alone, which is not conducive to achieving a narrower frame around the display area. In addition, the distance between the common electrode lead and the common electrode is large, and the width of the bridging conductive layer is long, which makes the resistance of the bridging conductive layer large, which is not conducive to improving the signal transmission speed, and will cause the Joule heat to increase, which is not conducive to the life of the display device using the display substrate.

[0049] At least one embodiment of the present disclosure provides a substrate, which includes: a base substrate, a peripheral circuit, and a common electrode lead. The base substrate includes a working area, a non-working area located around the working area, and an outer contour edge; the non-working area includes a peripheral area close to the working area; the peripheral circuit is arranged in the peripheral area; the common electrode lead is arranged along at least part of the outer contour edge of the base substrate; the orthographic projection of the common electrode lead on the base substrate at least partially overlaps with the orthographic projection of the peripheral circuit on the base substrate, and the common electrode lead is insulated from the peripheral circuit.

[0050] At least one embodiment of the present disclosure further provides an electronic device including the above-mentioned substrate.

[0051] At least one embodiment of the present disclosure further provides a substrate manufacturing method, the method comprising: providing a base substrate, the base substrate having an outer contour edge and including a working area and a peripheral area outside the working area; forming a peripheral circuit in the peripheral area; and forming a common electrode lead along at least part of the outer contour edge of the base substrate. In the method, the common electrode lead at least partially overlaps with the peripheral circuit in a direction perpendicular to the base substrate and is insulated from the peripheral circuit.

[0052] The structures, methods and technical effects involved in the present disclosure are described in detail below through several specific embodiments.

[0053] Embodiment 1

[0054] Figure 3 A schematic plan view of a substrate provided in this embodiment, Figure 4A For along Figure 3 An exemplary cross-sectional diagram of the H-H' line in FIG. Figure 4B For along Figure 3 Another exemplary cross-sectional schematic diagram of the H-H' line in FIG. Figure 4C For along Figure 3 Another exemplary cross-sectional schematic diagram of the H-H' line in FIG. Figure 4D For along Figure 3 Another exemplary cross-sectional schematic diagram of the H-H' line in FIG.

[0055] The present embodiment provides a substrate peripheral circuit structure, which includes: a base substrate, a peripheral circuit and a common electrode lead. The base substrate includes a working area, a non-working area located around the working area and an outer contour edge; the non-working area includes a peripheral area close to the working area; the peripheral circuit is arranged in the peripheral area; the common electrode lead is arranged along at least part of the outer contour edge of the base substrate; the orthographic projection of the common electrode lead on the base substrate at least partially overlaps with the orthographic projection of the peripheral circuit on the base substrate, and the common electrode lead is insulated from the peripheral circuit. For example, the substrate provided in the present embodiment can be an array substrate, a display substrate, etc.

[0056] For example, Figure 4AAs shown, the substrate 10 includes a base substrate 1, a peripheral area 102 and a common electrode lead 4. The base substrate 1 includes a working area 103, a non-working area 101 located around the working area 103 and an outer contour edge 12, and the non-working area 101 is located on the side of the working area 103 close to the outer contour edge 12 of the base substrate 1. The non-working area 101 includes a peripheral area 102 close to the working area 103. For example, the working area 103 can be a display area or a light-emitting area, etc., and correspondingly, the non-working area 101 can be a non-display area or a non-light-emitting area, etc. Although the non-working area 101 is not used for display, light emission, etc., circuits, pads, interconnect structures, etc. for supporting and realizing functions such as display and light emission can be provided therein.

[0057] A peripheral circuit layer 2 is disposed on the base substrate 1. The peripheral circuit layer 2 includes a peripheral circuit 13 ( Figure 4A The peripheral circuit structure is not specifically shown in the figure), which is used to control the working state of the working unit in the working area 103. For example, when the working unit is a light-emitting unit, the peripheral circuit 13 can be used to control whether the light-emitting unit emits light or not and the light intensity. The peripheral circuit 13 can be, for example, a driving circuit, such as a gate driving circuit. The type and specific structure of the peripheral circuit 13 are not limited in this embodiment.

[0058] like Figure 3 As shown, the common electrode lead 4 is arranged along the outer contour edge 12 of the base substrate 1. In other examples, the common electrode lead 4 can also be arranged along part of the outer contour edge 12 of the base substrate 1. The orthographic projection of the common electrode lead 4 on the base substrate 1 partially overlaps with the orthographic projection of the peripheral circuit 13 on the base substrate 1. That is, in the direction perpendicular to the base substrate 1, a part of the common electrode lead 4 overlaps with a part of the peripheral circuit 12. In addition, the common electrode lead 4 is insulated from the peripheral circuit 12. Figure 2 Compared with the substrate shown in the figure, the substrate 10 provided in this embodiment can reduce the width of the common electrode lead 4 alone in the non-working area 101. Applying the peripheral circuit structure to the substrate, panel or display device is conducive to achieving a narrower frame around the working area. Alternatively, since a part of the common electrode lead 4 overlaps with a part of the peripheral circuit 12, the space occupied by the common electrode lead 4 is reduced, which is conducive to increasing the width of the common electrode lead 4 to reduce the resistance of the common electrode lead 4. This is conducive to improving the conduction speed of the signal in the common electrode lead on the one hand, and on the other hand, it is conducive to reducing the power consumption of the common electrode lead and the Joule heat generated during the operation, reducing the temperature rise caused by the Joule heat, and thus helping to improve the life of the device such as the display device using the substrate peripheral circuit structure.

[0059] It should be noted that the width of the common electrode lead 4 in this embodiment refers to Figure 3 The size of the dimension h in the direction perpendicular to the outer contour edge 12 is shown in FIG.

[0060] For example, the substrate 10 may further include a common electrode 7, which extends from the working area 103 to the peripheral area 102, and the common electrode 7 is electrically connected to the common electrode lead 4, so that a common electrical signal (voltage) is transmitted to the common electrode 7 via the common electrode lead 4 to control or drive the working state of the working area 103.

[0061] For example, Figure 3 and Figure 4A As shown, the substrate 10 may further include a bridging conductive layer 6, which is located in the peripheral area 102, insulated from the peripheral circuit 13, extending across the peripheral circuit 13 and electrically connecting the common electrode lead 4 and the common electrode 7. For example, a portion of the common electrode 7 may be located in the peripheral area 102 and extend from the peripheral area 102 to the working area 103. One end of the common electrode 7 away from the working area 103 is electrically connected to the bridging conductive layer 6. For example, one end of the common electrode 7 away from the working area 103 may be directly in contact with one end of the bridging conductive layer 6 close to the working area 103 to achieve electrical connection, that is, the common electrode 7 is directly overlapped with the bridging conductive layer 6 to achieve electrical connection between the common electrode 7 and the bridging conductive layer 6. At the same time, the bridging conductive layer 6 is electrically connected to the common electrode lead 4, so that the bridging conductive layer 6 can electrically connect the common electrode lead 4 and the common electrode 7. For example, one end of the bridging conductive layer 6 away from the working area 103 is directly overlapped with the common electrode lead 4 to achieve electrical connection between the two. This direct overlap form is conducive to reducing contact resistance and is easy to manufacture. Usually, the common electrode 7 can be formed by chemical vapor deposition or magnetron sputtering, and the cross-connecting conductive layer 6 can be formed by photolithography. The dimensional accuracy of the film layer formed by chemical vapor deposition or magnetron sputtering is lower than that of the photolithography, and it is usually necessary to reserve sufficient packaging space at the position of the outer contour edge 12 of the substrate 1 near the non-working area 101 around the substrate. If the common electrode 7 is directly overlapped with the common electrode lead 4, a larger packaging space needs to be reserved. Therefore, the provision of a cross-connecting conductive layer can improve the dimensional accuracy when reserving packaging space, which is further conducive to achieving a narrower frame.

[0062] In the substrate peripheral circuit structure provided in this embodiment, at least a portion of the common electrode lead 4 overlaps with the peripheral circuit 13, which is also conducive to reducing the width of the cross-connected conductive layer 6, thereby reducing the resistance of the cross-connected conductive layer 6. This is conducive to improving the conduction speed of the signal in the cross-connected conductive layer on the one hand, and on the other hand, it is conducive to reducing the power consumption and Joule heat generated by the cross-connected conductive layer during operation, reducing the temperature rise caused by Joule heat, and thus helping to improve the life of the device using the substrate peripheral circuit structure, such as a display device. The width of the cross-connected conductive layer 6 refers to the width of the cross-connected conductive layer 6 in the direction where the above-mentioned dimension h is located.

[0063] For example, the materials of the cross-connection conductive layer 6, the common electrode lead 4 and the common electrode 7 are transparent conductive materials or opaque conductive materials. The transparent conductive materials may be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), etc. The opaque conductive materials may be, for example, metal materials, such as copper, aluminum, copper alloy, aluminum alloy, etc., which have high electrical conductivity. The cross-connection conductive layer 6 and the common electrode lead 4 use the above or other types of materials with high electrical conductivity, which is conducive to improving the speed of common signal transmission. For example, when the working area 103 is a light-emitting area, and it is necessary to make light from Figure 4A When the light is emitted from one side of the common electrode 7, the common electrode 7 is made of transparent material.

[0064] The types of materials listed above are only illustrative examples. This embodiment does not limit the materials of the jumper conductive layer, the common electrode lead and the common electrode, and those skilled in the art can make selections according to specific needs.

[0065] For example, the peripheral circuit 13 may include an external connection part 9, and the external connection part 9 includes an external connection point 901 and an external connection wire 902. The peripheral circuit 13 may include an internal connection part and an external connection part 9. The internal connection part refers to a conductive structure formed by interconnecting various components of the peripheral circuit 13, for example, the peripheral circuit 13 is a driving circuit, such as a gate driving circuit or a data driving circuit. The following is an exemplary description using the peripheral circuit 13 as a gate driving circuit as an example, and the gate driving circuit is a GOA type. The internal connection part includes the wires inside each driving unit of the gate driving circuit and between each driving unit, and the parts connected between the thin film transistor and the capacitor. The external connection part 9 includes the part of the peripheral circuit 13 connected to its external signal transmission structure. For example, the external connection part 9 includes an external connection point 901 and an external connection wire 902 connected to multiple driving units of the gate driving circuit, and the external connection wire 902 can be used to electrically connect the external connection point 901 to the external signal transmission structure. For example, the external connection part 9 can be used to connect to a timing controller.

[0066] For example, the peripheral area 102 includes a first area 1021 away from the working area 103 and a second area 1022 close to the working area. The orthographic projection of the external connection point 901 on the base substrate 1 does not overlap with the orthographic projection of the common electrode lead 4 on the base substrate 1. That is, the external connection point 901 is arranged in the second area 1022 of the peripheral area 102, and the second area 1022 does not overlap with the common electrode lead 4 at least partially in the direction perpendicular to the base substrate 1. This makes it easy to open a via hole above the external connection point 901 and to arrange the external connection wire 902, so that this process will not be hindered by the common electrode lead 4.

[0067] For example, the substrate 10 may further include an interlayer insulating layer 3, which is disposed between the peripheral circuit 13 and the common electrode lead 4, covers the peripheral circuit 13, and thereby insulates the peripheral circuit 13 from the common electrode lead 4. For example, the material of the interlayer insulating layer 3 may be an organic insulating material, such as resin and rubber, or an inorganic insulating material, such as silicon nitride. Of course, the material of the interlayer insulating layer 3 is not limited to the above-mentioned types, and this embodiment does not limit this.

[0068] For example, the interlayer insulating layer 3 includes a via hole exposing the external connection point 901 of the peripheral circuit 13, and the external connection wire 902 is electrically connected to the external connection point 901 of the peripheral circuit 13 through the via hole. For example, the external connection wire 902 can be electrically connected to an external controller such as a timing controller, so that the external controller can control the working state of the working area 103 together with the peripheral circuit, such as controlling the opening and closing of the working unit of the working area 103 and performing line-by-line scanning.

[0069] For example, the external connection wire 902 can be made of the same material as the common electrode lead 4 and be arranged in the same layer. This is conducive to simplifying the structure and simplifying the manufacturing process. Therefore, the material of the external connection wire 902 can refer to the previous description of the material of the common electrode lead 4.

[0070] For example, the substrate 10 may further include a flat layer 5 covering the peripheral circuit 13 and a portion of the common electrode lead 4, which can insulate the external connection portion 9 of the peripheral circuit 13 from the jumper conductive layer 6 and the common electrode 7 located above the flat layer, and provide a flat surface for arranging functional devices in the working area 103. The flat layer 5 exposes a portion of the common electrode lead 4 so that the jumper conductive layer 6 can be electrically connected to the common electrode lead 4.

[0071] For example, in Figure 4A In the example shown, the interlayer insulating layer 3 forms a step portion on the side close to the outer contour edge 12 of the base substrate 1, and the common electrode lead 4 covers the step portion and extends from a lower position relative to the base substrate 1 to a higher position. Of course, in other examples of this embodiment, the above-mentioned step portion may also be absent. For example, in Figure 4BIn the example shown, the interlayer insulating layer 3 has a flat surface on a side close to the outer contour edge of the base substrate 1 . In this case, the common electrode lead 4 is disposed on the flat surface.

[0072] The above example is a case where a portion of the common electrode lead 4 overlaps with the first region 1021 of the peripheral region 102 in a direction perpendicular to the base substrate 1. In another example of this embodiment, Figure 4C As shown, the entire common electrode lead 4 overlaps with the peripheral circuit 13 in a direction perpendicular to the base substrate 1, that is, overlaps with the first area 1021 of the peripheral area 102 in a direction perpendicular to the base substrate 1. In this way, the width of the non-working area 101 can be further reduced, thereby further reducing the frame width of a device such as a display device using the substrate peripheral circuit structure 10.

[0073] In another example of this embodiment, Figure 4D As shown, the common electrode 7 and the crossover conductive layer 6 can also be integrally formed to realize electrical connection between the common electrode 7 and the common electrode lead 4. It can be understood that the crossover conductive layer 6 may not be provided, and the common electrode 7 and the common electrode lead 4 are directly overlapped to realize electrical connection between the two.

[0074] exist Figures 4A-4D In the example shown, the external connection point 901 is located on a side of the common electrode lead 4 away from the outer contour edge 12 of the base substrate 1 .

[0075] In another example, the external connection point may also be located on a side of the common electrode lead close to the outer contour edge of the substrate. Figure 4E A schematic plan view of another substrate peripheral circuit structure provided in this embodiment; Figure 4F For along Figure 4E A schematic cross-sectional view of the G-G' line in FIG. Figure 4F As shown, the external connection point 901 is located on one side of the common electrode lead 4 close to the outer edge of the base substrate 1, that is, the connection point 901 is located between the common electrode lead 4 and the outer edge of the base substrate 1. Figures 4A-4D Compared to the example shown, Figure 4F The example shown can further reduce the length of the jumper conductive layer 6 and thus further reduce the resistance of the jumper conductive layer 6 . Figure 4F For other technical effects produced by the example shown, please refer to the above description and will not be repeated here.

[0076] Figure 4G yes Figure 4A A partial enlarged schematic diagram of a peripheral circuit in FIG. Figure 4GAs shown, the peripheral circuit may include: a plurality of thin film transistors arranged on the substrate 1, each thin film transistor including a first part 1301 and a gate 1305 of the thin film transistor. The first part 1301 of the thin film transistor includes a source, a drain and a channel region. The peripheral circuit may also include a first insulating layer 1302 covering the first part 1301 of the thin film transistor, a capacitor and a peripheral circuit signal output lead 1306. The peripheral circuit signal output lead 1306 is configured to output the output signal of the peripheral circuit to the working area inside the non-working area. The capacitor includes a first plate 1304 and a second plate 1310 arranged oppositely. The gate 1305 of the thin film transistor, the first plate 1304 of the capacitor and the peripheral circuit signal output lead 1306 are arranged in the same layer, all arranged on the first insulating layer 1302, and the materials thereof may be the same and may be formed simultaneously by the same process. The peripheral circuit may also include a second insulating layer 1307 covering the gate 1305, the first plate 1304 of the capacitor and the peripheral circuit signal output lead 1306. The first insulating layer 1302 and the second insulating layer 1307 include a second via hole exposing a source or a drain of the thin film transistor.

[0077] The peripheral circuit also includes an internal connection part, which includes a connecting line, for example, the connecting line includes a first part 1311. The second plate 1310 of the capacitor, the connecting line and the external connection point 901 are arranged on the second insulating layer 1307. The source or drain of multiple thin film transistors is electrically connected through the second part 1305 of the connecting line via the second via hole. The second plate 1310 of the capacitor is electrically connected to the source or drain of one or more thin film transistors through the first part 1311 of the connecting line via the second via hole. In addition, the second plate 1310 of the capacitor and the connecting line 1311 can be integrally formed, so that they can be formed simultaneously by the same material through the same process. In addition, the external connection point 901, the second plate 1310 of the capacitor and the connecting line are arranged in the same layer. It should be noted that the same layer arrangement in the present disclosure means that the structures arranged in the same layer can be formed simultaneously by the same material through the same process, rather than that these structures have the same height relative to the substrate. Therefore, the external connection point 901, the second electrode plate 1310 of the capacitor and the connection line are made of the same material, from the same film layer and through the same process, which is conducive to simplifying the structure and preparation process of the peripheral circuit.

[0078] For example, the connection line further includes a second portion 1312 and a third portion 1313. The two thin film transistors can be electrically connected through the second portion 1312 of the connection line. The third portion 1313 of the connection line can electrically connect the source or drain of the thin film transistor to the peripheral circuit signal output lead 1306.

[0079] For example, the materials of the external connection point 901, the second plate 1310 of the capacitor and the connecting wire can be copper, aluminum, copper alloy, aluminum alloy, silver, chromium, etc., but are not limited to the types listed above. This embodiment does not limit the materials of each component, and those skilled in the art can refer to conventional techniques.

[0080] In the substrate provided in this embodiment, the entire peripheral circuit 13 is located below the interlayer insulating layer 3, that is, the interlayer insulating layer 3 covers the peripheral circuit 13. For example, the interlayer insulating layer 3 covers the external connection point 901, the second plate 1310 of the capacitor, and the connecting line. In this way, a flat insulating layer can be formed on the peripheral circuit 13. When the common electrode lead 4 is arranged above the interlayer insulating layer 3, and the common electrode lead 4 partially or completely overlaps with the peripheral circuit below the interlayer insulating layer 3, the common electrode lead 4 can be insulated from the peripheral circuit 13.

[0081] For example, the substrate provided in the embodiment of the present disclosure may be an array substrate or a display substrate. Figure 5A A schematic plan view of an array substrate provided in this embodiment, Figure 5B A schematic plan view of another array substrate provided in this embodiment, Figure 5C A schematic plan view of another array substrate provided in this embodiment; Figure 6 For along Figure 5A Schematic diagram of the cross section of the G-G' line.

[0082] For example, Figure 5A As shown, the common electrode lead 4 and the peripheral circuit of the peripheral area 102 are used to control the working state of the working area 103. The common electrode lead 4 and the peripheral area 102 can be located on the left side of the array substrate 100 near the outer edge of the array substrate 100, and the control signal is input to the working area 103 from the left side. Figure 5B As shown, the common electrode lead 4 and the peripheral area 102 can also be arranged on the upper side of the array substrate 100 near the outer edge of the outer contour thereof, and the control signal is input from the upper side to the working area 103. Figure 5C As shown, the common electrode lead 4 and the peripheral area 102 can also be arranged on the opposite sides of the array substrate 100, such as the left and right sides, close to the outer contour edge thereof. In this way, the control signal can be input to the working area 103 on both sides at the same time, which can achieve the technical effect of reducing signal delay, so that the array substrate 100 can achieve a better working effect. For the case where the plane area of ​​the array substrate 100 is large, this technical effect is more prominent. It should be noted that the "left", "right" and "upper" in this embodiment refer to the relative positions shown in the corresponding drawings.

[0083] For example, Figure 6As shown, the working area 103 is provided with a plurality of array elements 14, and the plurality of array elements include a common electrode 7, and the common electrode 7 is electrically connected to the common electrode lead 4. For example, the array element 14 may be an organic light emitting diode device, and the organic light emitting diode device may be a top emission, bottom emission, etc. structure. Exemplarily, the organic light emitting diode device may include: an anode 15 disposed on the base substrate 1, a cathode disposed on the base substrate 1 opposite to the anode 15, and an organic light emitting layer 16 disposed between the anode 15 and the cathode. Figure 6 In the example shown, the cathode is the common electrode 7, in which case the common electrode lead 4 is the common cathode lead, and a low-level signal is input to the common electrode 7 during operation. For example, the anode 15 may be a reflective electrode or a reflective layer may be provided adjacent to the anode 15 (not shown in the figure), and during operation, light is emitted from the cathode side; or the cathode may be a reflective electrode or a reflective layer may be provided adjacent to the cathode, and during operation, light is emitted from the anode side. In other examples of this embodiment, the positions of the anode and the cathode may be interchanged, for example, the anode may also be the common electrode 7, in which case the common electrode lead 4 is the common anode lead, and a high-level signal is input to the common electrode 7 during operation.

[0084] For example, the organic light emitting diode device may further include a pixel defining layer 8 to define a plurality of light emitting units or pixel units to prevent light from interfering with each other between adjacent light emitting units or adjacent pixel units. The pixel defining layer 8 includes an opening, the organic light emitting layer 16 is disposed in the opening, and the common electrode 7 may cover the pixel defining layer 8.

[0085] For example, the peripheral circuit 13 may be a gate driving circuit or a data driving circuit, etc. For example, the gate driving circuit or the data driving circuit includes a thin film transistor, a capacitor, a gate line lead or a data line lead, etc.

[0086] The array substrate provided in this embodiment can be used in electronic devices such as display devices and lighting devices. In the array substrate provided in this embodiment, the width of the common electrode lead 4 alone in the non-working area 101 is reduced, so that the array substrate has a narrower frame, so that the display device or lighting device using the array substrate can achieve a narrower frame. The display device or lighting device using the array substrate can achieve a narrower frame. While achieving a narrow frame, the saved space can also be used to increase the width of the common electrode lead to reduce the resistance of the common electrode lead. In this way, the resistance of the common electrode lead can be reduced, which is beneficial to improving the conduction speed of the signal in the common electrode lead on the one hand, and on the other hand, it is beneficial to reduce the power consumption of the common electrode lead and the Joule heat generated during operation, and reduce the temperature rise caused by Joule heat, so as to improve the life of the array substrate, display device or lighting device.

[0087] Embodiment 2

[0088] This embodiment provides an electronic device, which includes any one of the substrates provided in the embodiments of the present disclosure. For example, the electronic device may be a display device, a lighting device, etc. Exemplarily, Figure 7 Schematic diagram of a display device provided in this embodiment. Figure 7 As shown, the display device includes any array substrate provided by the embodiments of the present disclosure. For example, the display device may be an organic light emitting diode display device. For example, the display device may be implemented as the following products: any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0089] Figure 7 It is only a schematic diagram of a display device including any one of the array substrates provided in the second embodiment. Those skilled in the art may refer to conventional technologies for other structures of the display device not shown, and this embodiment does not limit them.

[0090] The display device provided in this embodiment can realize a narrow frame. While realizing a narrow frame, it is also helpful to increase the width of the common electrode lead to reduce the resistance of the common electrode lead. In this way, the resistance of the common electrode lead can be reduced, which is helpful to improve the conduction speed of the signal in the common electrode lead on the one hand, and is helpful to reduce the power consumption and Joule heat generated by the common electrode lead during operation on the other hand, and reduce the temperature rise caused by Joule heat, thereby helping to increase the life of the array substrate, the display device or the lighting device.

[0091] Embodiment 3

[0092] This embodiment provides a method for manufacturing an array substrate, the method comprising: providing a base substrate, the base substrate having an outer contour edge and including a working area and a peripheral area outside the working area; forming a peripheral circuit in the peripheral area; and forming a common electrode lead along at least part of the outer contour edge of the base substrate. In the method, the orthographic projection of the common electrode lead on the base substrate at least partially overlaps with the orthographic projection of the peripheral circuit on the base substrate, and the common electrode lead is insulated from the peripheral circuit.

[0093] Demonstratively, Figures 8A-8M A schematic diagram of a method for manufacturing an array substrate provided by an embodiment of the present disclosure is provided below. The method is described below by taking the formation of an array substrate including an organic light emitting diode device in a working area as an example.

[0094] like Fig. 8AAs shown, a substrate substrate 1 is provided. The substrate substrate 1 may be, for example, a glass substrate, a quartz substrate, a resin (e.g., polyethylene) substrate, etc. The substrate substrate 1 has an outer contour edge 12 and includes a working area 103 and a non-working area 101 located outside the working area 103. The non-working area 101 includes a peripheral area 102 close to the working area 103. A peripheral circuit layer 2 is formed on the substrate substrate 1, including forming a peripheral circuit 13 in the peripheral area 2. The peripheral circuit 13 may be, for example, a driving circuit, such as a gate driving circuit or a data driving circuit. The following exemplifies a method for manufacturing the circuit by taking the peripheral circuit 13 as a gate driving circuit as an example.

[0095] Figures 9A-9F Schematic diagram of a method for manufacturing the driving circuit. Forming the peripheral circuit 13 includes forming an internal connection part and an external connection part of the peripheral circuit 13. The peripheral area 102 includes a first area 2021 away from the working area 103 and a second area 1022 close to the working area 103. The internal connection part is located in the first area 1021 of the peripheral area 102, and the external connection part includes an external connection point and an external connection wire. The external connection point is formed in the second area 1022 of the peripheral area 102, and the orthographic projection of the external connection point on the base substrate 1 does not overlap with the orthographic projection of the common electrode lead 4 on the base substrate 1. The following is an example of forming a thin film transistor.

[0096] like Fig. 9A As shown, a first portion 1301 of a plurality of thin film transistors and a first insulating layer 1302 are formed in the first region 1021 by using conventional techniques in the art. The first portion 1301 includes a channel region, a source region, and a drain region.

[0097] like Fig. 9B As shown, a gate metal layer 1303 is formed on the first insulating layer 1302, for example, the gate metal layer 1303 can be formed by chemical vapor deposition or magnetron sputtering. The material of the gate metal layer 1303 can be copper, aluminum, copper alloy, aluminum alloy, silver, chromium, etc., but is not limited to the above listed types.

[0098] Forming the peripheral circuit includes forming a gate metal layer pattern, for example, it may include forming the gates of multiple thin film transistors, the first plate of the capacitor, the interconnection between the gates of the multiple thin film transistors, and the pattern of the peripheral circuit output leads through the same process. Fig. 9C As shown, the gate metal layer 1303 is patterned to simultaneously form a plurality of gate electrodes 1305 corresponding to the first portions 1301 of the plurality of thin film transistors, a first plate 1304 of the capacitor, and a pattern of interconnecting the plurality of gate electrodes 1305 and a peripheral circuit signal output lead 1306. For example, the patterning may be implemented using a photolithography process.

[0099] like Fig.9DAs shown, a second insulating layer 1307 is formed to cover the pattern formed by the gate metal layer 1303. A second via hole 1308 is formed in the first insulating layer 1302 and the second insulating layer 1307 to expose the source and drain of the plurality of thin film transistors. For example, the material of the first insulating layer 1302 and the second insulating layer 1307 may be an inorganic insulating material, such as silicon nitride. At this time, the second via hole 1308 may be formed by a photolithography process of exposure-development-etching. For example, the material of the first insulating layer 1302 and the second insulating layer 1307 may also be an inorganic insulating material or an organic insulating material, and the organic insulating material may be, for example, a photosensitive organic insulating material. In this case, the second via hole 1308 may be formed by an exposure-development process. In this way, the etching steps can be reduced and the process can be simplified.

[0100] For example, the method further includes forming a second metal layer pattern, which may include forming a second plate of a capacitor, a first portion of a connection line electrically connecting the second plate of the capacitor to a source or drain, a second portion of a connection line electrically connecting the source or drain of a plurality of thin film transistors, a third portion of a connection line electrically connecting the source or drain of the thin film transistor to a peripheral circuit signal output lead, and an external connection point through the same process. Exemplarily, as Fig.9E As shown, a second metal layer 1309 is formed on the second insulating layer 1307, and the second metal layer 1309 is electrically connected to the source region and the drain region of the active layer of the thin film transistor through the second via 1308. For example, the second metal layer 1309 can be formed by a chemical vapor deposition method or a magnetron sputtering method. The material of the second metal layer 1309 can be copper, aluminum, copper alloy, aluminum alloy, silver, chromium, etc., but is not limited to the above-listed types.

[0101] like Fig.9F As shown, the second metal layer 1309 is patterned to simultaneously form a second plate 1310 of the capacitor, a first portion 1311 of a connecting line electrically connecting the second plate 1310 of the capacitor to a source or a drain, a second portion 1312 of a connecting line electrically connecting the sources or drains of a plurality of thin film transistors and electrically connecting the source of the thin film transistor, a third portion 1313 of a connecting line electrically connecting the source or drain of the thin film transistor to a peripheral circuit signal output lead 1306, and a pattern of an external connection point 901.

[0102] For example, the external connection point 901 can be located in the second region 1022 during the patterning of the second metal layer 1309. For example, it can be electrically connected to the source or drain of multiple thin film transistors in each row, and can also be used to connect to a controller outside the gate drive circuit 13, such as a timing controller. Fig. 8AThe peripheral circuit layer 2 shown realizes the formation of the internal connection part of the peripheral circuit in the first area 1021 of the peripheral area 102, and makes the external connection point 901 located in the second area 1022 of the peripheral area 102, so as to prepare for the subsequent formation of the external connection part of the peripheral circuit in the second area 1022. The method provided by this embodiment can simultaneously form a part of the peripheral circuit devices (such as the second plate of the capacitor and the external connection point) and the connection pattern between each device using the second metal layer 1309, without having to separately form the metal for connecting each device after forming the peripheral circuit devices, which is conducive to simplifying the process. It should be noted that Fig.9F The number of the external connection point 901 shown in the figure is one, which is only used as an exemplary description, and the number of the external connection point 901 can also be multiple.

[0103] like Figure 8B As shown, the method also includes forming an interlayer insulating layer 3 on the peripheral circuit layer 2. The entire peripheral circuit 13 is located below the interlayer insulating layer 3, that is, the interlayer insulating layer 3 covers the peripheral circuit 13. For example, the interlayer insulating layer 3 covers the external connection point 901, the second plate 1310 of the capacitor and the connecting line. In this way, a flat insulating layer can be formed on the peripheral circuit 13. When a common electrode lead 4 is arranged above the interlayer insulating layer 3, and part or all of the common electrode lead 4 overlaps with the peripheral circuit below the interlayer insulating layer 3, the common electrode lead 4 can be insulated from the peripheral circuit 13. The material of the interlayer insulating layer 3 can be the same as that of the first insulating layer 1302 mentioned above, please refer to the above description. For example, the interlayer insulating layer 3 can be formed by coating, deposition, etc.

[0104] like Figure 8C As shown, a via hole 301 exposing an external connection point 901 is formed in the interlayer insulating layer 3. The specific method can refer to the above description of the method for forming the second via hole 1308.

[0105] like Fig.8D As shown, a common electrode lead layer 901 is formed on the interlayer insulating layer 3. The material of the common electrode lead layer 901 may be, for example, a transparent conductive material or an opaque conductive material. The transparent conductive material may be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), etc. The opaque conductive material may be, for example, a metal material, such as copper, aluminum, copper alloy, etc., which have high electrical conductivity. The common electrode lead layer 901 may be formed by a method such as a chemical vapor deposition method or a magnetron sputtering method.

[0106] like Fig. 8EAs shown, for example, the common electrode lead layer 901 can be patterned by a photolithography process to form a common electrode lead 4 along at least part of the outer contour edge of the base substrate 1. The projection of the common electrode lead 4 on the base substrate 1 overlaps with a part of the projection of the internal connection part of the peripheral circuit 13 of the peripheral area 102 on the base substrate 1, that is, it overlaps with the internal connection part of the peripheral circuit of the peripheral area 102 in the direction perpendicular to the base substrate 1. In this way, in the array substrate obtained by the method provided by this embodiment, the width occupied by the common electrode lead 4 in the non-working area 101 can be reduced, so that the array substrate can have a narrower frame, so that the display device or lighting device using the array substrate can achieve a narrower frame. The saved space can also be used to increase the width of the common electrode lead to reduce the resistance of the common electrode lead.

[0107] exist Fig. 8E In the embodiment, the interlayer insulating layer 3 is located between the peripheral circuit 13 and the common electrode lead 4, covering the peripheral circuit 13, thereby isolating the peripheral circuit 13 from the common electrode lead 4. The external connection part 9 of the peripheral circuit 13 includes an external connection point 901 and an external connection wire 902. The external connection wire 902 is formed while the common electrode lead 4 is patterned by the common electrode lead layer 901, that is, the external connection wire 902 of the peripheral circuit 13 and the common electrode lead 4 are formed by the same process. This is conducive to simplifying the preparation process of the array substrate. The external connection wire 902 is electrically connected to the external connection point 901 via the via 301. As a result, the external connection point 901 is formed in the second area 1022 of the peripheral area that does not overlap with the common electrode lead 4 in the direction perpendicular to the base substrate 1, so as to open a via hole above the external connection point 901 and set the external connection wire 902, so that this process will not be hindered by the common electrode lead 4.

[0108] like Figure 8F As shown, a flat layer 5 is formed to cover the base substrate 1. The specific forming method and materials of the flat layer 5 can refer to conventional techniques in the art.

[0109] like Figure 8G As shown, the planar layer 5 is patterned to form an opening, which exposes at least a portion of the common electrode lead 4.

[0110] like Figure 8H As shown, a pixel defining layer 8 is formed on the planar layer 5 by photolithography. The pixel defining layer 8 has an opening.

[0111] like Fig.8IAs shown, a conductive layer 602 is formed on the flat layer 5. The material of the conductive layer 602 may be a transparent conductive material or an opaque conductive material. The transparent conductive material may be, for example, indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive material may be, for example, a metal material, such as copper, aluminum, copper alloy, aluminum alloy, etc. For example, the conductive layer 602 may be formed by a chemical vapor deposition method or a magnetron sputtering method. It should be noted that the material and specific manufacturing method of the conductive layer 602 are not limited to the above-mentioned types.

[0112] like Figure 8J As shown, for example, photolithography can be used to pattern the conductive layer 602 to simultaneously form the cross-connected conductive layer 6 and the anode 15. Of course, in other examples, Figure 8J The anode 15 formed in the embodiment can also be changed to a cathode. In this example, the anode is used as an example for explanation. The anode 15 is located in the working area 103 and is located in the opening of the pixel defining layer 8. The bridging conductive layer 6 is formed in the peripheral area 101, and is insulated from the peripheral circuit 13 and extends across the peripheral circuit 13. The bridging conductive layer 6 is electrically connected to the common electrode lead 4. In this example, one end of the bridging conductive layer 6 away from the working area 103 is directly overlapped with the common electrode lead 4 to achieve electrical connection between the two. This form of direct overlap is conducive to reducing contact resistance and is easy to manufacture.

[0113] like Figure 8K As shown, the organic light emitting layer 16 may be formed on the anode 15 by coating or deposition, for example. In other examples, it may also be an electroluminescent layer (eg, an organic electroluminescent layer).

[0114] like Figure 8L As shown, the common electrode 7 is formed in the working area 103. For example, the common electrode 7 can cover the organic light-emitting layer 16 and the pixel defining layer 8, and extend to the peripheral area 102 to directly contact the jumper conductive layer 6 to achieve electrical connection between the two, so as to achieve electrical connection between the common electrode 7 and the common electrode lead 4 via the jumper conductive layer 6. That is, the jumper conductive layer 6 electrically connects the common electrode lead 4 and the common electrode 7. By the above method, the following can be formed: Figure 8L The array substrate 100 is shown.

[0115] Figure 8M for Figure 8L FIG. 2 is an enlarged schematic diagram of a part 20 of the array substrate 100 in FIG. The enlarged schematic diagram exemplarily shows the structure of the peripheral circuit 13 .

[0116] The embodiments of the present disclosure provide a display substrate peripheral circuit structure, an array substrate and a manufacturing method thereof, and a display device, in which the common electrode lead is at least partially overlapped and insulated with a first area of ​​the peripheral area close to the outer contour edge of the base substrate, so that the width occupied by the common electrode lead alone in the non-working area can be reduced. When the peripheral circuit structure is applied to a display device, etc., it is conducive to achieving a narrower frame.

[0117] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A substrate, comprising: The substrate comprises a working area and a non-working area located around the working area; the non-working area comprises a peripheral area close to the working area and a non-circuit area far from the working area; A peripheral circuit is arranged in the peripheral area; A common electrode lead is arranged in the non-working area; Common electrode; as well as A jumper conductive layer is located in the non-working area, wherein the material of the jumper conductive layer is an opaque conductive material, the jumper conductive layer electrically connects the common electrode and the common electrode lead, and the orthographic projection of the jumper conductive layer on the base substrate at least partially overlaps with the orthographic projection of the peripheral circuit area on the base substrate, and the jumper conductive layer is insulated from the peripheral circuit.

2. The substrate according to claim 1, wherein The jumper conductive layer extends across the peripheral circuit, and the material of the jumper conductive layer is a metal material.

3. The substrate according to claim 1, wherein The opaque conductive material includes aluminum.

4. The substrate according to claim 1, wherein The bridging conductive layer is arranged on a side of the common electrode lead away from the base substrate.

5. The substrate according to claim 1, wherein The bridging conductive layer is arranged on a side of the common electrode facing the base substrate.

6. The substrate according to claim 1, wherein The peripheral circuit is not located in the non-circuit area, the orthographic projection of the common electrode lead on the base substrate at least partially overlaps with the orthographic projection of the peripheral circuit on the base substrate, and the common electrode lead is insulated from the peripheral circuit.

7. The substrate of claim 1 further comprising an outer contour edge, wherein: The common electrode lead is arranged along at least a portion of the outer contour edge of the base substrate, and a portion of the common electrode lead is located in the non-circuit area.

8. The substrate according to claim 1, wherein The common electrode extends from the operating area to the non-operating area.

9. The substrate according to claim 1, wherein The jumper conductive layer includes two surfaces that directly contact the common electrode lead and the common electrode, respectively.

10. The substrate according to claim 7, further comprising an interlayer insulating layer, wherein The interlayer insulating layer is disposed between the peripheral circuit and the common electrode lead, and covers the peripheral circuit to insulate the peripheral circuit from the common electrode lead.

11. The substrate according to claim 7, wherein One end of the interlayer insulating layer close to the outer contour edge of the base substrate has a flat surface, and the common electrode lead is arranged on the flat surface; The peripheral circuit includes an external connection part, and the external connection part includes an external connection point and an external connection wire; The interlayer insulating layer includes a via hole exposing an external connection point of the peripheral circuit, and the external connection wire is electrically connected to the external connection point of the peripheral circuit through the via hole.

12. The substrate according to claim 1, wherein The peripheral circuit comprises: At least one thin film transistor, wherein the thin film transistor comprises a gate, a source and a drain; The capacitor comprises a first electrode plate and a second electrode plate which are arranged opposite to each other, wherein the first electrode plate and the gate electrode of the thin film transistor are arranged in the same layer; a peripheral circuit signal output lead configured to output an output signal of the peripheral circuit to the working area; and A connecting line, including a first portion; Wherein, the second electrode plate of the capacitor is electrically connected to the source or drain of the thin film transistor through the first part of the connecting line; The external connection point, the second plate of the capacitor, and the connection line are arranged in the same layer.

13. The substrate according to claim 1, wherein The peripheral circuit is a GOA type gate driving circuit.

14. The substrate according to claim 1, wherein The peripheral circuit includes an external connection part, and the external connection part includes an external connection point and an external connection wire; The external connection wire and the common electrode lead are made of the same material and are arranged in the same layer.

15. The substrate according to claim 14, wherein The external connection part of the peripheral circuit also includes an external connection node; The external connection point is disposed in a second area of ​​the peripheral area, wherein an orthographic projection of the external connection point on the base substrate does not overlap with an orthographic projection of the common electrode lead on the base substrate; and The external connection point is located at a side of the common electrode lead that is close to an outer contour edge of the substrate, or the external connection point is located at a side of the common electrode lead that is away from an outer contour edge of the substrate.

16. An electronic device comprising the substrate according to any one of claims 1 to 15.

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