Display panel and method of manufacturing the same

Abstract

The invention relates to a display panel and a method of manufacturing the same. The display panel includes: a base layer; a plurality of light emitting elements disposed on the base layer; a partition wall disposed between the plurality of light emitting elements and electrically connecting electrodes of the plurality of light emitting elements; and a plurality of inorganic patterns disposed on the plurality of light emitting elements. A recessed portion recessed in a direction toward the base layer is defined in the partition wall, and each of the plurality of inorganic patterns is disposed on the partition wall and covers one side surface of the partition wall defining the recessed portion.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a display panel and a method of manufacturing the display panel, and particularly, to a display panel having reliability and a method of manufacturing the display panel. Background Art

[0002] The display device is activated according to the electrical signal. The display device may include a display panel that displays an image. Among display panels, an organic light emitting display panel has low power consumption, high brightness, and high response speed.

[0003] Among display panels, an organic light emitting display panel includes an anode, a cathode and a light emitting pattern. The light emitting pattern is separated for each light emitting area, and the cathode supplies a common voltage to each light emitting area. Summary of the invention

[0004] Embodiments of the present disclosure provide a display panel having reduced defects by preventing moisture from penetrating into a light emitting element, and a method of manufacturing the same.

[0005] According to an embodiment, a display panel includes: a substrate layer; a plurality of light emitting elements arranged on the substrate layer; a partition wall disposed between the plurality of light emitting elements and electrically connecting electrodes of the plurality of light emitting elements; and a plurality of inorganic patterns disposed on the plurality of light emitting elements. A recessed portion recessed in a direction toward the substrate layer is defined in the partition wall, and each of the plurality of inorganic patterns is disposed on the partition wall and covers a first side surface of the partition wall defining the recessed portion.

[0006] The partition wall may include a first sub-partition wall and a second sub-partition wall, the first sub-partition wall and the second sub-partition wall being spaced apart from each other, and the recessed portion being between the first sub-partition wall and the second sub-partition wall.

[0007] The display panel may further include: a dummy pattern disposed between the partition wall and the inorganic pattern.

[0008] The dummy pattern may include: a first dummy pattern disposed on the first sub-partition wall; and a second dummy pattern disposed on the second sub-partition wall.

[0009] The recessed portion may include a first recessed portion and a second recessed portion spaced apart from each other.

[0010] The partition wall may further include a third sub-partition wall disposed between the first concave portion and the second concave portion.

[0011] The dummy pattern may not be disposed on the third sub-partition wall.

[0012] The display panel may further include a bridge electrode electrically connecting the first sub partition wall and the second sub partition wall.

[0013] Each of the plurality of light emitting elements may include the electrode electrically connected to the partition wall and a first electrode disposed on the base layer, and the bridge electrode and the first electrode may be disposed on the same layer.

[0014] The display panel may further include: a pixel defining film, in which a light emitting opening is defined, and disposed on the substrate layer. A portion of the first electrode is exposed through the light emitting opening. A first contact hole and a second contact hole may be defined in the pixel defining film, the first contact hole electrically connecting the first sub-partition wall and the bridge electrode, and the second contact hole electrically connecting the second sub-partition wall and the bridge electrode.

[0015] Each of the plurality of light-emitting elements may include: a first electrode disposed on the substrate layer; a light-emitting layer disposed on the first electrode; and a second electrode disposed on the light-emitting layer. The display panel may further include: a pixel defining film in which a light-emitting opening is defined and disposed on the substrate layer. A portion of the first electrode is exposed through the light-emitting opening. The second electrode may be the electrode electrically connected to the partition wall.

[0016] The partition wall may include: a first partition wall layer, disposed on the pixel defining film; and a second partition wall layer, disposed on the first partition wall layer; and a second side surface of the first partition wall layer close to the light-emitting opening may be further recessed in a direction away from the light-emitting opening than a third side surface of the second partition wall layer close to the light-emitting opening.

[0017] The second electrode may be in direct contact with the first partition wall layer.

[0018] The depth of the recessed portion may be smaller than the thickness of the partition wall.

[0019] An open area through which a portion of the first side surface of the partition wall is exposed may be defined between a bottom surface of the recess and the inorganic pattern.

[0020] According to an embodiment, a method for manufacturing a display panel includes: providing a preliminary display panel, the preliminary display panel including a substrate layer, a first electrode disposed on the substrate layer, and a preliminary pixel defining film disposed on the substrate layer and covering the first electrode; forming a preliminary partition wall on the preliminary pixel defining film; patterning the preliminary partition wall to form a partition wall, in which a recessed portion recessed in a direction toward the substrate layer is defined, and the partition wall has conductivity; forming a light-emitting layer on the first electrode; forming a second electrode electrically connected to the partition wall on the light-emitting layer; and forming an inorganic pattern on a portion of the partition wall and the second electrode. The inorganic pattern is disposed on the partition wall and covers one side surface of the partition wall defining the recessed portion.

[0021] The partition wall may include a first sub-partition wall and a second sub-partition wall, the first sub-partition wall and the second sub-partition wall are spaced apart from each other, and the recessed portion is between the first sub-partition wall and the second sub-partition wall, the preliminary display panel may further include a bridging electrode, the bridging electrode is disposed on the base layer and electrically connects the first sub-partition wall and the second sub-partition wall, and the bridging electrode may be formed in the same process as the process of forming the first electrode.

[0022] The method may further include: before the forming of the preliminary partition wall, forming a contact hole in the preliminary pixel defining film, the contact hole electrically connecting the preliminary partition wall and the bridge electrode.

[0023] The forming of the inorganic pattern may include: forming an inorganic layer on the second electrode and the partition wall; and forming the inorganic pattern by patterning the inorganic layer so that the inorganic layer does not overlap at least a portion of the recessed portion.

[0024] The method may further include forming an opening in the preliminary partition wall to overlap with the first electrode. The opening and the recessed portion may be formed simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other aspects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0026] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure.

[0027] Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure.

[0028] Figure 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0029] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0030] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the present disclosure.

[0031] Figure 5 According to an embodiment of the present disclosure, Figure 3 A cross-sectional view of the display panel taken along line II'.

[0032] Fig. 6A According to an embodiment of the present disclosure, Figure 4 sectional view of the display panel taken along line II-II'.

[0033] Figure 6B yes Fig. 6A An enlarged view of region AA' is shown in FIG.

[0034] Figure 7 According to another embodiment Fig. 6A An enlarged view of region AA' is shown in FIG.

[0035] Figure 8 According to yet another embodiment Fig. 6A An enlarged view of region AA' is shown in FIG.

[0036] FIG. 9A to FIG. 9K are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] Since the present disclosure is variously modified and has alternative forms, its embodiments will be illustrated in the drawings and will be described in detail herein. However, it should be understood that the present disclosure is not limited to the specific disclosure and includes all changes, equivalents and substitutes included in the spirit and scope of the present disclosure.

[0038] In the present specification, the expression that a first component (or region, layer, portion, part, etc.) is “disposed on”, “connected to” or “coupled to” a second component means that the first component is directly disposed on / connected to / coupled to the second component, or means that a third component is interposed therebetween.

[0039] The same reference numerals refer to the same components. In addition, in the drawings, in order to effectively describe the technical contents, the thickness, ratio and size of the components are exaggerated.

[0040] For example, "an element" has the same meaning as "at least one element", unless the context clearly indicates otherwise. "At least one" should not be interpreted as limiting "one". "Or" means "and / or". The term "and / or" includes all combinations of one or more components that can be limited by the relevant configuration.

[0041] The terms "first", "second", etc. are used to describe various components, but the components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the scope of the present disclosure, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Unless otherwise clearly indicated in the context, a singular expression includes a plural expression.

[0042] In addition, the terms "below", "under", "on", "over" and the like are used to describe the relationship between components illustrated in the drawings. These terms have relative concepts and are described with reference to directions indicated in the drawings.

[0043] Unless otherwise defined, all terms (including technical terms and scientific terms) used in this specification have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. In addition, the terms used in this article should be interpreted as having the same meaning as in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless the terms are clearly defined in this article.

[0044] It will be understood that the terms “comprises,” “includes,” “has,” etc. specify the presence of features, numbers, steps, operations, elements or components, or a combination thereof, described in the specification, and do not exclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements or components, or a combination thereof.

[0045] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0046] Figure 1A is a perspective view of a display device according to an embodiment of the present disclosure. Figure 1B is an exploded perspective view of a display device according to an embodiment of the present disclosure. Figure 2 is a cross-sectional view of a display panel according to an embodiment of the present disclosure.

[0047] In one embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an external billboard. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer ("PC"), a laptop computer, a personal digital terminal, a vehicle navigation unit, a game console, a smart phone, a tablet PC, and a camera. These devices are presented only as embodiments and may be used as other display devices as long as the display device does not depart from the concept of the present disclosure. In one embodiment, the display device DD is exemplarily illustrated as a smart phone.

[0048] refer to Figure 1A , Figure 1B and Figure 2 , the display device DD may display an image IM in a third direction DR3 on a display surface FS parallel to the first direction DR1 and the second direction DR2. The image IM may include a static image as well as a dynamic image. In FIG. 1 , a table window and an icon are illustrated as examples of the image IM. The display surface FS on which the image IM is displayed may correspond to the front surface of the display device DD.

[0049] In one embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each member are defined with respect to the direction in which the image IM is displayed. The front surface and the rear surface may be opposite to each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. At the same time, the directions indicated by the first direction to the third directions DR1, DR2 and DR3 are relative concepts and may be changed to other directions. In the specification, the phrase "on a plane" may mean a state when observed in the third direction DR3 (i.e., in a plan view).

[0050] like Figure 1B As shown in FIG. 1 , the display device DD according to the embodiment may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to constitute the appearance of the display device DD.

[0051] The window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may be an area having a visible light transmittance of about 90% or more.

[0052] The border area BZA may be an area having a relatively lower transmittance than the transmittance of the transmission area TA. The border area BZA may define the shape of the transmission area TA. The border area BZA may be adjacent to the transmission area TA and surround the transmission area TA. Meanwhile, this is exemplarily illustrated, and in the window WP according to an embodiment of the present disclosure, the border area BZA may be omitted. The window WP may include at least one functional layer of an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, and is not limited to the embodiment.

[0053] The display module DM may be disposed under the window WP. The display module DM may be a component that substantially generates an image IM. The image IM generated by the display module DM is displayed on a display surface IS of the display module DM and is visually recognized by a user from the outside through the transmission area TA.

[0054] The display surface IS of the display module DM may include a display area DA and a non-display area NDA. The display area DA may be an area activated according to an electrical signal. The non-display area NDA is adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA is an area covered by the frame area BZA and cannot be visually recognized from the outside.

[0055] like Figure 2 As shown in , the display module DM according to the embodiment may include a display panel DP and an input sensor INS. Although not separately illustrated, the display device DD according to the embodiment of the present disclosure may further include a protection member disposed on the lower surface of the display panel DP or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0056] The display panel DP may be a light-emitting display panel, but the present disclosure is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting pattern in the organic light-emitting display panel includes an organic light-emitting material. The light-emitting pattern in the inorganic light-emitting display panel includes quantum dots, quantum rods, or micro light-emitting diodes ("LEDs"). Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0057] The display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a display element layer DP-OLED, and an encapsulation layer TFE. The input sensor INS may be directly disposed on the encapsulation layer TFE. In this specification, the phrase "component A is directly disposed on component B" means that no adhesive layer is disposed between component A and component B.

[0058] The base layer BL may include at least one plastic film. The base layer BL is a flexible substrate and may include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. In this specification, it can be seen that a display area DA and a non-display area NDA are defined in the base layer BL, and in this case, it can be further seen that a component arranged on the base layer BL is arranged to overlap with the display area DA or the non-display area NDA.

[0059] The circuit element layer DP-CL includes at least one insulating layer and circuit elements. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit elements include signal lines, pixel driving circuits, etc.

[0060] The display element layer DP-OLED may include a conductive partition wall and a light emitting element. The light emitting element may include an anode, a light emitting pattern and a cathode, and the light emitting pattern may include at least one light emitting pattern.

[0061] The encapsulation layer TFE includes a plurality of thin films, some of which are arranged to improve optical efficiency, and some of which are arranged to protect the organic light emitting diode.

[0062] The input sensor INS acquires coordinate information of the external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. The input sensor INS may include a single layer or multiple layers of insulating layers. The input sensor INS may detect the external input, for example, in a capacitive manner. In the present disclosure, the operation method of the input sensor INS is not particularly limited, and in an embodiment of the present disclosure, the input sensor INS may detect the external input in an electromagnetic induction method or a pressure detection method. Meanwhile, in an embodiment of the present disclosure, the input sensor INS may be omitted.

[0063] like Figure 1B As shown in , the housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0064] The housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates including glass, plastic, or metal or a combination thereof. The housing HAU may stably protect the components of the display device DD housed in the internal space from external impacts.

[0065] Figure 3 is a plan view of a display panel according to an embodiment of the present disclosure.

[0066] refer to Figure 3 The display panel DP may include a base layer BL, and the base layer BL is divided into Figure 2A display area DA and a non-display area NDA are described.

[0067] The display panel DP may include pixels PX arranged in the display area DA and signal lines SGL electrically connected to the pixels PX. The display panel DP may include a driving circuit GDC and a pad portion PLD arranged in the non-display area NDA.

[0068] The pixels PX may be arranged in the first direction DR1 and the second direction DR2. The pixels PX may include a plurality of pixel rows extending in the first direction DR1 and arranged in the second direction DR2 and a plurality of pixel columns extending in the second direction DR2 and arranged in the first direction DR1.

[0069] The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each gate line GL may be connected to a corresponding pixel among the pixels PX, and each data line DL may be connected to a corresponding pixel among the pixels PX. The power line PL may be electrically connected to the pixel PX. The control signal line CSL may be connected to the drive circuit GDC to provide a control signal to the drive circuit GDC.

[0070] The driving circuit GDC may include a gate driving circuit. The gate driving circuit may generate a gate signal and sequentially output the generated gate signal to the gate line GL. The gate driving circuit may further output another control signal to the pixel driving circuit.

[0071] The pad portion PLD may be a portion connected to a flexible circuit board. The pad portion PLD may include a pixel pad D-PD, and the pixel pad D-PD may be a pad for connecting the flexible circuit board to the display panel DP. Each pixel pad D-PD may be connected to a corresponding signal line among the signal lines SGL. The pixel pad D-PD may be connected to a corresponding pixel PX through the signal line SGL. In addition, any pixel pad among the pixel pads D-PD may be connected to a drive circuit GDC.

[0072] In addition, the pad portion PLD may further include an input pad. The input pad may be used to connect the flexible circuit board to the input sensor INS (see Figure 2 However, the present disclosure is not limited thereto, and in another embodiment, the input pad may be arranged on the input sensor INS (see Figure 2 ) and connected to the pixel pad D-PD and a separate circuit board. Alternatively, the input sensor INS can be omitted (see Figure 2 ) and may further not include an input pad.

[0073] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment of the present disclosure. Figure 4When the display module DM (see Figure 2 ) of the display surface IS (see Figure 2 ) Observation display module DM (see Figure 2 ) and illustrates the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B and the partition walls PW.

[0074] refer to Figure 4 , the display area DA may include first to third light-emitting areas PXA-R, PXA-G, and PXA-B and a peripheral area NPXA surrounding the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may correspond to areas emitting light provided by the light-emitting element, respectively. The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be arranged according to the display module DM (see FIG. Figure 2 ) is classified by the color of the light emitted externally.

[0075] The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may respectively provide first to third color lights having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, examples of the first to third color light beams are not necessarily limited to the above examples.

[0076] Each of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be defined as an area in which the upper surface of the anode is exposed by the light-emitting opening, which will be described below. The peripheral area NPXA may set a boundary between the first to third light-emitting areas PXA-R, PXA-G, and PXA-B, and prevent color mixing between the first to third light-emitting areas PXA-R, PXA-G, and PXA-B.

[0077] The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be provided so that their numbers are all plural, and may be repeatedly arranged in a specific arrangement form in the display area DA. For example, the first light-emitting area PXA-R and the third light-emitting area PXA-B may be alternately arranged along the first direction DR1 to constitute a "first group". The second light-emitting area PXA-G may be arranged along the first direction DR1 to constitute a "second group". Each of the "first group" and the "second group" may be provided in plurality, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0078] One second light emitting region PXA-G may be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0079] Figure 4 The arrangement form of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B is exemplarily illustrated, but the present disclosure is not limited thereto, and the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may be arranged in various forms. Figure 4 As shown in FIG. 1 , the first to third light-emitting regions PXA-R, PXA-G, and PXA-B may have Alternatively, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have a stripe arrangement or a diamond arrangement. Layout form.

[0080] The first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have various shapes on a plane. For example, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have shapes such as a polygonal shape, a circular shape, or an elliptical shape. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a rhombus shape) on a plane and the second light emitting region PXA-G having an octagonal shape are exemplarily illustrated.

[0081] The first to third light emitting regions PXA-R, PXA-G, and PXA-B may have the same shape on a plane, or may have at least partially different shapes. Figure 4 The first and third light emitting regions PXA-R and PXA-B having the same shape on a plane and the second light emitting region PXA-G having a shape different from the first and third light emitting regions PXA-R and PXA-B are exemplarily illustrated.

[0082] At least some of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may have different areas on a plane. In one embodiment, the area of ​​the first light-emitting area PXA-R emitting red light may be larger than the area of ​​the second light-emitting area PXA-G emitting green light, and may be smaller than the area of ​​the third light-emitting area PXA-B emitting blue light. However, the size relationship between the areas of the first to third light-emitting areas PXA-R, PXA-G, and PXA-B according to the color of the emitted light is not limited thereto, and may depend on the display module DM (see Figure 2In addition, the present disclosure is not limited thereto, and in another embodiment, the first to third light-emitting areas PXA-R, PXA-G, and PXA-B may also have the same area on a plane.

[0083] The display module DM (see Figure 2 ) of the first to third light emitting areas PXA-R, PXA-G and PXA-B may be shaped, area, arranged and / or the like according to the color of the emitted light or the display module DM (see Figure 2 ) size and structure can be designed in various ways, and are not limited to Figure 4 The embodiment shown in FIG.

[0084] According to an embodiment of the present disclosure, the partition wall PW may not overlap with the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. The partition wall PW may have a shape surrounding the first to third light-emitting areas PXA-R, PXA-G, and PXA-B. In detail, the partition wall PW may have a closed line shape surrounding the first to third light-emitting areas PXA-R, PXA-G, and PXA-B on a plane. A recessed portion DEP may be formed in the partition wall PW. The detailed shapes of the partition wall PW and the recessed portion DEP will be described below.

[0085] Figure 5 According to an embodiment of the present disclosure, Figure 3 A cross-sectional view of the display panel taken along line II'. Figure 5 In the description of Figure 2 Description will be made, and description of the same figure numbers will be omitted.

[0086] Figure 5 Enlarged diagram display area DA (see Figure 4 ) in a light emitting area PXA, and Figure 5 The light emitting area PXA may correspond to Figure 4 one of the first to third light emitting areas PXA-R, PXA-G and PXA-B.

[0087] refer to Figure 5 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and an encapsulation layer TFE.

[0088] The display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, etc. The insulating layers, semiconductor layers, and conductive layers are formed by coating, deposition, etc. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching. In this way, semiconductor patterns, conductive patterns, signal lines, etc. included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0089] The circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR, a signal transmission region SCL, first to fifth insulating layers 10, 20, 30, 40 and 50, an electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0090] The buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the coupling force between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked.

[0091] The semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, the present disclosure is not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5 A portion of the semiconductor pattern is exemplarily illustrated, and the semiconductor pattern may be further arranged in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see FIG. Figure 4 ). The semiconductor pattern may be arranged across a plurality of light emitting regions PXA-R, PXA-G, and PXA-B in a specific rule. Depending on whether the semiconductor pattern is doped, the semiconductor pattern may have different electrical properties. The semiconductor pattern may include a first region having a high doping concentration and a second region having a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0092] The conductivity of the first region is greater than that of the second region, and the first region can be substantially used as an electrode or a signal line. The second region can substantially correspond to an active portion (or channel) of a transistor. In other words, a portion of the semiconductor pattern can be an active portion of a transistor, another portion of the semiconductor pattern can be a source or drain of the transistor, and another portion of the semiconductor pattern can be a conductive region.

[0093] The source S, the active portion A, and the drain D of the transistor TR may be formed of a semiconductor pattern. Figure 5 A portion of a signal transmission region SCL formed of a semiconductor pattern is illustrated Although not separately illustrated, the signal transmission region SCL may be connected to a drain D of the transistor TR on a plane.

[0094] The first to fifth insulating layers 10, 20, 30, 40, and 50 may be disposed on the buffer layer BFL. The first to fifth insulating layers 10, 20, 30, 40, and 50 may be inorganic layers or organic layers.

[0095] The first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active portion A, the drain D, and the signal transmission region SCL of the transistor TR disposed on the buffer layer BFL. The gate G of the transistor TR may be disposed on the first insulating layer 10. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the electrode EE.

[0096] The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transmission region SCL through a contact hole CNT-1 passing through the first to third insulating layers 10, 20, and 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0097] The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0098] The display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP.

[0099] The light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode).

[0100] The anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined as passing through the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission area SCL through the first connection electrode CNE1 and the second connection electrode CNE2, and thus electrically connected to the corresponding circuit element. The anode AE ​​may include a single-layer structure or a multi-layer structure. The anode AE ​​may include a plurality of layers including ITO and Ag. For example, the anode AE ​​may include a layer including ITO (hereinafter, referred to as a lower ITO layer), a layer provided on the lower ITO layer and including Ag (hereinafter, referred to as an Ag layer), and a layer provided on the Ag layer and including ITO (hereinafter, referred to as an upper ITO layer).

[0101] The pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The pixel defining film PDL may define a light emitting opening OP-E. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0102] The sacrificial pattern SP may be disposed between the anode AE ​​and the pixel defining film PDL. A sacrificial opening OP-S may be defined in the sacrificial pattern SP, and a portion of the upper surface of the anode AE ​​is exposed through the sacrificial opening OP-S. In a plan view, the sacrificial opening OP-S may overlap with the light emitting opening OP-E.

[0103] According to the embodiment, in the cross section, the upper surface of the anode AE ​​may be spaced apart from the pixel defining film PDL with the sacrificial pattern SP interposed therebetween, and accordingly, damage to the anode AE ​​may be prevented during formation of the light emitting opening OP-E.

[0104] On a plane, the size of the light-emitting opening OP-E may be smaller than the size of the sacrificial opening OP-S. That is, the inner surface of the pixel-defining film PDL defining the light-emitting opening OP-E may be closer to the center of the anode AE ​​than the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S. However, the present disclosure is not limited thereto, and in another embodiment, the inner surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be substantially aligned with the inner surface of the pixel-defining film PDL defining the light-emitting opening OP-E. In this case, the light-emitting area PXA may be regarded as the area of ​​the anode AE ​​exposed from the corresponding sacrificial opening OP-S.

[0105] The pixel definition layer PDL may include an inorganic insulating material. For example, the pixel definition layer PDL may include silicon nitride (SiN x ). The pixel defining film PDL may be disposed between the anode AE ​​and the partition wall PW, and prevents electrical connection between the anode AE ​​and the partition wall PW.

[0106] The light emitting pattern EP may be disposed on the anode AE. The light emitting pattern EP may include a light emitting pattern including a light emitting material. The light emitting pattern EP may further include a hole injection layer and a hole transport layer disposed between the anode AE ​​and the light emitting pattern, and may further include an electron transport layer and an electron injection layer disposed on the light emitting pattern. The light emitting pattern EP may be referred to as an "organic layer" or an "intermediate layer".

[0107] The light emitting pattern EP may be patterned through the end portion defined by the partition wall PW. The light emitting pattern EP may be disposed inside the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL exposed from the partition wall opening OP-P.

[0108] The cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned through an end portion defined by the partition wall PW. At least a portion of the cathode CE may be disposed on a side surface of the partition wall PW defining the partition wall opening OP-P.

[0109] The cathode CE may be conductive. The cathode CE may be formed of various materials such as metal, transparent conductive oxide ("TCO"), and conductive polymer materials as long as the material may be conductive. For example, the cathode CE may contain silver (Ag), magnesium (Mg), lead (Pb), copper (Cu), or a compound thereof.

[0110] The partition wall PW may be disposed on the pixel defining film PDL. A partition wall opening OP-P may be defined in the partition wall PW. The partition wall opening OP-P may correspond to (or overlap) the light emitting opening OP-E in a plan view and expose at least a portion of the cathode CE.

[0111] The partition wall PW may have an undercut shape in cross section (ie, in a cross-sectional view). The partition wall PW may include a plurality of layers stacked sequentially, and at least one of the plurality of layers may be recessed in a direction parallel to the first direction DR1 compared to the other layers. Accordingly, the partition wall PW may include an end portion.

[0112] The partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be disposed on the pixel definition film PDL, and the second partition wall layer L2 may be disposed on the first partition wall layer L1. The thickness of the first partition wall layer L1 may be greater than the thickness of the second partition wall layer L2, but the present disclosure is not limited thereto. In another embodiment, the cathode CE may contact the side surface of the first partition wall layer L1.

[0113] The side surface S_L2 of the second partition wall layer L2 may be closer to the center of the anode AE ​​than the side surface S_L1 of the first partition wall layer L1 in a plan view. That is, the side surface S_L1 of the first partition wall layer L1 may be further recessed in a direction away from the center of the anode AE ​​than the side surface S_L2 of the second partition wall layer L2. The first partition wall layer L1 may be further recessed relative to the light emitting area PXA than the second partition wall layer L2. The first partition wall layer L1 may be formed to be undercut relative to the second partition wall layer L2. The portion of the second partition wall layer L2 protruding from the first partition wall layer L1 toward the light emitting area PXA may be defined as an end portion inside the partition wall PW.

[0114] The first partition wall layer L1 and the second partition wall layer L2 may include a conductive material. For example, the conductive material may include a metal, a TCO, or a combination thereof. For example, the metal includes gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The TCO may include indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide, indium oxide, indium gallium oxide, indium gallium zinc oxide ("IGZO"), or aluminum zinc oxide.

[0115] Figure 5 Each of the side surfaces S_L1 of the first partition wall layer L1 and the side surfaces S_L2 of the second partition wall layer L2 is exemplarily illustrated to be perpendicular to the upper surface of the pixel definition film PDL, but the present disclosure is not limited thereto. In addition, for example, the partition wall PW may have a conical shape or an inverted conical shape. The partition wall PW may receive a bias voltage (or a cathode voltage). The cathode CE may be electrically connected to the first partition wall layer L1 and receive a bias voltage.

[0116] The dummy pattern DMP may be disposed on the partition wall PW. The dummy pattern DMP may include a first dummy layer D1 and a second dummy layer D2. The first dummy layer D1 and the second dummy layer D2 may be sequentially stacked on an upper surface of the second partition wall layer L2 of the partition wall PW in the third direction DR3.

[0117] The first dummy layer D1 may include an organic material. For example, the first dummy layer D1 may include the same material as that of the light emitting pattern EP. The first dummy layer D1 may be formed simultaneously with the light emitting pattern EP through one process and may be formed separately from the light emitting pattern EP by the undercut shape of the partition wall PW.

[0118] The second dummy layer D2 may include a conductive material. For example, the second dummy layer D2 may include the same material as that of the cathode CE. The second dummy layer D2 may be formed simultaneously with the cathode CE through one process, and may be formed separately from the cathode CE by the undercut shape of the partition wall PW.

[0119] The dummy opening OP-D may be defined in the dummy pattern DMP. The dummy opening OP-D may correspond to the light emitting opening OP-E. On a plane, each of the first dummy layer D1 and the second dummy layer D2 may have a closed line shape surrounding the light emitting area PXA.

[0120] Figure 5 It is exemplarily illustrated that the inner surface of the first dummy layer D1 and the inner surface of the second dummy layer D2 are aligned with the side surface S_L2 of the second partition wall layer L2, but the present disclosure is not limited thereto, and in another embodiment, the first dummy layer D1 and the second dummy layer D2 may cover the side surface S_L2 of the second partition wall layer L2.

[0121] The encapsulation layer TFE may be disposed on the display element layer DP-OLED. The encapsulation layer TFE may include a lower inorganic pattern (or inorganic pattern) LIL, an organic film OL, and an upper inorganic film UIL.

[0122] The lower inorganic pattern LIL may be disposed to correspond to the light emitting element ED and the partition wall PW. For example, a first portion of the lower inorganic pattern LIL may be disposed on the light emitting element ED, and a second portion of the lower inorganic pattern LIL may be disposed on the partition wall PW (second partition wall layer L2). A portion of the lower inorganic pattern LIL may be disposed on the cathode CE to cover the light emitting element ED. Although not shown, the lower inorganic pattern LIL disposed on the partition wall PW may extend on the partition wall PW and cover the recessed portion DEP (see FIG. 1 ) of the partition wall PW that is defined to be formed in the partition wall PW. Figure 4 ) is a side surface of the . A detailed description thereof will be described below.

[0123] The organic film OL may cover the lower inorganic pattern LIL and provide a flat upper surface. The upper inorganic film UIL may be disposed on the organic film OL.

[0124] The lower inorganic pattern LIL and the upper inorganic film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0125] Fig. 6A According to an embodiment of the present disclosure, Figure 4 sectional view of the display panel taken along line II-II'. Figure 6B yes Fig. 6A An enlarged view of region AA' is shown in FIG.

[0126] Fig. 6A is an enlarged view of a first light emitting area PXA-R and a second light emitting area PXA-G, and Figure 5 The description of the light emitting area PXA in FIG. 1 may be similarly applied to each of the first light emitting area PXA-R and the second light emitting area PXA-G. In addition, although not shown, Figure 4 The description of the third light emitting area PXA-B shown in FIG. Fig. 6A The description of the first light emitting area PXA-R and the second light emitting area PXA-G illustrated in FIG.

[0127] refer to Fig. 6A The display panel DP according to the embodiment may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED (see Figure 5The display element layer DP-OLED may include light emitting elements ED1 and ED2, sacrificial patterns SP1 and SP2, a pixel defining film PDL, partition walls PW, and dummy patterns DMP1 and DMP2. Fig. 6A The circuit element layer DP-CL is simply illustrated, and the description of the circuit element layer DP-CL is the same as Figure 5 The description is repeated and will therefore be omitted.

[0128] The light emitting elements ED1 and ED2 may include a first light emitting element ED1 and a second light emitting element ED2.

[0129] The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1, and the second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The first anode AE1 and the second anode AE2 may be provided in a plurality of patterns. In an embodiment, the first light emitting pattern EP1 may provide red light, and the second light emitting pattern EP2 may provide green light.

[0130] In one embodiment, a first light emitting opening OP1-E and a second light emitting opening OP2-E may be defined in the pixel defining film PDL. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The first light emitting region PXA-R may be defined as a region of the upper surface of the first anode AE1 exposed by the first light emitting opening OP1-E. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The second light emitting region PXA-G may be defined as a region of the upper surface of the second anode AE2 exposed by the second light emitting opening OP2-E.

[0131] In one embodiment, the sacrificial patterns SP1 and SP2 may include a first sacrificial pattern SP1 and a second sacrificial pattern SP2. The first sacrificial pattern SP1 and the second sacrificial pattern SP2 may be arranged on the upper surface of the first anode AE1 and the upper surface of the second anode AE2, respectively. A first sacrificial opening OP1-S and a second sacrificial opening OP2-S corresponding to the first light emitting opening OP1-E and the second light emitting opening OP2-E may be defined in the first sacrificial pattern SP1 and the second sacrificial pattern SP2, respectively.

[0132] The first light emitting pattern EP1 and the first cathode CE1 may be disposed inside the first light emitting opening OP1-E and the first partition wall opening OP1-P, and the second light emitting pattern EP2 and the second cathode CE2 may be disposed inside the second light emitting opening OP2-E and the second partition wall opening OP2-P.

[0133] The partition wall PW may be disposed on the pixel definition film PDL. Figure 5The light emitting patterns EP1 and EP2 may be patterned and deposited in units of pixels through the end portions defined in the partition wall PW. That is, the light emitting patterns EP1 and EP2 may be formed together using an open mask, but may be easily divided in units of pixels through the partition wall PW.

[0134] The first cathode CE1 and the second cathode CE2 may be in contact with the side surface of the partition wall PW. In an embodiment of the present disclosure, the first cathode CE1 and the second cathode CE2 may be physically separated by the partition wall PW forming the end portion, may be in contact with the partition wall PW inside the partition wall openings OP1-P and OP2-P, may be electrically connected to each other, and thus may receive a common voltage. That is, the electrodes (i.e., cathodes) of the light-emitting elements ED1 and ED2 spaced apart from each other may be electrically connected to each other through the partition wall PW, and thus may receive a common voltage. As a result, a common cathode voltage may be uniformly provided to the light-emitting elements ED1 and ED2.

[0135] When the light emitting patterns EP1 and EP2 are patterned using a fine metal mask ("FMM"), a support spacer protruding from the partition wall PW to support the FMM should be provided. In addition, since the FMM is spaced apart from the substrate surface on which patterning is performed by the height of the partition wall PW and the spacer, the realization of high resolution may be limited. In addition, since the FMM is in contact with the spacer, after the patterning process of the light emitting patterns EP1 and EP2, foreign matter may remain on the spacer and the spacer may be damaged due to the impact of the FMM. Accordingly, a defective display panel may be formed.

[0136] According to an embodiment of the present disclosure, the display panel DP includes a partition wall PW, and thus the light emitting elements ED1 and ED2 can be easily physically separated from each other. Accordingly, current leakage or driving error between adjacent light emitting areas PXA-R and PXA-G can be prevented, and independent driving of each of the light emitting elements ED1 and ED2 can be performed.

[0137] In particular, the light emitting patterns EP1 and EP2 do not utilize the display area DA (see Figure 2 ) is patterned, and thus a display panel DP having improved process reliability due to a reduced defect rate can be provided. Since patterning can be performed even when a separate supporting spacer protruding from the partition wall PW is not provided, the areas of the light emitting areas PXA-R and PXA-G can be miniaturized, and thus a display panel DP that easily achieves high resolution can be provided.

[0138] Furthermore, when manufacturing a large-area display panel DP, a display panel DP can be provided which can reduce process costs by omitting production of a large-area mask and can improve process reliability by being free from defects that may occur in the large-area mask.

[0139] The recessed portion DEP may be formed in the partition wall PW. The recessed portion DEP may be recessed in a direction perpendicular to the upper surface of the base layer BL (or toward the base layer BL). In detail, the recessed portion DEP may be recessed in a direction opposite to the third direction DR3. The recessed portion DEP may be formed to completely pass through the partition wall PW. That is, the upper surface of the pixel defining film PDL may be exposed by the recessed portion DEP, and hereinafter, the bottom surface of the recessed portion DEP may refer to the upper surface of the pixel defining film PDL.

[0140] The recessed portion DEP may include a first recessed portion DEP1 and a second recessed portion DEP2 spaced apart from the first recessed portion DEP1 in the fourth direction DR4. The partition wall PW may be divided into first to third sub-partition walls SPW1, SPW2, and SPW3 by the first recessed portion DEP1 and the second recessed portion DEP2. As an example of the present disclosure, the first sub-partition wall SPW1 is provided in a closed loop form to surround the first light emitting area PXA-R, and the second sub-partition wall SPW2 is provided in a closed loop form to surround the second light emitting area PXA-G. The third sub-partition wall SPW3 is disposed between the first sub-partition wall SPW1 and the second sub-partition wall SPW2. The first recessed portion DEP1 is provided between the first sub-partition wall SPW1 and the third sub-partition wall SPW3, and the second recessed portion DEP2 is provided between the second sub-partition wall SPW2 and the third sub-partition wall SPW3. The third sub-partition wall SPW3 may be disposed between the first recessed portion DEP1 and the second recessed portion DEP2. The present disclosure is not limited to the above description, and the recessed portion DEP may include three or more recessed parts.

[0141] The display panel DP of the present disclosure may further include a bridging electrode BE disposed on the circuit element layer DP-CL. The bridging electrode BE may be covered by a pixel defining film PDL. As an example of the present disclosure, the bridging electrode BE is disposed at the same layer as the layer of the first anode AE1 and the second anode AE2. First to third contact holes CNT-1a, CNT-2a and CNT-3a exposing the bridging electrode BE are provided in the pixel defining film PDL. The bridging electrode BE may contact the first to third sub-partition walls SPW1, SPW2 and SPW3 through the first to third contact holes CNT-1a, CNT-2a and CNT-3a formed in the pixel defining film PDL. Therefore, the bridging electrode BE may electrically connect the first to third sub-partition walls SPW1, SPW2 and SPW3 spaced apart from each other.

[0142] The dummy patterns DMP1 and DMP2 may include a first dummy pattern DMP1 and a second dummy pattern DMP2. The first dummy pattern DMP1 may be disposed on the first sub-partition wall SPW1, and the second dummy pattern DMP2 may be disposed on the second sub-partition wall SPW2. The dummy patterns DMP1 and DMP2 may not be disposed on the third sub-partition wall SPW3.

[0143] The first dummy pattern DMP1 may include a (1-1)th dummy layer D11 and a (1-2)th dummy layer D12 disposed on the (1-1)th dummy layer D11. The (1-1)th dummy layer D11 and the (1-2)th dummy layer D12 may be disposed on the first sub-partition wall SPW1. The second dummy pattern DMP2 may include a (2-1)th dummy layer D21 and a (2-2)th dummy layer D22 disposed on the (2-1)th dummy layer D21. The (2-1)th dummy layer D21 and the (2-2)th dummy layer D22 may be disposed on the second sub-partition wall SPW2. The first dummy pattern DMP1 and the second dummy pattern DMP2 may surround the first light emitting region PXA-R and the second light emitting region PXA-G, respectively, on a plane.

[0144] The encapsulation layer TFE may include lower inorganic patterns (or inorganic patterns) LIL1 and LIL2 , an organic film OL, and an upper inorganic film UIL.

[0145] In an embodiment of the present disclosure, the lower inorganic patterns LIL1 and LIL2 may include first and second lower inorganic patterns LIL1 and LIL2. The first and second lower inorganic patterns LIL1 and LIL2 may be provided in a pattern form in which the first and second lower inorganic patterns LIL1 and LIL2 are spaced apart from each other.

[0146] The first and second lower inorganic patterns LIL1 and LIL2 may cover the first and second light emitting elements ED1 and ED2, respectively. In detail, the first and second lower inorganic patterns LIL1 and LIL2 may be disposed on the first and second cathodes CE1 and CE2 to cover the first and second cathodes CE1 and CE2, respectively.

[0147] According to an embodiment of the present disclosure, the first lower inorganic pattern LIL1 and the second lower inorganic pattern LIL2 may cover the side surface of the partition wall PW. In detail, the first lower inorganic pattern LIL1 may cover one side surface of the first sub-partition wall SPW1 defining the first recessed portion DEP1, and the second lower inorganic pattern LIL2 may cover one side surface of the second sub-partition wall SPW2 defining the second recessed portion DEP2.

[0148] In this way, when the partition wall PW includes the recessed portions DEP1 and DEP2, the length from the portion (i.e., the first portion) of the lower inorganic patterns LIL1 and LIL2 covering the light emitting elements ED1 and ED2 to the other portion (i.e., the second portion) of the lower inorganic patterns LIL1 and LIL2 arranged on the partition wall PW can be increased. When the length of the second portion of the lower inorganic patterns LIL1 and LIL2 increases, the moisture penetration path leading to the light emitting elements ED1 and ED2 can be increased. As a result, the light emitting elements ED1 and ED2 having improved process reliability and reduced defects by preventing moisture from penetrating into the light emitting elements ED1 and ED2 can be provided.

[0149] refer to Figure 6B The partition wall PW may be divided into first to third sub-partition walls SPW1, SPW2, and SPW3 by the first recessed portion DEP1 and the second recessed portion DEP2. The first to third sub-partition walls SPW1, SPW2, and SPW3 may be electrically connected to each other through a bridge electrode BE disposed on the circuit element layer DP-CL.

[0150] In a plan view, a first contact hole CNT-1a may be formed in a portion of the pixel defining film PDL that overlaps with the first sub-partition wall SPW1, a second contact hole CNT-2a may be formed in a portion of the pixel defining film PDL that overlaps with the second sub-partition wall SPW2, and a third contact hole CNT-3a may be formed in a portion of the pixel defining film PDL that overlaps with the third sub-partition wall SPW3. The first sub-partition wall SPW1 and the bridge electrode BE may be electrically connected to each other through the first contact hole CNT-1a, the second sub-partition wall SPW2 and the bridge electrode BE may be electrically connected to each other through the second contact hole CNT-2a, and the third sub-partition wall SPW3 and the bridge electrode BE may be electrically connected to each other through the third contact hole CNT-3a. As a result, the first to third sub-partition walls SPW1, SPW2, and SPW3 may be electrically connected to each other through the bridge electrode BE. According to an embodiment of the present disclosure, the third contact hole CNT-3a may be omitted. As a result, only the first sub-partition wall SPW1 and the second sub-partition wall SPW2 may be electrically connected to each other through the bridge electrode BE, and the third sub-partition wall SPW3 may not be electrically connected to the first sub-partition wall SPW1 and the second sub-partition wall SPW2. Figure 5 The transistor TR shown in the figure.

[0151] The first sub-partition wall SPW1 may include a first partition wall layer L1a and a second partition wall layer L2a sequentially stacked. The first partition wall layer L1a and the second partition wall layer L2a may be respectively Figure 51 and 2 are the same as the first partition wall layer L1 and the second partition wall layer L2 of the partition wall PW illustrated in FIG. The first partition wall layer L1a and the second partition wall layer L2a may respectively include a first side surface S_SL1a and a second side surface S_SL2a defining the first recessed portion DEP1. In a plan view, the first side surface S_SL1a of the first partition wall layer L1a may be further recessed than the second side surface S_SL2a of the second partition wall layer L2a in a direction away from the center of the first recessed portion DEP1. That is, in a plan view, the second partition wall layer L2a may form an end portion protruding toward the center of the first recessed portion DEP1 relative to the first partition wall layer L1a.

[0152] The second sub-partition wall SPW2 may include a first partition wall layer L1b and a second partition wall layer L2b sequentially stacked. The first partition wall layer L1b and the second partition wall layer L2b may be Figure 5 The first partition wall layer L1 and the second partition wall layer L2 of the partition wall PW illustrated in the figure are the same. The first partition wall layer L1b and the second partition wall layer L2b may respectively include a first side surface S_SL1b and a second side surface S_SL2b defining the first recessed portion DEP1. In a plan view, the first side surface S_SL1b of the first partition wall layer L1b may be further recessed than the second side surface S_SL2b of the second partition wall layer L2b in a direction away from the center of the second recessed portion DEP2. That is, the second partition wall layer L2b may form an end portion protruding toward the center of the second recessed portion DEP2 relative to the first partition wall layer L1b.

[0153] The third sub-partition wall SPW3 may include a first partition wall layer L1c and a second partition wall layer L2c stacked sequentially. The first partition wall layer L1c and the second partition wall layer L2c of the third sub-partition wall SPW3 may be formed in the same manner as the first partition wall layer L1a and the second partition wall layer L2a of the first sub-partition wall SPW1, and may contain the same material as the first partition wall layer L1a and the second partition wall layer L2a. In addition, the first partition wall layer L1c and the second partition wall layer L2c of the third sub-partition wall SPW3 may be formed in the same manner as the first partition wall layer L1b and the second partition wall layer L2b of the second sub-partition wall SPW2, and may contain the same material as the first partition wall layer L1b and the second partition wall layer L2b.

[0154] The first dummy pattern DMP1 may be disposed on the second partition wall layer L2a of the first sub-partition wall SPW1. The first dummy pattern DMP1 may include a metal material. Since the first dummy pattern DMP1 is formed on the second partition wall layer L2a, when moisture penetrates into the first light emitting element ED1 (see FIG. 1 ), the first dummy pattern DMP1 may be disposed on the second partition wall layer L2a. Fig. 6A), moisture or the like undergoes an oxidation reaction with the metal material, and thus it is possible to prevent moisture from penetrating into the first light emitting element ED1.

[0155] The second dummy pattern DMP2 may be disposed on the second partition wall layer L2b of the second sub-partition wall SPW2. The second dummy pattern DMP2 may include a metal material. Since the second dummy pattern DMP2 is formed on the second partition wall layer L2b, when moisture penetrates into the second light emitting element ED2 (see FIG. 1 ), the second dummy pattern DMP2 may be disposed on the second partition wall layer L2b. Fig. 6A ), moisture or the like undergoes an oxidation reaction with the metal material, and thus it is possible to prevent moisture from penetrating into the second light emitting element ED2.

[0156] According to an embodiment of the present disclosure, a first open area OPA1 may be defined between a bottom surface of the first recessed portion DEP1 and the first lower inorganic pattern LIL1, and a portion of a side surface of the first sub-partition wall SPW1 may be exposed through the first open area OPA1. In detail, a portion of the first side surface S_SL1a of the first partition wall layer L1a adjacent to the bottom surface of the first recessed portion DEP1 may be exposed through the first open area OPA1. According to an embodiment of the present disclosure, a second open area OPA2 may be defined between a bottom surface of the second recessed portion DEP2 and the second lower inorganic pattern LIL2, and a portion of a side surface of the second sub-partition wall SPW2 may be exposed through the second open area OPA2. In detail, a portion of the first side surface S_SL1b of the first partition wall layer L1b adjacent to the bottom surface of the second recessed portion DEP2 may be exposed through the second open area OPA2. The first open area OPA1 and the second open area OPA2 are areas in which dummy patterns are initially formed, and may be formed by Fig. 6A ) by removing the dummy pattern in the process.

[0157] Figure 7 According to another embodiment Fig. 6A An enlarged view of the region AA' illustrated in FIG. A description repeated with the above description will be omitted.

[0158] refer to Figure 7 , a recessed portion DEPa may be formed in the partition wall PWa. According to an embodiment of the present disclosure, a single recessed portion DEPa may be formed in the partition wall PWa. Since a single recessed portion DEPa is formed in the partition wall PWa, the partition wall PWa may include a first sub-partition wall SPW1a and a second sub-partition wall SPW2a. That is, the first sub-partition wall SPW1a and the second sub-partition wall SPW2a may be separated by the recessed portion DEPa. Figure 6B Compared with the partition wall PW of FIG. 1 , the partition wall PWa according to the embodiment may not include the third sub-partition wall SPW3 .

[0159] The first sub-partition wall SPW1a may include a first partition wall layer L1c and a second partition wall layer L2c stacked sequentially. The first partition wall layer L1c may include a first side surface S_SL1c, and the second partition wall layer L2c may include a second side surface S_SL2c. The second sub-partition wall SPW2a may include a first partition wall layer L1d and a second partition wall layer L2d stacked sequentially. The first partition wall layer L1d may include a first side surface S_SL1d, and the second partition wall layer L2d may include a second side surface S_SL2d. The first side surface S_SL1c of the first partition wall layer L1c and the second side surface S_SL2c of the second partition wall layer L2c may correspond to one side surface of the defined recessed portion DEPa of the first sub-partition wall SPW1a, and the first side surface S_SL1d of the first partition wall layer L1d and the second side surface S_SL2d of the second partition wall layer L2d may correspond to one side surface of the defined recessed portion DEPa of the second sub-partition wall SPW2a.

[0160] The first lower inorganic pattern LIL1 may cover one side surface of the first sub-partition wall SPW1 a defining the recessed portion DEPa, and the second lower inorganic pattern LIL2 may cover one side surface of the second sub-partition wall SPW2 a defining the recessed portion DEPa.

[0161] The recessed portion DEPa may include a structure surrounding the light emitting elements ED1 and ED2 on a plane. That is, the recessed portion DEPa may include an integrally formed structure surrounding the light emitting elements ED1 and ED2. The recessed portion DEPa may be disposed in the peripheral area NPXA (see Figure 4 )middle.

[0162] Figure 8 According to yet another embodiment Fig. 6A An enlarged view of region AA' is shown in FIG.

[0163] refer to Figure 8, a first recessed portion DEP1b and a second recessed portion DEP2b may be defined in the partition wall PWb. According to an embodiment of the present disclosure, a thickness Th1 of the partition wall PWb may be greater than each of a depth T2a of the first recessed portion DEP1b and a depth T2b of the second recessed portion DEP2b. In detail, the partition wall PWb may include a first partition wall layer L1e and a second partition wall layer L2e stacked sequentially. The sum of the thicknesses of the first partition wall layer L1e and the second partition wall layer L2e in the third direction DR3 may be greater than each of a depth T2a of the first recessed portion DEP1b and a depth T2b of the second recessed portion DEP2b. The depth T2a of the first recessed portion DEP1b and the depth T2b of the second recessed portion DEP2b may be the same. However, the present disclosure is not limited thereto, and the depth T2a of the first recessed portion DEP1b and the depth T2b of the second recessed portion DEP2b may be different from each other.

[0164] Since the thickness Th1 of the partition wall PWb is greater than each of the depth T2a of the first recessed portion DEP1b and the depth T2b of the second recessed portion DEP2b, the partition wall PWb includes one first partition wall layer L1e, but may include a plurality of second partition wall layers L2e separated by the recessed portion DEPb. In this case, no second partition wall layer L2e may be provided. Fig. 6A In addition, the first cathode CE1 and the second cathode CE2 (see Fig. 6A ) may be in contact with the partition wall PWb, may be electrically connected to each other, and thus may receive a common voltage.

[0165] FIG. 9A to FIG. 9K are cross-sectional views illustrating some of the operations of a method of manufacturing a display panel according to an embodiment of the present disclosure. FIG. 9A to FIG. 9K In the description of the method for manufacturing a display panel, the same / similar reference numerals are used in FIGS. Figure 8 The same / similar components described in the drawings will be referred to herein and their repeated description will be omitted.

[0166] refer to Fig.9A The method for manufacturing a display panel according to an embodiment of the present disclosure may include an operation of providing a preliminary display panel DP-P. The preliminary display panel DP-P provided in the embodiment may include a base layer BL, a circuit element layer DP-CL, an anode AE, a sacrificial pattern SP, and a bridge electrode BE. In another embodiment, the preliminary display panel DP-P may further include: Fig. 9B The preliminary pixel defining film PDL-P shown in FIG.

[0167] The circuit element layer DP-CL can be formed by a general method for manufacturing circuit elements, wherein an insulating layer, a semiconductor layer and a conductive layer are formed by a coating method or a deposition method, and the insulating layer, the semiconductor layer and the conductive layer are selectively patterned by photolithography and etching processes to form a semiconductor pattern, a conductive pattern or a signal line, etc.

[0168] The anode AE ​​and the sacrificial pattern SP may be formed by the same patterning process. The bridge electrode BE may be formed by the same process as the anode AE. Although not shown, the anode AE ​​and the bridge electrode BE may be separated by a patterning process of a metal integrally formed.

[0169] refer to Fig. 9B A preliminary pixel defining film PDL-P may be formed on the circuit element layer DP-CL. The preliminary pixel defining film PDL-P may cover all of the anode AE, the bridge electrode BE, and the sacrificial pattern SP. A contact hole CNT may be formed in the preliminary pixel defining film PDL-P, and a portion of the bridge electrode BE is exposed through the contact hole CNT.

[0170] Afterwards, refer to Fig. 9C , a preliminary partition wall PW-P including a first partition wall layer L1 and a second partition wall layer L2 may be formed on the preliminary pixel defining film PDL-P. The operation of forming the preliminary partition wall PW-P may include an operation of forming the first partition wall layer L1 including a conductive material on the preliminary pixel defining film PDL-P and an operation of forming the second partition wall layer L2 including an inorganic material on the first partition wall layer L1. The second partition wall layer L2 may also include a conductive material.

[0171] The operation of forming the first partition wall layer L1 may be performed by a process of depositing a conductive material. In an embodiment of the present disclosure, the conductive material may include a metal. In detail, the first partition wall layer L1 may include aluminum (Al). For example, the operation of forming the first partition wall layer L1 may be performed by a sputtering deposition process.

[0172] The operation of forming the second partition wall layer L2 may be performed by a process of depositing an inorganic material. In an embodiment of the present disclosure, the second partition wall layer L2 may include silicon nitride (SiN x ), silicon oxide (SiO 2 ), silicon oxynitride (SiON) and aluminum oxide (Al 2 O 3 The operation of forming the second partition wall layer L2 may be performed by a chemical vapor deposition (“CVD”) process or an atomic layer deposition (“ALD”) process.

[0173] Afterwards, refer to Fig. 9C and Fig.9D, an operation of forming a first photoresist layer PR1 on the preliminary partition wall PW-P may be performed. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary partition wall PW-P and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, a first optical opening OP-PR1 overlapping the anode AE ​​in a plan view and a second optical opening OP-PR2 overlapping the bridge electrode BE may be formed in the first photoresist layer PR1.

[0174] Afterwards, refer to Fig.9E and Fig.9F , an operation of forming a pixel opening (or opening) POP overlapping with the anode AE ​​in a plan view and a recessed portion DEP spaced apart from the pixel opening POP in a first direction DR1 in the preliminary partition wall PW-P may be performed. The operation of forming the pixel opening POP and the recessed portion DEP may include an operation of patterning the preliminary partition wall PW-P. That is, the first photoresist layer PR1 may be used as a mask, the preliminary partition wall PW-P that does not overlap with the first photoresist layer PR1 in a plan view may be first etched, and thus a preliminary pixel opening POP-P and a preliminary recessed portion DEP-P may be formed. The first etching operation may be performed by a dry etching process. The side surface of the preliminary partition wall PW-P that defines the preliminary pixel opening POP-P and the preliminary recessed portion DEP-P may be formed parallel to the third direction DR3.

[0175] Thereafter, the preliminary pixel opening POP-P and the preliminary recessed portion DEP-P may be secondary etched. The secondary etching operation may be performed in an environment where the etching selectivity between the first partition wall layer L1 and the second partition wall layer L2 is high. In detail, the first photoresist layer PR1 is used as a mask, an operation of patterning the side surface of the preliminary partition wall PW-P defining the preliminary pixel opening POP-P and the preliminary recessed portion DEP-P is performed, and thus the partition wall PW may be formed.

[0176] Since the etching rate of the second partition wall layer L2 with respect to the etching solution is greater than the etching rate of the first partition wall layer L1 with respect to the etching solution, the first partition wall layer L1 can be mainly etched. Accordingly, the first partition wall layer L1 and the second partition wall layer L2 can respectively include a first side surface S_L1a and a second side surface S_L2a defining the pixel opening POP. In addition, the first partition wall layer L1 and the second partition wall layer L2 can respectively include a first side surface S_L1b and a second side surface S_L2b defining the recessed portion DEP. In a plan view, the first side surface S_L1a defining the pixel opening POP can be further recessed inward than the second side surface S_L2a, and in a plan view, the first side surface S_L1b defining the recessed portion DEP can be further recessed inward than the second side surface S_L2b.

[0177] refer to Figure 9G , an operation of etching the preliminary pixel defining film PDL-P to form the pixel defining film PDL may be performed. The process of etching the preliminary pixel defining film PDL-P may be performed using a dry etching method, and may be performed using the second photoresist layer PR2 as a mask. A light emitting opening OP-E may be formed in the pixel defining film PDL. Thereafter, an operation of etching a sacrificial pattern SP may be performed. The process of etching the sacrificial pattern SP may be performed using a dry etching method, and may be performed using the second photoresist layer PR2 as a mask.

[0178] A sacrificial opening OP-S corresponding to the light emitting opening OP-E may be formed in the sacrificial pattern SP. At least a portion of the anode AE ​​may be exposed from the sacrificial pattern SP and the pixel defining film PDL through the sacrificial opening OP-S and the light emitting opening OP-E.

[0179] The process of etching the sacrificial pattern SP may be performed in an environment where the etching selectivity between the sacrificial pattern SP and the anode AE ​​is high, and thus the anode AE ​​may be prevented from being etched together. That is, the sacrificial pattern SP having a greater etching rate than that of the anode AE ​​is disposed between the pixel defining film PDL and the anode AE, and thus the anode AE ​​may be prevented from being etched together and damaged in the etching process.

[0180] Afterwards, refer to Figure 9H , the second photoresist layer PR2 (see Figure 9G ) thereafter, an operation of forming the light emitting pattern EP and an operation of forming the cathode CE are performed.

[0181] The operation of forming the light emitting pattern EP and the operation of forming the cathode CE may be performed by a deposition process. In one embodiment, the operation of forming the light emitting pattern EP may be performed by a thermal evaporation process, and the operation of forming the cathode CE may be performed by a sputtering process.

[0182] In the operation of forming the light emitting pattern EP, the light emitting pattern EP may be separated by the end portion TP formed on the first side surface S_L1a and the second side surface S_L2a defining the pixel opening POP, and may be disposed inside the light emitting opening OP-E. In the operation of forming the light emitting pattern EP, the first dummy layer D1 spaced apart from the light emitting pattern EP may be formed together on the second partition wall layer L2. In addition, the first dummy layer D1 may be formed inside the recessed portion DEP.

[0183] In the operation of forming the cathode CE, the cathode CE may be separated by an end portion TP formed on a first side surface S_L1a and a second side surface S_L2a defining a pixel opening POP, and may be disposed inside the light emitting opening OP-E. The cathode CE may be provided at a high input angle compared to the light emitting pattern EP, and thus the cathode CE may be formed to contact the first side surface S_L1a of the first partition wall layer L1. In the operation of forming the cathode CE, a second dummy layer D2 spaced apart from the cathode CE may be formed together on the second partition wall layer L2. The second dummy layer D2 may be disposed on the first dummy layer D1. In addition, the second dummy layer D2 may also be formed inside the recessed portion DEP. The anode AE, the light emitting pattern EP, and the cathode CE may constitute a light emitting element ED.

[0184] Thereafter, although not shown, an operation of forming a capping pattern on the cathode CE may be added. In this case, similar to the cathode CE, the capping pattern may be separated by the terminal portion TP and formed as a dummy pattern on the second partition wall layer L2.

[0185] refer to Fig.9I and Figure 9J , a step of forming a lower inorganic pattern LIL may be performed.

[0186] refer to Fig.9I , an inorganic layer LIL-P may be formed to cover the light emitting element ED and the partition wall PW. The inorganic layer LIL-P may be formed by a deposition process. In one embodiment, the inorganic layer LIL-P may include, for example, silicon nitride (SiN x ) of an inorganic material. For example, the inorganic layer LIL-P can be formed by a CVD process.

[0187] The inorganic layer LIL-P may cover the light emitting element ED. In addition to the light emitting element ED, the inorganic layer LIL-P may be disposed in the recessed portion DEP. In detail, the inorganic layer LIL-P may cover the first side surface S_L1a and the second side surface S_L2a defining the pixel opening POP in the pixel opening POP, and may cover the first side surface S_L1b and the second side surface S_L2b defining the recessed portion DEP in the recessed portion DEP.

[0188] Afterwards, refer to Figure 9J , an operation of forming a third photoresist layer PR3 and an operation of forming a lower inorganic pattern LIL may be performed. In the operation of forming the third photoresist layer PR3, the third photoresist layer PR3 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the third photoresist layer PR3 may be formed into a pattern shape that does not overlap with the recessed portion DEP in a plan view.

[0189] The operation of forming the lower inorganic pattern LIL may include the operation of patterning the inorganic layer LIL-P. In the operation of patterning the inorganic layer LIL-P, the inorganic layer LIL-P may be patterned by dry etching so that the portion of the inorganic layer LIL-P overlapping with the recessed portion DEP in a plan view is removed. A portion of the lower inorganic pattern LIL may be disposed inside the pixel opening POP and cover the light emitting element ED, and the other portion of the lower inorganic pattern LIL may be formed to cover the portion of the first side surface S_L1b and the second side surface S_L2b defining the recessed portion DEP. After the operation of forming the lower inorganic pattern LIL, the sub-dummy pattern S-DMP may remain in the recessed portion DEP. In the operation of forming the lower inorganic pattern LIL, the third photoresist layer PR3 is formed and patterned on the portion (i.e., the first partition wall layer L1 and the light emitting element ED) that does not overlap the recessed portion DEP spaced apart from the light emitting element ED in a plan view, and thus the light emitting element ED may be prevented from being damaged in the process.

[0190] Afterwards, refer to Figure 9K , the method may include removing the sub-dummy pattern S-DMP, then forming an organic film OL and an upper inorganic film UIL and thus completing the operation of the display panel DP. The organic film OL may be formed by applying an organic material by an inkjet method, but the present disclosure is not limited thereto. The organic film OL provides a flat upper surface. Thereafter, the upper inorganic film UIL may be formed by depositing an inorganic material. Thus, a display panel including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED (see, for example, Figure 5 ) and encapsulation layer TFE (see e.g. Figure 5 ) display panel DP.

[0191] According to the present disclosure, since a patterned light emitting pattern may be provided without using a metal mask, a display panel having improved process reliability and easily achieving high resolution may be provided.

[0192] The partition wall included in the display panel according to the present disclosure may include a recessed portion. Since the inorganic pattern covering the light-emitting element is formed to cover one side surface of the partition wall defining the recessed portion, the moisture penetration path leading to the light-emitting element can be increased. As a result, a light-emitting element having improved process reliability and reduced defects by preventing moisture from penetrating into the light-emitting element can be provided.

[0193] Although the above description has been made with reference to the embodiments of the present disclosure, it will be appreciated that persons skilled in the art or persons having ordinary knowledge in the art may make various modifications and changes to the present disclosure without departing from the spirit and technical scope of the present disclosure described in the appended claims.

[0194] Therefore, the technical scope of the present disclosure is not limited to the detailed description of the specification, but should be defined by the appended claims.

Claims

1. A display panel, comprising: Basal layer; A plurality of light emitting elements are arranged on the base layer; a partition wall disposed between the plurality of light emitting elements and configured to electrically connect electrodes of the plurality of light emitting elements; as well as a plurality of inorganic patterns arranged on the plurality of light emitting elements, wherein a recessed portion recessed in a direction toward the base layer is defined in the partition wall, and Each of the plurality of inorganic patterns is disposed on the partition wall and covers a first side surface of the partition wall defining the recessed portion. 2 . The display panel according to claim 1 , wherein the partition wall comprises a first sub-partition wall and a second sub-partition wall, the first sub-partition wall and the second sub-partition wall are spaced apart from each other, and the recessed portion is between the first sub-partition wall and the second sub-partition wall.

3. The display panel according to claim 2, further comprising: The dummy pattern is disposed between the partition wall and the inorganic pattern.

4. The display panel according to claim 3, wherein the dummy pattern comprises: a first dummy pattern, arranged on the first sub-partition wall; as well as The second dummy pattern is arranged on the second sub-partition wall. The display panel of claim 3 , wherein the recessed portion comprises a first recessed portion and a second recessed portion spaced apart from each other. 6 . The display panel of claim 5 , wherein the partition wall further comprises a third sub-partition wall disposed between the first concave portion and the second concave portion. 7 . The display panel of claim 6 , wherein the dummy pattern is not disposed on the third sub-partition wall.

8. The display panel according to claim 2, further comprising: The bridge electrode is configured to electrically connect the first sub-partition wall and the second sub-partition wall.

9. The display panel according to claim 8, wherein each of the plurality of light emitting elements comprises the electrode electrically connected to the partition wall and a first electrode provided on the base layer, and The bridge electrode and the first electrode are arranged on the same layer.

10. The display panel according to claim 9, further comprising: a pixel defining film, in which a light emitting opening is defined, and is disposed on the base layer, wherein a portion of the first electrode is exposed through the light emitting opening, A first contact hole and a second contact hole are defined in the pixel defining film, wherein the first contact hole is configured to electrically connect the first sub-partition wall and the bridge electrode, and the second contact hole is configured to electrically connect the second sub-partition wall and the bridge electrode.

11. The display panel according to claim 1, wherein each of the plurality of light emitting elements comprises: A first electrode, disposed on the base layer; A light-emitting layer is disposed on the first electrode; as well as A second electrode is disposed on the light-emitting layer; The display panel further comprises: a pixel defining film, in which a light emitting opening is defined, and is disposed on the base layer, wherein a portion of the first electrode is exposed through the light emitting opening, and The second electrode is the electrode electrically connected to the partition wall.

12. The display panel according to claim 11, wherein the partition wall comprises: A first partition wall layer is disposed on the pixel definition film; as well as a second partition wall layer disposed on the first partition wall layer, and A second side surface of the first partition wall layer close to the light emitting opening is further recessed than a third side surface of the second partition wall layer close to the light emitting opening in a direction away from the light emitting opening. 13 . The display panel according to claim 12 , wherein the second electrode is in direct contact with the first partition wall layer. The display panel according to claim 1 , wherein a depth of the recessed portion is smaller than a thickness of the partition wall. 15 . The display panel of claim 1 , wherein an open area is defined between a bottom surface of the recessed portion and the inorganic pattern, and a portion of the first side surface of the partition wall is exposed through the open area.

16. A method for manufacturing a display panel, the method comprising: Providing a preliminary display panel, the preliminary display panel comprising a base layer, a first electrode disposed on the base layer, and a preliminary pixel defining film disposed on the base layer and configured to cover the first electrode; forming a preliminary partition wall on the preliminary pixel definition film; patterning the preliminary partition wall to form a partition wall in which a recessed portion recessed in a direction toward the base layer is defined, and the partition wall has conductivity; forming a light-emitting layer on the first electrode; forming a second electrode electrically connected to the partition wall on the light emitting layer; as well as forming an inorganic pattern on a portion of the partition wall and the second electrode, The inorganic pattern is disposed on the partition wall and covers one side surface of the partition wall defining the recessed portion.

17. The method according to claim 16, wherein the partition wall comprises a first sub-partition wall and a second sub-partition wall, the first sub-partition wall and the second sub-partition wall are spaced apart from each other, and the recessed portion is between the first sub-partition wall and the second sub-partition wall, The preliminary display panel further includes a bridging electrode disposed on the base layer and configured to electrically connect the first sub-partition wall and the second sub-partition wall, and The bridge electrode is formed in the same process as that of forming the first electrode.

18. The method according to claim 17, further comprising: Before the forming of the preliminary partition wall, a contact hole is formed in the preliminary pixel defining film, the contact hole being configured to electrically connect the preliminary partition wall and the bridge electrode.

19. The method according to claim 16, wherein the forming the inorganic pattern comprises: forming an inorganic layer on the second electrode and the partition wall; as well as The inorganic pattern is formed by patterning the inorganic layer so that the inorganic layer does not overlap at least a portion of the recessed portion.

20. The method according to any one of claims 16 to 18, further comprising: forming an opening in the preliminary partition wall so as to overlap with the first electrode, The opening and the recessed portion are formed simultaneously.

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