Display substrate and display device

Abstract

The display substrate provided by the embodiment of the invention is beneficial to realizing narrowing of a frame. The display substrate comprises a substrate, and a circuit structure layer and a light-emitting structure layer which are sequentially arranged on the substrate. The display area comprises a first display area and a second display area which are arranged in the first direction, and the second display area is located between the first display area and the first frame area in the first direction. The circuit structure layer comprises a plurality of pixel circuits located in the first display area, a plurality of multiplexing circuits located in the second display area and a plurality of data lines located in the display area; the plurality of data lines are connected to the plurality of pixel circuits and the plurality of multiplexing circuits. The light-emitting structure layer comprises a plurality of light-emitting elements located in the display area. The at least one pixel circuit is connected with the at least one light-emitting element, and orthographic projections of the at least one light-emitting element and the connected pixel circuit on the substrate are arranged in a staggered manner along a first direction; the orthographic projections of the plurality of multiplexing circuits on the substrate are at least partially overlapped with the orthographic projections of the plurality of light-emitting elements on the substrate.

Description

Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] This embodiment provides a display substrate and a display device.

[0005] On the one hand, this embodiment provides a display substrate, comprising: a substrate, a circuit structure layer and a light-emitting structure layer sequentially arranged on the substrate. The substrate comprises a display area and a first frame area located at least on one side of the display area, and the display area comprises: a first display area and a second display area arranged along a first direction, and the second display area is located between the first display area and the first frame area along the first direction. The circuit structure layer comprises: a plurality of pixel circuits located in the first display area, a plurality of multiplexing circuits located in the second display area, and a plurality of data lines located in the display area; the plurality of data lines are connected to the plurality of pixel circuits and the plurality of multiplexing circuits. The light-emitting structure layer comprises: a plurality of light-emitting elements located in the display area; at least one pixel circuit among the plurality of pixel circuits is connected to at least one light-emitting element among the plurality of light-emitting elements, and the orthographic projection of the at least one light-emitting element and the connected pixel circuit on the substrate is staggered along the first direction; the orthographic projection of the plurality of multiplexing circuits on the substrate at least partially overlaps with the orthographic projection of the plurality of light-emitting elements located in the second display area on the substrate.

[0006] In some exemplary embodiments, an orthographic projection of at least one of the plurality of light emitting elements on the substrate is located on a side of an orthographic projection of a connected pixel circuit on the substrate close to the first frame region.

[0007] In some exemplary embodiments, an orthographic projection of a light emitting region of at least one of the plurality of light emitting elements on the substrate does not overlap with an orthographic projection of a connected pixel circuit on the substrate.

[0008] In some exemplary embodiments, the plurality of light-emitting elements include: a plurality of light-emitting element groups, the plurality of light-emitting element groups are arrayed along the first direction and a second direction, the second direction intersecting the first direction; at least one of the plurality of light-emitting element groups includes: a first light-emitting element emitting a first color light, a second light-emitting element emitting a second color light, and a third light-emitting element emitting a third color light. In a single light-emitting element group, the first light-emitting element and the second light-emitting element are aligned and arranged along the first direction, and are located on the same side of the third light-emitting element along the second direction.

[0009] In some exemplary embodiments, the at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode arranged in sequence along a direction away from the substrate; the first electrode is connected to the corresponding pixel circuit through a first conversion electrode; the first conversion electrode and the multiple data lines are in the same layer structure, and the first conversion electrode extends along the first direction.

[0010] In some exemplary embodiments, the circuit structure layer also includes: a plurality of first power lines located in the display area; the plurality of first power lines extend along the first direction and are arranged along a second direction, and the second direction intersects with the first direction; the plurality of first power lines are connected to the plurality of pixel circuits, and the plurality of first power lines and the plurality of data lines are in the same layer structure.

[0011] In some exemplary embodiments, the circuit structure layer also includes: a first border power line located in the second display area, the first border power line being located along the first direction on a side of the multiple multiplexing circuits close to the multiple pixel circuits; the first border power line extending along the second direction and connected to the multiple first power lines.

[0012] In some exemplary embodiments, the first frame power line is located on a side of the plurality of first power lines close to the substrate.

[0013] In some exemplary embodiments, the circuit structure layer further includes: a plurality of first gaskets located in the second display area, the first gaskets and the first power line being an integral structure. The at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode sequentially arranged in a direction away from the substrate; the orthographic projection of the first electrode of the at least one light-emitting element on the substrate at least partially overlaps with the orthographic projection of the first gasket on the substrate.

[0014] In some exemplary embodiments, the at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode sequentially arranged in a direction away from the substrate. In the second display area, the first electrode of the at least one light-emitting element overlaps with the orthographic projections of the two first power lines on the substrate, and the orthographic projections of the edges of the first electrode extending along the first direction on the substrate at least partially overlap with the orthographic projections of the two first power lines on the substrate.

[0015] In some exemplary embodiments, the first frame area includes: a first sub-frame area extending along a second direction, and a first corner area and a second corner area located at both ends of the first sub-frame area along the second direction; the second direction intersects the first direction. The second display area includes: a sub-display area extending along the second direction, and a first corner display area and a second corner display area located at both sides of the sub-display area along the second direction; the first corner display area is connected to the first corner area and the first display area, and the second corner display area is connected to the second corner area and the first display area.

[0016] In some exemplary embodiments, the circuit structure layer also includes: a plurality of first signal lines connected to the plurality of pixel circuits and extending along the second direction, and a plurality of connecting lines connected to the plurality of first signal lines, and an orthographic projection of a plurality of multiplexing circuits located in the first corner display area and the second corner display area on the substrate overlaps with an orthographic projection of at least one of the plurality of connecting lines on the substrate.

[0017] In some exemplary embodiments, the circuit structure layer further includes: a plurality of multiplexed data lines. At least one of the plurality of multiplexed circuits includes: nine multiplexed control transistors, the gates of the nine multiplexed control transistors are connected to nine different multiplexed control lines, the first electrodes of the nine multiplexed control transistors are connected to the same multiplexed data line, and the second electrodes of the nine multiplexed control transistors are connected to different data lines; in the sub-display area, the nine multiplexed control transistors of the at least one multiplexed circuit are arranged in sequence along the second direction.

[0018] In some exemplary embodiments, at least one pixel circuit among the plurality of pixel circuits includes: a driving transistor, a compensation transistor, and a data writing transistor. The gate of the driving transistor is connected to the second electrode of the compensation transistor, the first electrode of the driving transistor is connected to the second electrode of the data writing transistor, and the second electrode of the driving transistor is connected to the first electrode of the compensation transistor; the first electrode of the data writing transistor is connected to the data line, the gate of the data writing transistor is connected to the first scan line, and the gate of the compensation transistor is connected to the second scan line. The transistor type of the compensation transistor is different from the transistor type of the driving transistor and the data writing transistor.

[0019] In some exemplary embodiments, the at least one pixel circuit further includes: a first reset transistor, a second reset transistor, and a third reset transistor. The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the second electrode of the driving transistor; the gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the first electrode of the light-emitting element; the gate of the third reset transistor is connected to the second reset control line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the first electrode of the driving transistor. The first reset control line and the second reset control line are in the same layer structure, and the first initial signal line, the second initial signal line, and the third initial signal line are located in different conductive layers.

[0020] In some exemplary embodiments, the at least one pixel circuit also includes: a first light-emitting control transistor and a second light-emitting control transistor; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting element.

[0021] On the other hand, this embodiment provides a display device, including the display substrate as mentioned above.

[0022] Other features and advantages of the present application will be described in the following description, and partly become apparent from the description, or be understood by implementing the present application. Other advantages of the present application can be realized and obtained by the schemes described in the description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0024] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure;

[0026] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided;

[0027] Figure 4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure;

[0028] Figure 5 for Figure 1 A partial enlarged schematic diagram of the middle area S1;

[0029] Figure 6 for Figure 1 A partial enlarged schematic diagram of the middle area S2;

[0030] Figure 7 for Figure 1 A partial enlarged schematic diagram of the middle area S3;

[0031] Fig. 8A for Figure 5 A schematic diagram of a first semiconductor layer in FIG.

[0032] Figure 8B for Figure 6 A schematic diagram of a first semiconductor layer in FIG.

[0033] Figure 8C for Figure 7 A schematic diagram of a first semiconductor layer in FIG.

[0034] Fig.9A for Figure 5 A schematic diagram of a display substrate after forming a first conductive layer;

[0035] Fig. 9B for Fig.9A A schematic diagram of a first conductive layer in FIG.

[0036] Fig. 9C for Figure 6 A schematic diagram of a display substrate after forming a first conductive layer;

[0037] Fig.9D for Figure 7 A schematic diagram of a display substrate after forming a first conductive layer;

[0038] Fig. 10A for Figure 5 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0039] Fig. 10B for Fig. 10A A schematic diagram of a second conductive layer in FIG.

[0040] Fig. 10C for Figure 6 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0041] Fig. 10D for Figure 7 A schematic diagram of a display substrate after a second conductive layer is formed in FIG.

[0042] Fig.11A for Figure 5 A schematic diagram of a display substrate in which a second semiconductor layer is formed;

[0043] Fig. 11B for Figure 6 A schematic diagram of a display substrate after forming a second semiconductor layer;

[0044] Fig. 12A for Figure 5 A schematic diagram of a display substrate after a third conductive layer is formed;

[0045] Fig. 12B for Figure 6 A schematic diagram of a display substrate after a third conductive layer is formed;

[0046] Fig.13A for Figure 5 A schematic diagram of a display substrate after a fifth insulating layer is formed;

[0047] Fig. 13B for Figure 6 A schematic diagram of a display substrate after a fifth insulating layer is formed;

[0048] Fig. 13C for Figure 7 A schematic diagram of a display substrate after a fifth insulating layer is formed;

[0049] Fig.14A for Figure 5 A schematic diagram of a display substrate after a fourth conductive layer is formed;

[0050] Fig. 14B for Fig.14A A schematic diagram of a fourth conductive layer in FIG.

[0051] Fig. 14C for Figure 6 A schematic diagram of a display substrate after a fourth conductive layer is formed;

[0052] Fig.14D for Fig. 14C A schematic diagram of a fourth conductive layer in FIG.

[0053] Fig.14E for Figure 7 A schematic diagram of a display substrate after a fourth conductive layer is formed;

[0054] Fig.15A for Figure 5 A schematic diagram of a display substrate after a sixth insulating layer is formed in FIG.

[0055] Fig. 15B for Figure 6 A schematic diagram of a display substrate after a sixth insulating layer is formed in FIG.

[0056] Fig.16A for Figure 5 A schematic diagram of a display substrate after a fifth conductive layer is formed in FIG.

[0057] Fig. 16B for Fig.16A A schematic diagram of a fifth conductive layer in FIG.

[0058] Fig. 16C for Figure 6 A schematic diagram of a display substrate after a fifth conductive layer is formed;

[0059] Fig.16D for Fig. 16C A schematic diagram of a fifth conductive layer in FIG.

[0060] Fig.16E for Figure 7 A schematic diagram of a display substrate after a fifth conductive layer is formed in FIG.

[0061] Fig.17 for Figure 5 A schematic diagram of a display substrate after a seventh insulating layer is formed;

[0062] Fig.18A for Figure 5 A schematic diagram of a display substrate after an anode layer is formed;

[0063] Fig.18B for Fig.18A Schematic diagram of the anode layer and the fifth conductive layer in FIG.

[0064] Fig.18C for Figure 7 A schematic diagram of a display substrate after an anode layer is formed;

[0065] Fig.19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0066] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. The embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0067] In the drawings, the size of one or more components, the thickness of a layer, or an area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to the size, and the shape and size of one or more components in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0068] The ordinal numbers such as "first", "second", and "third" in this specification are provided to avoid confusion of constituent elements, and are not intended to limit the quantity. The "plurality" in this disclosure means two or more.

[0069] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the orientation of the constituent elements being described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the circumstances.

[0070] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal connection of two elements. For ordinary technicians in this field, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "connection" may include "electrical connection", and "electrical connection" may include the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.

[0071] In this specification, a transistor refers to an element including at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region where current mainly flows.

[0072] In this specification, the first electrode may be a drain electrode, the second electrode may be a source electrode, or the first electrode may be a source electrode, the second electrode may be a drain electrode. In addition, the gate electrode may also be referred to as a control electrode. In the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0073] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0074] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0075] In this specification, "about" and "substantially" mean that the limits are not strictly defined and the situation within the range of process and measurement errors is allowed. In this disclosure, "same" may include the situation where the numerical value differs by less than 10%.

[0076] In this specification, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, line segment or strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" means "the main part of A extends along direction B".

[0077] In this specification, "A and B are of the same layer structure" means that A and B are formed simultaneously by the same patterning process. "The same layer" does not always mean that the thickness of the layer or the height of the layer is the same in the cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection range of A, or the orthographic projection of A covers the orthographic projection of B.

[0078] In order to better meet people's needs for multiple functions and a better screen experience (for example, a display with an ultra-high screen-to-body ratio), narrow-frame display screen design has gradually become the mainstream form of display devices. However, multiplexing circuits are usually set in the lower frame area, which increases the size of the lower frame and is not conducive to the narrow frame design.

[0079] The present embodiment provides a display substrate, comprising: a substrate, a circuit structure layer and a light-emitting structure layer sequentially arranged on the substrate. The substrate comprises a display area and a first frame area located at least on one side of the display area, and the display area comprises: a first display area and a second display area arranged along a first direction, and the second display area is located between the first display area and the first frame area along the first direction. The circuit structure layer comprises: a plurality of pixel circuits located in the first display area, a plurality of multiplexing circuits located in the second display area, and a plurality of data lines located in the display area; the plurality of data lines are connected to the plurality of pixel circuits and the plurality of multiplexing circuits. The light-emitting structure layer comprises: a plurality of light-emitting elements located in the display area; at least one pixel circuit among the plurality of pixel circuits is connected to at least one light-emitting element among the plurality of light-emitting elements, and the orthographic projection of the at least one light-emitting element and the connected pixel circuit on the substrate is staggered along the first direction; the orthographic projection of the plurality of multiplexing circuits on the substrate at least partially overlaps with the orthographic projection of the plurality of light-emitting elements located in the second display area on the substrate.

[0080] The display substrate provided in this embodiment, by staggering the pixel circuit and the light-emitting element along the first direction, allows the multiplexing circuit to be set below some of the light-emitting elements, thereby helping to reduce the space occupied by the multiplexing circuit in the frame area and facilitating the realization of a narrow frame design.

[0081] In some exemplary embodiments, the orthographic projection of at least one of the plurality of light-emitting elements on the substrate may be located on a side of the orthographic projection of the connected pixel circuit on the substrate close to the first frame area. In some examples, the orthographic projection of the light-emitting area of ​​at least one of the plurality of light-emitting elements on the substrate may not overlap with the orthographic projection of the connected pixel circuit on the substrate. In this example, the light-emitting area of ​​the light-emitting element may refer to the overlapping area of ​​the anode of the light-emitting element exposed by the pixel opening of the pixel definition layer and the light-emitting functional layer and cathode. By adjusting the relative position of the light-emitting element and the pixel circuit in this example, the multiplexing circuit can be set below the light-emitting element, thereby facilitating the realization of a narrow frame design.

[0082] In some exemplary embodiments, the first frame area may include: a first sub-frame area extending along the second direction, and a first corner area and a second corner area located at both ends of the first sub-frame area along the second direction; the second direction intersects the first direction. The second display area may include: a sub-display area extending along the second direction, and a first corner display area and a second corner display area located at both sides of the sub-display area along the second direction; the first corner display area is connected to the first corner area and the first display area, and the second corner display area is connected to the second corner area and the first display area.

[0083] In some exemplary embodiments, the circuit structure layer may further include: a plurality of first signal lines connected to the plurality of pixel circuits and extending along the second direction, and a plurality of connection lines connected to the plurality of first signal lines, and the orthographic projections of the plurality of multiplexing circuits located in the first corner display area and the second corner display area on the substrate overlap with the orthographic projections of at least one of the plurality of connection lines on the substrate. In some examples, the plurality of first signal lines may include a plurality of gate lines (such as a first scan line, a second scan line, a light emitting control line, a first reset control line and a second reset control line), a plurality of initial signal lines (such as a first initial signal line, a second initial signal line and a third initial signal line), and a routing line for transmitting a first voltage signal along the second direction; the plurality of connection lines may include: a plurality of first connection lines connected to the plurality of gate lines, a plurality of second connection lines connected to the plurality of initial signal lines, and a plurality of third connection lines connected to the plurality of routing lines for transmitting the first voltage signal along the second direction. In this example, by disposing a multiplexing circuit in the first corner display area and the second corner display area and disposing one or more connecting lines away from the substrate side, it is beneficial to ensure the flatness of the anode of the light-emitting element.

[0084] The solution of this embodiment is described below by means of some examples.

[0085] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, such as Figure 1As shown, the display substrate may be a closed polygon including linear edges, such as a rectangular rounded shape. The display substrate may include: a display area AA and a frame area BB located around the display area AA. The frame area BB may include: a first frame area B1 located on one side of the display area AA in the first direction D1, and the remaining frame areas located on the remaining sides of the display area AA, and the remaining frame areas may include: a second frame area B2 located on the side of the display area AA away from the first frame area B1 along the first direction D1, and a third frame area B3 and a fourth frame area B4 located on opposite sides of the display area AA along the second direction D2. For example, the first frame area B1 may be the lower frame area of ​​the display substrate, the second frame area B2 may be the upper frame area of ​​the display substrate, the third frame area B3 may be the left frame area of ​​the display substrate, and the fourth frame area B4 may be the right frame area of ​​the display substrate.

[0086] In some examples, such as Figure 1 As shown, the first frame area B1 may include: a first sub-frame area B10 extending along the second direction D2, and a first corner area B11 and a second corner area B12 located at both ends of the first sub-frame area B10 along the second direction D2. The first corner area B11 may be connected to the third frame area B3, and the second corner area B12 may be connected to the fourth frame area B4. The second frame area B2 may include: a second sub-frame area B20 extending along the second direction D2, and a third corner area B21 and a fourth corner area B22 located at both ends of the second sub-frame area B20 along the second direction D2. The third corner area B21 may be connected to the third frame area B3, and the fourth corner area B22 may be connected to the fourth frame area B4. The first corner area B11, the second corner area B12, the third corner area B21, and the fourth corner area B22 each correspond to the arc edge of the display area AA. The edges of the first corner region B11, the second corner region B12, the third corner region B21, and the fourth corner region B22 away from the display area AA may all be curved edges (e.g., arc-shaped edges). The first corner region B11 and the second corner region B12 may be referred to as lower corner regions, and the third corner region B21 and the fourth corner region B22 may be referred to as upper corner regions.

[0087] In some examples, the display area AA may include: a first display area A1 and a second display area A2. The second display area A2 may be located between the first display area A1 and the first frame area B1 along the first direction D1. The second display area A2 may include: a sub-display area A21 extending along the second direction D2, and a first corner display area A22a and a second corner display area A22b located on both sides of the sub-display area A21 along the second direction D2. The sub-display area A21 may be located between the first display area A1 and the first sub-frame area B10 of the first frame area B1. The first corner display area A22a may be located between the first corner area B11 and the sub-display area A21 along the second direction D2, and the second corner display area A22b may be located between the second corner area B12 and the sub-display area A21 along the second direction D2. The first corner display area A22a may be connected to the first corner area B11 and the first display area A1, and the second corner display area A22b may be connected to the second corner area B12 and the first display area A1.

[0088] In some examples, the first display area A1 may include: a plurality of pixel circuits, a plurality of light-emitting elements, a plurality of gate lines, and a plurality of data lines. The second display area A2 may include: a plurality of light-emitting elements and a plurality of multiplexing circuits. A plurality of gate lines may extend along the second direction D2 and be arranged along the first direction D1; a plurality of data lines may extend along the first direction D1 and be arranged along the second direction D2. A plurality of data lines may be connected to a plurality of pixel circuits and configured to provide data signals to the plurality of pixel circuits. A plurality of gate lines may be connected to a plurality of pixel circuits and configured to provide gate control signals to the plurality of pixel circuits. For example, the gate control signal may include a scan signal, or may include a scan signal and a light-emitting control signal, or may include a scan signal, a reset control signal, and a light-emitting control signal.

[0089] In some examples, the second direction D2 may be an extension direction of the gate lines in the display area AA (e.g., a row direction); the first direction D1 may be an extension direction of the data lines in the display area AA (e.g., a column direction). The first direction D1 and the second direction D2 may intersect each other, for example, may be perpendicular to each other.

[0090] In some examples, a pixel unit of display area AA may include: three light-emitting elements, and the three light-emitting elements may include: a first light-emitting element emitting a first color light (e.g., red light), a second light-emitting element emitting a second color light (e.g., green light), and a third light-emitting element emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four light-emitting elements, and the four light-emitting elements may include a first light-emitting element emitting red light, a second light-emitting element emitting green light, a third light-emitting element emitting blue light, and a fourth light-emitting element emitting white light. For another example, a pixel unit may include four light-emitting elements, and the four light-emitting elements may include a first light-emitting element emitting red light, a third light-emitting element emitting blue light, and two second light-emitting elements emitting green light.

[0091] In some examples, the shape of the light-emitting element may be a rectangle, a rhombus, a pentagon, or a hexagon. When a pixel unit includes three light-emitting elements, the three light-emitting elements may be arranged in parallel horizontally, vertically, or in a triangle; when a pixel unit includes four light-emitting elements, the four light-emitting elements may be arranged in parallel horizontally, vertically, or in a square. However, this embodiment is not limited to this.

[0092] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including: mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, and the light-emitting element may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as required. In some examples, the light-emitting element may include: an anode, a cathode, and a light-emitting functional layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0093] In some examples, the pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. Wherein, T in the above circuit structure refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include a P-type transistor and an N-type transistor. In other examples, the multiple transistors in the pixel circuit may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the yield of the product.

[0094] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this exemplary embodiment is described by taking an 8T1C structure as an example. In some examples, such as Figure 2 As shown, the pixel circuit of this example may include eight transistors (i.e., the first transistor T1 to the eighth transistor T8) and a storage capacitor Cst. The first transistor T1 is also called the first reset transistor, the second transistor T2 is also called the compensation transistor, the third transistor T3 is also called the driving transistor, the fourth transistor T4 is also called the data writing transistor, the fifth transistor T5 is also called the first light emission control transistor, the sixth transistor T6 is also called the second light emission control transistor, the seventh transistor T7 is also called the second reset transistor, and the eighth transistor T8 is also called the third reset transistor. The light emitting element EL may include a first electrode, a second electrode, and a light emitting functional layer disposed between the first electrode and the second electrode. Among them, the first electrode of the light emitting element EL may be an anode, and the second electrode of the light emitting element EL may be a cathode.

[0095] In some examples, the first transistor T1, the third transistor T3 to the eighth transistor T8 may be first type transistors, for example, P type transistors, and the second transistor T2 may be second type transistors, for example, N type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors of the pixel circuit may all be P type transistors, or may all be N type transistors.

[0096] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can adopt a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can adopt an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor adopts low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor adopts an oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, and oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0097] In some examples, such as Figure 2 As shown, the pixel circuit can be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power line VDD, the second power line VSS, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1 and the second reset control line RST2. The first power line VDD is configured to provide a constant first voltage signal to the pixel circuit, the second power line VSS is configured to provide a constant second voltage signal to the pixel circuit, and the first voltage signal is greater than the second voltage signal. The first scan line GL1 is configured to provide a first scan signal to the pixel circuit. The second scan line GL2 is configured to provide a second scan signal to the pixel circuit. The data line DL is configured to provide a data signal to the pixel circuit. The light emission control line EML is configured to provide a light emission control signal to the pixel circuit. The first reset control line RST1 is configured to provide a first reset control signal to the pixel circuit. The second reset control line is configured to provide a second reset control signal to the pixel circuit.

[0098] In some examples, such as Figure 2As shown, the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the third node N3, and the second electrode of the second transistor T2 is electrically connected to the first node N1. The gate of the fifth transistor T5 is electrically connected to the light emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the light emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power supply line VDD.

[0099] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0100] Figure 3 for Figure 2 The working timing diagram of the pixel circuit provided is as follows. Figure 3 right Figure 2 The working process of the pixel circuit shown in FIG. 1 is described below. The first transistor T1, the third transistor T3 to the eighth transistor T8 of the pixel circuit may be P-type transistors, and the second transistor T2 may be an N-type transistor.

[0101] In some examples, such as Figure 2 and Figure 3 As shown, in a frame display time period, the working process of the pixel circuit may at least include: a first stage P1, a second stage P2, a third stage P3 and a fourth stage P4.

[0102] The first stage P1 is called the first reset stage. The second reset control signal provided by the second reset control line RST2 is a low-level signal, which turns on the seventh transistor T7 and the eighth transistor T8; the second scan signal provided by the second scan line GL2 is a high-level signal, which turns on the second transistor T2. The eighth transistor T8 is turned on, so that the third initial signal provided by the third initial signal line INIT3 is provided to the second node N2. The seventh transistor T7 is turned on, so that the second initial signal provided by the second initial signal line INIT2 is provided to the fourth node N4, and the fourth node N4 is initialized. The first scan signal provided by the first scan line GL1 is a high-level signal, the first reset control signal provided by the first reset control line RST1 is a high-level signal, and the light control signal provided by the light control line EML is a high-level signal, so that the fourth transistor T4, the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting element EL does not emit light.

[0103] The second stage P2 is called the second reset stage. The first reset control signal provided by the first reset control line RST1 is a low-level signal, and the first transistor T1 is turned on; the second scan signal provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. The first transistor T1 and the second transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, and the first node N1 is initialized. The second reset control signal provided by the second reset control line RST2 is a high-level signal, the first scan signal provided by the first scan line GL1 is a high-level signal, and the light-emitting control signal provided by the light-emitting control line EML is a high-level signal, so that the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are turned off. In this stage, the light-emitting element EL does not emit light.

[0104] The third stage P3 is called the data writing stage or the threshold compensation stage. The first scanning signal provided by the first scanning line GL1 is a low-level signal, and the fourth transistor T4 is turned on; the second scanning signal provided by the second scanning line GL2 is a high-level signal, and the second transistor T2 is turned on. In this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4 and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, and the voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The first reset control signal provided by the first reset control line RST1 is a high level signal, the second reset control signal provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0105] In the fourth stage P4, the light control signal provided by the light control line EML can be switched from a high level signal to a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The second scan signal provided by the second scan line GL2 is a low level signal, so that the second transistor T2 is turned off. The first scan signal provided by the first scan line GL1, the first reset control signal provided by the first reset control line RST1, and the second reset control signal provided by the second reset control line RST2 are high level signals, so that the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8 are turned off. The first voltage signal output by the first power line VDD provides a driving voltage to the anode of the light emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, driving the light emitting element EL to emit light.

[0106] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0107] I=K×(Vgs-Vth) 2 =K×[(Vdd-Vdata+|Vth|)-Vth] 2 =K×[Vdd-Vdata] 2 ;

[0108] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and Vdd is the voltage of the first voltage signal output by the first power line VDD.

[0109] It can be seen from the above formula that the current flowing through the light-emitting element has nothing to do with the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can better compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the poor display caused by low frequency and improve the display effect of the light-emitting element.

[0110] Figure 4 FIG. 4 is an equivalent circuit diagram of a multiplexing circuit according to at least one embodiment of the present disclosure. Figure 4 In the example, a multiplexing circuit 31 with a 1:9 design is used as an example. Figure 4 As shown, one multiplexing circuit 31 may be electrically connected to nine multiplexing control lines (e.g., including the first multiplexing control line ML1 to the ninth multiplexing control line ML9), one multiplexing data line SL, and a plurality of data lines (e.g., including the first data line DL1 to the ninth data line DL9). The multiplexing circuit 31 may include nine multiplexing control transistors (i.e., the first multiplexing control transistor M1 to the ninth multiplexing control transistor M9). The gates of the nine multiplexing control transistors can be connected to different multiplexing control lines respectively, that is, the gate of the first multiplexing control transistor M1 is connected to the first multiplexing control line ML1, the gate of the second multiplexing control transistor M2 is connected to the second multiplexing control line ML2, the gate of the third multiplexing control transistor M3 is connected to the third multiplexing control line ML3, the gate of the fourth multiplexing control transistor M4 is connected to the fourth multiplexing control line ML4, the gate of the fifth multiplexing control transistor M5 is connected to the fifth multiplexing control line ML5, the gate of the sixth multiplexing control transistor M6 is connected to the sixth multiplexing control line ML6, the gate of the seventh multiplexing control transistor M7 is connected to the seventh multiplexing control line ML7, the gate of the eighth multiplexing control transistor M8 is connected to the eighth multiplexing control line ML8, and the gate of the ninth multiplexing control transistor M9 is connected to the ninth multiplexing control line ML9.

[0111] In some examples, the first electrodes of the nine multiplexing control transistors may all be connected to the same multiplexing data line SL. The second electrodes of the nine multiplexing control transistors are respectively connected to different data lines of the display area. For example, the second electrode of the first multiplexing control transistor M1 is connected to the first data line DL1, the second electrode of the second multiplexing control transistor M2 is connected to the second data line DL2, the second electrode of the third multiplexing control transistor M3 is connected to the third data line DL3, the second electrode of the fourth multiplexing control transistor M4 is connected to the fourth data line DL4, the second electrode of the fifth multiplexing control transistor M5 is connected to the fifth data line DL5, the second electrode of the sixth multiplexing control transistor M6 is connected to the sixth data line DL6, the second electrode of the seventh multiplexing control transistor M7 is connected to the seventh data line DL7, the second electrode of the eighth multiplexing control transistor M8 is connected to the eighth data line DL8, and the second electrode of the ninth multiplexing control transistor M9 is connected to the ninth data line DL9. Each data line may be connected to at least one column of pixel circuits in the display area. A column of pixel circuits may include a plurality of pixel circuits arranged along the first direction D1. The nine multiplexing control lines can control the multiple multiplexing circuits 31 to provide data signals to the corresponding column pixel circuits in the display area.

[0112] Figure 5 for Figure 1 A partial enlarged schematic diagram of the middle area S1. Figure 6 for Figure 1 A partial enlarged schematic diagram of the middle area S2. Figure 7 for Figure 1 A partial enlarged schematic diagram of the middle area S3. Figure 5 The circuit structure layer in the example is illustrated by taking a row (e.g., the nth row, where n is an integer greater than 0) of three columns of pixel circuits (e.g., including the jth column, the j+1th column, and the j+2th column, where j is an integer greater than 0) of the first display area A1. The nth row of pixel circuits may be the last row of pixel circuits in the first display area A1. Figure 6 The circuit structure layer is illustrated by taking the two rows (for example, the mth row and the m+1th row, where m can be an integer greater than 0 and less than n) and four columns (for example, including the kth column, the k+1th column, the k+2th column and the k+3th column, where k is an integer greater than 0 and less than j) of pixel circuits in the first display area A1 close to the first corner display area A22a as an example. Figure 7 The circuit structure layer in FIG. 1 is illustrated by taking a multiplexing circuit in the second display area A2 as an example.

[0113] In some examples, such as Figures 5 to 7As shown, the multiple light-emitting elements of the display area AA may include: multiple light-emitting element groups, and the multiple light-emitting element groups may be arranged in an array along the first direction D1 and the second direction D2. One light-emitting element group may include: a first light-emitting element EL1 that emits a first color light, a second light-emitting element EL2 that emits a second color light, and a third light-emitting element EL3 that emits a third color light. One light-emitting element group may correspond to one of the aforementioned pixel units. In one light-emitting element group, the first light-emitting element EL1 and the second light-emitting element EL2 may be aligned and arranged along the first direction D1, and be located on the same side of the third light-emitting element EL3 along the second direction D2. For example, the first light-emitting element EL1 may be a red light-emitting element, the second light-emitting element EL2 may be a green light-emitting element, and the third light-emitting element EL3 may be a blue light-emitting element.

[0114] In some examples, the orthographic projections of the light-emitting regions of the first light-emitting element EL1, the second light-emitting element EL2, and the third light-emitting element EL3 on the substrate may all be rectangular. The orthographic projection area of ​​the light-emitting region of the second light-emitting element EL2 on the substrate may be larger than the orthographic projection area of ​​the light-emitting region of the first light-emitting element EL1 on the substrate, and the orthographic projection area of ​​the light-emitting region of the third light-emitting element EL3 on the substrate may be larger than the orthographic projection area of ​​the light-emitting region of the second light-emitting element EL2 on the substrate. In this example, the light-emitting region of the light-emitting element refers to the overlapping area of ​​the anode of the light-emitting element exposed by the pixel opening of the pixel definition layer and the light-emitting functional layer and cathode.

[0115] In some examples, such as Figure 5 and Figure 6 As shown, in the first display area A1, the orthographic projection of the light-emitting element and the connected pixel circuit on the substrate may be staggered along the first direction D1. The orthographic projection of the light-emitting element on the substrate may be located on the side of the orthographic projection of the connected pixel circuit on the substrate close to the second display area A2 in the first direction D1. Among them, the orthographic projection of the light-emitting area of ​​the light-emitting element on the substrate may partially overlap with the orthographic projection of the connected pixel circuit on the substrate or may not overlap. For example, the orthographic projection of the light-emitting area of ​​the first light-emitting element EL1 on the substrate may partially overlap with the orthographic projection of the connected pixel circuit on the substrate, the orthographic projection of the light-emitting area of ​​the second light-emitting element E2 on the substrate may not overlap with the orthographic projection of the connected pixel circuit on the substrate, and the orthographic projection of the light-emitting area of ​​the third light-emitting element EL3 on the substrate may not overlap with the orthographic projection of the connected pixel circuit on the substrate.

[0116] In some examples, such as Figure 5 , Figure 6 and Figure 7As shown, in the second display area A2, the orthographic projection of the light-emitting area of ​​the light-emitting element on the substrate may overlap with the orthographic projection of the multiplexing circuit on the substrate. The multiple multiplexing control lines connected to the multiplexing circuit (for example, including the first multiplexing control line ML1 to the ninth multiplexing control line ML9) may extend along the second direction D2 and be arranged along the first direction D1. For example, the multiple multiplexing control lines may all be located in the first border area B1. In other examples, a portion of the multiple multiplexing control lines may be located in the second display area, and another portion of the multiplexing control lines may be located in the first border area B1.

[0117] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate. The "patterning process" mentioned in the embodiments of the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be performed by any one or more of spraying, spin coating, and inkjet printing, and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure.

[0118] The term "A and B are arranged in the same layer" as used in this specification means that A and B are formed simultaneously through the same patterning process, or the distances between the surfaces of A and B close to the substrate and the substrate are substantially the same, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The "thickness" of the film layer is the dimension of the film layer in a direction perpendicular to the display substrate. In this specification, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0119] In some exemplary embodiments, a process of preparing a display substrate may include the following operations.

[0120] (1) Provide a substrate. In some examples, the substrate may be a rigid substrate or a flexible substrate. For example, the rigid substrate may be, but is not limited to, one or more of glass and quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0121] (2) Forming a first semiconductor layer. In some examples, a first semiconductor film is deposited on a substrate, and the first semiconductor film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0122] Fig. 8A for Figure 5 A schematic diagram of a first semiconductor layer in FIG. Figure 8B for Figure 6 A schematic diagram of a first semiconductor layer in FIG. Figure 8C for Figure 7 Schematic diagram of the first semiconductor layer in FIG. Fig. 8A , Figure 8B and Figure 8C As shown, the first semiconductor layer of the display substrate may include: an active layer of multiple first-type transistors of multiple pixel circuits located in the first display area A1 (for example, including: an active layer T10 of a first transistor, an active layer T30 of a third transistor, an active layer T40 of a fourth transistor, an active layer T50 of a fifth transistor, an active layer T60 of a sixth transistor, an active layer T70 of a seventh transistor, and an active layer T80 of an eighth transistor), and an active layer of multiple multiplexing control transistors of multiple multiplexing circuits located in the second display area A2 (for example, including an active layer M10 of a first multiplexing control transistor to an active layer M90 of a ninth multiplexing control transistor).

[0123] In some examples, such as Fig. 8A and Figure 8BAs shown, the active layer T30 of the third transistor, the active layer T40 of the fourth transistor, the active layer T50 of the fifth transistor, the active layer T60 of the sixth transistor, and the active layer T70 of the seventh transistor of a pixel circuit may be an integrated structure. The active layer T10 of the first transistor may be located on one side of the active layer T30 of the third transistor along the first direction D1, and the active layer T80 of the eighth transistor may be located on the other side of the active layer T30 of the third transistor along the first direction D1. The active layer T80 of the eighth transistor and the active layer T70 of the seventh transistor may be aligned and arranged along the second direction D2. The active layer T10 of the first transistor may be aligned and arranged with the active layer T60 of the sixth transistor along the first direction D1.

[0124] In some examples, such as Fig. 8A and Figure 8B As shown, the orthographic projections of the active layer T10 of the first transistor, the active layer T40 of the fourth transistor, the active layer T60 of the sixth transistor, the active layer T70 of the seventh transistor and the active layer T80 of the eighth transistor on the substrate may be I-shaped, the orthographic projection of the active layer T30 of the third transistor on the substrate may be S-shaped, and the orthographic projection of the active layer T50 of the fifth transistor on the substrate may be T-shaped.

[0125] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region. The material of the semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and has semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, doped with impurities, and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as a wiring doped with impurities, which may be used to electrically connect the transistors. This embodiment is not limited to this.

[0126] In some examples, such as Fig. 8A and Figure 8B As shown, the second area of ​​the active layer T30 of the third transistor can be used as the first area of ​​the active layer T60 of the sixth transistor at the same time. The second area of ​​the active layer T60 of the sixth transistor can be used as the second area of ​​the active layer T70 of the seventh transistor at the same time. The first area of ​​the active layer T30 of the third transistor can be used as the second area of ​​the active layer T40 of the fourth transistor and the second area of ​​the active layer T50 of the fifth transistor at the same time. The first area of ​​the active layer T40 of the fourth transistor, the first area of ​​the active layer T70 of the seventh transistor, and the first area of ​​the active layer T50 of the fifth transistor can be independently set.

[0127] In some examples, such as Figure 8CAs shown, the active layers of the nine multiplexing control transistors of the multiplexing circuit (for example, including the active layer M10 of the first multiplexing control transistor, the active layer M20 of the second multiplexing control transistor, the active layer M30 of the third multiplexing control transistor, the active layer M40 of the fourth multiplexing control transistor, the active layer M50 of the fifth multiplexing control transistor, the active layer M60 of the sixth multiplexing control transistor, the active layer M70 of the seventh multiplexing control transistor, the active layer M80 of the eighth multiplexing control transistor, and the active layer M90 of the ninth multiplexing control transistor) can be aligned along the second direction D2. The positive projection of the active layer M10 of the first multiplexing control transistor to the active layer M90 of the ninth multiplexing control transistor on the substrate can be a rectangle.

[0128] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on a substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first insulating layer may also be referred to as a first gate insulating layer; and the first conductive layer may also be referred to as a first gate metal layer.

[0129] Fig.9A for Figure 5 A schematic diagram of a display substrate after forming a first conductive layer; Fig. 9B for Fig.9A Schematic diagram of the first conductive layer in FIG. Fig. 9C for Figure 6 Schematic diagram of a display substrate after forming a first conductive layer. Fig.9D for Figure 7 Schematic diagram of a display substrate after forming a first conductive layer.

[0130] In some examples, such as 9A to 9DAs shown, the first conductive layer of the display substrate may include: gates of multiple first-type transistors of multiple pixel circuits located in the first display area A1 (for example, including the gate of the first transistor T1, the gate of the third transistor T3, the gate of the fourth transistor T4, the gate of the fifth transistor T5, the gate of the sixth transistor T6, the gate of the seventh transistor T7, and the gate of the eighth transistor T8) and first electrodes Cst-1 of multiple storage capacitors, multiple first scan lines (for example, including the first scan lines GL1(n), GL1(m), GL(m+1)), multiple first shielding electrodes 203, multiple light-emitting control lines (for example, including the light-emitting control lines EML(n), EML(m), EML(m+1)), multiple first reset control lines (for example, including first reset control lines RST1(n), RST1(m-1), RST1(m), RST1(m+1)), and multiple second reset control lines (for example, including second reset control lines RST2(n), RST2(m), RST2(m+1)), gates of multiple multiplexing control transistors of multiple multiplexing circuits located in the second display area A2 (for example, including the gate M11 of the first multiplexing control transistor M1 to the gate M91 of the ninth multiplexing control transistor M9) and multiple first auxiliary electrodes 201.

[0131] In some examples, such as Fig.9A and Fig. 9B As shown, the first scan line GL1(n) may extend along the second direction D2. A plurality of first shielding electrodes 203 may be connected to a side of the first scan line GL1(n) away from the third transistor T3. The orthographic projection of the first shielding electrode 203 on the substrate may be a rectangle. The orthographic projection of the first shielding electrode 203 on the substrate may be located between the orthographic projections of the active layer T40 of the fourth transistor T4 of two adjacent pixel circuits in the same row of pixel circuits on the substrate. The overlapping portion of the first scan line GL1(n) with the active layer T40 of the fourth transistor T4 may serve as the gate of the fourth transistor T4.

[0132] In some examples, the orthographic projection of the first electrode Cst-1 of the storage capacitor on the substrate may be a rectangle. The first electrode Cst-1 of the storage capacitor may also serve as the gate of the third transistor T3.

[0133] In some examples, the orthographic projection of the first reset control line RST1(n) on the substrate may be a straight line extending along the second direction D2. The first reset control line RST1(n) may be located along the first direction D1 on a side of the first scan line GL1(n) away from the third transistor T3. The overlapped portion of the first reset control line RST1(n) with the active layer T10 of the first transistor T1 may serve as the gate of the first transistor T1.

[0134] In some examples, the positive projection of the second reset control line RST2(n) on the substrate may be a zigzag extending along the second direction D2. The second reset control line RST2(n) may be located along the first direction D1 on a side of the third transistor T3 away from the first scan line GL1(n). The overlapping portion of the second reset control line RST2(n) with the active layer T70 of the seventh transistor T7 may serve as the gate of the seventh transistor T7, and the overlapping portion of the second reset control line RST2(n) with the active layer T80 of the eighth transistor T8 may serve as the gate of the eighth transistor T8.

[0135] In some examples, the positive projection of the light emitting control line EML (n) on the substrate may be in the shape of a zigzag extending along the second direction D2. The light emitting control line EML (n) may be located on a side of the second reset control line RST2 (n) close to the third transistor T3 along the first direction D1. The overlapping portion of the light emitting control line EML (n) with the active layer of the sixth transistor T6 may serve as the gate of the sixth transistor T6, and the overlapping portion of the light emitting control line EML (n) with the active layer of the fifth transistor T5 may serve as the gate of the fifth transistor T5.

[0136] In some examples, such as Fig.9D As shown, the gate M11 of the first multiplexing control transistor M1, the gate M21 of the second multiplexing control transistor M2, the gate M31 of the third multiplexing control transistor M3, the gate M41 of the fourth multiplexing control transistor M4, the gate M51 of the fifth multiplexing control transistor M5, the gate M61 of the sixth multiplexing control transistor M6, the gate M71 of the seventh multiplexing control transistor M7, the gate M81 of the eighth multiplexing control transistor M8 and the gate M91 of the ninth multiplexing control transistor M9 can be arranged in sequence along the second direction D2, and extend along the first direction D1, for example, can extend to the first frame area B1. The first auxiliary electrode 201 can be located on the side of the gate M11 of the first multiplexing control transistor M1 away from the gate M21 of the second multiplexing control transistor. The positive projection of the first auxiliary electrode 201 on the substrate can be a rectangle.

[0137] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second insulating layer may also be referred to as a second gate insulating layer, and the second conductive layer may also be referred to as a second gate metal layer.

[0138] Fig. 10A for Figure 5 A schematic diagram of a display substrate after a second conductive layer is formed in FIG. Fig. 10B for Fig. 10A Schematic diagram of the second conductive layer in . Fig. 10C for Figure 6 Schematic diagram of a display substrate after a second conductive layer is formed. Fig. 10D for Figure 7 Schematic diagram of a display substrate after a second conductive layer is formed.

[0139] In some examples, such as FIG. 10A to FIG. 10D As shown, the second conductive layer of the display substrate may include: a second electrode Cst-2 of a storage capacitor of a plurality of pixel circuits located in the first display area A1, a plurality of first initial signal lines (for example, including first initial signal lines INIT1(n-1), INIT1(n), INIT1(m-1), INIT1(m)), a plurality of second scanning auxiliary lines (for example, including second scanning auxiliary lines GL2b(n), GL2b(m), GL2b(m+1)), a plurality of second auxiliary electrodes 202 located in the second display area A2, and a multiplexed data line SL.

[0140] In some examples, such as FIG. 10A to FIG. 10C As shown, the second electrode Cst-2 of the storage capacitor may have a first hollow portion K0. The orthographic projection of the first hollow portion K0 on the substrate may be located within the orthographic projection range of the first electrode Cst-1 of the storage capacitor on the substrate. The orthographic projections of the second electrode Cst-2 and the first electrode Cst-1 of the storage capacitor on the substrate overlap.

[0141] In some examples, the orthographic projection of the first initial signal line INIT1(n) on the substrate may be a straight line extending along the second direction D2. The orthographic projection of the first initial signal line INIT1(n) on the substrate may be located on a side of the orthographic projection of the first reset control line RST1(n) on the substrate close to the second display area A2.

[0142] In some examples, the orthographic projection of the second scanning auxiliary line GL2b(n) on the substrate may be a zigzag line extending along the second direction D2. The orthographic projection of the second scanning auxiliary line GL2b(n) on the substrate may be located between the orthographic projections of the first scanning line GL1(n) and the first reset control line RST1(n) on the substrate.

[0143] In some examples, such as Fig. 10D As shown, the orthographic projection of the second auxiliary electrode 202 on the substrate may be a rectangle and may be located between the orthographic projections of the gate M31 of the third multiplexing control transistor M3 and the gate M41 of the fourth multiplexing control transistor M4 on the substrate.

[0144] In some examples, such as Fig. 10DAs shown, the multiplexing data line SL may extend along the first direction D1 to the first frame area B1. The orthographic projection of the multiplexing data line SL on the substrate may be located between the orthographic projections of the gate M61 of the sixth multiplexing control transistor M6 and the gate M71 of the seventh multiplexing control transistor M7 on the substrate.

[0145] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the third insulating layer may also be referred to as a third gate insulating layer. For example, the material of the second semiconductor layer may be IGZO.

[0146] Fig.11A for Figure 5 Schematic diagram of a display substrate after forming a second semiconductor layer. Fig. 11B for Figure 6 Schematic diagram of a display substrate after forming a second semiconductor layer. In some examples, such as Fig.11A and Fig. 11B As shown, the second semiconductor layer of the display substrate may include: an active layer of the second type transistor of a plurality of pixel circuits located in the first display area A1 (eg, an active layer T20 including the second transistor).

[0147] In some examples, such as Fig.11A and Fig. 11B As shown, the active layer T20 of the second transistor may include: a channel region T20-0, a first region T20-1, and a second region T20-2. The active layer T20 of the second transistor may extend along the first direction D1. The orthographic projection of the second region T20-2 of the second transistor on the substrate may be a rectangle. The orthographic projection of the second region T20-2 of the second transistor on the substrate may be located within the range of the orthographic projection of the first shielding electrode 203 on the substrate.

[0148] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed, and the third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the fourth insulating layer may also be referred to as a fourth gate insulating layer, and the third conductive layer may also be referred to as a third gate metal layer.

[0149] Fig. 12A for Figure 5 Schematic diagram of a display substrate after a third conductive layer is formed. Fig. 12B for Figure 6 Schematic diagram of a display substrate after forming a third conductive layer. In some examples, such as Fig. 12A and Fig. 12BAs shown, the third conductive layer of the display substrate may include: a plurality of second scan lines located in the first display area A1 (for example, including second scan lines GL2(n), GL2(m), GL2(m+1)) and a plurality of third initial signal lines (for example, including third initial signal lines INIT3(n), INIT3(m), INIT3(m+1)).

[0150] In some examples, such as Fig. 12A and Fig. 12B As shown, the orthographic projection of the second scan line GL2(n) on the substrate may be a zigzag shape extending along the second direction D2. The orthographic projection of the second scan line GL2(n) on the substrate overlaps with the orthographic projection of the second scan auxiliary line GL2b(n) on the substrate. The overlapping portion of the second scan line GL2(n) with the active layer T20 of the second transistor T2 may serve as the gate of the second transistor T2. The overlapping portion of the second scan auxiliary line GL2b(n) with the active layer T20 of the second transistor T2 may serve as the bottom gate of the second transistor T2. The second scan line GL2(n) and the second scan auxiliary line GL2b(n) may be configured to receive the same signal.

[0151] In some examples, such as Fig. 12A and Fig. 12B As shown, the orthographic projection of the third initial signal line INIT3(n) on the substrate may be a zigzag line extending along the second direction D2. The orthographic projection of the third initial signal line INIT3(n) on the substrate may overlap with the orthographic projection of the second reset control line RST2(n) on the substrate.

[0152] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0153] Fig.13A for Figure 5 Schematic diagram of a display substrate after a fifth insulating layer is formed. Fig. 13B for Figure 6 Schematic diagram of a display substrate after a fifth insulating layer is formed. Fig. 13C for Figure 7 Schematic diagram of a display substrate after a fifth insulating layer is formed.

[0154] In some examples, such as FIG. 13A to FIG. 13CAs shown, the fifth insulating layer of the display substrate may be provided with a plurality of vias, for example, may include: the first via V1 to the twenty-seventh via V27. Among them, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the first via V1 to the twelfth via V12 may be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the thirteenth via V13 to the seventeenth via V17 may be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer and the third insulating layer in the eighteenth via V18 and the twenty-second via V22 may be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer and the fourth insulating layer in the twenty-third via V23 to the twenty-fourth via V24 may be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer in the twenty-fifth via V25 and the twenty-seventh via V27 may be removed to expose a portion of the surface of the third conductive layer.

[0155] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source-drain metal layer.

[0156] Fig.14A for Figure 5 A schematic diagram of a display substrate after a fourth conductive layer is formed; Fig. 14B for Fig.14A Schematic diagram of the fourth conductive layer in . Fig. 14C for Figure 6 A schematic diagram of a display substrate after a fourth conductive layer is formed; Fig.14D for Fig. 14C Schematic diagram of the fourth conductive layer in . Fig.14E for Figure 7 Schematic diagram of a display substrate after a fourth conductive layer is formed.

[0157] In some examples, such as FIG. 14A to FIG. 14EAs shown, the fourth conductive layer of the display substrate may include: a plurality of connecting electrodes located in the first display area A1 (for example, including the first connecting electrode 301 to the ninth connecting electrode 309), a plurality of second initial signal lines (for example, including the second initial signal lines INIT2(n), INIT2(n+1), INIT2(m), INIT2(m+1)); a plurality of connecting electrodes located in the second display area A2 (for example, including the eleventh connecting electrode 311 to the fifteenth connecting electrode 315), a first border power line 33, the first and second electrodes of a plurality of multiplexed control transistors (for example, including the first electrode M12 and the second electrode M13 of the first multiplexed control transistor M1, the first electrode M82 and the second electrode M83 of the eighth multiplexed control transistor M8), and a multiplexed connection electrode 34; and a plurality of multiplexed control lines located in the first border area B1 (for example, including the first multiplexed control line ML1 to the ninth multiplexed control line ML9).

[0158] In some examples, such as Fig.14A and Fig. 14B As shown, the orthographic projection of the first connection electrode 301 on the substrate may be a strip extending along the first direction D1. The first connection electrode 301 may be connected to the first region of the active layer T10 of the first transistor T1 through the tenth via hole V10, and may also be connected to the first initial signal line INIT1(n) through the nineteenth via hole V19.

[0159] In some examples, the orthographic projection of the second connection electrode 302 on the substrate may be substantially L-shaped. One end of the second connection electrode 302 may be connected to the first region of the active layer T60 of the sixth transistor T6 through the third via hole V3, and the other end may be connected to the second region of the active layer T10 of the first transistor T1 through the ninth via hole V9, and may also be connected to the first region T20-1 of the active layer T20 of the second transistor T2 through the twenty-fourth via hole V24.

[0160] In some examples, the orthographic projection of the third connection electrode 303 on the substrate may be a zigzag shape extending along the first direction D1. The third connection electrode 303 may be connected to the gate T31 of the third transistor T3 through the thirteenth via hole V13, and may also be connected to the second region T20-2 of the active layer T20 of the second transistor T2 through the twenty-third via hole V23.

[0161] In some examples, the orthographic projection of the fourth connection electrode 304 on the substrate may be a strip extending in a direction intersecting both the first direction D1 and the second direction D2. The fourth connection electrode 304 may be connected to the first region of the active layer T80 of the eighth transistor T8 through a fourth via hole V4, and may also be connected to the third initial signal line INIT3(n) through a twenty-seventh via hole V27.

[0162] In some examples, the orthographic projection of the fifth connection electrode 305 on the substrate may be substantially rectangular. The fifth connection electrode 305 may be connected to the second region of the active layer T60 of the sixth transistor T6 through the second via hole V2.

[0163] In some examples, the orthographic projection of the sixth connection electrode 306 on the substrate may be substantially L-shaped. The sixth connection electrode 306 may be connected to the second region of the active layer T80 of the eighth transistor T8 through the fifth via hole V5 and may also be connected to the second region of the active layer T50 of the fifth transistor T5 through the sixth via hole V6.

[0164] In some examples, the orthographic projection of the seventh connection electrode 307 on the substrate may be substantially rectangular. The seventh connection electrode 307 may be connected to the first region of the active layer T40 of the fourth transistor T4 through the eighth via hole V8.

[0165] In some examples, the orthographic projection of the eighth connection electrode 308 on the substrate may be roughly T-shaped. The eighth connection electrode 308 may be connected to the second electrode Cst-2 of the storage capacitor through two eighteenth vias V18 arranged vertically, and may also be connected to the first region of the active layer T50 of the fifth transistor T5 through the seventh via V7. The eighth connection electrode 308 connected to a row of pixel circuits may be an integrated structure, so that the transmission of the first voltage signal along the second direction D2 can be realized.

[0166] In some examples, the orthographic projection of the ninth connection electrode 309 on the substrate may be a strip extending along the first direction D1. The ninth connection electrode 309 may be connected to the first region of the active layer T70 of the seventh transistor T7 through the first via hole V1.

[0167] In some examples, the second initial signal line INIT2(n) may be a straight line extending along the second direction D2. The second initial signal line INIT2(n) and a plurality of ninth connection electrodes 309 connected to a row (e.g., the nth row) of pixel circuits may be an integral structure. The orthographic projection of the second initial signal line INIT2(n) on the substrate may overlap with the orthographic projection of the first reset control line RST1(n-1) on the substrate.

[0168] In this example, multiple first initial signal lines can be located in the second conductive layer, multiple second initial signal lines can be located in the fourth conductive layer, and multiple third initial signal lines can be located in the third conductive layer. By arranging the first initial signal lines, the second initial signal lines, and the third initial signal lines in different conductive layers, it is helpful to save the space occupied by the wiring.

[0169] In some examples, such as Fig. 14C and Fig.14DAs shown, the eleventh connecting electrode 311 to the fifteenth connecting electrode 315 can be located in the first corner display area A22a of the second display area. The orthographic projections of the eleventh connecting electrode 311 to the fifteenth connecting electrode 315 on the substrate can all be roughly rectangular. The eleventh connecting electrode 311 can be connected to the end of the third initial signal line INIT3(m+1) extending to the first corner display area A22a through the twenty-fifth via hole V25. The twelfth connecting electrode 312 can be connected to the end of the light emitting control line EML(m+1) extending to the first corner display area A22a through the sixteenth via hole V16. The thirteenth connecting electrode 313 can be an integrated structure with the eighth connecting electrode 308 connected to the pixel circuit of the m+1th row. The fourteenth connection electrode 314 may be connected to the end of the second scan line GL2(m+1) extending to the first corner display area A22a through the twenty-sixth via hole V26, and may also be connected to the end of the second scan auxiliary line GL2b(m+1) extending to the first corner display area A22a through the twenty-second via hole V22. The fifteenth connection electrode 315 may be connected to the end of the first reset control line RST1(m+1) extending to the first corner display area A22a through the seventeenth via hole V17.

[0170] In some examples, such as Fig.14A and Fig.14E As shown, the first frame power line 33 can be located in the second display area A2 and can be located between the nth row of pixel circuits and a row of multiplexing circuits along the first direction D1. The orthographic projection of the first frame power line 33 on the substrate can be a straight line extending along the second direction D2.

[0171] In some examples, such as FIG. 14A to FIG. 14E As shown, the first electrode M12 of the first multiplexing control transistor M1 can be connected to the first area of ​​the active layer M10 of the first multiplexing control transistor M1 through a plurality of (e.g., four) eleventh vias V11 arranged vertically. The second electrode M13 of the first multiplexing control transistor M1 can be connected to the second area of ​​the active layer M10 of the first multiplexing control transistor M1 through a plurality of (e.g., four) twelfth vias V12 arranged vertically. The first electrode M82 of the eighth multiplexing control transistor M8 can be connected to the first area of ​​the active layer M80 of the eighth multiplexing control transistor M8, and the second electrode M83 of the eighth multiplexing control transistor M8 can be connected to the second area of ​​the active layer M80 of the eighth multiplexing control transistor M8.

[0172] In some examples, the reuse connection electrode 34 may be located on a side of the multiplexing circuit away from the first display area A1. The reuse connection electrode 34 and the first electrode M12 of the first multiplexing control transistor M1 to the first electrode of the ninth multiplexing control transistor M9 of a multiplexing circuit may be an integral structure. In the sub-display area of ​​the second display area A2, the positive projection of the reuse connection electrode 34 on the substrate may be a straight line extending along the second direction D2. The reset connection electrode 34 may be connected to the first auxiliary electrode 201 through the fourteenth via hole V14, may be connected to the second auxiliary electrode 202 through the twentieth via hole V20, and may be connected to the reuse data line SL through the twenty-first via hole V21.

[0173] In some examples, such as Fig.14E As shown, in the first sub-frame area of ​​the first frame area B1, a plurality of multiplexing control lines may extend along the second direction D2 and be arranged in sequence along the first direction D1. For example, the first multiplexing control line ML1 can be connected to the gate M11 of the first multiplexing control transistor M1 through the fifteenth via V15; the second multiplexing control line ML2 can be connected to the gate M21 of the second multiplexing control transistor M2; the third multiplexing control line ML3 can be connected to the gate M31 of the third multiplexing control transistor M3; the fourth multiplexing control line ML4 can be connected to the gate M41 of the fourth multiplexing control transistor M4; the fifth multiplexing control line ML5 can be connected to the gate M51 of the fifth multiplexing control transistor M5; the sixth multiplexing control line ML6 can be connected to the gate M61 of the sixth multiplexing control transistor M6; the seventh multiplexing control line ML7 can be connected to the gate M71 of the seventh multiplexing control transistor M7; the eighth multiplexing control line ML8 can be connected to the gate M81 of the eighth multiplexing control transistor M8; and the ninth multiplexing control line ML9 can be connected to the gate M91 of the ninth multiplexing control transistor M9.

[0174] (9) Forming a sixth insulating layer. In some examples, a sixth insulating film is coated on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form a sixth insulating layer. In some examples, the sixth insulating layer may also be referred to as a first flat layer.

[0175] Fig.15A for Figure 5 Schematic diagram of a display substrate after the sixth insulating layer is formed. Fig. 15B for Figure 6 Schematic diagram of a display substrate after forming a sixth insulating layer. In some examples, such as Fig.15A and Fig. 15BAs shown, the sixth insulating layer of the display substrate may be provided with a plurality of via holes, for example, may include: the 31st via hole V31 to the 40th via hole V40. The sixth insulating layer in the 31st via hole V31 to the 40th via hole V40 may be removed to expose part of the surface of the fourth conductive layer.

[0176] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the sixth insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source-drain metal layer.

[0177] Fig.16A for Figure 5 Schematic diagram of a display substrate after a fifth conductive layer is formed. Fig. 16B for Fig.16A Schematic diagram of the fifth conductive layer in . Fig. 16C for Figure 6 Schematic diagram of a display substrate after a fifth conductive layer is formed. Fig.16D for Fig. 16C Schematic diagram of the fifth conductive layer in . Fig.16E for Figure 7 Schematic diagram of a display substrate after a fifth conductive layer is formed.

[0178] In some examples, such as FIG. 16A to FIG. 16E As shown, the fifth conductive layer of the display substrate may include: multiple first power lines (for example, including first power lines VDD(j), VDD(j+1), VDD(j+2), VDD(k), VDD(k+1), VDD(k+2), VDD(k+3)), multiple data lines (for example, including first data line DL1, second data line DL2, third data line DL3, seventh data line DL7, eighth data line DL8 and ninth data line DL9), multiple first gaskets 51, multiple second gaskets 52, multiple first transfer electrodes (for example, including first transfer electrodes 410a, 410b and 410c), and multiple connecting lines (for example, including second connecting line 401, third connecting line 403, first connecting line 402, 404 and 405).

[0179] In some examples, such as FIG. 16A to FIG. 16BAs shown, the first transfer electrodes 410a, 410b and 410c can extend along the first direction D1, so that the pixel circuit and the connected light-emitting element can be misaligned in the first direction D1. One end of the first transfer electrode 410a can be connected to the fifth connection electrode 305 connected to the pixel circuit of the jth column and the nth row through the thirty-first via hole V31, and the other end can be connected to the anode of the first light-emitting element EL1 later. One end of the first transfer electrode 410b can be connected to the pixel circuit of the j+1th column and the nth row, and the other end can be connected to the anode of the second light-emitting element EL2 later. One end of the first transfer electrode 410c can be connected to the pixel circuit of the j+2th column and the nth row, and the other end can be connected to the anode of the third light-emitting element EL3 later.

[0180] In some examples, a plurality of first power lines may extend along the first direction D1 and be arranged along the second direction D2. For example, the first power line VDD(j) may extend along the first direction D1 and extend from the first display area A1 to the second display area A2. The first power line VDD(j) may be connected to the eighth connection electrode 308 through the thirty-second via hole V32 in the first display area A1 to achieve electrical connection with the storage capacitor and the fifth transistor of the pixel circuit, and may also be connected to the first frame power line 33 through the thirty-fourth via hole V34 in the second display area A2.

[0181] In some examples, at least one first power line may be an integral structure with the first gasket 51 located in the second display area A2. For example, the first gasket 51 adjacent to the first multiplexing control transistor M1 may be an integral structure with the first power line VDD(j). The orthographic projection of the first gasket 51 on the substrate may be a rectangle. The maximum length of the first gasket 51 along the second direction D2 may be greater than the maximum length of the portion of the first power line VDD(j) in the second display area A2 along the second direction D2. The orthographic projection of the first gasket 51 on the substrate may be located on the side of the first multiplexing control transistor M1 away from the second multiplexing control transistor M2. This example can help ensure the flatness of the anode of the light-emitting element in the second display area A2 by providing the first gasket.

[0182] In some examples, at least one first power line may be an integral structure with the second gasket 52 located in the first display area A1. The orthographic projection of the second gasket 52 on the substrate may be a rectangle, such as a square. For example, the first power line VDD(j) may be an integral structure with the second gasket 52. The maximum length of the second gasket 52 along the second direction D2 may be greater than or equal to the maximum length of the first power line VDD(j) along the second direction D2. In this example, the second gasket 52 is provided to facilitate ensuring the flatness of the anode of the light-emitting element in the first display area A1.

[0183] In some examples, the plurality of data lines may extend along the first direction D1 and be arranged along the second direction D2. For example, the first data line DL1 may extend along the first direction D1 and extend from the first display area A1 to the second display area A2; the first data line DL1 may be connected to the seventh connection electrode 307 through the thirty-third via hole V33 in the first display area A1 to achieve connection with the fourth transistor of the pixel circuit; the first data line DL1 may also be connected to the second electrode M13 of the first multiplexing control transistor M1 through the thirty-fifth via hole V35 in the second display area A2.

[0184] In some examples, such as Fig. 16C and Fig.16D As shown, multiple connection lines (for example, including a second connection line 401, a third connection line 403, a first connection line 402, 404 and 405) can extend from the first corner display area A22a to the third border area, wherein the first connection line connected to the gate line can achieve electrical connection with the gate drive circuit located in the third border area. The second connection line 401 can be connected to the eleventh connection electrode 311 through the thirty-sixth via hole V36 to achieve electrical connection with the third initial signal line INIT3(m+1); the first connection line 402 can be connected to the twelfth connection electrode 312 through the thirty-seventh via hole V37 to achieve electrical connection with the light-emitting control line EML(m+1); the third connection line 403 can be connected to the thirteenth connection electrode 313 through the thirty-eighth via hole V38 to achieve electrical connection with the eighth connection electrode connected to the m+1th row of pixel circuits to provide a first voltage signal along the second direction D2; the first connection line 404 can be connected to the fourteenth connection electrode 314 through the thirty-ninth via hole V39 to achieve electrical connection with the second scanning line GL2(m+1) and the second scanning auxiliary line GL2b(m+1); the first connection line 405 can be connected to the fifteenth connection electrode 315 through the fortieth via hole V40 to achieve electrical connection with the first reset control line RST1(m).

[0185] In some examples, in the first corner display area A22a, the orthographic projections of the plurality of connection lines on the substrate overlap with the orthographic projections of the plurality of multiplexing control transistors of the multiplexing circuit on the substrate, which can help increase the flatness of the anode of the light-emitting element prepared subsequently.

[0186] (11) Forming a seventh insulating layer. In some examples, a seventh insulating film is coated on the substrate on which the aforementioned pattern is formed, and the seventh insulating film is patterned by a patterning process to form a seventh insulating layer. In some examples, the seventh insulating layer may also be referred to as a second flat layer.

[0187] Fig.17 for Figure 5Schematic diagram of a display substrate after forming a seventh insulating layer. In some examples, such as Fig.17 As shown, the seventh insulating layer of the display substrate may be provided with a plurality of via holes, for example, may include the 41st to 43rd via holes V41 to V43. The seventh insulating layer within the 41st to 43rd via holes V41 to V43 may be removed to expose a portion of the surface of the fifth conductive layer.

[0188] At this point, the circuit structure layer of the display substrate is prepared. The circuit structure layer of this example may include: a first semiconductor layer, a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, a third insulating layer, a second semiconductor layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a fourth conductive layer, a sixth insulating layer, a fifth conductive layer, and a seventh insulating layer sequentially arranged on the substrate.

[0189] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer and the fifth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0) and silicon oxynitride (SiON), and can be a single layer, a multi-layer or a composite layer. The sixth insulating layer and the seventh insulating layer can be made of organic materials such as polyimide, acrylic or polyethylene terephthalate. However, this embodiment is not limited to this.

[0190] (12) Forming a light-emitting structure layer and a packaging structure layer in sequence.

[0191] In some examples, an anode film is deposited on a substrate forming the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer. Subsequently, a pixel definition film is coated, and a pixel definition layer is formed by masking, exposure, and development processes. The pixel definition layer may be formed with a plurality of pixel openings exposing the anode layer. A light-emitting functional layer is formed in the aforementioned pixel openings, and the light-emitting functional layer is connected to the anode layer. For example, the pixel definition layer may be made of an organic material such as polyimide, acrylic, or polyethylene terephthalate. Subsequently, a cathode film is deposited, and the cathode film is patterned by a patterning process to form a cathode layer, and the cathode of the light-emitting element is connected to the light-emitting functional layer. Subsequently, an encapsulation layer is formed on the cathode layer, and the encapsulation layer may include a laminated structure of inorganic material / organic material / inorganic material.

[0192] Fig.18A for Figure 5Schematic diagram of a display substrate after an anode layer is formed. Fig.18B for Fig.18A Schematic diagram of the anode layer and the fifth conductive layer in FIG. Fig.18C for Figure 7 Schematic diagram of a display substrate after forming an anode layer in the embodiment. 18A to 18C As shown, the anode layer of the display substrate may include: anodes of multiple light-emitting elements (for example, including the anode EL11 of the first light-emitting element EL1, the anode EL21 of the second light-emitting element EL2, and the anode EL31 of the third light-emitting element EL3), and multiple second transfer electrodes (for example, including second transfer electrodes 420a, 420b and 420c).

[0193] In some examples, the second transfer electrode 420a is an integral structure with the anode EL11 of the first light-emitting element EL1. The second transfer electrode 420b is an integral structure with the anode EL21 of the second light-emitting element EL2. The second transfer electrodes 420a and 420b may extend along the first direction D1. The second transfer electrode 420a may be connected to the first transfer electrode 410a, and the second transfer electrode 420b may be connected to the first transfer electrode 410b. The second transfer electrode 420c may be an integral structure with the anode EL31 of the third light-emitting element EL3. In this example, the electrical connection between the pixel circuit and the light-emitting element may be ensured by setting the second transfer electrode, and the pixel circuit and the connected light-emitting element may be staggered along the first direction D1.

[0194] In some examples, such as Fig.18B As shown, in the second display area A2, the orthographic projection of the anode EL21 of the second light emitting element EL2 on the substrate may partially overlap with the orthographic projection of the first spacer 51 on the substrate to ensure the flatness of the anode of the second light emitting element EL2.

[0195] In some examples, such as Fig.18B As shown, in the second display area A2, the orthographic projection of the anode EL31 of the third light-emitting element EL3 on the substrate may have a first edge EL31-1 and a second edge EL31-2 extending along the first direction D1. The orthographic projection of the first edge EL31-1 on the substrate may overlap with the orthographic projection of the first power line VDD(j+1) on the substrate, for example, it may be located within the orthographic projection range of the first power line VDD(j+1) on the substrate; the orthographic projection of the second edge EL31-2 on the substrate may overlap with the orthographic projection of the first power line VDD(j+2) on the substrate, for example, it may be located within the orthographic projection range of the first power line VDD(j+2) on the substrate. This example can ensure the flatness of the anode of the third light-emitting element EL3, which is conducive to preventing the occurrence of defects such as color deviation.

[0196] In some examples, the encapsulation structure layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer may be arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0197] The structure of the display substrate of this embodiment and its preparation process are only an exemplary description. In some exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs. The preparation process of this exemplary embodiment can be implemented using currently mature preparation equipment, can be well compatible with existing preparation processes, and has simple process implementation, easy implementation, high production efficiency, low production cost, and high yield rate.

[0198] The display substrate provided in this embodiment is arranged so that the multiplexing circuit can be arranged below some of the light-emitting elements by staggering the pixel circuit and the light-emitting element along the first direction, thereby facilitating the reduction of the space occupied by the multiplexing circuit in the frame area and facilitating the realization of a narrow frame design. For example, the length of the first frame area reduced along the first direction D1 can be greater than or equal to the maximum length of a row of pixel circuits along the first direction D1.

[0199] Fig.19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Fig.19 As shown, the display device 91 may include a display substrate 910. The display substrate 910 may be an OLED display substrate. The display device 91 may be: an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, or a navigator, or any other product or component with a display function. However, this embodiment is not limited thereto.

[0200] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example" or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0201] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate, characterized in that: include: A substrate, comprising a display area and a first frame area located at at least one side of the display area, wherein the display area comprises: a first display area and a second display area arranged along a first direction, wherein the second display area is located between the first display area and the first frame area along the first direction; A circuit structure layer is arranged on the substrate, the circuit structure layer comprising: a plurality of pixel circuits located in the first display area, a plurality of multiplexing circuits located in the second display area, and a plurality of data lines located in the display area; the plurality of data lines are connected to the plurality of pixel circuits and the plurality of multiplexing circuits; A light-emitting structure layer is arranged on a side of the circuit structure layer away from the substrate, and the light-emitting structure layer includes: a plurality of light-emitting elements located in the display area; at least one pixel circuit among the plurality of pixel circuits is connected to at least one light-emitting element among the plurality of light-emitting elements, and the at least one light-emitting element and the connected pixel circuit are staggered along the first direction in the orthographic projection of the substrate; the orthographic projections of the plurality of multiplexing circuits on the substrate at least partially overlap with the orthographic projections of the plurality of light-emitting elements located in the second display area on the substrate.

2. The display substrate according to claim 1, characterized in that: The orthographic projection of at least one of the plurality of light-emitting elements on the substrate is located on a side of the orthographic projection of the connected pixel circuit on the substrate close to the first frame area.

3. The display substrate according to claim 1, characterized in that: An orthographic projection of a light emitting region of at least one of the plurality of light emitting elements on the substrate does not overlap with an orthographic projection of a connected pixel circuit on the substrate.

4. The display substrate according to claim 1, characterized in that: The plurality of light emitting elements include: a plurality of light emitting element groups, the plurality of light emitting element groups are arranged in an array along the first direction and a second direction, the second direction intersecting the first direction; At least one of the plurality of light emitting element groups comprises: a first light emitting element emitting a first color light, a second light emitting element emitting a second color light, and a third light emitting element emitting a third color light; In a single light emitting element group, the first light emitting element and the second light emitting element are aligned along the first direction and are located on the same side of the third light emitting element along the second direction.

5. The display substrate according to claim 1, characterized in that: The at least one light-emitting element includes: a first electrode, a light-emitting functional layer, and a second electrode arranged in sequence along a direction away from the substrate; the first electrode is connected to the corresponding pixel circuit through a first switching electrode; the first switching electrode and the multiple data lines are in the same layer structure, and the first switching electrode extends along the first direction.

6. The display substrate according to claim 1, characterized in that: The circuit structure layer also includes: a plurality of first power lines located in the display area; the plurality of first power lines extend along the first direction and are arranged along a second direction, and the second direction intersects with the first direction; the plurality of first power lines are connected to the plurality of pixel circuits, and the plurality of first power lines and the plurality of data lines are in the same layer structure.

7. The display substrate according to claim 6, characterized in that: The circuit structure layer also includes: a first frame power line located in the second display area, the first frame power line is located along the first direction on the side of the multiple multiplexing circuits close to the multiple pixel circuits; the first frame power line extends along the second direction and is connected to the multiple first power lines.

8. The display substrate according to claim 7, characterized in that: The first frame power line is located on a side of the plurality of first power lines close to the substrate.

9. The display substrate according to claim 6, characterized in that: The circuit structure layer further includes: a plurality of first gaskets located in the second display area, wherein the first gaskets and the first power line are an integrated structure; The at least one light-emitting element comprises: a first electrode, a light-emitting functional layer and a second electrode arranged in sequence along a direction away from the substrate; the orthographic projection of the first electrode of the at least one light-emitting element on the substrate at least partially overlaps with the orthographic projection of the first gasket on the substrate.

10. The display substrate according to claim 6, characterized in that: The at least one light-emitting element comprises: a first electrode, a light-emitting functional layer, and a second electrode which are sequentially arranged in a direction away from the substrate; In the second display area, the first electrode of the at least one light-emitting element overlaps with the orthographic projections of the two first power lines on the substrate, and the orthographic projections of the edges of the first electrode extending along the first direction on the substrate at least partially overlap with the orthographic projections of the two first power lines on the substrate.

11. The display substrate according to claim 1, characterized in that: The first frame area includes: a first sub-frame area extending along a second direction, and a first corner area and a second corner area located at two ends of the first sub-frame area along the second direction; the second direction intersects the first direction; The second display area includes: a sub-display area extending along the second direction, and a first corner display area and a second corner display area located on both sides of the sub-display area along the second direction; the first corner display area is connected to the first corner area and the first display area, and the second corner display area is connected to the second corner area and the first display area.

12. The display substrate according to claim 11, characterized in that: The circuit structure layer also includes: a plurality of first signal lines connected to the plurality of pixel circuits and extending along the second direction, and a plurality of connecting lines connected to the plurality of first signal lines, and the orthographic projection of a plurality of multiplexing circuits located in the first corner display area and the second corner display area on the substrate overlaps with the orthographic projection of at least one of the plurality of connecting lines on the substrate.

13. The display substrate according to claim 11, characterized in that: The circuit structure layer also includes: a plurality of multiplexed data lines; At least one of the multiplexing circuits comprises: nine multiplexing control transistors, gates of the nine multiplexing control transistors are connected to nine different multiplexing control lines, first electrodes of the nine multiplexing control transistors are connected to the same multiplexing data line, and second electrodes of the nine multiplexing control transistors are connected to different data lines among the plurality of data lines; In the sub-display area, nine multiplexing control transistors of the at least one multiplexing circuit are arranged in sequence along the second direction.

14. The display substrate according to claim 1, characterized in that: At least one pixel circuit among the plurality of pixel circuits comprises: a driving transistor, a compensation transistor and a data writing transistor; The gate of the driving transistor is connected to the second electrode of the compensation transistor, the first electrode of the driving transistor is connected to the second electrode of the data writing transistor, and the second electrode of the driving transistor is connected to the first electrode of the compensation transistor; The first electrode of the data writing transistor is connected to the data line, the gate of the data writing transistor is connected to the first scanning line, and the gate of the compensation transistor is connected to the second scanning line; The transistor type of the compensation transistor is different from the transistor types of the drive transistor and the data write transistor.

15. The display substrate according to claim 14, characterized in that: The at least one pixel circuit further includes: a first reset transistor, a second reset transistor and a third reset transistor; The gate of the first reset transistor is connected to the first reset control line, the first electrode of the first reset transistor is connected to the first initial signal line, and the second electrode of the first reset transistor is connected to the second electrode of the driving transistor; The gate of the second reset transistor is connected to the second reset control line, the first electrode of the second reset transistor is connected to the second initial signal line, and the second electrode of the second reset transistor is connected to the first electrode of the light emitting element; The gate of the third reset transistor is connected to the second reset control line, the first electrode of the third reset transistor is connected to the third initial signal line, and the second electrode of the third reset transistor is connected to the first electrode of the driving transistor; The first reset control line and the second reset control line are in the same layer structure, and the first initial signal line, the second initial signal line and the third initial signal line are in different conductive layers.

16. The display substrate according to claim 14, characterized in that: The at least one pixel circuit also includes: a first light-emitting control transistor and a second light-emitting control transistor; the gate of the first light-emitting control transistor and the gate of the second light-emitting control transistor are both connected to the light-emitting control line, the first electrode of the first light-emitting control transistor is connected to the first power line, the second electrode of the first light-emitting control transistor is connected to the first electrode of the driving transistor, the first electrode of the second light-emitting control transistor is connected to the second electrode of the driving transistor, and the second electrode of the second light-emitting control transistor is connected to the first electrode of the light-emitting element.

17. A display device, characterized in that: The invention comprises the display substrate as claimed in any one of claims 1 to 16.

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