Multi-end-face semiconductor device for gate-all-around integrated device

Abstract

The present invention relates to a semiconductor device for an integrated device, such as a nanosheet device, a fork device or a complementary field effect transistor device. The semiconductor device includes a substrate layer (101, 102) and a semiconductor structure partially arranged in a trench formed in the substrate layer and partially protruding from the trench. The protruding end of the semiconductor structure is formed by at least a first end face (103) and a second end face (104) of a semiconductor material of the semiconductor structure, the first end face (103) and the second end face (104) being arranged at an angle to each other. A first layer stack (105) and a second layer stack (106) are arranged on the protruding ends, each layer stack comprising one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner. The first layer stack is disposed on the first end face and the second layer stack is disposed on the second end face. The first step and the second step may be contiguous or may be separated.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, for example, an integrated device including a semiconductor device. The integrated device may be a nanosheet device, or a fork-sheet device, or a complementary field effect transistor (CFET) device. The semiconductor device includes a multi-end-facet semiconductor structure having a multi-end-facet layer stack, wherein the multi-end-facet layer stack forms a FET structure. Background Art

[0002] Integrated devices including transistor structures can improve device performance by increasing the effective transistor width. This can be achieved by using a stack of multiple semiconductor nanosheet channel layers. The effective transistor width depends on the channel width and channel height of each of the nanosheet channel layers and on the total number of nanosheet channel layers used.

[0003] Therefore, one way to increase the effective transistor width is to increase the number of nanosheet channel layers. However, this number is limited by the sheet efficiency of the first nanosheet channel layer in the stack.

[0004] Another way to increase the effective transistor width is to increase the corresponding channel width of the stacked nanosheet channel layers. However, traditionally, (100) nanosheet channel layers are arranged on (100) substrates, which limits the maximum channel width. Summary of the invention

[0005] In view of the above, the present invention aims to increase the effective transistor width in a semiconductor device in different ways. However, at the same time, one object of the present invention is also to not significantly increase the total height of the stack. Another object of the present invention is to provide an integrated device based on the performance improvement of the semiconductor device.

[0006] The above can be achieved by what is described in the independent claim. Advantageous implementations are defined in the dependent claims.

[0007] A first aspect of the present invention provides a semiconductor device, comprising: a substrate layer; a semiconductor structure, partially arranged in a groove formed in the substrate layer and partially protruding from the groove, wherein the protruding end of the semiconductor structure is formed by at least a first end face and a second end face of the semiconductor material of the semiconductor structure, wherein the first end face and the second end face are arranged at a certain angle to each other; a first layer stack and a second layer stack, arranged on the protruding end of the semiconductor structure, wherein the first layer stack and the second layer stack each include one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner, and wherein the first layer stack is arranged on the first end face of the protruding end of the semiconductor structure, and the second layer stack is arranged on the second end face of the protruding end of the semiconductor structure.

[0008] The protruding end of the semiconductor structure may be formed by two or more end faces, wherein in this case, three or more end faces are each arranged at an angle to another end face. The first layer stack may be a first epitaxial layer stack (epitaxial growth), and the second layer stack may be a second epitaxial layer stack.

[0009] By forming a layer stack on at least the first end face and the second end face of two or more end faces of the semiconductor structure, the effective transistor width of the transistor formed based on the first semiconductor layer (e.g., sacrificial layer) and the second semiconductor layer (e.g., channel layer) can be increased without increasing the number of stacked layers, and the height of the stack in the stacking direction of the layers is not significantly increased. Therefore, using the semiconductor device of the first aspect, an integrated device with improved performance can be designed.

[0010] In an implementation of the first aspect, the first end face and the second end face are both {111} crystal end faces or {311} crystal end faces of the semiconductor material of the semiconductor structure.

[0011] In the case where the protruding end of the semiconductor structure is formed by two or more end faces, for example, the third end face and the fourth end face may both be {111} crystal end faces (if the first end face and the second end face are both {311} crystal end faces), or may both be {311} crystal end faces (if the first end face and the second end face are both {111} crystal end faces). These types of end faces enable high-quality epitaxial growth of the first semiconductor layer and the second semiconductor layer.

[0012] In an implementation of the first aspect, the first end surface and the second end surface are adjacent to each other at a common edge and / or form a tip of the protruding end of the semiconductor structure.

[0013] Therefore, the first end face and the second end face can be in direct contact with each other. If there is a third end face, the third end face can be adjacent to the first end face or the second end face at a common edge. If there is also a fourth end face, the fourth end face can also be adjacent to the first end face or the second end face at another common edge (for example, an end face that the third end face is not adjacent to). For example, the third end face can have a common edge with the first end face. The first end face can have this common edge with the third end face, and can also have another common edge with the second end face. Finally, the fourth end face can have another common edge with the second end face. Therefore, the four end faces can be arranged adjacent to each other in the order of the third end face, the first end face, the second end face, and the fourth end face. For example, the protruding end of the semiconductor structure can therefore be an angular shape, such as a triangle-like shape.

[0014] In an implementation of the first aspect, two or more semiconductor layers of the first layer stack and two or more semiconductor layers of the second layer stack are respectively adjacent to each other and form a first multi-end-faceted layer stack, wherein the first multi-end-faceted layer stack includes one or more first multi-end-faceted semiconductor layers and one or more second multi-end-faceted semiconductor layers stacked in an alternating manner.

[0015] Such a multi-end face layer stack can be simultaneously grown with high efficiency and quality on each of at least the first end face and the second end face (optionally the third end face or other end faces).

[0016] In an implementation of the first aspect, the semiconductor device also includes a multi-faceted semiconductor spacer layer arranged on the first multi-faceted layer stack, and a second multi-faceted layer stack arranged on the multi-faceted isolation layer, wherein the second multi-faceted layer stack includes one or more first multi-faceted semiconductor layers and one or more second multi-faceted semiconductor layers stacked in an alternating manner.

[0017] In this manner, the semiconductor device is suitable for forming a CFET device.

[0018] In an implementation of the first aspect, the semiconductor device further includes a dielectric material, wherein the dielectric material separates the first end surface and the first layer stack from the second end surface and the second layer stack.

[0019] Therefore, the first end surface and the second end surface are not in direct contact with each other.

[0020] In an implementation of the first aspect, the first semiconductor layer is made of silicon germanium, and the second semiconductor layer is made of silicon; or the first semiconductor layer is made of silicon germanium having a first germanium content, and the second semiconductor layer is made of silicon germanium having a second germanium content, and the second germanium content is different from the first germanium content.

[0021] In an implementation of the first aspect, the first multi-end-facet semiconductor layer is made of silicon germanium with a germanium content ranging from 15% to 20%, and the multi-end-facet semiconductor spacer layer is made of silicon germanium with a germanium content ranging from 25% to 50%.

[0022] This is beneficial for further integration of the semiconductor device into the CFET device. The second multi-faceted semiconductor layer may be made of silicon.

[0023] In an implementation of the first aspect, the semiconductor structure is made of crystalline silicon.

[0024] The semiconductor structure may be an epitaxially grown epitaxial structure.Other material systems are also possible, such as III-V type semiconductor material systems.

[0025] In an implementation of the first aspect, the substrate layer includes silicon oxide.

[0026] Other substrate layer materials, for example other oxides or materials based on different semiconductor material systems are also possible.

[0027] In an implementation manner of the first aspect, the semiconductor device further includes a dielectric layer, which respectively covers a protruding portion of the semiconductor structure and an outer surface of each layer stack.

[0028] In an implementation of the first aspect, the semiconductor device further includes a gate structure, which is arranged on the substrate layer and surrounds a portion of the semiconductor structure protruding from the trench and each layer stack.

[0029] In this way, a full-surround gate structure can be formed.

[0030] A second aspect of the present invention provides an integrated device including a semiconductor device, wherein: the integrated device is a nanosheet device; or the integrated device is a fork-sheet device; or the integrated device is a complementary field effect transistor (CFET) device.

[0031] The integrated device of the second aspect may have improved device performance due to the increased transistor width enabled by the semiconductor device.

[0032] A third aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising: forming a substrate layer and forming a groove in the substrate layer; forming a semiconductor structure at least partially in the groove, wherein the semiconductor structure has a free end, and the free end is formed by at least a first end face and a second end face of a semiconductor material of the semiconductor structure; epitaxially growing a multi-end face layer stack on the first end face and the second end face of the free end of the semiconductor structure, wherein the multi-end face layer stack comprises one or more first multi-end face semiconductor layers and one or more second multi-end face semiconductor layers stacked in an alternating manner.

[0033] In an implementation of the third aspect, the multi-end surface layer stack is formed on the free end of the semiconductor structure in the trench; or, the multi-end surface layer stack is formed on the free end protruding from the trench.

[0034] In an implementation of the third aspect, the method also includes etching into the multi-end-face layer stack and the semiconductor structure to completely separate the multi-end-face layer stack into a first layer stack and a second layer stack respectively arranged on the first end face and the second end face, wherein the first layer stack and the second layer stack each include one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner.

[0035] In an implementation of the third aspect, the method further includes: epitaxially growing a multi-faceted semiconductor spacer layer on the first multi-faceted layer stack; and epitaxially growing a second multi-faceted layer stack on the multi-faceted spacer layer, wherein the second multi-faceted layer stack includes one or more first multi-faceted semiconductor layers and one or more second multi-faceted semiconductor layers stacked in an alternating manner.

[0036] The method of the third aspect may have an implementation manner corresponding to the implementation manner of the semiconductor device of the first aspect, for example, regarding the various materials used. The method of the third aspect achieves the same advantages as the semiconductor device of the first aspect described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In conjunction with the accompanying drawings, the following description of specific embodiments will illustrate the above aspects and their implementation methods, wherein:

[0038] Figure 1 Two exemplary semiconductor devices provided by the present invention are shown.

[0039] Figure 2 The method for manufacturing a semiconductor device provided by the present invention is shown.

[0040] Figure 3Two exemplary process flows for manufacturing semiconductor devices provided by the present invention are shown.

[0041] Figure 4 continue Figure 3 Two exemplary process flows are shown.

[0042] Figure 5 continue Figure 3 Two exemplary process flows are shown.

[0043] Figure 6 Two exemplary process flows for manufacturing semiconductor devices provided by the present invention are shown. DETAILED DESCRIPTION

[0044] Figure 1 Two examples of the semiconductor device 100 provided by the present invention are shown. Figure 1 An example in (a) and Figure 1 (b) Another example. The semiconductor device 100 can be used to manufacture an integrated device. For example, the integrated device can be a nanosheet device, a fork sheet device, or a CFET device. Different process flows can be used to manufacture such integrated devices including the semiconductor device 100, respectively. The semiconductor device 100 can implement an n-type or p-type FET in the integrated device.

[0045] exist Figure 1 In the two examples shown, the semiconductor device 100 includes a substrate layer 101, which may include or may be made of silicon oxide. In addition, the semiconductor device 100 includes a semiconductor structure 102, which may include or may be made of crystalline silicon. Alternative materials for the semiconductor structure 102 are other silicon-based semiconductor materials or III-V type semiconductor materials. The semiconductor structure 102 may be an epitaxial structure, i.e., may be grown epitaxially. Figure 1 As shown, the semiconductor structure 102 is partially arranged in a trench formed in the substrate layer 101 and partially protrudes from the trench. That is, a first portion of the semiconductor structure 102 is located inside the substrate layer 101 (in the trench), and a second portion of the semiconductor structure 102 is located outside the substrate layer 101 (protruding from the trench in the substrate layer 101). Specifically, the second portion of the semiconductor structure 102 protruding from the trench has a protruding end.

[0046] The protruding end of the semiconductor structure 102 is formed by at least a first end face 103 and a second end face 104 of the semiconductor material of the semiconductor structure 102. As explained above, there may be more than these two end faces. Therefore, the protruding end is a multi-faceted end of the semiconductor substrate 102. The first end face 103 and the second end face 104 are arranged at an angle to each other. The first end face 103 and the second end face 104 can both be {111} crystal end faces of the semiconductor material of the semiconductor substrate 102, and can also be {311} crystal end faces of the semiconductor material of the semiconductor structure 102.

[0047] In addition, the semiconductor device 100 includes a first layer stack 105 and a second layer stack 106, which are arranged on the protruding end of the semiconductor structure 102. Thus, the first layer stack 105 is arranged on the first end face 103, and the second layer stack 106 is arranged on the second end face 104 of the protruding end of the semiconductor structure 102. The first layer stack 105 includes one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner. Similarly, the second layer stack 106 includes one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner. The first semiconductor layer can be made of silicon germanium, and the second semiconductor layer can be made of silicon. Alternatively, the first semiconductor layer can be made of silicon germanium with a first germanium content, and the second semiconductor layer can be made of silicon germanium with a second germanium content, which is different from the first germanium content. Alternatively, the first semiconductor material layer and the second semiconductor material layer can be based on different semiconductor material systems, such as III-V type semiconductor material systems.

[0048] exist Figure 1 In the first example shown in (a), the first end face 103 and the second end face 104 are adjacent and thus may have a common edge. In this case, two or more semiconductor layers of the first layer stack 105 (i.e., one or more first semiconductor layers and one or more second semiconductor layers of the first layer stack 105) and two or more semiconductor layers of the second layer stack 106 (i.e., one or more first semiconductor layers and one or more second semiconductor layers of the second layer stack 106) are adjacent to each other, respectively. That is, each first semiconductor layer of the first layer stack 105 is adjacent to the first semiconductor layer of the second layer stack 106, and each second semiconductor layer of the first layer stack 105 is adjacent to the second semiconductor layer of the second layer stack 106. In this way, the first layer stack 105 and the second layer stack 106 may constitute a multi-end face layer stack, which is arranged on the protruding end of the semiconductor structure 102 above the two end faces 103 and 104.

[0049] exist Figure 1In the second example shown in (b), the first end face 103 and the second end face 104 are not adjacent and are separated from each other. Therefore, the first end face 103 and the second end face 104 do not have or form a common edge. For example, the first end face 103 and the second end face 104 can be separated by a trench in the semiconductor structure 102 (as shown in the figure), or can be separated from each other by a dielectric material therebetween (which can be filled in the trench shown), as described below.

[0050] Figure 2 A general method 200 for manufacturing the semiconductor device 100 of the present invention is shown (particularly Figure 1 The method 200 includes a step 201 of forming a substrate layer 101 and further forming a trench in the substrate layer 101. The substrate layer 101 may be a top portion of a substrate, wherein a bottom portion of the substrate may be made of a crystalline semiconductor material. For example, the trench may be etched into the substrate layer 101, wherein photolithography may be used. The method 200 also includes a step 202 of forming a semiconductor structure 102 at least partially in the trench. For example, the semiconductor structure 102 may be epitaxially grown into the trench. When the semiconductor structure 102 is formed (e.g., epitaxially grown), the semiconductor structure 102 is provided with a free end. The free end is formed (at least at some point during the formation process) by at least a first end face 103 and a second end face 104 of the semiconductor material of the semiconductor structure 102. For example, as a result of epitaxially growing the semiconductor structure 102 into the trench, the first end face 103 and the second end face 104 may be automatically grown at some point.

[0051] The method 200 further comprises a step 203 of epitaxially growing a multi-end facet layer stack on the first end face 103 and the second end face 104 of the free end of the semiconductor structure 102. Thus, as described above, the multi-end facet layer stack may consist of a first layer stack 105 and a second layer stack 106. The epitaxial growth may be performed simultaneously on at least the first end face 103 and the second end face 104. The multi-end facet layer stack comprises one or more first multi-end facet semiconductor layers and one or more second multi-end facet semiconductor layers stacked in an alternating manner. The general method 200 may directly produce Figure 1 (a) The semiconductor device 100 , wherein the first layer stack 105 and the second layer stack 106 constitute a multi-end layer stack, and the first multi-end semiconductor layer and the second multi-end semiconductor layer constitute the first semiconductor layer and the second semiconductor layer of the first layer stack 105 and the second layer stack 106 , respectively.

[0052] To obtain Figure 1(b) The semiconductor device 100, the method 200 may further include the following steps: partially etching into the multi-end surface layer stack and the semiconductor structure 102, so as to completely separate the multi-end surface layer stack into the first layer stack 105 and the second layer stack 106, that is, to separate the first layer stack 105 and the second layer stack 106 constituting the multi-end surface layer stack. The first layer stack 105 and the second layer stack 106 are arranged on the first end surface 103 and the second end surface 104, respectively.

[0053] Figure 3 , Figure 4 and Figure 5 Two exemplary process flows are shown, wherein these process flows may be Figure 2 Specific implementations of the method 200 are shown. Two exemplary process flows can be used to manufacture the semiconductor device 100. Both exemplary process flows start with a substrate layer 101 (top left), which can be made of silicon dioxide and includes a trench into which a semiconductor structure 102 has been partially grown. The semiconductor structure 102 can be made of silicon, for example. The growth of the semiconductor structure 102 can be epitaxial, for example, by molecular beam epitaxy or chemical vapor deposition.

[0054] The first exemplary process flow continues to step 1a, in which the semiconductor structure 102 is further grown or formed in the trench, thereby forming a first end face 103 and a second end face 104. For example, the first end face 103 and the second end face 105 can be automatically formed due to the epitaxial growth of the semiconductor structure 102 in the trench. The first end face 103 and the second end face 104 are now adjacent at the common edge 301, and thus form the tip of the free end of the semiconductor structure 102. In the first exemplary process flow, the first end face 103 and the second end face 104 can specifically be a {311} crystal end face of the semiconductor material of the semiconductor substrate 102. Such a semiconductor material can be a silicon material, or a silicon-based material, or a III-V type semiconductor material.

[0055] The first exemplary process flow continues to step 2a, wherein a first layer stack 105 and a second layer stack 106 are formed on the first end face 103 and the second end face 104, respectively, by forming a multi-end face layer stack 304 on the free end of the semiconductor substrate 102. For example, the first layer stack 105 and the second layer stack 106 can be formed by being adjacent to each other as described above to form the multi-end face layer stack 304. Specifically, each semiconductor layer of each layer stack 105 and 106 is adjacent to the corresponding semiconductor layer of another layer stack 106 and 105. It should be noted that in this first exemplary process flow, the multi-end face layer stack 304 is formed on the free end of the semiconductor structure 102 in the trench.

[0056] The first exemplary process flow continues to step 3a, in which the substrate layer 101 is partially removed, for example by etching and optionally using photolithography, on both sides of the semiconductor structure 102. In this way, the first end face 103, the second end face 104 and the multi-end face layer stack on these end faces 103 and 104 are exposed, so that these end faces 103 and 104 and the multi-end face layer stack 304 protrude from the trench formed in the substrate layer 101.

[0057] The second exemplary process flow continues from the starting point (top left) to step 1b, wherein the substrate layer 101 is etched to be flush with the semiconductor structure 101, and the semiconductor structure 102 is further grown or formed, so that a first end face 103 and a second end face 104 are formed, for example, these end faces 103 and 104 grow automatically due to the epitaxial growth of the semiconductor structure 102. Similarly, the first end face 103 and the second end face 104 are adjacent at the common edge 301 and form the tip of the free end of the semiconductor structure 102. However, unlike the first end face 103 and the second end face 103 in the first exemplary process flow, which are formed in the trench, in the second exemplary process flow, the first end face 103 and the second end face 104 protrude from the trench. In the second exemplary process flow, the first end face 103 and the second end face 104 can be specifically {111} crystal end faces of the semiconductor material of the semiconductor structure 102. Such a semiconductor material can be a silicon material, or a silicon-based material, or a III-V type semiconductor material.

[0058] The second exemplary process flow continues to step 2b, where a first layer stack 105 and a second layer stack 106 are formed on the first end surface 103 and the second end surface 104, respectively, by forming a multi-end surface layer stack 304 similar to the above description. The multi-end surface layer stack 304 is formed on the free ends of the semiconductor structure 102 protruding from the trench.

[0059] The second exemplary process flow continues to step 3 b where a spin-on-carbon (SOC) layer 302 (or similar capping layer) and a hard mask layer 303 on top of the SOC layer 302 are deposited on the substrate layer 101 and over the semiconductor structure 102 including the multi-faceted layer stack 304 .

[0060] The second exemplary process flow continues to step 4b, where the SOC layer 302 and the hard mask layer 303 are used to respectively etch the sides of the semiconductor structure 102 and the multi-faceted layer stack 304. Furthermore, the SOC layer 302 and the hard mask layer 303 are then removed.

[0061] exist Figure 4, the intermediate semiconductor device 100 produced by step 3a of the first exemplary process flow and by step 4b of the second exemplary process flow is shown again, and these intermediate semiconductor devices 100 are similar or identical. Then, Figure 3 The two exemplary process flows continue to a common step 5, in which a dielectric layer 401 is formed. The dielectric layer 401 covers the protruding portion of the semiconductor structure 102 and the outer surface of the multi-end layer stack 304 (composed of the first layer stack 105 and the second layer stack 106), respectively. In addition, in step 5, a gate structure 402 is formed on the substrate layer 101, wherein the gate structure 402 surrounds the portion of the semiconductor structure 102 protruding from the trench and the multi-end layer stack 304 disposed on the semiconductor structure 102, as well as the dielectric layer 401. The gate structure 402 can be made of amorphous silicon and can be a dummy gate structure (which can be removed in a subsequent process step and can be replaced by a metal gate structure). The dielectric layer 401 can be silicon oxide or a similar material.

[0062] Figure 4 The process steps shown can be used to manufacture an integrated device, which is a nanosheet device and includes a semiconductor device 100. Then, Figure 4 The process flow can be further continued, for example, in a conventional manner. For example, the same process steps for manufacturing conventional nanosheet devices can be followed.

[0063] Also in Figure 5 , again showing the intermediate semiconductor devices produced by step 3a of the first exemplary process flow and by step 4b of the second exemplary process flow, which are similar or identical. Then, Figure 3 The two exemplary process flows may optionally continue with common steps 6 to 10 (instead of Figure 4 The common step shown in 5).

[0064] In step 6, a SOC layer 503 and two hard mask structures 502 are formed on the substrate layer 101 and around the semiconductor structure 102, wherein the semiconductor structure 102 includes a multi-end layer stack 304 (composed of at least a first layer stack 105 and a second layer stack 106).

[0065] In step 7, the SOC layer 503 and the hard mask structure 502 are used to form a groove 504. Specifically, the groove 504 can be etched into the multi-end surface layer stack and the semiconductor structure 102 to completely separate the multi-end surface layer stack 304 into a first layer stack 105 and a second layer stack 106, which are arranged on the first end surface 103 and the second end surface 104, respectively.

[0066] In step 8, the SOC layer 503 and the hard mask structure 502 are removed, for example, by selectively etching the SOC and / or hard mask material.

[0067] In step 9, a dielectric material 501 is deposited into the trench 504 and over the semiconductor structure 102 and the first layer stack 105 and the second layer stack 106 protruding from the substrate layer 101. The dielectric material 501 may be silicon oxide or a similar material.

[0068] In step 10, the portion of dielectric material 501 not formed in trench 504 is removed. For example, this is achieved by performing an isotropic etch, which may include photolithographic patterning. Thus, dielectric material 501 now separates first end face 103 and first layer stack 105 from second end face 104 and second layer stack 106.

[0069] Figure 5 The process steps shown can be used to manufacture an integrated device that is a fork-piece device and includes the semiconductor device 100. Figure 5 The process flow can be continued further, for example, with the same process steps for manufacturing a conventional fork blade device.

[0070] Figure 6 A third exemplary process flow and a fourth exemplary process flow for manufacturing a semiconductor device 100 provided by the present invention are shown.

[0071] The third and fourth exemplary process flows both start with a substrate layer 101 (top left), which may be made of silicon dioxide, and a portion of a semiconductor structure 102 is grown in a trench in the substrate layer 101. The semiconductor structure 102 may be epitaxially grown and / or may be made of crystalline silicon.

[0072] The third exemplary process flow continues to step 1c, where a first end face 103 and a second end face 104 are formed on the semiconductor substrate 102 in the trench. This may be the result of epitaxial growth of the semiconductor substrate 102, but may also be achieved in another way.

[0073] The third exemplary process flow continues to step 2c, where, similar to the above description, the first multi-facet layer stack 304 is epitaxially grown on the first end face 103 and the second end face 104, respectively. In addition, the multi-facet semiconductor spacer layer 602 is epitaxially grown on the first multi-facet layer stack 304, and the second multi-facet layer stack is epitaxially grown 601 on the multi-facet spacer layer 602. The first multi-facet layer stack 304 and the second multi-facet layer stack 601 each include one or more first multi-facet semiconductor layers and one or more second multi-facet semiconductor layers stacked in an alternating manner. The first multi-facet semiconductor layer can be made of silicon germanium with a germanium content in the range of 15% to 20%. The multi-facet semiconductor spacer layer 602 can be made of silicon germanium with a germanium content in the range of 25% to 50%. The second multi-facet semiconductor spacer layer can be made of silicon.

[0074] The third exemplary process flow continues to step 3 c , where the substrate layer 101 is etched on both sides of the semiconductor substrate 102 , the multi-faceted layer stack 304 , 601 and the multi-faceted semiconductor spacer layer 602 to expose these components and cause them to protrude from the substrate layer 101 .

[0075] The fourth exemplary process flow continues to step 1d, where the first end surface 103 and the second end surface 104 are formed on the semiconductor substrate 102 in the trench. Step 1d is similar to step 1c.

[0076] The fourth exemplary process flow continues to step 2d, where the substrate layer 101 is first etched so that the semiconductor substrate 102 having the first end face 103 and the second end face 104 protrudes from the substrate layer 101. Then, the first multi-end face layer stack 304, the multi-end face semiconductor spacer layer 602 and the second multi-end face layer stack 601 are grown on the protruding ends of the semiconductor structure 102.

[0077] The fourth exemplary process flow continues to step 3d where the SOC layer 302 and the hard mask layer 303 are formed on the substrate layer 101 and over the semiconductor substrate 102 with the multi-facet layer stack and the multi-facet spacer layers 304 , 601 , 602 , respectively.

[0078] The fourth exemplary process flow continues to step 4d, wherein the substrate layer 101 is etched on both sides of the semiconductor substrate 102, the multi-faceted layer stacks 304, 601 and the multi-faceted semiconductor spacer 602 to form a pillar-like or fin-like structure. As a result, these multi-faceted layer stacks 304, 601 and the multi-faceted semiconductor spacer 602 are narrowed, wherein a similar structure as that produced in step 3c of the third exemplary process flow is obtained.

[0079] The third exemplary process flow and the fourth exemplary process flow may be used to manufacture an integrated device that is a CFET device and includes the semiconductor device 100. For example, both the third exemplary process flow and the fourth exemplary process flow may then continue to process steps as also used in conventional monolithic CFET device production methods.

[0080] The invention has been described in conjunction with various embodiments as examples and implementations. However, from a study of the drawings, the invention and the independent claims, other variations will be understood and implemented by those skilled in the art in implementing the claimed subject matter. In the claims and in the specification, the word "comprising" does not exclude other elements or steps, and "a" does not exclude a plurality. A single element or other unit may fulfil the functions of several entities or items described in the claims. The enumeration of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. A semiconductor device, characterized in that: include: substrate layer; a semiconductor structure partially disposed in a trench formed in the substrate layer and partially protruding from the trench, wherein the protruding end of the semiconductor structure is formed by at least a first end surface and a second end surface of the semiconductor material of the semiconductor structure, wherein the first end surface and the second end surface are arranged at a certain angle to each other; a first epitaxial layer stack and a second epitaxial layer stack, the first epitaxial layer stack and the second epitaxial layer stack being arranged on a protruding end of the semiconductor structure, Wherein, the first epitaxial layer stack and the second epitaxial layer stack each include one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner, and wherein the first epitaxial layer stack is arranged on the first end face of the protruding end of the semiconductor structure, and the second epitaxial layer stack is arranged on the second end face of the protruding end of the semiconductor structure.

2. The semiconductor device according to claim 1, wherein: The semiconductor structure is a silicon-based structure, wherein the first end face and the second end face are both {111} crystal end faces or {311} crystal end faces of a silicon-based material of the silicon-based structure.

3. The semiconductor device according to claim 1 or 2, characterized in that: The first end surface and the second end surface adjoin at a common edge and / or form a tip of the protruding end of the semiconductor structure.

4. The semiconductor device according to any one of claims 1 to 3, characterized in that The two or more semiconductor layers of the first epitaxial layer stack and the two or more semiconductor layers of the second epitaxial layer stack are respectively adjacent to each other and form a first multi-end-faceted layer stack, which includes one or more first multi-end-faceted semiconductor layers and one or more second multi-end-faceted semiconductor layers stacked in an alternating manner.

5. The semiconductor device according to claim 3 or 4, characterized in that: It also includes a multi-end-faceted semiconductor spacer layer arranged on the first multi-end-faceted layer stack, and a second multi-end-faceted layer stack arranged on the multi-end-faceted isolation layer, wherein the second multi-end-faceted layer stack includes one or more first multi-end-faceted semiconductor layers and one or more second multi-end-faceted semiconductor layers stacked in an alternating manner.

6. The semiconductor device according to claim 1 or 2, characterized in that: Also included is a dielectric material that separates the first end surface and the first epitaxial layer stack from the second end surface and the second epitaxial layer stack.

7. The semiconductor device according to any one of claims 1 to 6, characterized in that: The first semiconductor layer is made of silicon germanium, and the second semiconductor layer is made of silicon; or The first semiconductor layer is made of silicon germanium with a first germanium content, and the second semiconductor layer is made of silicon germanium with a second germanium content, which is different from the first germanium content.

8. The semiconductor device according to claim 7 and 5, characterized in that The first semiconductor layer is made of silicon germanium with a germanium content ranging from 15% to 20%, and the multi-end semiconductor spacer layer is made of silicon germanium with a germanium content ranging from 25% to 50%.

9. The semiconductor device according to any one of claims 1 to 8, characterized in that The semiconductor structure is made of crystalline silicon.

10. The semiconductor device according to any one of claims 1 to 9, characterized in that: The substrate layer includes silicon oxide.

11. The semiconductor device according to any one of claims 1 to 10, characterized in that: A dielectric layer is also included, and the dielectric layer covers the protruding portion of the semiconductor structure and the outer surface of each epitaxial layer stack respectively.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that Also included is a gate structure disposed on the substrate layer and surrounding a portion of the semiconductor structure protruding from the trench and each epitaxial layer stack.

13. An integrated device comprising a semiconductor device, characterized in that: The integrated device is a nanosheet device, and the semiconductor device is according to claim 3 or 4; or The integrated device is a fork-piece device, and the semiconductor device is according to claim 6; or The integrated device is a complementary field effect transistor (CFET) device, and the semiconductor device is according to claim 5 or 8.

14. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a substrate layer and forming a trench in the substrate layer; forming a semiconductor structure at least partially in the trench, Wherein, the semiconductor structure has a free end, and the free end is formed by at least a first end surface and a second end surface of a semiconductor material of the semiconductor structure; epitaxially growing a multi-end face layer stack on the first end face and the second end face of the free end of the semiconductor structure, The multi-end-facet layer stack includes one or more first multi-end-facet semiconductor layers and one or more second multi-end-facet semiconductor layers stacked in an alternating manner.

15. The method according to claim 14, characterized in that: The multi-end surface layer stack is formed in the trench on the free end of the semiconductor structure; or The multi-end layer stack is formed on the free end protruding from the groove.

16. The method according to claim 14 or 15, characterized in that Also includes: etching into the multi-end surface layer stack and the semiconductor structure to completely separate the multi-end surface layer stack into a first layer stack and a second layer stack respectively arranged on the first end surface and the second end surface, The first layer stack and the second layer stack each include one or more first semiconductor layers and one or more second semiconductor layers stacked in an alternating manner.

17. The method according to claim 14 or 15, characterized in that Also includes: epitaxially growing a multi-faceted semiconductor spacer layer on the first multi-faceted layer stack; epitaxially growing a second multi-faceted layer stack on the multi-faceted spacer layer, The second multi-end-facet layer stack includes one or more first multi-end-facet semiconductor layers and one or more second multi-end-facet semiconductor layers stacked in an alternating manner.

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