Display panel, preparation method thereof and display device

Abstract

The invention discloses a display panel, a preparation method thereof and a display device. The display panel comprises: a first substrate (2); a driving circuit layer (22) including a plurality of thin film transistors (TFTs); the planarization layer (3) comprises a first part (301), a second part (302) and a third part (303); the thickness of the first part (301) is smaller than that of the second part (302), and the thickness of the third part (303) is smaller than that of the second part (302); the first portion (301) comprises a first via (304); the light emitting device (4) comprises an anode (401); the anode (401) covers the first part (301) and the side surface of the second part (302) adjacent to the first part (301), and the included angle (alpha) between the surface of the side, deviating from the first substrate (2), of the part, covering the side surface of the second part (302), of the anode (401) and the plane parallel to the first substrate (2) is greater than 0; the anode (401) is electrically connected with a thin film transistor (TFT) through a first via hole (304); the orthographic projection of the pixel definition layer (5) on the first substrate (2) covers the orthographic projection of the first via hole (304) on the first substrate (2).

Description

Display panel and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a manufacturing method thereof, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) devices have become a highly competitive and promising next-generation display technology due to their advantages such as all-solid-state structure, high brightness, full viewing angle, fast response speed, and wide operating temperature range.

[0003] Currently, OLED display products include multiple sub-pixels, each of which includes an OLED device. However, there is a problem of lateral light leakage between adjacent sub-pixels, which affects the display effect.

[0004] Summary of the Invention

[0005] An embodiment of the present disclosure provides a display panel including a plurality of sub-pixels, the display panel including:

[0006] a first substrate;

[0007] A driving circuit layer, located on one side of the first substrate, comprising a plurality of thin film transistors;

[0008] The planarization layer is located on a side of the first substrate facing away from the driving circuit layer, and includes: a plurality of first portions, a second portion, and a third portion; in a direction perpendicular to the first substrate, the thickness of the first portion is less than the thickness of the second portion, and the thickness of the third portion is less than the thickness of the second portion; the orthographic projection of the second portion on the first substrate surrounds the orthographic projection of the first portion on the first substrate; the orthographic projection of the first portion on the first substrate covers the orthographic projection of the light-emitting area of ​​the sub-pixel on the first substrate, and the orthographic projection of the third portion on the first substrate falls within the orthographic projection of the first substrate within the region between the light-emitting areas of adjacent sub-pixels; the first portion includes a first via hole extending through the thickness thereof;

[0009] A plurality of light-emitting devices are located on a side of the planarization layer facing away from the first substrate; the light-emitting devices include an anode; the anode covers the first portion and a side surface of a second portion adjacent to the first portion, and the angle between a surface of a portion of the side surface of the anode covering the second portion facing away from the first substrate and a plane parallel to the first substrate is greater than 0; the anode is electrically connected to the thin film transistor through a first via hole;

[0010] The pixel definition layer is located on the side of the anode away from the planarization layer; the orthographic projection of the pixel definition layer on the first substrate covers the orthographic projection of the first via hole on the first substrate.

[0011] In some embodiments, an angle between a surface of a portion of the side of the anode covering the second portion facing away from the first substrate and a plane parallel to the first substrate is greater than or equal to 30° and less than or equal to 50°.

[0012] In some embodiments, in a direction perpendicular to the first substrate, a thickness of the first portion is equal to a thickness of the third portion.

[0013] In some embodiments, in a direction perpendicular to the first substrate, a difference between a thickness of the second portion and a thickness of the first portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0014] In some embodiments, the pixel definition layer includes multiple first opening areas and multiple second opening areas; the orthographic projection of the first opening area on the first substrate falls within the orthographic projection of the first part on the first substrate, and the orthographic projection of the second opening area on the first substrate falls within the orthographic projection of the third part on the first substrate; the orthographic projection of the second part on the first substrate falls within the orthographic projection of the pixel definition layer on the first substrate.

[0015] In some embodiments, a ratio of an area where an orthographic projection of the second portion on the first substrate overlaps with an orthographic projection of the pixel definition layer on the first substrate to an area of ​​the orthographic projection of the pixel definition layer on the first substrate is less than or equal to 76%.

[0016] In some embodiments, a maximum distance between a surface of the pixel definition layer facing away from the first substrate and the first portion is greater than or equal to 1.5 micrometers and less than or equal to 2.5 micrometers.

[0017] In some embodiments, the display panel further includes: a driving circuit layer, located between the first substrate and the planarization layer, including a plurality of thin film transistors;

[0018] The first portion includes a first via hole extending through the thickness of the first portion, and the anode is electrically connected to the thin film transistor through the first via hole;

[0019] The orthographic projection of the pixel definition layer on the first substrate covers the orthographic projection of the first via hole on the first substrate.

[0020] In some embodiments, the display panel further comprises:

[0021] A plurality of auxiliary electrodes are arranged in the same layer as the anode and are insulated from each other; the orthographic projections of the auxiliary electrodes on the first substrate fall within the orthographic projections of the second portion on the first substrate.

[0022] In some embodiments, the pixel definition layer further includes a plurality of third opening regions, and the orthographic projections of the third opening regions on the first substrate fall within the orthographic projections of the auxiliary electrodes on the first substrate.

[0023] In some embodiments, the pixel definition layer includes a plurality of fourth portions and a plurality of fifth portions, the fourth portion has a third opening area, and the orthographic projection of the fifth portion on the first substrate covers the orthographic projection of the first via hole on the first substrate;

[0024] The fourth part and the fifth part are connected as one piece.

[0025] In some embodiments, the transmittance of the pixel definition layer to light with a wavelength greater than or equal to 380 nanometers and less than or equal to 700 nanometers is less than 5%.

[0026] In some embodiments, the display panel further includes: a second substrate located on a side of the pixel definition layer facing away from the first substrate; and a filling layer located between the second substrate and the pixel definition layer.

[0027] In some embodiments, the distance h between adjacent first opening regions satisfies: h≥a×b / (db);

[0028] Wherein, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate; d is the distance between the second part and the first part in a direction perpendicular to the first substrate; and b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate.

[0029] In some embodiments, the distance h between adjacent first opening regions satisfies: h≥a×b / (cb);

[0030] Among them, a is the distance between the second substrate and the anode covering the first part in the direction perpendicular to the first substrate; c is the maximum distance between the side of the pixel definition layer away from the first substrate and the first part in the direction perpendicular to the first substrate; b is the maximum width of the first opening area in the direction parallel to the plane of the first substrate.

[0031] In some embodiments, the display panel includes a curved region;

[0032] In the curved area, the distance h between two adjacent first opening areas satisfies:

[0033]

[0034] Wherein, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate; d is the distance between the second part and the first part in a direction perpendicular to the first substrate; b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate; and K is the curvature of the curved area.

[0035] In some embodiments, the display panel includes a curved region;

[0036] In the curved area, the distance h between two adjacent first opening areas satisfies:

[0037]

[0038] Wherein, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate, c is the maximum distance between the side of the pixel definition layer facing away from the first substrate and the first part in a direction perpendicular to the first substrate, b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate, and K is the curvature of the curved area.

[0039] An embodiment of the present disclosure provides a method for manufacturing a display panel, comprising:

[0040] A driving circuit layer is formed on one side of the first substrate; the driving circuit layer includes a plurality of thin film transistors;

[0041] A pattern of a planarization layer is formed on a side of the driving circuit layer facing away from the first substrate; wherein the planarization layer includes: a plurality of first portions, a second portion, and a third portion; in a direction perpendicular to the first substrate, the thickness of the first portion is less than the thickness of the second portion, and the thickness of the third portion is less than the thickness of the second portion; the orthographic projection of the second portion on the first substrate surrounds the orthographic projection of the first portion on the first substrate; the orthographic projection of the first portion on the first substrate covers the orthographic projection of the light-emitting area of ​​the sub-pixel on the first substrate, and the orthographic projection of the third portion on the first substrate falls within the orthographic projection of the first substrate within the region between the light-emitting areas of adjacent sub-pixels; and the first portion includes a first via hole extending through the thickness thereof;

[0042] A plurality of anodes are formed on a side of the planarization layer facing away from the first substrate; the anodes cover the first portion and a side surface of a second portion adjacent to the first portion, and an angle between a surface of a portion of the side surface of the anode covering the second portion facing away from the first substrate and a plane parallel to the first substrate is greater than 0; the anodes are electrically connected to the thin film transistor through a first via hole;

[0043] A pattern of a pixel definition layer is formed on a side of the anode facing away from the planarization layer; the orthographic projection of the pixel definition layer on the first substrate covers the orthographic projection of the first via hole on the first substrate.

[0044] In some embodiments, forming a pattern of a planarization layer on a side of the driving circuit layer facing away from the first substrate specifically includes:

[0045] Depositing a planarization layer material on a side of the driving circuit layer away from the first substrate to form a planarization layer;

[0046] A half-tone mask process is used on the planarization layer to form a first portion, a second portion and a third portion.

[0047] In some embodiments, forming a pattern of a pixel definition layer on a side of the anode facing away from the planarization layer specifically includes:

[0048] forming a pixel definition layer on a side of the anode facing away from the planarization layer;

[0049] A graphic process is used to form multiple first opening areas and multiple second opening areas; the orthographic projection of the first opening area on the first substrate falls within the orthographic projection of the first part on the first substrate, the orthographic projection of the second opening area on the first substrate falls within the orthographic projection of the third part on the first substrate, and the orthographic projection of the second part on the first substrate falls within the orthographic projection of the pixel definition layer on the first substrate.

[0050] A display device provided by an embodiment of the present disclosure includes the display panel provided by an embodiment of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0052] FIG1 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0053] FIG2 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0054] FIG3 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0055] FIG4 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0056] FIG5 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0057] FIG6 is a schematic diagram of relevant dimensions of a display panel provided by an embodiment of the present disclosure;

[0058] FIG7 is a schematic diagram of relevant dimensions of another display panel provided by an embodiment of the present disclosure;

[0059] FIG8 is a schematic diagram of relevant dimensions of another display panel provided by an embodiment of the present disclosure;

[0060] FIG9 is a schematic diagram of relevant dimensions of another display panel provided by an embodiment of the present disclosure;

[0061] FIG10 is a schematic diagram of a first opening area of ​​a display panel provided by an embodiment of the present disclosure;

[0062] FIG11 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0063] FIG12 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0064] FIG13 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0065] FIG14 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0066] FIG15 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0067] FIG16 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0068] FIG17 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0069] FIG18 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0070] FIG19 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0071] FIG20 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0072] FIG21 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0073] FIG22 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0074] FIG23 is a schematic diagram of a first opening area of ​​another display panel provided by an embodiment of the present disclosure;

[0075] FIG24 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0076] FIG25 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0077] FIG26 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0078] FIG27 is a schematic structural diagram of another display panel provided by an embodiment of the present disclosure;

[0079] FIG28 is a schematic flow chart of a method for manufacturing a display panel provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0081] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0082] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0083] An embodiment of the present disclosure provides a display panel, as shown in FIG1 , including a plurality of sub-pixels. The display panel includes:

[0084] a first substrate 2;

[0085] The driving circuit layer 22 is located on one side of the first substrate 2 and includes a plurality of thin film transistors TFT;

[0086] The planarization layer 3 is located on a side of the first substrate 2 facing away from the driving circuit layer 22 and includes: a plurality of first portions 301, a second portion 302, and a third portion 303. In a direction perpendicular to the first substrate 2, a thickness l1 of the first portion 301 is less than a thickness l2 of the second portion 302, and a thickness l3 of the third portion 303 is less than a thickness l2 of the second portion 302. The orthographic projection of the second portion 302 on the first substrate 2 surrounds the orthographic projection of the first portion 301 on the first substrate 2. The orthographic projection of the first portion 301 on the first substrate 2 covers the orthographic projection of the light-emitting area 1 of the sub-pixel on the first substrate 2, and the orthographic projection of the third portion 303 on the first substrate 2 falls within the orthographic projection of the first substrate 2 between the light-emitting areas 1 of adjacent sub-pixels. The first portion 301 includes a first via 304 extending through its thickness.

[0087] Multiple light-emitting devices 4 are located on a side of the planarization layer 3 facing away from the first substrate 2. The light-emitting devices 4 include an anode 401. The anode 401 covers the first portion 301 and the side of the second portion 302 adjacent to the first portion 301. The angle α between the surface of the portion of the anode 401 covering the side of the second portion 302 facing away from the first substrate 2 and the plane parallel to the first substrate 2 is greater than 0. The anode 401 is electrically connected to the thin-film transistor TFT through the first via 304.

[0088] The pixel definition layer 5 is located on the side of the anode 401 away from the planarization layer 3 ; the orthographic projection of the pixel definition layer 5 on the first substrate 2 covers the orthographic projection of the first via hole on the first substrate 2 .

[0089] For ease of distinction, as shown in FIG1 , in the embodiment of the present disclosure, the portion of the anode 401 covering the side of the second portion 302 is referred to as a first anode portion 4011 , and the portion of the anode 401 covering the first portion 301 is referred to as a second anode portion 4012 .

[0090] The display panel provided by the embodiment of the present disclosure has a planarization layer including a first part and a second part that are adjacent and have different thicknesses. The first part corresponds to the light-emitting area of ​​the sub-pixel, that is, the planarization layer has a recessed portion in the area corresponding to the light-emitting area of ​​the sub-pixel, so that the angle between the side of the second part and the surface of the first part facing away from the first substrate is greater than 0. In this way, when the anode covers the side of the second part adjacent to the first part, the angle α between the surface of the first anode part facing away from the first substrate and the plane parallel to the first substrate is greater than 0, that is, the angle between the first anode part and the second anode part is greater than 0. The part of the anode covering the side of the second part can serve as a reflective layer to reflect the light-emitting device to emit light laterally (towards the direction of the first part). For example, in Figure 1, the first anode part 4011 reflects the light m, thereby reducing lateral light leakage of the sub-pixel and improving the display effect. Furthermore, the planarization layer further includes a third portion adjacent to the second portion and having a different thickness than the second portion. The third portion is located in the region between the sub-pixel light-emitting regions, i.e., in the region between the sub-pixel light-emitting regions. The planarization layer has a recessed portion, thereby increasing the step difference between the light-emitting region of the sub-pixel and the region outside the light-emitting region of the sub-pixel. During the cell alignment process, the recessed portion can accommodate filler material, which is beneficial for filling and draining the filler material. It can also act as a pressure divider during the cell alignment process, avoiding damage to the film layers on one side of the array substrate during the pressing process, thereby improving the yield of the top-emitting display panel. Moreover, for a flexible display panel, the provision of the recessed region can reduce the force applied to the region corresponding to the light-emitting region of the sub-pixel during the bending process of the display panel, thereby facilitating the bending and fracture of the film layers in the region corresponding to the light-emitting region of the sub-pixel. In addition, a first via hole is provided in the first portion to electrically connect the anode to the thin film transistor, i.e., the first via hole is formed in the region where the planarization layer is thinner. The depth of the first via hole is shallow, which can reduce the difficulty of preparing the first via hole and can also reduce the thickness of the photoresist coating during the first via hole preparation process, reducing the risk of residual photoresist after stripping. Furthermore, the orthographic projection of the pixel definition layer on the first substrate covers the orthographic projection of the first via hole on the first substrate, that is, the pixel definition layer covers the area corresponding to the first via hole, thereby planarizing the area of ​​the first via hole.

[0091] In some embodiments, as shown in FIG. 1 , the light emitting device 4 further includes: a light emitting functional layer 402 located on a side of the anode 401 away from the first portion 301 , and a cathode 403 located on a side of the light emitting functional layer 402 away from the anode 401 .

[0092] In a specific implementation, the light-emitting device is, for example, an organic light-emitting diode device, and the light-emitting functional layer includes an organic light-emitting layer, and may further include an electron injection layer, an electron transport layer, a hole transport layer, a hole injection layer, and the like.

[0093] In some embodiments, the angle between the side surface of the second portion 302 and the surface of the first portion 301 facing away from the first substrate 2 is greater than or equal to 30° and less than or equal to 50°. Accordingly, the angle α between the surface of the portion of the anode 401 covering the side surface of the second portion 302 facing away from the first substrate 2 and a plane parallel to the first substrate 2 is greater than or equal to 30° and less than or equal to 50°. That is, the angle α between the first anode portion 4011 and the second anode portion 4012 is greater than or equal to 30° and less than or equal to 50°.

[0094] It should be noted that when the angle α is larger, the reflection angle of the first anode portion is larger, thereby improving the effect of preventing lateral light leakage. However, an angle that is too large will also cause the light emitted from the luminous area of ​​the sub-pixel farther away to be reflected by the first anode portion at the angle to the luminous areas of other sub-pixels, resulting in light leakage. In the display panel provided by the embodiment of the present disclosure, the angle α between the first anode portion 4011 and the second anode portion 4012 is greater than or equal to 30° and less than or equal to 50°, thereby ensuring the effect of using the first anode portion to alleviate lateral light leakage.

[0095] In some embodiments, as shown in FIG. 1 , in a direction perpendicular to the first substrate 2 , a thickness l1 of the first portion 301 is equal to a thickness l3 of the third portion 303 .

[0096] In a specific implementation, the planarization layer can be made of, for example, acrylic or polyimide, facilitating fabrication using photolithography. A half-tone mask process can be used to fabricate the planarization layer, with the first and second portions having different exposure doses, and the second and third portions having different exposure doses. When the first and third portions have the same thickness, the exposure doses for the first and third portions are the same, reducing the difficulty of fabricating the planarization layer.

[0097] In some embodiments, in a direction perpendicular to the first substrate 2 , a difference between a thickness l2 of the second portion 302 and a thickness l1 of the first portion 301 , ie, l2 − l1 , is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0098] In this way, when the thickness of the planarization layer is determined, the size of the area of ​​the anode serving as a reflective layer can be increased as much as possible while ensuring the flatness of the film layer below the first part, so as to reflect as much lateral light as possible, which is more conducive to alleviating lateral light leakage of the sub-pixel.

[0099] Correspondingly, when l1=l3, l2-l3 is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

[0100] In some embodiments, as shown in Figure 1, the pixel definition layer 5 includes multiple first opening areas 501 and multiple second opening areas 502; the orthographic projection of the first opening area 501 on the first substrate 2 falls within the orthographic projection of the first part 301 on the first substrate 2, and the orthographic projection of the second opening area 502 on the first substrate 2 falls within the orthographic projection of the third part 303 on the first substrate 2; the orthographic projection of the second part 302 on the first substrate 2 falls within the orthographic projection of the pixel definition layer 5 on the first substrate 2.

[0101] In a specific implementation, the pixel definition layer covers the edges of the first anode portion and the second anode portion, and the first opening area corresponds to the light-emitting area of ​​the sub-pixel. The pixel definition layer can also be made of materials such as acrylic or polyimide.

[0102] In some embodiments, an angle between a side surface of the pixel definition layer and the second anode portion is greater than or equal to 10° and less than or equal to 50°.

[0103] In some embodiments, the pixel definition layer is a light-shielding pixel definition layer; the pixel definition layer 5 has a transmittance of less than 5% for light with a wavelength greater than or equal to 380 nanometers and less than or equal to 700 nanometers. In other words, the light-shielding pixel definition layer has a transmittance of less than 5% for light in the visible light band, which can further reduce lateral light leakage from the light-emitting device and improve the display effect.

[0104] In some embodiments, the thickness of the pixel definition layer in the area covering the second portion is greater than or equal to 1 μm and less than or equal to 1.5 μm; and the maximum distance between the surface of the pixel definition layer 5 facing away from the first substrate 2 and the first portion 301 is greater than or equal to 1.5 μm and less than or equal to 2.5 μm. This ensures that the light-shielding pixel definition layer has a shielding effect on reducing lateral leakage of the light-emitting device.

[0105] In a specific implementation, as shown in FIG1 , the thin-film transistor (TFT) includes: an active layer 601, a gate electrode G, a source electrode S, and a drain electrode D. FIG1 illustrates a thin-film transistor (TFT) with a top-gate structure; however, the thin-film transistor (TFT) may also have a bottom-gate or other structure. As shown in FIG1 , the driving circuit layer 6 also includes: a buffer layer 602 located between the first substrate and the active layer; a first gate insulating layer 603 located between the active layer 601 and the gate electrode G; and an interlayer insulating layer 604 located between the first gate insulating layer 603 and the source electrode S and the drain electrode D. The anode 401 is electrically connected to the drain electrode D of the thin-film transistor (TFT) via a first via 304.

[0106] In some embodiments, as shown in FIG2 and FIG3 , the display panel further includes:

[0107] A plurality of auxiliary electrodes 7 are provided in the same layer as the anode 401 and are insulated from each other; the orthographic projection of the auxiliary electrodes 7 on the first substrate 2 falls within the orthographic projection of the second portion 302 on the first substrate 2 .

[0108] In the display panel provided by the embodiments of the present disclosure, the auxiliary electrode is electrically connected to the cathode, thereby enabling the auxiliary electrode to provide a driving signal to the cathode. The auxiliary electrode is disposed in the second portion, i.e., in the area where the planarization layer is thicker, to prevent excessive overlap between the cathode and the auxiliary electrode, which could lead to disconnection, thereby improving the yield rate of display panel production.

[0109] It should be noted that FIG3 is a cross-sectional view along line AA′ in FIG2 .

[0110] In some embodiments, as shown in FIG3 , the display panel further includes a connecting electrode 11 electrically connected to the auxiliary electrode 7 ; the connecting electrode 11 is located between the planarization layer 3 and the interlayer insulating layer 604 . The connecting electrode 11 can, for example, be provided on the same layer as the source S and drain D of the thin film transistor. In a specific implementation, a driving signal can be provided to the auxiliary electrode and the cathode via the connecting electrode.

[0111] In some embodiments, as shown in Figures 2 and 3, the pixel definition layer 5 further includes a plurality of third opening regions 503, the orthographic projections of the third opening regions 503 on the first substrate 2 falling within the orthographic projections of the auxiliary electrode 7 on the first substrate 2. This allows the cathode to be electrically connected to the auxiliary electrode in the third opening regions.

[0112] In some embodiments, as shown in FIG2 , the pixel definition layer 5 includes a plurality of fourth portions 504 and a plurality of fifth portions 505 , wherein the fourth portion 504 has a third opening area 503 , and the orthographic projection of the fifth portion 505 on the first substrate 2 covers the orthographic projection of the first via hole 304 on the first substrate 2 ;

[0113] The fourth portion 504 and the fifth portion 505 are integrally connected.

[0114] It should be noted that, since the fourth part needs to be provided with a third opening area exposing the auxiliary electrode so that the cathode is electrically connected to the auxiliary electrode in the third opening area, and the pixel definition layer also needs to be provided with a second opening area exposing the third part in the area outside the light-emitting area of ​​the sub-pixel, therefore, in the direction parallel to the plane where the first substrate is located, the width of the fourth part surrounding the third opening area is smaller, and the fourth part is integrally connected with the fifth part which is also located in the area outside the light-emitting area of ​​the sub-pixel, which can reduce the risk of wire breakage caused by the smaller width of the pixel definition layer and improve the yield of the display panel.

[0115] In some embodiments, a ratio of an area where an orthographic projection of the second portion on the first substrate overlaps with an orthographic projection of the pixel definition layer on the first substrate to an area of ​​the orthographic projection of the pixel definition layer on the first substrate is less than or equal to 76%.

[0116] In some embodiments, as shown in FIG. 4 and FIG. 5 , the display panel further includes: a second substrate 8 located on a side of the pixel definition layer 5 away from the first substrate 2 , and a filling layer 9 located between the second substrate 8 and the pixel definition layer 5 .

[0117] In some embodiments, as shown in FIG. 4 and FIG. 5 , the display panel further includes: an encapsulation layer 10 located between the filling layer 9 and the cathode 403 ; the encapsulation layer 10 includes an organic encapsulation layer 1001 and a first inorganic encapsulation layer 1002 that are stacked.

[0118] In Figure 4 , the organic encapsulation layer does not fill the uneven areas corresponding to the first, second, and third openings. The surface of the subsequently formed first inorganic encapsulation layer 1002 facing away from the first substrate 2 has a concave-convex shape, which still provides areas for accommodating the material of the filling layer 9, facilitating the filling and drainage of the filling material.

[0119] Alternatively, as shown in FIG. 5 , the organic encapsulation layer 1001 may be used for planarization.

[0120] Of course, in a specific implementation, the encapsulation layer may further include a second inorganic encapsulation layer located between the cathode and the organic encapsulation layer.

[0121] In some embodiments, the distance h between adjacent first opening regions satisfies: h≥a×b / (db);

[0122] Wherein, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate; d is the distance between the second part and the first part in a direction perpendicular to the first substrate; and b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate.

[0123] In a specific implementation, as shown in FIG6 , when h=a×b / (db), the light emitted laterally by the light-emitting device can be completely reflected by the first anode portion, so that when h≥a×b / (db), light leakage between sub-pixels caused by the lateral light emission of the light-emitting device can still be completely eliminated. The specific values ​​of h, a, b, and d can be set according to actual needs.

[0124] In some embodiments, the distance h between adjacent first opening regions satisfies: h≥a×b / (cb);

[0125] Among them, a is the distance between the second substrate and the anode covering the first part in the direction perpendicular to the first substrate; c is the maximum distance between the side of the pixel definition layer away from the first substrate and the first part in the direction perpendicular to the first substrate; b is the maximum width of the first opening area in the direction parallel to the plane of the first substrate.

[0126] In a specific implementation, when the pixel definition layer is a light-shielding pixel definition layer, the pixel definition layer can also block the lateral light emission. Therefore, as shown in FIG7 , when h=a×b / (cb), the lateral light emitted by the light-emitting device can be completely eliminated, so that when h≥a×b / (cb), the light leakage between sub-pixels caused by the lateral light emission of the light-emitting device can still be completely eliminated. The specific values ​​of h, a, b, and c can be set according to actual needs.

[0127] In some embodiments, the display panel includes a curved region;

[0128] In the curved area, the distance h between two adjacent first opening areas satisfies:

[0129]

[0130] Wherein, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate; d is the distance between the second part and the first part in a direction perpendicular to the first substrate; b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate; and K is the curvature of the curved area.

[0131] In specific implementation, is the curvature radius of the curved surface area of ​​the display panel, as shown in Figure 8. The light emitted laterally by the light emitting device can be completely reflected by the first anode portion, so that when While still being able to completely eliminate light leakage between sub-pixels caused by lateral light emission of the light-emitting device, the specific values ​​of h, a, d, b, and K can be set according to actual needs.

[0132] In some embodiments, the display panel includes a curved region;

[0133] In the curved area, the distance h between two adjacent first opening areas satisfies:

[0134]

[0135] Wherein, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate, c is the maximum distance between the side of the pixel definition layer facing away from the first substrate and the first part in a direction perpendicular to the first substrate, b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate, and K is the curvature of the curved area.

[0136] In specific implementation, as shown in FIG9 , when The light emitted laterally by the light emitting device can be completely reflected by the first anode portion, so that when While still being able to completely eliminate light leakage between sub-pixels caused by lateral light emission of the light-emitting device, the specific values ​​of h, a, d, b, and K can be set according to actual needs.

[0137] It should be noted that FIG2 illustrates an example in which the first opening regions are rectangular, i.e., the light-emitting regions of the sub-pixels are rectangular, and the rectangular first opening regions are arranged in a regular array along the first direction X and the second direction Y. Of course, in a specific implementation, when the first opening regions are rectangular, the multiple first opening regions may also be arranged in other manners.

[0138] In a specific implementation, for example, as shown in Figures 10 to 13, the plurality of first opening areas include a first sub-pixel opening area 5011, a second sub-pixel opening area 5012, and a third sub-pixel opening area 5013; as shown in Figure 10, the second sub-pixel opening area 5012 is staggered with the first sub-pixel opening area 5011, and the second sub-pixel opening area 5012 is staggered with the third sub-pixel opening area 5013; as shown in Figure 11, a pixel PX includes the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013, and in the first direction X, the first sub-pixel opening area 5011 is adjacent to the second sub-pixel opening area 5012 and the third sub-pixel opening area 5013, and the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013 are adjacent to each other .... The outline of the three arranged pixel opening areas 5013 is a rectangle; as shown in Figure 12, in the first direction X, the projection of the first sub-pixel opening area 5011 and the projection of the second sub-pixel opening area 5012 both overlap with the projection of the third sub-pixel opening area 5013, and the projection of the first sub-pixel opening area 5011 and the projection of the third sub-pixel opening area 5013 have a non-overlapping area, and in the second direction Y, the projection of the first sub-pixel opening area 5011 and the projection of the second sub-pixel opening area 5012 have an overlapping area; as shown in Figure 13, the first sub-pixel opening area 5011, the second sub-pixel opening area 5012 and the third sub-pixel opening area 5013 included in a pixel PX are arranged in two rows, and the center line of the first sub-pixel opening area 5011, the second sub-pixel opening area 5012 and the third sub-pixel opening area 5013 is a triangle.

[0139] In a specific implementation, as shown in Figures 10, 11, and 12, the areas of the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013 are not exactly the same, or, as shown in Figure 13, the areas of the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013 are exactly the same.

[0140] Alternatively, in a specific implementation, as shown in Figures 14 to 18, at least part of the first opening area, i.e., the light-emitting area of ​​the sub-pixel, may also be of other shapes. As shown in Figure 14, the first sub-pixel opening area 5011 and the third sub-pixel opening area 5013 are rectangular in shape, and the second sub-pixel opening area 5012 is L-shaped; as shown in Figure 15, the first sub-pixel opening area 5011 and the second sub-pixel opening area 5012 are L-shaped, and the third sub-pixel opening area 5013 is rectangular in shape; as shown in Figures 16 and 17, the first sub-pixel opening area 5011 and the second sub-pixel opening area 5012 are pentagonal in shape, and the third sub-pixel opening area 5013 is rectangular in shape; as shown in Figure 18, the shapes of the first sub-pixel opening area 5011, the second sub-pixel opening area 5012 and the third sub-pixel opening area 5013 are all irregular polygons.

[0141] Alternatively, in a specific implementation, as shown in Figures 19 to 23, the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013 are all non-rectangular. As shown in Figures 19 to 20, the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013 are all octagonal, and the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013 included in a pixel PX are arranged in two rows, and the center line of the first sub-pixel opening area 5011, the second sub-pixel opening area 5012, and the third sub-pixel opening area 5013 forms a triangle. The first opening area 501 shown in Figure 21 is an asymmetric octagon, the first opening area 501 shown in Figure 22 is a hexagon, and the first opening area 501 shown in Figure 23 is a heptagon.

[0142] In some embodiments, as shown in Figures 24 and 25 , the display panel further includes a first light-shielding layer 12 and a photoluminescent layer 13. The first light-shielding layer 12 includes fourth opening regions 1201 corresponding one-to-one with the first opening regions, and the photoluminescent layer 13 is located within at least a portion of the fourth opening regions 1201. As shown in Figure 24 , the first light-shielding layer 12 and the photoluminescent layer 13 are located on the side of the second substrate 8 facing the first substrate 2. Alternatively, as shown in Figure 25 , the first light-shielding layer 12 and the photoluminescent layer 13 are located on the side of the second substrate 8 facing away from the first substrate 2.

[0143] In a specific implementation, the photoluminescent layer is used to absorb light emitted by the light-emitting device to radiate light of a desired color, thereby improving the display effect.

[0144] In a specific implementation, the sub-pixels include a red sub-pixel, a blue sub-pixel, and a green sub-pixel.

[0145] In some embodiments, the photoluminescent layer is a quantum dot photoluminescent layer.

[0146] In some embodiments, a photoluminescent layer is disposed in each fourth opening region.

[0147] Alternatively, in some embodiments, a photoluminescent layer is provided only in the fourth opening area corresponding to the red sub-pixel and the green sub-pixel. In this case, the light-emitting devices are all blue light-emitting devices. The photoluminescent layer includes: a red light quantum dot layer provided in the fourth opening area corresponding to the red sub-pixel, and a green light quantum dot layer provided in the fourth opening area corresponding to the green sub-pixel. The red light quantum dot layer absorbs blue light and radiates green light, and the green light quantum dot layer absorbs blue light and radiates green light. Since the light-emitting device is a blue light-emitting device, the display panel can achieve full-color display without providing a quantum dot layer in the fourth opening area corresponding to the blue sub-pixel. The display also includes: a light-transmitting filling layer located in the fourth opening corresponding to the blue sub-pixel.

[0148] In some embodiments, as shown in Figures 26 and 27 , the display panel further includes a second light-shielding layer 14 and color resists 15. The second light-shielding layer 14 includes fifth openings 1401 corresponding one-to-one with the first openings, and the color resists 15 are located within the fifth openings 1401. In Figure 26 , the second light-shielding layer 14 and the color resists 15 are located between the first light-shielding layer 12 and the second substrate 8. In Figure 27 , the second light-shielding layer 14 and the color resists 15 are located on the side of the first light-shielding layer 12 facing away from the second substrate 8.

[0149] The display panel provided by the embodiment of the present disclosure further has color resists disposed in the area corresponding to the light-emitting area of ​​the sub-pixel, thereby improving the color purity of the light emitted by the display panel.

[0150] In a specific implementation, the color resist includes a red color resist corresponding to the red sub-pixel, a blue color resist corresponding to the blue sub-pixel, and a green color resist corresponding to the green sub-pixel.

[0151] Based on the same inventive concept, an embodiment of the present disclosure provides a method for manufacturing a display panel, as shown in FIG28 , comprising:

[0152] S101, forming a driving circuit layer on one side of a first substrate; the driving circuit layer includes a plurality of thin film transistors;

[0153] S102. Form a pattern of a planarization layer on a side of the driving circuit layer facing away from the first substrate; wherein the planarization layer includes: a plurality of first portions, a second portion, and a third portion; in a direction perpendicular to the first substrate, the thickness of the first portion is less than the thickness of the second portion, and the thickness of the third portion is less than the thickness of the second portion; the orthographic projection of the second portion on the first substrate surrounds the orthographic projection of the first portion on the first substrate; the orthographic projection of the first portion on the first substrate covers the orthographic projection of the light-emitting area of ​​the sub-pixel on the first substrate, and the orthographic projection of the third portion on the first substrate falls within the orthographic projection of the first substrate within the region between the light-emitting areas of adjacent sub-pixels; and the first portion includes a first via hole extending through the thickness thereof;

[0154] S103, forming a plurality of anodes on a side of the planarization layer facing away from the first substrate; the anodes cover the first portion and a side surface of a second portion adjacent to the first portion, and an angle between a surface of a portion of the side surface of the anode covering the second portion facing away from the first substrate and a plane parallel to the first substrate is greater than 0; the anodes are electrically connected to the thin film transistor through a first via hole;

[0155] S104 , forming a pattern of a pixel definition layer on a side of the anode facing away from the planarization layer; an orthographic projection of the pixel definition layer on the first substrate covers an orthographic projection of the first via hole on the first substrate.

[0156] The method for preparing a display panel provided by an embodiment of the present disclosure forms a first part and a second part adjacent to each other and having different thicknesses on a planarization layer. When the anode covers the side surface of the second part adjacent to the first part, the angle between the part of the anode covering the side surface of the second part and the part of the anode covering the surface of the first part is greater than 0. The part of the anode covering the side surface of the second part can serve as a reflective layer to reflect light from the light-emitting device to the side, thereby reducing lateral light leakage of sub-pixels and improving the display effect. Furthermore, the planarization layer further includes a third portion adjacent to the second portion and having a different thickness than the second portion. The third portion is located in the region between the sub-pixel light-emitting regions, i.e., the planarization layer has a recessed portion in the region between the sub-pixel light-emitting regions, thereby increasing the step difference between the sub-pixel light-emitting region and the region outside the sub-pixel light-emitting region. During the cell alignment process, the recessed portion can accommodate filler material, facilitating the filling and drainage of the filler material. It can also act as a pressure divider during the cell alignment process, preventing damage to the film layers on one side of the array substrate during the pressing process, thereby improving the yield of the top-emitting display panel. Furthermore, for a flexible display panel, the provision of the recessed region can reduce the force applied to the region corresponding to the sub-pixel light-emitting region during the bending process of the display panel, thereby preventing the film layers in the region corresponding to the sub-pixel light-emitting region from bending and fracturing. Furthermore, a first via hole is provided in the first portion to electrically connect the anode to the thin film transistor, i.e., the first via hole is formed in the region where the planarization layer is thinner. The depth of the first via hole is shallow, which can reduce the difficulty of preparing the first via hole and also reduce the thickness of the photoresist coating during the first via hole preparation process, thereby reducing the risk of residual photoresist after stripping. Furthermore, the orthographic projection of the pixel definition layer on the first substrate covers the orthographic projection of the first via hole on the first substrate, that is, the pixel definition layer covers the area corresponding to the first via hole, thereby planarizing the area of ​​the first via hole.

[0157] In some embodiments, forming a pattern of a planarization layer on a side of the driving circuit layer facing away from the first substrate specifically includes:

[0158] Depositing a planarization layer material on a side of the driving circuit layer away from the first substrate to form a planarization layer;

[0159] A half-tone mask process is used on the planarization layer to form a first portion, a second portion and a third portion.

[0160] In some embodiments, forming a pattern of a pixel definition layer on a side of the anode facing away from the planarization layer specifically includes:

[0161] forming a pixel definition layer on a side of the anode facing away from the planarization layer;

[0162] A graphic process is used to form multiple first opening areas and multiple second opening areas; the orthographic projection of the first opening area on the first substrate falls within the orthographic projection of the first part on the first substrate, the orthographic projection of the second opening area on the first substrate falls within the orthographic projection of the third part on the first substrate, and the orthographic projection of the second part on the first substrate falls within the orthographic projection of the pixel definition layer on the first substrate.

[0163] In some embodiments, after forming the pixel definition layer, the method further includes:

[0164] forming a light-emitting functional layer in the first opening area;

[0165] A cathode is formed on the side of the light-emitting functional layer facing away from the anode.

[0166] In some embodiments, after forming the cathode, the method further comprises:

[0167] forming an organic encapsulation layer and an inorganic encapsulation layer in sequence on a side of the cathode facing away from the first substrate;

[0168] In some embodiments, after forming the inorganic encapsulation layer, the method further includes:

[0169] A filling layer is formed on the side of the inorganic encapsulation layer away from the organic encapsulation layer, and a second substrate is arranged on the side of the filling layer away from the first substrate using a cell-aligning process.

[0170] In some embodiments, forming a driving circuit layer on one side of the first substrate specifically includes:

[0171] A buffer layer, an active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode are sequentially formed on the first substrate.

[0172] A display device provided by an embodiment of the present disclosure includes the display panel provided by an embodiment of the present disclosure.

[0173] The display device provided in the embodiments of the present disclosure is any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. Other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure. The implementation of the display device can be referenced to the above-described display panel embodiments, and any repetitive details will not be repeated.

[0174] In summary, the display panel and the preparation method thereof provided by the embodiments of the present disclosure, the planarization layer includes a first part and a second part that are adjacent and have different thicknesses, and the first part corresponds to the light-emitting area of ​​the sub-pixel, that is, the planarization layer has a recessed portion in the area corresponding to the light-emitting area of ​​the sub-pixel, so that when the anode covers the side of the second part adjacent to the first part, the angle a between the surface of the part of the side of the second part covered by the anode facing away from the first substrate and the plane parallel to the first substrate is greater than 0, that is, the angle between the part of the side of the second part covered by the anode and the part of the surface of the first part covered by the anode is greater than 0, and the part of the side of the second part covered by the anode can be used as a reflective layer to reflect the light-emitting device to emit light laterally (towards the direction of the first part), thereby reducing lateral light leakage of the sub-pixel and improving the display effect. Furthermore, the planarization layer further includes a third portion adjacent to the second portion and having a different thickness than the second portion. The third portion is located in the region between the sub-pixel light-emitting regions, i.e., in the region between the sub-pixel light-emitting regions. The planarization layer has a recessed portion, thereby increasing the step difference between the light-emitting region of the sub-pixel and the region outside the light-emitting region of the sub-pixel. During the cell alignment process, the recessed portion can accommodate filler material, which is beneficial for filling and draining the filler material. It can also act as a pressure divider during the cell alignment process, avoiding damage to the film layers on one side of the array substrate during the pressing process, thereby improving the yield of the top-emitting display panel. Moreover, for a flexible display panel, the provision of the recessed region can reduce the force applied to the region corresponding to the light-emitting region of the sub-pixel during the bending process of the display panel, thereby facilitating the bending and fracture of the film layers in the region corresponding to the light-emitting region of the sub-pixel. In addition, a first via hole is provided in the first portion to electrically connect the anode to the thin film transistor, i.e., the first via hole is formed in the region where the planarization layer is thinner. The depth of the first via hole is shallow, which can reduce the difficulty of preparing the first via hole and can also reduce the thickness of the photoresist coating during the first via hole preparation process, reducing the risk of residual photoresist after stripping. Furthermore, the orthographic projection of the pixel definition layer on the first substrate covers the orthographic projection of the first via hole on the first substrate, that is, the pixel definition layer covers the area corresponding to the first via hole, thereby planarizing the area of ​​the first via hole.

[0175] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0176] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if such changes and modifications of the embodiments of the present invention fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A display panel comprising a plurality of sub-pixels, wherein: The display panel includes: a first substrate; a driving circuit layer, located on one side of the first substrate, comprising a plurality of thin film transistors; A planarization layer is located on a side of the first substrate facing away from the driving circuit layer, and includes: a plurality of first portions, a second portion, and a third portion; in a direction perpendicular to the first substrate, the thickness of the first portion is less than the thickness of the second portion, and the thickness of the third portion is less than the thickness of the second portion; the orthographic projection of the second portion on the first substrate surrounds the orthographic projection of the first portion on the first substrate; the orthographic projection of the first portion on the first substrate covers the orthographic projection of the light-emitting area of ​​the sub-pixel on the first substrate, and the orthographic projection of the third portion on the first substrate falls within the orthographic projection of the first substrate so as to fall within the region between the light-emitting areas of adjacent sub-pixels; the first portion includes a first via hole extending through the thickness thereof; a plurality of light-emitting devices located on a side of the planarization layer facing away from the first substrate; the light-emitting devices including an anode; the anode covering the first portion and a side surface of the second portion adjacent to the first portion, the angle between a surface of a portion of the anode covering the side surface of the second portion facing away from the first substrate and a plane parallel to the first substrate being greater than 0; the anode being electrically connected to the thin film transistor through the first via hole; A pixel definition layer is located on a side of the anode facing away from the planarization layer; the orthographic projection of the pixel definition layer on the first substrate covers the orthographic projection of the first via hole on the first substrate.

2. The display panel according to claim 1, wherein The angle between the surface of the portion of the side of the second portion of the anode covering the side away from the first substrate and the surface parallel to the first substrate is greater than or equal to 30° and less than or equal to 50°.

3. The display panel according to claim 1 or 2, wherein: In a direction perpendicular to the first substrate, a thickness of the first portion is equal to a thickness of the third portion.

4. The display panel according to claim 3, wherein: In a direction perpendicular to the first substrate, a difference between a thickness of the second portion and a thickness of the first portion is greater than or equal to 0.5 micrometers and less than or equal to 1 micrometer.

5. The display panel according to any one of claims 1 to 4, wherein: The pixel definition layer includes multiple first opening areas and multiple second opening areas; the orthographic projection of the first opening area on the first substrate falls within the orthographic projection of the first part on the first substrate, and the orthographic projection of the second opening area on the first substrate falls within the orthographic projection of the third part on the first substrate; the orthographic projection of the second part on the first substrate falls within the orthographic projection of the pixel definition layer on the first substrate. The display panel according to claim 5 , wherein: A ratio of an area where an orthographic projection of the second portion on the first substrate overlaps with an orthographic projection of the pixel definition layer on the first substrate to an area of ​​an orthographic projection of the pixel definition layer on the first substrate is less than or equal to 76%.

7. The display panel according to claim 5 or 6, wherein: A maximum distance between a surface of the pixel definition layer facing away from the first substrate and the first portion is greater than or equal to 1.5 micrometers and less than or equal to 2.5 micrometers.

8. The display panel according to any one of claims 5 to 7, wherein: The display panel further includes: A plurality of auxiliary electrodes are provided in the same layer as the anode and are insulated from each other; the orthographic projections of the auxiliary electrodes on the first substrate fall within the orthographic projection of the second portion on the first substrate.

9. The display panel according to claim 8, wherein: The pixel definition layer further includes a plurality of third opening areas, and the orthographic projections of the third opening areas on the first substrate fall within the orthographic projections of the auxiliary electrodes on the first substrate.

10. The display panel according to claim 9, wherein: The pixel definition layer includes a plurality of fourth portions and a plurality of fifth portions, the fourth portion has the third opening area, and the orthographic projection of the fifth portion on the first substrate covers the orthographic projection of the first via hole on the first substrate; The fourth part and the fifth part are integrally connected.

11. The display panel according to any one of claims 1 to 10, wherein: The transmittance of the pixel definition layer to light with a wavelength greater than or equal to 380 nanometers and less than or equal to 700 nanometers is less than 5%.

12. The display panel according to any one of claims 1 to 11, wherein: The display panel further includes: a second substrate located on a side of the pixel definition layer facing away from the first substrate, and a filling layer located between the second substrate and the pixel definition layer.

13. The display panel according to claim 12, wherein: The distance h between adjacent first opening areas satisfies: h≥a×b / (db); Among them, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate; d is the distance between the second part and the first part in a direction perpendicular to the first substrate; b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate.

14. The display panel according to claim 12, wherein: The distance h between adjacent first opening areas satisfies: h≥a×b / (cb); Among them, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate; c is the maximum distance between the side of the pixel definition layer away from the first substrate and the first part in a direction perpendicular to the first substrate; b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate.

15. The display panel according to claim 12, wherein: The display panel includes a curved area; In the curved surface area, the distance h between two adjacent first opening areas satisfies: Among them, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate; d is the distance between the second part and the first part in a direction perpendicular to the first substrate; b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate; K is the curvature of the curved area.

16. The display panel according to claim 12, wherein: The display panel includes a curved area; In the curved surface area, the distance h between two adjacent first opening areas satisfies: Among them, a is the distance between the second substrate and the anode covering the first part in a direction perpendicular to the first substrate, c is the maximum distance between the side of the pixel definition layer away from the first substrate and the first part in a direction perpendicular to the first substrate, b is the maximum width of the first opening area in a direction parallel to the plane of the first substrate, and K is the curvature of the curved area.

17. A method for preparing a display panel, wherein: The method comprises: forming a driving circuit layer on one side of the first substrate; the driving circuit layer includes a plurality of thin film transistors; A pattern of a planarization layer is formed on a side of the driving circuit layer facing away from the first substrate; wherein the planarization layer includes: a plurality of first portions, a second portion, and a third portion; in a direction perpendicular to the first substrate, the thickness of the first portion is less than the thickness of the second portion, and the thickness of the third portion is less than the thickness of the second portion; the orthographic projection of the second portion on the first substrate surrounds the orthographic projection of the first portion on the first substrate; the orthographic projection of the first portion on the first substrate covers the orthographic projection of the light-emitting area of ​​the sub-pixel on the first substrate, and the orthographic projection of the third portion on the first substrate falls within the orthographic projection of the first substrate so as to fall within the region between the light-emitting areas of adjacent sub-pixels; the first portion includes a first via hole extending through the thickness thereof; A plurality of anodes are formed on a side of the planarization layer facing away from the first substrate; the anodes cover the first portion and a side surface of the second portion adjacent to the first portion, and an angle between a surface of a portion of the anode covering the side surface of the second portion facing away from the first substrate and a plane parallel to the first substrate is greater than 0; the anodes are electrically connected to the thin film transistor through the first via hole; A pattern of a pixel definition layer is formed on a side of the anode facing away from the planarization layer; an orthographic projection of the pixel definition layer on the first substrate covers an orthographic projection of the first via hole on the first substrate.

18. The method according to claim 17, wherein Forming a pattern of a planarization layer on a side of the driving circuit layer facing away from the first substrate specifically includes: Depositing a planarization layer material on a side of the driving circuit layer away from the first substrate to form a planarization layer; A half-tone mask process is used on the planarization layer to form the first portion, the second portion, and the third portion.

19. The method according to claim 17, wherein The method further comprises forming a pattern of a pixel definition layer on a side of the anode facing away from the planarization layer, specifically comprising: forming a pixel definition layer on a side of the anode facing away from the planarization layer; A graphical process is used to form multiple first opening areas and multiple second opening areas; the orthographic projection of the first opening area on the first substrate falls within the orthographic projection of the first part on the first substrate, the orthographic projection of the second opening area on the first substrate falls within the orthographic projection of the third part on the first substrate, and the orthographic projection of the second part on the first substrate falls within the orthographic projection of the pixel definition layer on the first substrate.

20. A display device, wherein: The display panel comprises the display panel according to any one of claims 1 to 16.

Images