Sonar emission signal source system based on DDS and working method

Abstract

The invention relates to the technical field of sonar emission signal source systems, in particular to a sonar emission signal source system based on a DDS and a working method. Comprising an ARM end, a main control circuit and a transmitting circuit, the ARM end is connected with the main control circuit, the main control circuit is connected with the transmitting circuit, the ARM end issues a working parameter instruction to the main control circuit, the main control circuit generates a corresponding waveform signal after receiving and analyzing the instruction, and the waveform signal is filtered through the transmitting circuit; the working parameters sent by the ARM end comprise center frequency, bandwidth and pulse width; the main control circuit uses an FPGA (Field Programmable Gate Array) as a main controller, the FPGA main control circuit adopts an XC6SLX16 / 25-2FTG256 chip, and the FPGA main control circuit is also connected with a 50MHz clock crystal oscillator, a serial SPI (Serial Peripheral Interface) configuration chip, a low-dropout voltage-stabilizing chip and a JTAG (Joint Test Action Group) interface; and the low-dropout voltage-stabilizing chip provides voltage for the system. A direct digital frequency synthesizer (DDS) technology is used, corresponding single-frequency signals or LFM signals can be generated according to received instructions of parameters such as frequency, bandwidth and pulse width of a working center, and application requirements of special occasions are met.

Description

Technical Field

[0001] The invention relates to the technical field of sonar emission signal source systems, and in particular to a sonar emission signal source system based on DDS and a working method. Background Art

[0002] Signal generator is a kind of equipment and instrument that can generate electronic signals of different frequencies and is widely used in daily scientific research and medical fields. It is also used in fields such as communications, mechanical and aerospace engineering and various maintenance projects. It is a common signal generation source.

[0003] Traditional signal generators contain a large number of analog components, and their structures are quite complex, with large size and weight, high power consumption, and generally have problems of insufficient accuracy and slow frequency switching speed. With the growing demand for measurement and control technology in many fields such as communication technology, satellite positioning systems, precision mechanical control, and aerospace measurement and control, the requirements for the stability, accuracy, and frequency bandwidth of signal generators are also increasing. However, traditional oscillators cannot meet these growing demands because the frequency signals they generate are not accurate enough, are too single, or can only be adjusted within a limited range.

[0004] Traditional frequency synthesis technology mainly includes analog frequency synthesis technology and frequency synthesis technology based on phase-locked loop (PLL). Among them, analog frequency synthesis technology mainly includes coherent synthesis method and incoherent synthesis method. Coherent synthesis method uses a standard frequency source as a reference, and obtains various frequency signals through frequency division, mixing and frequency multiplication. Incoherent synthesis method uses multiple standard frequency sources as a reference, and obtains various frequency signals through linear operations on these reference frequency signals. The standard frequency source is provided by LC, RC oscillator circuit or crystal oscillator circuit. By manually converting the frequency range and waveform, the designed signal source can only generate several fixed signal waveforms, which is difficult to meet the application requirements of various occasions and some special occasions, and has poor stability and low accuracy. Frequency synthesis technology based on phase-locked loop (PLL) applies phase feedback theory and phase-locked technology to the design of signal source, and obtains various frequency signals through addition, subtraction, multiplication and division operations of phase-locked loop. This method has a simple structure, is easy to integrate, and has greatly improved frequency accuracy, but its process is complex, the resolution is not high, and it is not easy to perform frequency conversion and computer program control, which makes the system software flexibility poor and the actual economic value is not high. In summary, some special application requirements urgently require a sonar signal source transmission system with high frequency resolution and fast frequency switching. Summary of the invention

[0005] The problem to be solved by the present invention is to provide a sonar signal source transmitting system with high frequency resolution and capable of realizing rapid frequency switching.

[0006] In view of the deficiencies of the prior art, the technical solution adopted by the present invention to solve the technical problems is: a sonar transmission signal source system based on DDS, comprising an ARM end, a main control circuit and a transmission circuit, the ARM end is connected to the main control circuit, the main control circuit is connected to the transmission circuit, the ARM end sends a working parameter instruction to the main control circuit, the main control circuit generates a corresponding waveform signal after receiving and parsing the instruction, and then filters the waveform signal through the transmission circuit; the working parameters sent by the ARM end include a center frequency, a bandwidth and a pulse width; the main control circuit uses an FPGA as a main controller, the FPGA main control circuit adopts an XC6SLX16 / 25-2FTG256 chip, the FPGA main control circuit is also connected to a 50MHz clock crystal oscillator, a serial SPI configuration chip, a low voltage difference voltage regulator chip and a JTAG interface; the low voltage difference voltage regulator chip provides 3.3V and 1.2V voltages for the system.

[0007] Preferably, the model of the serial SPI configuration chip is M25P16.

[0008] Preferably, the low voltage dropout voltage regulator chip model is AMS1117.

[0009] Preferably, the P7 pin of the XC6SLX16 / 25-2FTG256 chip is connected to a 50MHz clock crystal oscillator, the P10 pin, the T10 pin, and the R11 pin are connected to M25P16, and the A15 pin, the C14 pin, the E14 pin, and the C12 pin are connected to the JTAG interface.

[0010] A working method of a sonar transmitting signal source system based on DDS, wherein the system software control part adopts a layered architecture, including a top-level module, a clock IP core module, a transmitting signal waveform configuration module and an RS422 serial port driver configuration module, and comprises the following steps:

[0011] Step 1, ARM sends the working parameter command to the FPGA main control circuit. The working parameter command is 8 bytes (64 bits) of data. The meaning of 8 bytes is as follows: a. 1-2 bytes: identifier; b. 3 bytes: transmission control; c. 4 bytes: frequency; d. 5 bytes: pulse width; e. 6-7 bytes: signal type (CW or LFM); f. 8 bytes: identifier;

[0012] Step 2: After receiving the working parameter command sent by the ARM terminal, the FPGA main control circuit will parse the working parameter command to generate the transmission signal form, transmission center frequency, transmission bandwidth, and transmission pulse width parameters;

[0013] Step 3: Analyze and generate the transmission signal form, transmission center frequency, transmission bandwidth, and transmission pulse width parameters to the transmission signal waveform configuration module. The transmission signal waveform configuration module realizes the excitation and drive of the transmission excitation signal form, and generates an excitation signal that meets the requirements and transmits it to the transmission circuit.

[0014] Preferably, the operation process of the transmission signal waveform configuration module in step 3 is as follows:

[0015] 3.1. First, determine the signal type, which includes CW signal and LFM signal;

[0016] 3.2. Calculate the frequency f of the output sinusoidal signal out ,

[0017]

[0018] Where: K is the frequency control word, f c is the crystal frequency, N is the number of DFFs in the frequency synthesis module

[0019] 3.3. Output the corresponding frequency waveform,

[0020] When the CW signal is single frequency, f out =f 0 ;

[0021] When the LFM signal is linear frequency modulated

[0022] Where: f out is the output frequency, f clk is the system clock, n is the number of clocks, f 0 is the center frequency, B is the bandwidth, and the pulse width is the pulse width sent from the ARM end.

[0023] The beneficial effects of the present invention are as follows: Compared with the traditional technology, the present invention uses direct digital frequency synthesizer technology (DDS), which is a new type of frequency synthesis technology and signal generation method, based on digital control, using high-precision phase accumulator and high clock signal, so as to achieve high-resolution frequency synthesis. Since the frequency conversion speed of DDS mainly depends on the time required for the frequency control word to change, after the frequency control word changes, the phase accumulator needs to accumulate the phase increment through a clock cycle to achieve frequency conversion, so the higher the clock frequency, the faster the frequency conversion time is, which can reach the nanosecond level, realize the rapid switching of frequency, and can keep the phase continuous when changing, and it is easy to realize the numerical control modulation of frequency, phase and amplitude. The present invention can generate a corresponding single-frequency signal or LFM signal according to the received instructions of the working center frequency, bandwidth, pulse width and other parameters; in view of the design requirements of the sonar transmitting signal source, the present invention uses the XC6SLX16 / 25-2FTG256 chip as the core control part, and can generate a corresponding single-frequency signal or LFM signal waveform according to the instructions of the working center frequency, bandwidth, pulse width and other parameters sent by the ARM end. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is the overall block diagram of the system of the present invention;

[0025] Figure 2 It is the schematic diagram of the XC6SLX16 / 25-2FTG256 chip involved in the present invention;

[0026] Figure 3 It is a connection diagram of the FPGA main control circuit in the present invention;

[0027] Figure 4 It is the circuit diagram of the U4A part of the XC6SLX16 / 25-2FTG256 chip in the present invention;

[0028] Figure 5 It is the circuit diagram of the U4B part of the XC6SLX16 / 25-2FTG256 chip in the present invention;

[0029] Figure 6 It is the circuit diagram of the U4C part of the XC6SLX16 / 25-2FTG256 chip in the present invention;

[0030] Figure 7 It is the circuit diagram of the XC6SLX16 / 25-2FTG256 chip U4D in the present invention;

[0031] Figure 8 It is the circuit diagram of the U4E and U4F parts of the XC6SLX16 / 25-2FTG256 chip in the present invention;

[0032] Fig. 9It is the circuit diagram of the U4G part of the XC6SLX16 / 25-2FTG256 chip in the present invention;

[0033] Fig.10 It is the circuit diagram of the low voltage difference voltage stabilizing chip in the present invention;

[0034] Fig.11 It is the JTAG interface circuit diagram of the present invention;

[0035] Fig.12 It is the circuit diagram of M25P16 in the present invention;

[0036] Fig.13 It is a 50MHz clock crystal oscillator circuit diagram of the present invention;

[0037] Fig.14 The present invention relates to a DDS structure principle diagram. DETAILED DESCRIPTION

[0038] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The embodiments of the present invention are provided for the purpose of illustration and description, and are not intended to be exhaustive or to limit the present invention to the disclosed forms. Many modifications and variations will be apparent to those of ordinary skill in the art. The embodiments are selected and described in order to better illustrate the principles and practical applications of the present invention, and to enable those of ordinary skill in the art to understand the present invention and thereby design various embodiments with various modifications suitable for specific uses.

[0039] In order to solve the problems raised in the background technology, the present invention provides a sonar transmission signal source system and working method based on DDS, including an ARM end, a main control circuit and a transmitting circuit, the ARM end is connected to the main control circuit, the main control circuit is connected to the transmitting circuit, the ARM end sends a working parameter instruction to the main control circuit, the main control circuit receives and analyzes the instruction and generates a corresponding waveform signal, and then the waveform signal is filtered and processed by the transmitting circuit. The overall block diagram of the system is as follows Figure 1 The main control circuit uses FPGA as the main controller, and implements direct frequency synthesis inside it to generate a signal waveform with corresponding frequency, bandwidth, and pulse width; the working parameters sent by the ARM end include parameter instructions such as center frequency, bandwidth, and pulse width.

[0040] This system communicates via the RS422 serial port, with the ARM end sending 8 bytes (64 bits) of data to the FPGA main control circuit. The meanings of these eight bytes are as follows:

[0041] a.1~2byte: identifier;

[0042] b.3byte: emission control;

[0043] c.4byte: frequency;

[0044] d.5byte: pulse width;

[0045] e.6~7 bytes: signal type (CW or LFM);

[0046] f.8 bytes: identifier.

[0047] After receiving the working parameter serial port command sent by the ARM end, the FPGA main control circuit will parse it and generate an excitation signal that meets the requirements and transmit it to the transmitting circuit.

[0048] The FPGA main control circuit uses the XC6SLX16 / 25-2FTG256 chip as the main control chip. The XC6SLX16 / 25-2FTG256 is an FPGA chip with rich logic resources such as 160,000 logic units and 372 I / O pins. The speed is up to 250MHz, and the power consumption is low. The maximum power consumption is 1.2W, which is energy-saving and environmentally friendly. The hardware schematic diagram of the XC6SLX16 / 25-2FTG256 chip is as follows Figure 2 The chip can mainly realize functions such as timing and logic control and digital signal processing by configuring logic units and connections, and realize data transmission and control functions by configuring I / O pins.

[0049] The main control circuit is as follows Figure 3 As shown, in addition to the main control chip XC6SLX16 / 25-2FTG256, the FPGA main control circuit is also connected to a 50MHz clock crystal oscillator, a serial SPI configuration chip, a low voltage dropout regulator chip and a JTAG interface. Figure 4-Figure 9 This is the circuit diagram of the main control chip XC6SLX16 / 25-2FTG256. Figure 4 It is the circuit diagram of the U4A part of the XC6SLX16 / 25-2FTG256 chip in the present invention; Figure 5 It is the circuit diagram of the U4B part of the XC6SLX16 / 25-2FTG256 chip in the present invention; Figure 6 It is the circuit diagram of the U4C part of the XC6SLX16 / 25-2FTG256 chip in the present invention; Figure 7 It is the circuit diagram of the XC6SLX16 / 25-2FTG256 chip U4D in the present invention; Figure 8 It is the circuit diagram of the U4E and U4F parts of the XC6SLX16 / 25-2FTG256 chip in the present invention; Fig. 9 This is the circuit diagram of the U4G portion of the XC6SLX16 / 25-2FTG256 chip in the present invention.

[0050] Fig.10This is the circuit diagram of the low voltage difference voltage regulator chip in the present invention. The model of the low voltage difference voltage regulator chip is AMS1117. AMS1117 is mainly used to reduce high voltage to a lower stable voltage. The input voltage range of AMS1117 is 4.75V to 12V, and the output voltage range is 1.2V to 5V. It integrates modules such as an error amplifier, a comparator, a reference voltage source and a voltage stabilization circuit. When the input voltage changes, the error amplifier will amplify the changing voltage signal and input it into the comparator. The comparator will compare it with the reference voltage and output a control signal. The control signal is processed by the voltage stabilization circuit to control the stability of the output voltage. Fig.10 The AMS1117-3.3 circuit shown provides 3.3V voltage for the system, and the AMS1117-1.2 circuit provides 1.2V voltage for the system.

[0051] Fig.11 This is the JTAG interface circuit diagram. The serial SPI configuration chip model is M25P16. Fig.12 This is the circuit diagram of M25P16, which is a 2M-byte serial Flash memory with advanced write protection mechanism and high-speed SPI bus access. Fig.13 This is the circuit diagram of 50MHz clock crystal oscillator. The P7 pin of U4C part of XC6SLX16 / 25-2FTG256 chip is connected to 50MHz clock crystal oscillator, the P10 pin, T10 pin and R11 pin of U4G part of XC6SLX16 / 25-2FTG256 chip are connected to M25P16, and the A15 pin, C14 pin, E14 pin and C12 pin of U4G part are connected to JTAG interface.

[0052] This system is mainly based on DDS to achieve the function of waveform signal generation. The DDS structure principle diagram is as follows Fig.14 As shown, the signal output method of DDS is a prior art and will not be described here. The system software control part of the present invention adopts a layered architecture, which mainly includes the following parts: a top-level module (the top-level reference of each functional module software), a clock IP core module, a transmission signal waveform configuration module and an RS422 serial port driver configuration module. The working method of the sonar transmission signal source system based on DDS includes the following steps:

[0053] Step 1, ARM sends the working parameter command to the FPGA main control circuit. The working parameter command is 8 bytes (64 bits) of data. The meaning of 8 bytes is as follows: a. 1-2 bytes: identifier; b. 3 bytes: transmission control; c. 4 bytes: frequency; d. 5 bytes: pulse width; e. 6-7 bytes: signal type (CW or LFM); f. 8 bytes: identifier;

[0054] Step 2: After receiving the working parameter command sent by the ARM terminal, the FPGA main control circuit will parse the working parameter command to generate the transmission signal form, transmission center frequency, transmission bandwidth, and transmission pulse width parameters;

[0055] Step 3: Analyze and generate the transmission signal form, transmission center frequency, transmission bandwidth, and transmission pulse width parameters to the transmission signal waveform configuration module. The transmission signal waveform configuration module realizes the excitation and drive of the transmission excitation signal form, and generates an excitation signal that meets the requirements and transmits it to the transmission circuit.

[0056] The RS422 serial port driver configuration module is as follows: The main function of the RS422 serial port driver configuration module is to accept the transmission command related instructions from the ARM side, and the signal source board parses the serial port command to generate the transmission signal form, transmission center frequency, transmission bandwidth, transmission pulse width and other related parameters, and then gives these parameters to the transmission signal waveform configuration module to realize the excitation and drive of the transmission excitation signal form. The function of the RS422 serial port driver configuration module is to realize the collection of serial port functions through the bottom-level call method. The modules called are the serial port sending module and the serial port receiving module. There is an edge detection circuit in the serial port receiving module, which captures the start bit of a frame of data by detecting the falling edge of uart_rxd at the serial port receiving end. Once the start bit is detected, a pulse of a clock cycle will be output as the serial port receiving flag signal (start_flag), and the serial port receiving process will be entered. The serial port receiving state is marked by rx_flag. The high rx_flag indicates that the serial port receiving process is in progress. At this time, the system clock counter and the receiving data counter are started to collect the data of the receiving port. The collected data is then stored in the corresponding bit of the receive data register, thereby realizing the serial-to-parallel conversion of the received data.

[0057] The serial port sending module is similar to the serial port receiving module. The cnt_data is used to calculate the serial port data byte received from the third. When the third byte is received, cnt_data is 1. When the fourth byte is received, cnt_data is 2, and so on. When the first identifier is received again, cnt_data is cleared. The received data is mapped to the relevant commands transmitted by counting cnt_data, as follows:

[0058] a. The third byte data: transmission control;

[0059] b. The fourth byte data: frequency;

[0060] c. The fifth byte data: pulse width;

[0061] d. The sixth and seventh bytes of data: signal type (CW or LFM);

[0062] The working process of the transmission signal waveform configuration module in step 3 above is as follows:

[0063] 3.1. First, determine the signal type. When the WAVE_TYPE signal is 00, the transmitted signal is in the CW type. When the WAVE_TYPE signal is 11, the transmitted signal is in the LFM type.

[0064] 3.2. Calculate the frequency f of the output sinusoidal signal out , the frequency control word of DDS is K, and the phase accumulator is N bits. Then, after 2N / K clock cycles, a sinusoidal signal of one cycle can be generated. Therefore, the frequency f of the output sinusoidal signal is out for:

[0065]

[0066] Where: K is the frequency control word, f c is the crystal frequency, and N is the number of DFFs in the frequency synthesis module.

[0067] When the operating frequency f out When the frequency is 40kHz, assuming the crystal frequency is 100MHz and N is 48, the K value can be calculated using the above formula.

[0068] 3.3、Output corresponding frequency waveform, f out The frequency of the output sinusoidal signal is determined by the pulse width, signal format and other parameter instructions sent by the ARM end. For a CW signal, it is a single-frequency signal. When the frequency is single, f out =f 0 ;

[0069] For the LFM signal form, its f out is a variable signal frequency form,

[0070] Linear frequency modulation

[0071] Where: f out is the output frequency, f clk is the system clock, n is the number of clocks, f 0 is the center frequency and B is the bandwidth.

[0072] Compared with the traditional technology, the present invention uses direct digital frequency synthesizer technology (DDS), which is a new frequency synthesis technology and signal generation method. It is based on digital control and uses a high-precision phase accumulator and a high clock signal to achieve high-resolution frequency synthesis. Since the frequency conversion speed of DDS mainly depends on the time required for the frequency control word to change, after the frequency control word changes, the phase accumulator needs to accumulate the phase increment through a clock cycle to achieve frequency conversion. Therefore, the higher the clock frequency, the faster the frequency conversion time is, which can reach the nanosecond level, and the frequency can be quickly switched. When the frequency is changed, the phase can be kept continuous, and the digital control modulation of the frequency, phase and amplitude can be easily achieved. The present invention can generate a corresponding single-frequency signal or LFM signal according to the received instructions of the working center frequency, bandwidth, pulse width and other parameters; in view of the design requirements of the sonar transmitting signal source, the present invention uses the XC6SLX16 / 25-2FTG256 chip as the core control part, and can generate a corresponding single-frequency signal or LFM signal waveform according to the instructions of the working center frequency, bandwidth, pulse width and other parameters sent by the ARM end. The system of the invention is a sonar signal source transmitting system which has high frequency resolution and can realize rapid frequency switching.

Claims

1. A sonar transmission signal source system based on DDS, characterized in that: It includes an ARM end, a main control circuit and a transmitting circuit. The ARM end is connected to the main control circuit, which is connected to the transmitting circuit. The ARM end sends working parameter instructions to the main control circuit. The main control circuit generates a corresponding waveform signal after receiving and parsing the instructions, and then filters the waveform signal through the transmitting circuit. The working parameters sent by the ARM end include center frequency, bandwidth, and pulse width. The main control circuit uses FPGA as the main controller. The FPGA main control circuit uses the XC6SLX16 / 25-2FTG256 chip. The FPGA main control circuit is also connected to a 50MHz clock crystal oscillator, a serial SPI configuration chip, a low-voltage difference voltage regulator chip and a JTAG interface. The low-voltage difference voltage regulator chip provides 3.3V and 1.2V voltages for the system.

2. The DDS-based sonar transmission signal source system as claimed in claim 1, characterized in that: The model of the serial SPI configuration chip is M25P16.

3. The DDS-based sonar transmission signal source system as claimed in claim 2, characterized in that: The low voltage dropout regulator chip model is AMS1117.

4. The DDS-based sonar transmission signal source system as claimed in claim 3, characterized in that: The P7 pin of the XC6SLX16 / 25-2FTG256 chip is connected to a 50MHz clock crystal, the P10 pin, T10 pin, and R11 pin are connected to M25P16, and the A15 pin, C14 pin, E14 pin, and C12 pin are connected to the JTAG interface.

5. A working method of a sonar transmitting signal source system based on DDS, wherein the system software control part adopts a layered architecture, including a top-level module, a clock IP core module, a transmitting signal waveform configuration module and an RS422 serial port driver configuration module, characterized in that: The following steps are included: Step 1, ARM sends the working parameter command to the FPGA main control circuit. The working parameter command is 8 bytes (64 bits) of data. The meaning of 8 bytes is as follows: a. 1-2 bytes: identifier; b. 3 bytes: transmission control; c. 4 bytes: frequency; d. 5 bytes: pulse width; e. 6-7 bytes: signal type (CW or LFM); f. 8 bytes: identifier; Step 2: After receiving the working parameter command sent by the ARM terminal, the FPGA main control circuit will parse the working parameter command to generate the transmission signal form, transmission center frequency, transmission bandwidth, and transmission pulse width parameters; Step 3: Analyze and generate the transmission signal form, transmission center frequency, transmission bandwidth, and transmission pulse width parameters to the transmission signal waveform configuration module. The transmission signal waveform configuration module realizes the excitation and drive of the transmission excitation signal form, and generates an excitation signal that meets the requirements and transmits it to the transmission circuit.

6. The working method of the DDS-based sonar transmission signal source system as claimed in claim 5, characterized in that: The working process of the transmission signal waveform configuration module in step 3 is as follows: 3.

1. First, determine the signal type, which includes CW signal and LFM signal; 3.

2. Calculate the frequency f of the output sinusoidal signal out , Where: K is the frequency control word, f c is the crystal frequency, N is the number of DFFs in the frequency synthesis module 3.

3. Output the corresponding frequency waveform, When the CW signal is single frequency, f out =f0; When the LFM signal is linear frequency modulated Where: f out is the output frequency, f clk is the system clock, n is the number of clocks, f0 is the center frequency, B is the bandwidth, and pulse width is the pulse width sent from the ARM end.

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