A method for placing a mask plate and a test key

Abstract

The present invention provides a method for placing a mask plate and a test key, wherein the mask plate includes a chip graphic area, a plurality of chip graphic areas are arranged in an array to form a chip area; an inner cutting road area is arranged between two adjacent rows of chip graphic areas; and a test key is arranged on the inner cutting road area; wherein the chip area is divided into a first peripheral area, a central area, and a second peripheral area connected in sequence; a plurality of test keys in the first peripheral area and the second peripheral area are arranged in sequence in the corresponding inner cutting road area; and the test keys in the central area are arranged in an outward diffusion shape with the center of the inner cutting road area located at the center as the center. Through the method for placing a mask plate and a test key provided by the present invention, the placed test keys can meet special measurement requirements.

Description

Technical Field

[0001] The invention relates to the field of semiconductors, and in particular to a method for placing a mask plate and a test key. Background Art

[0002] A test key is a small circuit structure used for electrical performance testing during semiconductor chip manufacturing. The test key is usually placed on the inner cutting area and is in the same direction as the chip. The inner cutting area is the area used to cut the wafer during semiconductor manufacturing. The inner cutting area can provide enough space for mechanical cutting to separate the wafer into individual chips.

[0003] In the semiconductor chip manufacturing process, during one exposure process, for a mask with similar length and width dimensions, since the maximum area that can be covered by the lithography machine is fixed, the number of inner cutting lanes in the mask that are placed in the same direction as the chip is reduced, resulting in a corresponding reduction in the number of test keys that can be placed, which cannot meet special measurement requirements. Therefore, there is room for improvement. Summary of the invention

[0004] The object of the present invention is to provide a method for placing a mask plate and a test key, so that the placed test key can meet special measurement requirements.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention provides a mask, comprising:

[0007] A chip pattern area, wherein a plurality of the chip pattern areas are arranged in an array to form a chip area;

[0008] An inner cutting road area is arranged between the chip pattern areas of two adjacent rows; and

[0009] A test key, arranged on the inner cutting track area;

[0010] The chip area is divided into a first peripheral area, a central area and a second peripheral area which are connected in sequence;

[0011] The plurality of test keys in the first peripheral area and the second peripheral area are sequentially arranged in the corresponding inner cutting lane areas;

[0012] The test keys in the central area are arranged to spread outwards with the center of the inner cutting path area located in the center as the center.

[0013] In one embodiment of the present invention, the first peripheral area is divided into a connected first area and a second area, the second peripheral area is divided into a connected third area and a fourth area, and the number of inner cutting road areas in the first area, the second area, the third area and the fourth area is equal.

[0014] In one embodiment of the present invention, the number of inner cutting street regions located in the central area is greater than the number of inner cutting street regions located in the first area.

[0015] In one embodiment of the present invention, among the multiple inner cutting street areas of any one of the first area, the second area, the third area and the fourth area, the multiple inner cutting street areas are sorted along the longitudinal direction of the chip graphic area, and the test keys are sequentially arranged in the inner cutting street areas of the first row. After the inner cutting street areas of the first row are filled, the remaining test keys are sequentially arranged in the inner cutting street areas of the next row.

[0016] In one embodiment of the present invention, among the multiple inner cutting road areas of any one of the first area, the second area, the third area and the fourth area, the multiple inner cutting road areas are sorted along the longitudinal direction of the chip graphic area, and the test keys are sequentially arranged in the inner cutting road areas of the last row. After the inner cutting road areas of the last row are filled, the remaining test keys are sequentially arranged in the inner cutting road areas of the previous row.

[0017] In one embodiment of the present invention, in the inner cutting street area, the test keys are arranged in the inner cutting street area in a sequential or reverse order along the lateral arrangement of the chip pattern area.

[0018] In one embodiment of the present invention, the number of inner cutting road areas in the central area is represented as n, and the multiple inner cutting road areas are sorted along the longitudinal direction of the chip graphic area. When n is an odd number, the first test key is set at the center of the inner cutting road area in the (n+1) / 2th row, and the other test keys are arranged on the inner cutting road area in an outward diffusion shape with the position of the first test key as the center.

[0019] In one embodiment of the present invention, when n is an even number, the first test key is arranged at the center of the inner cutting path area of ​​the n / 2th row or the (n+2) / 2th row, and the other test keys are arranged on the inner cutting path area in an outwardly diffused manner with the position of the first test key as the center.

[0020] In one embodiment of the present invention, after determining the location of the first test key, the other test keys are arranged around the periphery of the first test key in a rectangular shape with the location of the first test key as the center, and the other test keys are arranged in a counterclockwise or clockwise order on the rectangular shape.

[0021] The present invention also provides a method for placing test keys of a mask, comprising:

[0022] Providing a mask;

[0023] Setting a chip pattern area on the mask, wherein a plurality of the chip pattern areas are arranged in an array to form a chip area;

[0024] An inner cutting path area is provided between the chip pattern areas of two adjacent rows;

[0025] Dividing the chip area into a first peripheral area, a central area and a second peripheral area which are connected in sequence;

[0026] In the first peripheral area and the second peripheral area, a plurality of test keys are sequentially arranged in the inner cutting track area;

[0027] In the central area, a plurality of test keys are arranged in the inner cutting track area in a diffused manner outwardly with the center of the inner cutting track area located at the center as the center.

[0028] As described above, the present invention provides a method for placing a mask and a test key. For a mask with similar length and width dimensions, by limiting the placement position of the test key for the through-hole layer without affecting conventional electrical measurements, the test key can meet special measurement requirements, thereby solving the problem of insufficient cutting path space in the traditional structure to place the test key.

[0029] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0031] Figure 1 is a schematic diagram of a mask in one embodiment of the present invention;

[0032] Figure 2 A schematic diagram of dividing a chip graphic area into nine-square grids in one embodiment of the present invention;

[0033] Figure 3 A schematic diagram of dividing a chip graphic area into four quadrants in one embodiment of the present invention;

[0034] Figure 4 A schematic diagram of dividing a chip graphic area into different areas in one embodiment of the present invention;

[0035] Figure 5 A schematic diagram of the placement of the test keys in the first area in one embodiment of the present invention;

[0036] Figure 6 is another schematic diagram of the placement of the test keys in the first area in one embodiment of the present invention;

[0037] Figure 7 A schematic diagram of another arrangement of the test keys in the first area in one embodiment of the present invention;

[0038] Figure 8 It is another schematic diagram of the placement of the test keys in the first area in one embodiment of the present invention;

[0039] Fig. 9 A schematic diagram of the placement of test keys in the central area in one embodiment of the present invention;

[0040] Fig.10 A schematic diagram of another arrangement of the test keys in the central area in one embodiment of the present invention;

[0041] Fig.11 It is a flow chart of a method for placing test keys of a mask in one embodiment of the present invention;

[0042] Fig.12 Schematic diagram of the measurement structure.

[0043] In the figure: 10, chip pattern area; 20, inner cutting road area; 30, test key; 40, chip area; 50, first area; 60, second area; 70, central area; 80, third area; 90, fourth area;

[0044] 411, Region 1; 412, Region 2; 413, Region 3; 414, Region 4; 415, Region 5; 416, Region 6; 417, Region 7; 418, Region 8; 419, Region 9;

[0045] 421, first quadrant; 422, second quadrant; 423, third quadrant; 424, fourth quadrant;

[0046] 100, first measurement structure; 200, second measurement structure; 300, third measurement structure. DETAILED DESCRIPTION

[0047] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0048] See also Figure 1 The present invention proposes a method for placing a mask and a test key, which can place the test key on the mask, especially for placing the test key 30 (Testkeys) used for special repeat uniformity function test.

[0049] See also Figure 1 In one embodiment, the mask may include a chip pattern area 10 , an inner cutting road area 20 and a test key 30 .

[0050] See also Figure 1 In one embodiment, during the wafer illumination and development process, the chip pattern area 10 on the mask is shielded to form a chip area on the wafer in the subsequent process. In one exposure unit (shot), the number of chip pattern areas 10 is multiple, and the multiple chip pattern areas 10 can be arranged in a rectangular array to form a chip area 40.

[0051] See also Figure 1 In one embodiment, the inner cutting road area 20 can be set between two adjacent rows of chip pattern areas 10. The inner cutting road area 20 refers to an area reserved between chips on a wafer for subsequent wafer cutting and separation. In the inner cutting road area 20, alignment marks and test keys 30 can be set for use in the manufacturing and testing process.

[0052] See also Figure 1 In one embodiment, the test keys 30 can be divided into test keys 30 for metal interconnect layers and test keys 30 for via layers according to the locations of different layers on the wafer.

[0053] In one embodiment, the test key 30 for the metal interconnect layer can be used for conventional process electrical testing. Conventional process electrical testing may include measuring the resistance, conductivity and other electrical properties of the metal interconnect layer to ensure the reliability and performance of these layers in actual use. The test key 30 for the metal interconnect layer may not be subject to position restrictions and may be located at any position in the inner cutting area 20 as long as the test requirements can be met.

[0054] In one embodiment, the test key 30 for the via layer can be used for special repeated uniformity functional tests. These tests can focus on detecting the uniformity and consistency of the via layer. Ensure that each via has consistent electrical performance in different locations and on different chips. The test key 30 for the via layer needs to be subject to positional restrictions.

[0055] In one embodiment, since the test key 30 is designed for testing film layers with different functions, although the number of all film layers (Full Layer) in the entire process is greater than the number of film layers (Testkey Layers) specifically used for testing, the test key 30 only selects the key film layers that need to be monitored. Therefore, the number and size of film layers specifically used for testing will not increase. In the actual process technology, the number of film layers where the test keys 30 for the through-hole layer are located needs to be determined based on the number of film layers where the test keys 30 for the metal interconnect layer are located. Therefore, the number of film layers where the test keys 30 for the through-hole layer are located is limited, and the test keys 30 for the through-hole layer need to be specially arranged to meet the special repetitive uniformity functional test.

[0056] See also Figure 2 In one embodiment, the chip region 40 formed by the plurality of chip graphic regions 10 may be in the shape of an M×N rectangular shape, where M represents the number of rows, N represents the number of columns, and M and N are positive integers. The chip region 40 may be divided in a nine-square grid manner to obtain nine different regions. These regions may be divided into region 1 411, region 2 412, region 3 413, region 414, region 5 415, region 6 416, region 7 417, region 8 418, and region 9 419.

[0057] See also Figure 3 In one embodiment, the chip region 40 is divided into four different regions in the form of coordinate axes with the center of the chip region 40 as the center. These regions can be divided into a first quadrant region 421, a second quadrant region 422, a third quadrant region 423, and a fourth quadrant region 424.

[0058] See also Figure 4In one embodiment, according to the above division method, the chip area 40 can be re-divided to obtain 5 different areas. These areas can be divided into a first area 50 (Va), a second area 60 (Vb), a central area 70 (Vc), a third area 80 (Vd) and a fourth area 90 (Ve). Among them, the first area 50 can include area one 411 and part of area four 414. The second area 60 can include the remaining part of area four 414 and area seven 417. The central area 70 can include area two 412, area five 415 and area eight 418. The third area 80 can include area three 413 and part of area six 416. The fourth area 90 can include the remaining part of area six 416 and area nine 419.

[0059] See also Figure 4 In one embodiment, the first area 50 and the second area 60 may form a first peripheral area. The third area 80 and the fourth area 90 may form a second peripheral area. At this time, the first peripheral area, the central area 70 and the second peripheral area may be connected in sequence, and the number of inner cutting road areas 20 therein may be the same. At the same time, the number of inner cutting road areas 20 located in the first area 50, the second area 60, the third area 80 and the fourth area 90 is equal. The number of inner cutting road areas 20 located in the central area 70 is greater than the number of inner cutting road areas 20 located in the first area 50. This is because a large number of measurement patterns (CD patterns) and photolithography alignment marks (Photo Mark) need to be placed in the inner cutting road areas 20 located in the central area 70 to ensure the accuracy of the manufacturing process and product quality.

[0060] See also Figure 4 In one embodiment, in the inner cutting zone 20 located in the first peripheral area, the central area 70 and the second peripheral area, the test keys 30 for the through-hole layer need to be placed according to a certain rule to meet the needs of subsequent special measurements.

[0061] See also Figure 4 In one embodiment, in the first peripheral area and the second peripheral area, a plurality of test keys 30 need to be sequentially arranged in the corresponding inner cutting lane areas 20. Taking the first area 50 as an example, a plurality of inner cutting lane areas 20 may be arranged in the first area 50.

[0062] In one embodiment, since the inner cutting street regions 20 are arranged in a lateral direction along the chip pattern region 10 , the inner cutting street regions 20 may be sorted in a longitudinal direction along the chip pattern region 10 to obtain the sorted inner cutting street regions 20 .

[0063] In one embodiment, for the multiple test keys 30 that need to be set in the first area 50, the multiple test keys 30 can be sequentially set in the first row of the inner cutting street area 20. After the first row of the inner cutting street area 20 is filled, the remaining test keys 30 are sequentially set in the next row of the inner cutting street area 20. For example, 4 test keys 30 are set in the inner cutting street area 20, and the number of test keys in each group is 4.

[0064] In one embodiment, the first group of test keys can be sequentially arranged in the first row of the cutting street area 20. The second group of test keys can be sequentially arranged in the second row of the cutting street area 20. Similarly, the nth group of test keys can be sequentially arranged in the nth row of the cutting street area 20, where n is a positive integer.

[0065] In one embodiment, the first group of test keys can be sequentially arranged in the last row of the inner cutting street area 20. After the inner cutting street area of ​​the last row is filled, the remaining test keys 30 are sequentially arranged in the inner cutting street area 20 of the previous row. For example, the second group of test keys can be sequentially arranged in the inner cutting street area 20 of the second to last row. By analogy, the last group of test keys can be sequentially arranged in the inner cutting street area 20 of the first row.

[0066] In one embodiment, in a certain row of the inner cutting street area 20, a plurality of test keys 30 may be sequentially arranged in the inner cutting street area 20 along the lateral arrangement direction of the chip pattern area 10, or may be arranged in the inner cutting street area 20 in reverse order along the lateral arrangement direction of the chip pattern area 10. The specific order of the arrangement of the test keys 30 may be set according to actual needs.

[0067] See also Figure 5 , Figure 6 , Figure 7 and Figure 8 In one embodiment, in the inner cutting lane area 20 located in the first area 50, the second area 60, the third area 80 and the fourth area 90, the arrangement of the test keys 30 may be the same or different. Take the arrangement of 8 test keys 30 in the first area 50 as an example for explanation. The 8 test keys 30 may be divided into TK1, TK2, TK3, TK4, TK5, TK6, TK7 and TK8 in sequence.

[0068] See also Figure 5 In one embodiment, in the first row of the cutting zone 20, the test keys 30 may be arranged in the order of TK1, TK2, TK3, and TK4. In the second row of the cutting zone 20, the test keys 30 may be arranged in the order of TK5, TK6, TK7, and TK8.

[0069] See also Figure 6In one embodiment, in the last row of the cutting road area 20, the test keys 30 can be arranged in the order of TK1, TK2, TK3, and TK4. In the penultimate row of the cutting road area 20, the test keys 30 can be arranged in the order of TK5, TK6, TK7, and TK8.

[0070] See also Figure 7 In one embodiment, in the first row of the cutting zone 20, the test keys 30 may be arranged in the order of TK4, TK3, TK2, and TK1. In the second row of the cutting zone 20, the test keys 30 may be arranged in the order of TK8, TK7, TK6, and TK5.

[0071] See also Figure 8 In one embodiment, in the last row of the cutting road area 20, the test keys 30 may be arranged in the order of TK4, TK3, TK2, and TK1. In the penultimate row of the cutting road area 20, the test keys 30 may be arranged in the order of TK8, TK7, TK6, and TK5.

[0072] In one embodiment, the specific arrangement of the test keys 30 in the first area 50 , the second area 60 , the third area 80 and the fourth area 90 is not limited, as long as it can satisfy the horizontal arrangement direction sequence or reverse sequence of the chip pattern area 10 .

[0073] In one embodiment, since a large number of measurement patterns and photolithography alignment marks need to be placed in the inner cutting zone 20 in the central area 70, multiple test keys 30 need to be arranged in the corresponding inner cutting zone 20 in the central area 70 in sequence according to another rule.

[0074] See also Fig. 9 and Fig.10 In one embodiment, in the inner cutting lane area 20 located in the central area 70, the test keys 30 also need to be arranged in a certain manner, and the first test key 30 needs to be set at the center of the inner cutting lane area 20 located at the center of the central area 70. Since the number of the inner cutting lane areas 20 located in the central area 70 may be an even number or an odd number, the specific position of the first test key 30 needs to be determined according to the number of the inner cutting lane areas 20 located in the central area 70.

[0075] In one embodiment, the number of inner cutting street areas 20 located in the central area 70 can be expressed as n. At this time, the multiple inner cutting street areas 20 located in the central area 70 can be sorted along the longitudinal direction of the chip pattern area 10, thereby obtaining multiple sorted inner cutting street areas 20. When n is an odd number, the first test key 30 can be set at the center of the inner cutting street area 20 in the (n+1) / 2th row. When n is an even number, the first test key 30 can be set at the center of the inner cutting street area 20 in the n / 2th row or the (n+2) / 2th row. For example, when the number of inner cutting street areas 20 is 5, the first test key 30 can be set at the center of the inner cutting street area 20 in the 3rd row. For another example, when the number of inner cutting street areas 20 is 6, the first test key 30 can be set at the center of the inner cutting street area 20 in the 3rd row or the 4th row.

[0076] In one embodiment, since there are multiple positions in the inner cutting zone 20 for placing the test key 30, the number may be an odd number or an even number. Therefore, the specific position of the first test key 30 in the inner cutting zone 20 also needs to be set. For example, the number of positions in the inner cutting zone 20 for placing the test key 30 can be expressed as m. When m is an odd number, the first test key 30 can be set at the (m+1) / 2th position. When n is an even number, the first test key 30 can be set at the n / 2th or (n+2) / 2th position. For example, when the number of positions in the inner cutting zone 20 where the test key 30 can be placed is 5, the first test key 30 can be set at the third position. For another example, when the number of positions in the inner cutting zone 20 where the test key 30 can be placed is 6, the first test key 30 can be set at the third position or the fourth position.

[0077] See also Fig. 9 and Fig.10 In one embodiment, after determining the specific position of the first test key 30 in the central area 70, the distribution positions of other test keys 30 can be determined according to the position of the first test key 30. For example, other test keys 30 can be arranged on the inner cutting path area 20 in an outwardly diffused shape with the position of the first test key 30 as the center.

[0078] In one embodiment, after the position of the first test key 30 is determined, the inner cutting zone 20 where it is located can be represented as the central inner cutting zone, and the number of rows in the central inner cutting zone can be represented as y. Since the test keys 30 are set on the inner cutting zone 20 at equal intervals, the inner cutting zone 20 of the (y-1)th row and the (y+1)th row can also be provided with corresponding positions for setting the test keys 30. When other test keys 30 need to be set, the other test keys 30 can be set around the first test key 30 with the first test key 30 as the center.

[0079] In one embodiment, the other test keys 30 can be arranged along a rectangle with the first test key 30 as the center, and can be arranged around the periphery of the first test key 30. Three test keys 30 can be arranged on the inner cutting road area 20 of the previous row and the next row, respectively. Test keys 30 can also be arranged on both sides of the first test key 30, respectively. At this time, the eight test keys 30 can cooperate with each other to form a rectangular shape around the first test key 30.

[0080] See also Fig. 9 and Fig.10 In one embodiment, 12 test keys 30 are set in the central area 70 as an example for explanation. The 12 test keys 30 can be divided into TK1, TK2, TK3, TK4, TK5, TK6, TK7, TK8, TK9, TK10, TK11, and TK12 in sequence. Among them, TK1 can be set at the center of the central inner cutting road area. For TK2, TK3, TK4, TK5, TK6, TK7, TK8, and TK9, 6 of them can be set on the inner cutting road area 20 of the (y-1) row and the (y+1) row, respectively, and the other 2 can be set on both sides of TK1, respectively. At this time, TK2, TK3, TK4, TK5, TK6, TK7, TK8, and TK9 can form an approximately rectangular shape, and TK1 is located at the center of the rectangle. TK10, TK11, and TK12 may be disposed on at least one of the inner cutting lane areas 20 of the (y-2) row, the y row, and the (y+2) row. For example, TK10, TK11, and TK12 may be disposed on the (y-2) row or the (y+2) row.

[0081] In one embodiment, when the central area 70 needs to be provided with a plurality of test keys 30, different test keys 30 can cooperate with each other to be provided on different inner cutting lane areas 20, thereby forming rectangles of different sizes. Different rectangles can be provided on the central area 70 in an outwardly diffused shape with the location of the first test key 30 as the center.

[0082] See also Fig. 9 and Fig.10In one embodiment, when multiple test keys 30 cooperate with each other to form a rectangular shape centered at the location of the first test key 30, multiple test keys 30 also need to be arranged on the rectangle according to certain rules. For example, multiple test keys 30 are arranged in a counterclockwise or clockwise order on the rectangular shape.

[0083] See also Fig.11 The present invention also provides a method for placing test keys of a mask, which can be applied to the above-mentioned mask to place the test keys 30. The placement method may include the following steps:

[0084] Step S10, providing a mask;

[0085] Step S20, setting a chip pattern area on the mask, wherein a plurality of chip pattern areas are arranged in an array to form a chip area;

[0086] Step S30, setting an inner cutting track area between two adjacent rows of chip pattern areas;

[0087] Step S40, dividing the chip area into a first peripheral area, a central area, and a second peripheral area that are sequentially connected;

[0088] Step S50, in the first peripheral area and the second peripheral area, a plurality of test keys are sequentially arranged in the inner cutting path area;

[0089] Step S60: In the central area, a plurality of test keys are arranged in the inner cutting zone in a diffused manner with the center of the inner cutting zone at the center as the center.

[0090] See also Fig.12 In one embodiment, after the test key 30 is placed in the corresponding inner scribe line area 20, the test key 30 can be formed on the corresponding scribe line of the wafer through processes such as exposure. When uniformity measurement is required at the lower left corner, center, and upper right corner of the wafer, for the uniformity measurement of the lower left corner of the wafer, the first measurement structure (TK V1) 100 can be formed by the test keys 30 in the second area 60 (Vb) and the central area 70 (Vc). For the uniformity measurement at the center of the wafer, the second measurement structure (TK V2) 200 can be formed by the test keys 30 in the first area 50 (Va) and the central area 70 (Vc). For the uniformity measurement at the upper right corner of the wafer, the third measurement structure (TK V3) 300 can be formed by the test keys 30 in the third area 80 (Vc) and the fourth area 90 (Vd).

[0091] It can be seen that in the above scheme, the unexpected effect of the present invention is that, for mask plates with similar length and width dimensions, by limiting the placement of the test keys for the through-hole layer without affecting conventional electrical measurements, the test keys can meet special measurement requirements, thereby solving the problem of insufficient cutting path space in the traditional structure to place the test keys.

[0092] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A mask, characterized in that: include: A chip pattern area, wherein a plurality of the chip pattern areas are arranged in an array to form a chip area; An inner cutting road area is arranged between the chip pattern areas of two adjacent rows; as well as A test key, arranged on the inner cutting track area; The chip area is divided into a first peripheral area, a central area and a second peripheral area which are connected in sequence; The plurality of test keys in the first peripheral area and the second peripheral area are sequentially arranged in the corresponding inner cutting road areas; the first peripheral area is divided into a first area and a second area connected, the second peripheral area is divided into a third area and a fourth area connected, the number of inner cutting road areas in the first area, the second area, the third area and the fourth area is equal; the number of inner cutting road areas in the central area is greater than the number of inner cutting road areas in the first area; The test keys in the central area are arranged to spread outwards with the center of the inner cutting path area located in the center as the center.

2. The mask according to claim 1, characterized in that: In the multiple inner cutting road areas of any one of the first area, the second area, the third area and the fourth area, the multiple inner cutting road areas are sorted along the longitudinal direction of the chip graphic area, and the test keys are sequentially arranged in the inner cutting road areas of the first row. After the inner cutting road areas of the first row are filled, the remaining test keys are sequentially arranged in the inner cutting road areas of the next row.

3. The mask according to claim 1, characterized in that: In the multiple inner cutting road areas of any one of the first area, the second area, the third area and the fourth area, the multiple inner cutting road areas are sorted along the longitudinal direction of the chip graphic area, and the test keys are sequentially arranged in the inner cutting road areas of the last row. After the inner cutting road areas of the last row are filled, the remaining test keys are sequentially arranged in the inner cutting road areas of the previous row.

4. The mask according to claim 2 or 3, characterized in that: In the inner cutting street area, the test keys are arranged in the inner cutting street area in a sequential or reverse order along the lateral arrangement of the chip pattern area.

5. The mask according to claim 1, characterized in that: The number of inner cutting lane areas in the central area is represented as n, and the multiple inner cutting lane areas are sorted along the longitudinal direction of the chip graphic area. When n is an odd number, the first test key is set at the center of the inner cutting lane area in the (n+1) / 2th row, and the other test keys are arranged on the inner cutting lane area in an outward diffusion shape with the position of the first test key as the center.

6. The mask according to claim 5, characterized in that: When n is an even number, the first test key is arranged at the center of the inner cutting path area of ​​the n / 2th row or the (n+2) / 2th row, and the other test keys are arranged on the inner cutting path area in an outwardly diffused manner with the position of the first test key as the center.

7. The mask according to claim 5 or 6, characterized in that: After determining the location of the first test key, the other test keys are arranged around the first test key in a rectangular shape with the location of the first test key as the center, and the other test keys are arranged in a counterclockwise or clockwise order on the rectangular shape.

8. A method for placing test keys of a mask, characterized in that: include: Providing a mask; Setting a chip pattern area on the mask, wherein a plurality of the chip pattern areas are arranged in an array to form a chip area; An inner cutting path area is provided between the chip pattern areas of two adjacent rows; Dividing the chip area into a first peripheral area, a central area and a second peripheral area which are connected in sequence; In the first peripheral area and the second peripheral area, a plurality of test keys are sequentially arranged in the inner cutting road area; the first peripheral area is divided into a first area and a second area connected, the second peripheral area is divided into a third area and a fourth area connected, the number of the inner cutting road areas in the first area, the second area, the third area and the fourth area is equal; the number of the inner cutting road areas in the central area is greater than the number of the inner cutting road areas in the first area; In the central area, a plurality of test keys are arranged in the inner cutting track area in a diffused manner outwardly with the center of the inner cutting track area located at the center as the center.

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