Read-write acceleration method and device, storage control chip and storage medium

Abstract

The invention discloses a read-write acceleration method and device, a storage control chip and a storage medium. The method comprises the following steps: processing a plurality of operation instructions according to a preset configuration rule to obtain a multi-transmission operation instruction list; storing the multi-transmission operation instruction list into a static random storage area; and reading the multi-transmission operation instruction table, and loading the operation instructions in the multi-transmission operation instruction table one by one to complete Flash read-write operation. According to the method, the MT mode is adopted to read and write the Flash, compared with an ST mode, the generated multi-transmission operation instruction list is stored in the static random storage area, and the NFCMU module for managing the Flash in the master control can directly access the static random storage area to read and load the multi-transmission operation instruction list, so that the Flash can be read and written in the MT mode. According to the invention, it is unnecessary to consume extra time to execute corresponding firmware codes to realize reading and loading in a CPU, so that the read-write operation processing of each main controller on Flash is accelerated.

Description

Technical Field

[0001] The present invention relates to the field of flash memory technology, and in particular to a read-write acceleration method, device, storage control chip and storage medium. Background Art

[0002] NAND Flash (Flash for short, the same below) is the most mainstream storage medium today and is widely used in the manufacture of various types of storage products, such as USB flash drives, SD cards, and SSDs (solid state drives). Storage products include storage control chips (referred to as master control, the same below), Flash, and PCB. The master control runs firmware that manages Flash to store data, and the PCB serves as a substrate for the electrical connection between the master control and Flash.

[0003] The read and write performance of storage products is positively correlated with the price. The higher the read and write performance, the higher the price. The read and write performance of storage products is affected by the master control, Flash, and firmware. In the related art, each time Flash performs a read and write task, the master control needs to configure a single operation instruction (Single Transfer, ST) to perform this read and write task. In ST mode, since it is the master control's CPU that operates the register to complete the operation instruction configuration, and the CPU execution code takes a certain amount of time, this will directly affect the read and write performance of Flash. Summary of the invention

[0004] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a read / write acceleration method, device, storage control chip and storage medium, which can improve the read / write performance of Flash. The first aspect of the present application provides a read / write acceleration method, comprising:

[0005] Processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table;

[0006] Storing the multi-transfer operation instruction table in a static random access memory area;

[0007] The multi-transfer operation instruction table is read, and the operation instructions in the multi-transfer operation instruction table are loaded one by one to complete the read and write operations on the Flash.

[0008] In one preferred embodiment, the processing of multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table includes:

[0009] When DMA processes the current batch of data, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transfer operation instruction table, which is used for processing the next batch of data.

[0010] In one preferred embodiment, the processing of multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table includes:

[0011] Read the operation information from the host, and determine the required operation instructions according to the operation information;

[0012] Sorting the plurality of operation instructions according to the operation sequence of the operation information;

[0013] Based on the sorting result, the plurality of operation instructions are combined, and an operation end flag is added at the end to obtain a multi-transmission operation instruction table.

[0014] In one of the preferred embodiments, the operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor, and the upper 4 bits represent the instruction information.

[0015] A second aspect of the present application provides a read-write acceleration device, comprising:

[0016] A configuration module, used for processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table;

[0017] A storage module, used for storing the multi-transmission operation instruction table in a static random access memory area;

[0018] The operation module is used to read the multi-transmission operation instruction table and load the operation instructions in the multi-transmission operation instruction table one by one to complete the read and write operations on the Flash.

[0019] In one preferred embodiment, the configuration module is used to process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table, including:

[0020] When DMA processes the current batch of data, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transfer operation instruction table, which is used for processing the next batch of data.

[0021] In one preferred embodiment, the configuration module includes:

[0022] A reading unit, used to read the operation information from the host end, and determine the required operation instructions according to the operation information;

[0023] A sorting unit, used to sort the plurality of operation instructions according to the operation sequence of the operation information;

[0024] The identification unit is used to combine the multiple operation instructions based on the sorting result, and add an operation end identification bit at the end to obtain a multi-transmission operation instruction table.

[0025] In one of the preferred embodiments, the operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor, and the upper 4 bits represent the instruction information.

[0026] A third aspect of the present application provides a storage control chip, comprising the read-write acceleration device as described above.

[0027] A fourth aspect of the present application provides a computer-readable storage medium storing executable code, which, when executed by a processor of an electronic device, enables the processor to execute the read-write acceleration method as described above.

[0028] The technical solution of the present application includes: processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table; storing the multi-transmission operation instruction table in a static random storage area; reading the multi-transmission operation instruction table, and loading the operation instructions in the multi-transmission operation instruction table one by one to complete the Flash read and write operations. The present application uses the MT mode to realize the reading and writing of Flash. Compared with the ST mode, the generated multi-transmission operation instruction table is stored in the static random storage area. The NFCMU module that manages Flash inside the main control can directly access the static random storage area to read and load the multi-transmission operation instruction table, without involving the CPU to consume extra time to execute the corresponding firmware code to realize reading and loading, thereby speeding up the main control's each read and write operation processing of Flash. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0030] Figure 1 It is a flowchart of a read-write acceleration method shown in an embodiment of the present application;

[0031] Figure 2 FIG. 1 is a flow chart of a read / write acceleration method in another embodiment of the present application;

[0032] Figure 3 Shown is a schematic diagram of the structure of a read-write acceleration device in an embodiment of the present application;

[0033] Figure 4 Shown is a schematic structural diagram of a read-write acceleration device in another embodiment of the present application;

[0034] Figure 5 FIG. 1 is a schematic diagram of the structure of a storage control chip in an embodiment of the present application;

[0035] Figure 6 Shown is a schematic diagram of the architecture of a storage control chip of the related art;

[0036] Figure 7 Shown is a schematic diagram of the architecture of the storage control chip of the present application;

[0037] Figure 8 Shown is a schematic diagram of waveform comparison between the related art and the present application. DETAILED DESCRIPTION

[0038] In order to facilitate the understanding of the present invention, the present invention will be described more comprehensively with reference to the accompanying drawings. The preferred embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thoroughly understood.

[0039] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only and do not represent the only implementation method.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0041] In the related art, each time Flash performs a read or write task, the master controller needs to configure a single operation instruction (SingleTransfer, ST) to execute this read or write task. In ST mode, since the master controller's CPU operates the register to complete the operation instruction configuration, and the CPU takes a certain amount of time to execute the code, this will directly affect the read and write performance of Flash.

[0042] Therefore, in order to solve the above technical problems, the present application provides a read-write acceleration method that can improve the read-write performance of Flash.

[0043] The technical solution of the present application is described in detail below with reference to the accompanying drawings.

[0044] Figure 1 The figure is a flow chart of a read-write acceleration method in one embodiment of the present application.

[0045] See also Figure 1 , a read-write acceleration method, comprising the following steps:

[0046] Step S110: Process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table.

[0047] It should be noted that an operation instruction is an instruction that enables Flash to perform read and write tasks. In layman's terms, it is equivalent to a "commander". Every time Flash performs a read and write task, it needs to "tell" Flash how to operate on the data.

[0048] In this embodiment, the structure of the operation instruction is shown in Table 1. Each operation instruction occupies at least 1 byte, where the "index factor" represents the specific type of the operation instruction, usually represented by the lower 4 bits. The "instruction information" represents the specific data included in the operation instruction, and the "instruction information" included in different types of operation instructions may be the same or different.

[0049] Position (unit: Bit) ≥4 0～3 type Command information (Info) Index factor

[0050] Table 1

[0051] The type and structure of the operation instruction can be designed by the master control manufacturer and are not specifically limited in this embodiment. For various storage protocols, common types of operation instructions may include the following: no operation, delayed operation, send command, send address, send small amount of data, send bulk data, receive small amount of data, receive bulk data, jump operation, end operation, etc. Among them, send address, send data, send small amount of data, receive small amount of data, send bulk data, receive bulk data are the most commonly used operations of the master control on Flash.

[0052] For example, if the operation instruction is to send an address, the corresponding index factor may be "0x05"; the instruction information includes the address length + address information, where the length of a single address is configurable, generally 4 bytes; the address information may be 1 or more.

[0053] For another example, if the operation instruction is to send a small amount of data, the corresponding index factor may be "0x06"; the instruction information includes data length + data, where the total length of the data is configurable, generally 4 bytes; the data may be 1 or more.

[0054] For example, if the operation instruction is to send batch data, the corresponding index factor can be "0x08"; the instruction information BufferID address + check code, BufferID address is the address to get data, BufferID address is equal to 2 N The check code is the check code of the data, which is used to verify the data to ensure the accuracy of the data.

[0055] In this embodiment, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transmission operation instruction table, which can be implemented as follows: read the operation information from the Host end, and determine the required operation instructions based on the operation information; sort the multiple operation instructions according to the operation order of the operation information; combine the multiple operation instructions based on the sorting result, and add an operation end identification bit at the end to obtain a multi-transmission operation instruction table.

[0056] Step S120, storing the multi-transfer operation instruction table in the static random access memory area.

[0057] It should be noted that the obtained multi-transfer operation instruction table is stored in a static random access memory area, namely, SRAM, and can be easily accessed at any time, thereby improving the reading and loading of the multi-transfer operation instruction table.

[0058] Step S130, read the multi-transfer operation instruction table, and load the operation instructions in the multi-transfer operation instruction table one by one to complete the Flash read and write operations.

[0059] The technical solution of this embodiment uses the MT mode to realize the reading and writing of Flash. Compared with the ST mode, the generated multi-transmission operation instruction table is stored in the static random storage area. The NFCMU module that manages the Flash inside the main control can directly access the static random storage area to read and load the multi-transmission operation instruction table, without involving the CPU to consume extra time to execute the corresponding firmware code to realize reading and loading, thereby speeding up each read and write operation processing of the main control on the Flash.

[0060] In addition, the technical solution of this embodiment does not require the Flash to execute each read and write task. The CPU needs to operate the register configuration to complete a single operation instruction each time before executing the current read and write task. The multi-transfer operation instruction table of this embodiment includes multiple operation instructions, and there is no need to wait for the CPU to configure the next operation instruction to be completed before executing the read and write of the next data after each data read and write is completed.

[0061] Figure 2 Shown is a flow chart of a read-write acceleration method in another embodiment of the present application.

[0062] See also Figure 2 , a read-write acceleration method, comprising the following steps:

[0063] Step S210: When DMA processes the current batch of data, multiple operation instructions are processed according to the preset configuration rules to obtain a multi-transfer operation instruction table, which is used for processing the next batch of data.

[0064] It should be noted that an operation instruction is an instruction that enables Flash to perform read and write tasks. In layman's terms, it is equivalent to a "commander". Every time Flash performs a read and write task, it needs to "tell" Flash how to operate on the data.

[0065] In this embodiment, the structure of the operation instruction is shown in Table 1 of step S110, which will not be described here. Each operation instruction occupies at least 1 byte, where the "index factor" represents the specific type of the operation instruction, usually represented by the lower 4 bits. The "instruction information" represents the specific data included in the operation instruction, and the "instruction information" included in different types of operation instructions may be the same or different.

[0066] The type and structure of the operation instruction can be designed by the master control manufacturer and are not specifically limited in this embodiment. For various storage protocols, common types of operation instructions may include the following: no operation, delayed operation, send command, send address, send a small amount of data, send bulk data, receive a small amount of data, receive bulk data, jump operation, end operation, etc. Among them, sending address, sending data, sending a small amount of data, receiving a small amount of data, sending bulk data, and receiving bulk data are the most commonly used operations of the master control on Flash. Please refer to step S110 for the schematic diagram of the operation type, which will not be repeated here.

[0067] In this embodiment, the current state of DMA is read. When DMA processes the current batch of data, the generation process of the multi-transfer operation instruction table is started, and the multiple operation instructions are processed using the preset configuration rules to obtain the multi-transfer operation instruction table, which is used for the next batch of data processing. When the multi-transfer operation instruction table is obtained using the preset configuration rules and multiple operation instructions, the timing selection point of the processing is optimized. DMA (Direct Memory Access) plays the role of processing data in the main control. When DMA processes data, it can use the preset configuration rules and multiple operation instructions to obtain the multi-transfer operation instruction table in advance, prepare for the next DMA to process data, shorten the interval time between DMA processing two data, and thereby improve the read and write performance of Flash.

[0068] Step S220: store the multi-transfer operation instruction table into the static random access memory area.

[0069] It should be noted that the obtained multi-transfer operation instruction table is stored in a static random access memory area, namely, SRAM, and can be easily accessed at any time, thereby improving the reading and loading of the multi-transfer operation instruction table.

[0070] Step S230: read the multi-transfer operation instruction table, and load the operation instructions in the multi-transfer operation instruction table one by one to complete the Flash read and write operations.

[0071] The technical solution of this embodiment uses the MT mode to realize the reading and writing of Flash. Compared with the ST mode, the generated multi-transmission operation instruction table is stored in the static random storage area. The NFCMU module that manages the Flash inside the main control can directly access the static random storage area to read and load the multi-transmission operation instruction table, without involving the CPU to consume extra time to execute the corresponding firmware code to realize reading and loading, thereby speeding up each read and write operation processing of the main control on the Flash.

[0072] In addition, the technical solution of this embodiment does not require the Flash to execute each read and write task. The CPU needs to operate the register configuration to complete a single operation instruction each time before executing the current read and write task. The multi-transfer operation instruction table of this embodiment includes multiple operation instructions, and there is no need to wait for the CPU to configure the next operation instruction to be completed before executing the read and write of the next data after each data read and write is completed.

[0073] In order to better understand the technical solution of the present application, the technical effects that can be achieved by the present application are described in detail below through specific cases (demonstrated in terms of the writing process, the reading process is similar to the writing process, and can be understood by referring to the writing process).

[0074] like Figure 6 The figure shows a schematic diagram of the architecture of the main control in the related art. The main control 800 includes: a CPU module 810, a register SFR820, an NFCMU module 830 and a DMA module 840, and the above functional modules interact through an AHB bus (not shown). Among them, the CPU module 810 receives signals and data from the Host end and manages other functional modules. The NFCMU module is used to manage Flash1000 and is the core functional module for the interaction between the main control 800 and Flash1000.

[0075] According to the processing flow of the main control 800 in the related art, when several data (including data A, B, C, D, E, F, G, H and I) are received, if these data are to be written into the Flash, first, the CPU module 810 needs to operate the register SFR820 to configure a single operation instruction (ST), that is, each data will need to correspond to 1 operation instruction before the operation, the main control 800 performs 8 write operations, and correspondingly, the CPU module 810 also needs to operate the register SFR820 8 times, otherwise 8 operation instructions cannot be generated, and the DMA module 840 needs to bring up the operation instruction corresponding to the read and load data before processing each data, such as Figure 8 The writing process diagram is shown in Figure 1. Figure 8 It can be seen that before writing data A, the operation instruction ST1 must be configured; before writing data B, the operation instruction ST2 must also be configured; and so on. That is, after the DMA module 850 completes writing a piece of data, it needs to wait for the CPU module 810 to configure the next operation instruction before executing the reading and writing of the next piece of data, which will affect the efficiency of the DMA module 850 in processing data. Therefore, the above-mentioned main control 800 processing architecture has defects.

[0076] For the architecture of the master control of this application, please refer to Figure 7 The main control 900 includes: a CPU module 910, a register SFR 920, an NFCMU module 930, a DMA module 940 and a static storage SRAM 950. The above functional modules interact through an AHB bus (not shown in the figure).

[0077] According to the processing flow of the master control 900 of this application, please refer to Figure 8 , still write data A~I. First, read the current state of DMA module 940 to determine whether DMA module 940 is processing data. If so, start the processing flow of the multi-transmission operation instruction table. Next, read the operation information from the Host end, determine the required operation instructions according to the operation information, and determine that the operation instructions are all write operations. According to the operation order of the operation information from the Host end, sort the multiple operation instructions, combine the multiple operation instructions based on the sorting result, and add the operation end flag at the end to obtain the multi-transmission operation instruction table, as shown in Table 2.

[0078]

[0079] Table 2

[0080] The obtained multi-transmission operation instruction table is stored in the static storage SRAM950 (the configuration of the operation instruction is still implemented by the CPU module 910 operation register SFR920, the specific process is referred to the previous text, and will not be repeated here). When data A~I need to be written, the NFCMU module 930 directly accesses the static storage SRAM950, reads and loads the multi-transmission operation instruction table, and writes the data A~I into the Flash in sequence according to the operation instructions of the multi-transmission operation instruction table. Since the multi-transmission operation instruction table is configured in advance when the DMA module 940 processes the previous data, the DMA module 940 does not need to wait too much time to start processing the data A~I, which greatly improves the writing performance of the Flash. In addition, in the processing flow of the related technology, each time the DMA module 850 completes the writing of a piece of data, it needs to wait for the CPU module 810 to configure the next operation instruction to complete before executing the reading and writing of the next piece of data. That is, each time data is written, the CPU module 910 must execute the firmware code to perform the configuration, which consumes time. However, in the technical solution of the present application, although the multi-transmission operation instruction table is also configured through the CPU module 910 operation register SFR920, it is processed in a unified and centralized manner, and only one firmware code needs to be executed to complete the configuration of all the operation instructions required for the data to be written, which can greatly save the resource overhead of the CPU module 910 and greatly improve the writing performance of the Flash.

[0081] Figure 8 It is a waveform comparison diagram of the related technology and the present application. The upper part is the waveform diagram generated according to the method of the related technology, and the lower part is the waveform diagram generated according to the method of the present application. After comparison, the dotted line part is the time that can be saved. According to the comparison of the waveform diagrams, it can be obtained that the technical solution of the present application has a considerable improvement in the read and write performance of Flash.

[0082] Corresponding to the aforementioned method embodiments, the present application also provides a read-write acceleration device and its corresponding embodiments.

[0083] Figure 3 A schematic diagram of the structure of a read-write acceleration device in an embodiment of the present application is shown.

[0084] See also Figure 3 , a read-write acceleration device 300 includes: a configuration module 310, a storage module 320 and an operation module 330.

[0085] The configuration module 310 is used to process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table.

[0086] In this embodiment, the operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor, and the upper 4 bits represent the instruction information.

[0087] In this embodiment, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transmission operation instruction table, which can be implemented as follows: read the operation information from the Host end, and determine the required operation instructions based on the operation information; sort the multiple operation instructions according to the operation order of the operation information; combine the multiple operation instructions based on the sorting result, and add an operation end identification bit at the end to obtain a multi-transmission operation instruction table.

[0088] The storage module 320 is used to store the multi-transfer operation instruction table in the static random access memory area.

[0089] The operation module 330 is used to read the multi-transfer operation instruction table and load the operation instructions in the multi-transfer operation instruction table one by one to complete the read and write operations on the Flash.

[0090] The present application realizes reading and writing of Flash by adopting MT mode. Compared with ST mode, the generated multi-transmission operation instruction table is stored in the static random storage area. The NFCMU module for managing Flash inside the main control can directly access the static random storage area to read and load the multi-transmission operation instruction table, without involving the CPU to consume extra time to execute the corresponding firmware code to realize reading and loading, thereby speeding up the main control's each read and write operation processing of Flash.

[0091] It should be noted that the read / write acceleration method implemented by the read / write acceleration device disclosed in this embodiment is the same as the above embodiment, so it will not be described in detail here. Optionally, each module in this embodiment and the above other operations or functions are respectively for implementing the methods in the above embodiments.

[0092] Figure 4 A schematic diagram of the structure of a read-write acceleration device in another embodiment of the present application is shown.

[0093] See also Figure 4 , a read-write acceleration device 300, comprising: a configuration module 310, a storage module 320 and an operation module 330. The functional description of the storage module 320 and the operation module 330 can be found in Figure 3 , I will not go into details here.

[0094] The configuration module 310 is used to process multiple operation instructions according to preset configuration rules when DMA processes the current batch of data, and obtain a multi-transfer operation instruction table, which is used for processing the next batch of data.

[0095] In this embodiment, the current state of DMA is read. When DMA processes the current batch of data, the generation process of the multi-transfer operation instruction table is started, and the multiple operation instructions are processed using the preset configuration rules to obtain the multi-transfer operation instruction table, which is used for the next batch of data processing. When the multi-transfer operation instruction table is obtained using the preset configuration rules and multiple operation instructions, the timing selection point of the processing is optimized. DMA (Direct Memory Access) plays the role of processing data in the main control. When DMA processes data, it can use the preset configuration rules and multiple operation instructions to obtain the multi-transfer operation instruction table in advance, prepare for the next DMA to process data, shorten the interval time between DMA processing two data, and thereby improve the read and write performance of Flash.

[0096] The configuration module 310 includes: a reading unit 311, and sorting units 312 and 313. Among them:

[0097] The reading unit 311 is used to read the operation information from the host end and determine the required operation instructions according to the operation information.

[0098] The sorting unit 312 is used to sort the multiple operation instructions according to the operation sequence of the operation information.

[0099] The identification unit 313 is used to combine multiple operation instructions based on the sorting result, and add an operation end identification bit at the end to obtain a multi-transmission operation instruction table.

[0100] The technical solution of this embodiment uses the MT mode to realize the reading and writing of Flash. Compared with the ST mode, the generated multi-transmission operation instruction table is stored in the static random storage area. The NFCMU module that manages the Flash inside the main control can directly access the static random storage area to read and load the multi-transmission operation instruction table, without involving the CPU to consume extra time to execute the corresponding firmware code to realize reading and loading, thereby speeding up each read and write operation processing of the main control on the Flash.

[0101] In addition, the technical solution of this embodiment does not require the Flash to execute each read and write task. The CPU needs to operate the register configuration to complete a single operation instruction each time before executing the current read and write task. The multi-transfer operation instruction table of this embodiment includes multiple operation instructions, and there is no need to wait for the CPU to configure the next operation instruction to be completed before executing the read and write of the next data after each data read and write is completed.

[0102] like Figure 5 Shown is a structural schematic diagram of a storage control chip in one embodiment of the present application.

[0103] Please refer to 5 , a storage control chip 500 includes the above-mentioned read-write acceleration device 300 .

[0104] The storage control chip 500 of the present application realizes reading and writing of Flash by adopting MT mode. Compared with ST mode, the generated multi-transmission operation instruction table is stored in the static random storage area. The NFCMU module for managing Flash inside the main control can directly access the static random storage area to read and load the multi-transmission operation instruction table, without involving the CPU to consume extra time to execute the corresponding firmware code to realize reading and loading, thereby speeding up the main control's each read and write operation processing of Flash.

[0105] The storage control chip 500 of this embodiment will read the current state of DMA. When DMA processes the current batch of data, it starts the generation process of the multi-transfer operation instruction table, uses the preset configuration rules to process multiple operation instructions, and obtains the multi-transfer operation instruction table. The multi-transfer operation instruction table is used for the next batch of data processing. When the multi-transfer operation instruction table is obtained by using the preset configuration rules and multiple operation instructions, the timing selection point of processing is optimized. DMA (Direct Memory Access) plays the role of processing data in the main control. When DMA processes data, it can use the preset configuration rules and multiple operation instructions to obtain the multi-transfer operation instruction table in advance, prepare for the next DMA to process data, shorten the interval time between DMA processing two data, and improve the read and write performance of Flash.

[0106] In addition, the storage control chip 500 of the present embodiment does not need Flash to execute each read and write task. The CPU needs to operate the register configuration to complete a single operation instruction each time before executing the current read and write task. The multi-transfer operation instruction table of the present embodiment includes multiple operation instructions, and there is no need to wait for the CPU to configure the next operation instruction to be completed before executing the read and write of the next data after each data read and write is completed.

[0107] In addition, the method according to the present application may also be implemented as a computer program or a computer program product, which includes computer program code instructions for executing some or all of the steps in the above method of the present application.

[0108] Alternatively, the present application can also be implemented as a computer-readable storage medium (or non-transitory machine-readable storage medium or machine-readable storage medium) on which executable code (or computer program or computer instruction code) is stored. When the executable code (or computer program or computer instruction code) is executed by a processor of an electronic device (or server, etc.), the processor executes part or all of the steps of the above-mentioned method according to the present application.

[0109] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The selection of terms used herein is intended to best explain the principles of the embodiments, practical applications, or improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for accelerating reading and writing, characterized in that: include: Processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table; Storing the multi-transfer operation instruction table in a static random access memory area; The multi-transfer operation instruction table is read, and the operation instructions in the multi-transfer operation instruction table are loaded one by one to complete the read and write operations on the Flash.

2. The read / write acceleration method according to claim 1, characterized in that: The method of processing multiple operation instructions according to the preset configuration rules to obtain a multi-transmission operation instruction table includes: When DMA processes the current batch of data, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transfer operation instruction table, which is used for processing the next batch of data.

3. The read / write acceleration method according to claim 2, characterized in that: The method of processing multiple operation instructions according to the preset configuration rules to obtain a multi-transmission operation instruction table includes: Read the operation information from the host, and determine the required operation instructions according to the operation information; Sorting the plurality of operation instructions according to the operation sequence of the operation information; Based on the sorting result, the plurality of operation instructions are combined, and an operation end flag is added at the end to obtain a multi-transmission operation instruction table.

4. The read / write acceleration method according to claim 1, characterized in that: The operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor, and the upper 4 bits represent the instruction information.

5. A read-write acceleration device, characterized in that: include: A configuration module, used for processing multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table; A storage module, used for storing the multi-transmission operation instruction table in a static random access memory area; The operation module is used to read the multi-transmission operation instruction table and load the operation instructions in the multi-transmission operation instruction table one by one to complete the read and write operations on the Flash.

6. The read-write acceleration device according to claim 5, characterized in that: The configuration module is used to process multiple operation instructions according to preset configuration rules to obtain a multi-transmission operation instruction table, including: When DMA processes the current batch of data, multiple operation instructions are processed according to preset configuration rules to obtain a multi-transfer operation instruction table, which is used for processing the next batch of data.

7. The read-write acceleration device according to claim 6, characterized in that: The configuration module includes: A reading unit, used to read the operation information from the host end, and determine the required operation instructions according to the operation information; A sorting unit, used to sort the plurality of operation instructions according to the operation sequence of the operation information; The identification unit is used to combine the multiple operation instructions based on the sorting result, and add an operation end identification bit at the end to obtain a multi-transmission operation instruction table.

8. The read / write acceleration method according to claim 5, characterized in that: The operation instruction includes an index factor and instruction information, wherein the lower 4 bits of the operation instruction represent the index factor, and the upper 4 bits represent the instruction information.

9. A storage control chip, characterized in that: It comprises the read-write acceleration device as described in claims 5 to 7.

10. A computer-readable storage medium, characterized in that: An executable code is stored, and when the executable code is executed by a processor of an electronic device, the processor is caused to execute the read / write acceleration method according to any one of claims 1 to 4.

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