A method for optimizing instruction encoding and decoding performance based on SIMD instruction acceleration

Abstract

The present invention discloses an instruction encoding and decoding performance optimization method based on SIMD instruction acceleration. The method establishes an operation code frequency table and a decoding information table for x86 instructions with a relatively high usage frequency, obtains an instruction stream within a set range when executing a program in an instruction dynamic conversion mode, establishes an x86 instruction group for the instructions existing in the operation code frequency table, and then uses NEON instructions to decode multiple x86 instruction groups in parallel according to the decoding information table to obtain intermediate data. Finally, NEON instructions are used to complete the encoding of the intermediate data according to the encoding rules of ARM instructions, and the conversion and execution of x86 instructions to ARM instructions is realized. By making full use of the parallel instruction characteristics of the ARM processor in the instruction decoding and encoding process, the efficiency of instruction conversion and execution is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of computer software development, and in particular relates to an instruction encoding and decoding performance optimization method based on SIMD instruction acceleration. Background Art

[0002] When running x86 architecture programs on ARM processors, the x86 architecture programs need to be converted into ARM instructions through dynamic instruction conversion. The decoding and encoding process of instructions in the conversion is relatively complex and time-consuming. When dealing with this process, the existing instruction dynamic conversion method cannot fully utilize the hardware advantages of ARM processors, resulting in low efficiency of x86 architecture programs when executing across architectures. Summary of the invention

[0003] In view of this, the present invention provides an instruction encoding and decoding performance optimization method based on SIMD instruction acceleration, which accelerates the instruction decoding and encoding process by utilizing the hardware acceleration characteristics of the ARM processor, thereby achieving efficient cross-architecture execution of x86 architecture programs.

[0004] The present invention provides a method for optimizing instruction encoding and decoding performance based on SIMD instruction acceleration, which specifically includes the following steps:

[0005] Step 1: establish an opcode frequency table and a decoding information table for x86 instructions with a high usage frequency, wherein the key of the decoding information table is the x86 instruction feature group and the value is the instruction conversion relationship, and the instruction conversion relationship includes multiple conversion relationship pairs; load and execute the executable file in the ARM system by dynamic instruction conversion;

[0006] Step 2, obtain the instruction stream, and the opcodes belonging to the opcode frequency table constitute the first opcode set; calculate the opcode-related instruction length of the first opcode set according to the opcode frequency table, and the byte sequence starting from the opcode and having a length equal to the instruction length is the x86 instruction group, forming the first instruction group set, and executing step 3; convert other instructions in the instruction stream into ARM instructions and execute step 5;

[0007] Step 3: Obtain the instruction conversion relationship of the x86 instruction group in the first instruction group set from the decoding information table, load the operand type into the NEON register named x86 instruction register, and load the instruction conversion relationship into the NEON register named ARM instruction register;

[0008] Step 4: Use NEON instructions to compare data in the x86 instruction register and the ARM instruction register in parallel, save conversion relationship pairs with the same operand type, use NEON instructions to decode the x86 instruction group in parallel according to the conversion relationship to form intermediate data, and use NEON instructions to encode the intermediate data into ARM instructions;

[0009] Step 5: If the executable file is executed and the conversion is completed, then the process ends; otherwise, proceed to step 2.

[0010] Furthermore, the method for obtaining the usage frequency of x86 instructions is: counting the occurrence frequencies of different opcodes in a set number of x86 programs, and using the occurrence frequencies as the usage frequencies corresponding to the opcodes.

[0011] Furthermore, the operation code frequency table includes instruction name, operation code and instruction encoding format.

[0012] Furthermore, the decoding information table is a hash table.

[0013] Furthermore, the conversion relationship pair is formed by an operand type and an ARM instruction or an ARM instruction combination and a decoding rule.

[0014] Furthermore, the x86 instruction feature group includes an opcode feature value, an addressing mode feature value, and an instruction prefix feature value.

[0015] Furthermore, the method for obtaining the instruction conversion relationship of the x86 instruction group in the first instruction group set from the decoding information table in step 3 is: extracting the opcode feature value of the x86 instruction group, if there is a unique x86 instruction feature group matching the opcode feature value in the decoding information table, then obtaining the instruction conversion relationship corresponding to the x86 instruction feature group; otherwise, extracting the addressing mode feature value of the x86 instruction group, searching for the x86 instruction feature group with the same feature value in the matched x86 instruction feature groups, if the result is unique, then obtaining the instruction conversion relationship corresponding to the x86 instruction feature group, otherwise obtaining the instruction conversion relationships corresponding to all matched x86 instruction feature groups.

[0016] Furthermore, the method of using NEON instructions in step 4 to decode the x86 instruction group in parallel according to the conversion relationship to form intermediate data is: extracting the ARM instructions or ARM instruction combinations and decoding rules in the conversion relationship pair, decoding the x86 instructions in the x86 instruction group into an ARM instruction set containing ARM instructions or ARM instruction combinations, decoding the operands therein into a set of data segments marked with operand types corresponding to the ARM instruction fields, and storing them in the memory to form intermediate data.

[0017] Furthermore, the method of using NEON instructions to encode the intermediate data into ARM instructions in step 4 is: using NEON instructions to load the intermediate data into NEON registers, and then using NEON instructions to encode the data in the ARM instruction set into ARM instruction opcodes according to the encoding rules of ARM instructions, and encoding the data in the data segment set into ARM instruction format operands.

[0018] Furthermore, the operation code characteristic value is obtained by extracting the upper 4 bits and the lower 4 bits of the operation code, and the addressing mode characteristic value is extracted according to the position of the addressing mode in the instruction by using a data interception algorithm. Beneficial Effects

[0019] The present invention establishes an opcode frequency table and a decoding information table for x86 instructions with a relatively high usage frequency, obtains an instruction stream within a set range when executing a program in an instruction dynamic conversion mode, establishes an x86 instruction group for the instructions existing in the opcode frequency table, and then uses NEON instructions to decode multiple x86 instruction groups in parallel according to the decoding information table to obtain intermediate data, and finally uses NEON instructions to complete the encoding of the intermediate data according to the encoding rules of ARM instructions, thereby realizing the conversion and execution of x86 instructions to ARM instructions. By making full use of the parallel instruction characteristics of the ARM processor in the instruction decoding and encoding processes, the efficiency of instruction conversion and execution is effectively improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A flow chart of a method for optimizing instruction encoding and decoding performance based on SIMD instruction acceleration provided by the present invention. DETAILED DESCRIPTION

[0021] The present invention is described in detail with reference to the following embodiments.

[0022] The invention provides an instruction encoding and decoding performance optimization method based on SIMD instruction acceleration, the core idea of ​​which is: establishing an opcode frequency table and a decoding information table for x86 instructions with a relatively high usage frequency, obtaining an instruction stream within a set range when executing a program in an instruction dynamic conversion mode, establishing an x86 instruction group for the instructions existing in the opcode frequency table, and then using NEON instructions to decode multiple x86 instruction groups in parallel according to the decoding information table to obtain intermediate data, and finally using NEON instructions to complete the encoding of the intermediate data according to the encoding rules of ARM instructions, thereby realizing the conversion and execution of x86 instructions to ARM instructions.

[0023] The present invention provides a method for optimizing instruction encoding and decoding performance based on SIMD instruction acceleration, the process is as follows: Figure 1 As shown, the specific steps include:

[0024] Step 1. Select x86 instructions with a higher usage frequency to establish an opcode frequency table, where the opcode frequency table includes instruction name, opcode and instruction encoding format; for the x86 instructions in the opcode frequency table, establish a decoding information table based on a hash table, where the key of the decoding information table is the x86 instruction feature group and the value is the instruction conversion relationship, where the x86 instruction feature group is used to describe the characteristics of the x86 instruction, and the instruction conversion relationship includes multiple conversion relationship pairs formed by operand type and ARM instruction or ARM instruction combination and decoding rules; load and execute the executable file in the ARM system through dynamic instruction conversion.

[0025] During the dynamic conversion of instructions, the ARM instructions actually converted from x86 instructions are not only related to the x86 instruction feature group, but also to the operands actually used by the ARM instructions. Therefore, the instruction conversion relationship corresponding to the same x86 instruction feature group contains multiple conversion relationship pairs formed by the x86 instruction operand type and its related ARM instructions or ARM instruction combinations.

[0026] The method for obtaining the usage frequency of x86 instructions is to count the occurrence frequencies of different opcodes in a set number of x86 programs, and the occurrence frequencies are the usage frequencies corresponding to the opcodes. For example, the occurrence frequencies of each opcode in the executable files and dynamic libraries in the Windows operating system installation directory are counted.

[0027] The instruction set architecture under the x86 architecture uses a variable-length instruction encoding format. The x86 instruction encoding format includes instruction prefixes of different lengths, opcodes (Opcodes), operands, and addressing modes. The instruction length of the x86 architecture can range from 1 to 15 bytes, and the common instruction length is 1 to 6 bytes.

[0028] In order to further improve the accuracy of instruction description by instruction features, the x86 instruction feature group constructed by the present invention includes an opcode feature value, an addressing mode feature value, an instruction prefix feature value, and the like.

[0029] In addition, in order to further improve the extraction efficiency of feature values, the present invention constructs a specific feature extraction algorithm, including obtaining the opcode feature value by extracting the upper 4 bits and the lower 4 bits of the opcode, and using a data interception algorithm to extract the addressing mode feature value according to the position of the addressing mode in the instruction.

[0030] The decoding information table in the present invention is established based on a hash table, so there may be hash conflicts caused by multiple feature values ​​having the same hash value. The present invention adopts a chain address method to handle hash conflicts, specifically: a linked list is created for the key-value pairs corresponding to the conflicting hash values, and the x86 instruction feature groups of these key-value pairs and their corresponding instruction conversion relationships are stored in the linked list.

[0031] To further improve the cache hit rate, the data in the decoding information table is sorted by access frequency, and frequently accessed decoding information is placed closer to the cache. Specifically: by maintaining access counters for entries in the decoding information table, the counters are increased each time they are accessed, and the decoding information table is reordered regularly to move entries with higher counter values ​​to the front. At the same time, in order to improve the query efficiency of the index, the hash table is regularly reorganized and optimized. For example, when the length of the linked list exceeds the threshold, the capacity and hash function of the hash table are recalculated, and all key-value pairs are reinserted into the new hash table to reduce hash conflicts and increase query speed.

[0032] For example, taking the addition instruction in ARM instructions as an example, if the operand type is an integer, the instruction used is ADD, such as ADD r0, r1, r2, which means adding the integers in registers r1 and r2, and storing the result in r0; if the operand type is a floating point number, the instruction used is FADD, such as FADD s0, s1, s2, which means adding the floating point numbers in single-precision floating point registers s1 and s2, and storing the result in s0.

[0033] Step 2, obtain the instruction stream of the set range, parse the instruction stream to extract the instruction opcodes contained therein, and form a first opcode set with the opcodes existing in the opcode frequency table; for each opcode in the first opcode set, determine the corresponding instruction encoding format according to the opcode frequency table to calculate the instruction length of the current instruction to be converted, and use the byte sequence starting from the opcode with the length of the instruction length as the x86 instruction group; form a first instruction group set with the x86 instruction groups corresponding to all the opcodes in the first opcode set, and execute step 3; for other instructions in the instruction stream, directly convert them into corresponding ARM instructions and then execute step 8.

[0034] In order to improve the efficiency of parallel execution during the dynamic conversion of instructions, the present invention obtains an instruction stream containing a set number of instructions to be converted as a set range as a parallel execution unit during the program execution process.

[0035] Starting from the beginning of the instruction stream, the scan is performed in bytes. When a byte matching the opcode in the opcode frequency table is encountered, the byte is used as a starting point to predict the length of the subsequent possible instruction according to the instruction encoding format of the x86 instruction.

[0036] Step 3. For each x86 instruction group in the first instruction group set, extract the opcode feature value of the x86 instruction group. If there is a unique x86 instruction feature group that matches the opcode feature value in the decoding information table, obtain the instruction conversion relationship corresponding to the x86 instruction feature group and execute step 4. Otherwise, extract the addressing mode feature value of the x86 instruction group, search for an x86 instruction feature group with the same feature value in the matched x86 instruction feature groups, and if the result is unique, obtain the instruction conversion relationship corresponding to the x86 instruction feature group and execute step 4. Otherwise, obtain the instruction conversion relationships corresponding to all matched x86 instruction feature groups and execute step 4.

[0037] Step 4, obtain the operands of each x86 instruction group in the first instruction group set, parse to obtain the operand type of each operand, load the operand type contained in each x86 instruction group into the corresponding NEON register respectively, and record these registers as x86 instruction registers; at the same time, load the instruction conversion relationship corresponding to the x86 instruction group obtained in step 3 into other corresponding NEON registers, and record these registers as ARM instruction registers, wherein the instruction register group is composed of the x86 instruction registers and ARM instruction registers of the same x86 instruction group.

[0038] Step 5, using NEON instructions to perform in parallel the comparison operation of the data in the x86 instruction register and the ARM instruction register in each instruction register group; the comparison method is to read data byte by byte from the x86 instruction register, compare the read byte data with the data in the ARM instruction register, and then save the conversion relationship pair corresponding to the operand type with equal comparison results in the comparison result register corresponding to the x86 instruction group.

[0039] Step 6, using NEON instructions to extract the ARM instructions or ARM instruction combinations and decoding rules in the conversion relationship pairs from each comparison result register in parallel, according to the ARM instructions or ARM instruction combinations and decoding rules, the x86 instructions in each x86 instruction group are decoded into an ARM instruction set containing ARM instructions or ARM instruction combinations, and the operands therein are decoded into a data segment set marked with the operand type corresponding to the ARM instruction field, and then the ARM instruction set and the data segment set are stored in the memory with a set data structure to form intermediate data. The operand types include: register operands, immediate operands, memory operands, integers, floating point types, etc.

[0040] Specifically, the present invention can use instructions such as vgetq_lane_u8 to extract information in the conversion relationship pair from the comparison result register. The decoded data is stored in the memory in a set data structure, wherein the set data structure can be a data structure that is easy to access and process, such as a linked list or a structure array.

[0041] Step 7: Use NEON instructions to load the intermediate data into NEON registers, and then use NEON instructions to encode the data in the ARM instruction set into ARM instruction opcodes according to the encoding rules of ARM instructions; encode the data in the data segment set, and encode the register data, immediate data or memory data into ARM instruction format operands; save the encoded data in the set memory area.

[0042] Step 8: If the executable file is executed to complete the conversion, then the process ends; otherwise, execute step 2. Example

[0043] In this embodiment, an instruction encoding and decoding performance optimization method based on SIMD instruction acceleration provided by the present invention is adopted to implement the execution of x86 instruction program in the ARM system, including the following steps:

[0044] S1-1. In this embodiment, a data grouping method based on instruction boundary prediction is used to group instructions. Compared with the existing data grouping method that simply divides by a fixed number of bytes without fully considering the characteristics of x86 instructions, the grouping method established by the present invention can solve the problem of the non-fixed length of x86 instructions. The specific steps are as follows:

[0045] Analyze the opcode distribution of x86 instructions and build an opcode frequency table. For example, common opcodes such as 0x8b appear more frequently.

[0046] When grouping data, start from the beginning of the instruction stream and scan in bytes. When encountering an opcode that matches a high-frequency opcode in the opcode frequency table, use this as a starting point to predict the subsequent possible instruction length based on the length encoding rule of x86 instructions.

[0047] To verify the accuracy of the prediction, a simple check is performed on the potential instruction group, such as checking whether the operands in the instruction group conform to the syntax rules of the x86 instruction, such as whether the register number is within a reasonable range.

[0048] After verification, the determined bits are arranged in order to form grouped data. Compared with the existing fixed-length grouping, this grouping method can more accurately divide the complete x86 instructions into a group, reduce invalid decoding operations caused by crossing instruction boundaries, and thus more efficiently utilize NEON instruction parallel decoding.

[0049] S1-2, using NEON instruction set parallel decoding, the specific steps are as follows:

[0050] S1-2.1. Use NEON instruction vld1q_u8 to load the grouped x86 instruction data into the NEON register. Assuming x86_instruction_stream is the memory address where the x86 instruction data is stored, the following is an example in the assembly code:

[0051] vld1.8 {q0}, [x86_instruction_stream] / / q0 is a NEON register

[0052] S1-2.2, when decoding in parallel, for each data block to be processed, first extract its key feature value. For example, for the new data block 0x8D 0x0A 0x11 0x22 0x33, extract the high 4 bits 0x8 and low 4 bits 0xD of the operation code 0x8D. At the same time, according to the decoding information table, extract other possible key feature values, such as addressing mode identification, etc.

[0053] Then, according to the extracted feature value, the corresponding position is searched in the decoding information table. If a matching feature value is found, the corresponding instruction data location information is obtained from the decoding information table. If there is a hash conflict, the matching feature value is searched sequentially in the linked list. During the search process, an optimization strategy can be adopted, such as adding a fast search cache at the head of the linked list to record the most recently accessed feature value and its corresponding location information. If the feature value of the next search hits in the cache, the location information is directly obtained without traversing the linked list.

[0054] Based on the acquired location information, the possible matching instruction data range can be quickly located, the decoding search range can be narrowed, and unnecessary decoding attempts can be reduced. For example, through index query, the possible matching instruction data range of a data block is obtained between memory addresses 0x1000 - 0x1010. Then, during parallel decoding, only the data within this range needs to be decoded in detail, without a comprehensive search of the entire instruction data set.

[0055] S1-2.3, parallel comparison of multiple groups of data based on registers: After loading multiple groups of x86 instruction data into different NEON registers (such as q0, q1, q2, etc., corresponding to instruction data of different groups) and loading the relevant decoding rule entries in the decoding information table into corresponding other NEON registers (assuming lookup_q0, lookup_q1, lookup_q2, etc., corresponding to the decoding information table content to be matched by each group of instruction data), start to use the parallel capability of the NEON instruction set to perform simultaneous decoding operations on multiple groups of data. Here, two groups of instruction data are used as an example for explanation. Assume that the first group of instruction data is loaded into the q0 register, and its corresponding decoding information table entry is loaded into the lookup_q0 register; the second group of instruction data is loaded into the q1 register, and the corresponding decoding information table entry is loaded into the lookup_q1 register.

[0056] Use the vceqq.u8 instruction to compare two groups of data at the same time. This instruction can compare multiple bytes of data in the register in parallel. For the first group, execute vceqq.u8 result_q0, q0, lookup_q0, which will compare each byte in the q0 register with the byte in the lookup_q0, and then store the comparison result in the result_q0 register; similarly, for the second group, execute vceqq.u8 result_q1, q1, lookup_q1, and store the comparison result of the second group in the result_q1 register.

[0057] In this way, multiple (for example, if there are n groups of instruction data, then these n groups are compared at the same time) instruction data loaded into different NEON registers can be compared in parallel with their corresponding decoding information table entries, giving full play to the advantage of NEON instructions that can process multiple data elements at one time, realizing the parallelization of comparison operations, and quickly obtaining preliminary matching comparison results for each group of data.

[0058] S1-2.4, parallel processing of multi-byte instructions and sliding window mechanism: Due to the different lengths of x86 instructions, there are multi-byte instructions. For example, the instruction MOV EAX, [EBX + 0x1234] may correspond to multiple bytes of machine code, assuming 8B 81 34 12 00 00, etc. When decoding and comparing, these multi-byte instructions need to accurately match the entire byte sequence. A sliding window mechanism is used to parallelize the matching of multi-byte instructions. Take a set of multi-byte instruction data as an example, assuming that it is loaded into the q_i register, where i represents the i-th group of instruction data, and the corresponding decoding information table entry is loaded into the lookup_q_i register.

[0059] Specifically, the vceqq.u8 instruction performs the first comparison of the entire byte sequence and stores the initial comparison result in the result_q_i register; if there is no complete match, the sliding window mechanism is started; otherwise, it is not started.

[0060] Move the window in parallel, one byte at a time, which can be achieved by performing logical shifts and reorganization of the data in the register, such as using instructions such as `vshl` to perform left shift operations to simulate window movement; then use the vceqq.u8 instruction again to compare the instruction data after the window is moved with the data at the corresponding position in the decoding information table entry to obtain a new comparison result. Repeat this process until a complete match is found or a reasonable window movement range is exhausted, such as movement within the instruction length range.

[0061] At the same time, for all multi-byte instruction data groups loaded into different NEON registers, assuming that there are m groups of multi-byte instruction data, the above-mentioned sliding window comparison operation is carried out in parallel, that is, the respective windows of these m groups of data are moved and compared at the same time. In this way, in the process of processing complex matching of multi-byte instructions, the parallelism of NEON instructions can be used to speed up the overall decoding speed and avoid the time loss caused by processing multi-byte instructions sequentially group by group.

[0062] S1-2.5, parallel application of early termination strategy. In the comparison process, in order to further improve efficiency, an early termination strategy is adopted and applied in parallel. When comparing bytes of each group of data, for example, for the comparison result of the first group of data stored in the result_q0 register, a NEON instruction is used to check whether there is a byte whose comparison result is 0, indicating a mismatch. For example, the minimum non-zero value in the register can be found through instructions such as vminv.u8. If the result is 0, it means that there is a byte mismatch, so as to determine whether there is a mismatch in the current byte comparison.

[0063] When a byte in a group of data is found to be mismatched, the comparison operation on the subsequent bytes of the current instruction of the group of data is immediately stopped. For example, instructions such as conditional jumps can be combined with the logical judgment results of NEON instructions to skip the execution of subsequent unnecessary comparison instructions and enter the comparison of the next group of data or the comparison link of the next instruction.

[0064] For all the multiple groups of data being compared, assuming n groups, this early termination judgment operation is carried out at the same time. As long as one group of data meets the early termination condition, its subsequent unnecessary comparisons can be quickly skipped, which reduces a lot of unnecessary calculations as a whole, makes full use of the parallel early termination strategy, and improves decoding efficiency.

[0065] Through the above-mentioned methods such as parallel comparison of multiple groups of data based on NEON instructions, parallelization of multi-byte instruction sliding window mechanism and parallel application of early termination strategy, the parallelization of the decoding process in the parallel search decoding step is realized, and multiple groups of x86 instruction data can be efficiently decoded at the same time, thereby accelerating the overall decoding speed.

[0066] S1-2.6. Based on the comparison results, use vgetq_lane_u8 and other instructions to extract the decoded information. The assembly code example is as follows:

[0067] vgetq_lane.u8 r0, q2, #0 / / Extract the result from the 0th channel of the q2 register and store it in register r0

[0068] The existing decoding method usually decodes instructions one by one, but the present invention utilizes the parallel processing capability of the NEON instruction set to decode multiple x86 instruction data at the same time, greatly improving the decoding speed. By constructing an optimized decoding information table, the efficiency of search and decoding is further improved.

[0069] S1-3. Intermediate data storage and organization: The decoded intermediate data is stored in the memory in a specific format for subsequent encoding.

[0070] S1-4, using NEON instruction set parallel encoding, including:

[0071] S1-4.1. Use NEON instructions to load the stored intermediate data into NEON registers. Assuming that intermediate_data_memory is the memory address where the intermediate data is stored, the assembly code example is as follows:

[0072] vld1.8 {q3}, [intermediate_data_memory] / / q3 is a NEON register used to store intermediate data

[0073] S1-4.2, ARM instruction encoding rules are relatively complex, involving the combination of multiple fields such as opcode, register number, immediate value, etc. When using the NEON instruction set for parallel encoding, the intermediate data is divided into different parts, corresponding to each field of the ARM instruction, specifically:

[0074] For the opcode part, according to the predefined mapping relationship, NEON instructions are used, such as the combination of vshlq_n_u8 and vorrq_u8, to shift and perform logical OR operations on the relevant bits in the intermediate data to generate the correct opcode field. Assuming that the opcode part in the intermediate data is stored in the low byte of q3, and the target opcode field is stored in the low byte of q4, the assembly code example is as follows:

[0075] vshlq_n.u8 q4, q3, #4 / / Shift left 4 bits

[0076] vorrq.u8 q4, q4, q3 / / logical or operation

[0077] For the register number part, bit operations are also performed through specific NEON instructions to extract the bits representing the register number in the intermediate data and convert them into the format required by the ARM instruction.

[0078] When processing immediate data, NEON instructions are used to perform arithmetic operations and bit operations according to the size and representation of the immediate data. For example, if the immediate data needs to be sign-extended, instructions such as vqmovn_s16 are used for extension operations.

[0079] In order to improve encoding efficiency, common encoding operations are pre-calculated and stored in a small decoding information table. For example, for some fixed opcodes and register combinations, the corresponding encoding results are pre-calculated and directly obtained from the decoding information table during encoding to reduce repeated calculations.

[0080] Encoding result storage: Store the encoded ARM instruction data in the specified memory area, using instructions such as vst1q_u8 to store it. Assuming arm_instruction_memory is the memory address for storing ARM instruction data, q4 is the NEON register for storing the encoding result, the assembly code example is as follows:

[0081] vst1.8 {q4}, [arm_instruction_memory]

[0082] In the encoding process, the existing method performs encoding operations sequentially, while the present invention utilizes the parallel computing capability of the NEON instruction set to perform encoding operations on multiple intermediate data at the same time, thereby significantly improving the encoding efficiency. Example

[0083] In this embodiment, an instruction encoding and decoding performance optimization method based on SIMD instruction acceleration provided by the present invention is used to complete the instruction conversion of the following sample code containing at least 10 x86 assembly instructions. The specific process is as follows:

[0084] The sample code is as follows:

[0085] MOV EAX, 0x1234

[0086] ADD EBX, EAX

[0087] SUB ECX, 0x5678

[0088] MOV EDX, [EAX]

[0089] CMP EAX, EBX

[0090] JNE label1

[0091] AND ESI, 0xFFFF

[0092] OR EDI, 0x8888

[0093] XOR EBP, ESI

[0094] INC EAX

[0095] DEC EBX

[0096] S2-1. Data preprocessing. Data grouping based on instruction boundary prediction:

[0097] The instructions in the sample code are grouped according to the characteristics of the opcode and the range of instruction length. For example, the MOV EAX, 0x1234 instruction can be grouped together according to its opcode and length characteristics; ADD EBX, EAX and SUB ECX, 0x5678 can be grouped together because their opcodes and instruction lengths are relatively regular. Similarly, the entire instruction sequence is divided into several appropriate data groups, as shown below:

[0098] The first group: MOV EAX, 0x1234 (the corresponding machine code is assumed to be B8 34 12 00 00)

[0099] The second group: ADD EBX, EAX (the corresponding machine code is assumed to be 01 D8), SUB ECX, 0x5678 (the corresponding machine code is assumed to be 81 E9 78 56 00 00)

[0100] The third group: MOV EDX, [EAX] (the corresponding machine code is assumed to be 8B 10), CMP EAX, EBX (the corresponding machine code is assumed to be 39 D8), JNE label1 (the corresponding machine code is assumed to be 75 XX, XX is the relative offset related byte)

[0101] The fourth group: AND ESI, 0xFFFF (the corresponding machine code is assumed to be 25 FF FF 00 00), OR EDI, 0x8888 (the corresponding machine code is assumed to be 09 FF), XOR EBP, ESI (the corresponding machine code is assumed to be 31 ED)

[0102] The fifth group: INC EAX (the corresponding machine code is assumed to be 40), DEC EBX (the corresponding machine code is assumed to be 4B)

[0103] S2-2. Parallel decoding using NEON instruction set

[0104] S2-2.1. Load data:

[0105] Use NEON instructions, such as vld1.8 {q0}, [x86_instruction_memory_group1], to load the first set of data into NEON register q0, where x86_instruction_memory_group1 is the memory address that stores the first set of x86 instruction machine codes. For other sets of data, use the corresponding vld1 series of instructions to load them into different NEON registers (for example, the second set is loaded into q1, etc.). These load operations can be initiated in parallel, using the parallel capabilities of the NEON instruction set to quickly read multiple sets of data into registers at the same time. For example, load the first and second sets of data in parallel:

[0106] vld1.8 {q0}, [x86_instruction_memory_group1]

[0107] vld1.8 {q1}, [x86_instruction_memory_group2]

[0108] S2-2.2, Decoding information table construction:

[0109] Construct a decoding information table based on a hash table structure. In the hash table, for different opcodes, such as MOV, ADD, SUB, and other opcodes, the corresponding decoding information is pre-stored, including key decoding elements such as instruction type, operand, and addressing mode. For example, for opcode B8 corresponding to the instruction of the form MOV EAX, immediate, the decoding information table stores the MOV instruction that transfers the immediate value to the EAX register, as well as the immediate value in the subsequent bytes and other related information. Similarly, the corresponding detailed decoding information is configured for other opcodes. The hash table is combined with the chain address method to handle conflicts, and the sorting mechanism is optimized according to the access frequency to improve the search efficiency.

[0110] S2-2.3, Parallel search decoding:

[0111] For each set of data loaded into the register, NEON instructions are used to perform lookup and decoding operations at the same time. For example, for the first set of data loaded into q0 (corresponding to the machine code of MOV EAX, 0x1234) and the second set of data loaded into q1 (including the machine code of ADD EBX, EAX and SUB ECX, 0x5678), assuming that lookup_table_entry_group1 points to the memory address of the decoding information table entry corresponding to the first set of data, and q2 is used to store the comparison result between the first set of data and the decoding information table, the following operations are performed in parallel:

[0112] vld1.8 {q2}, [lookup_table_entry_group1]

[0113] vceqq.u8 q3, q0, q2 / / Compare the first set of data with the contents of the decoding information table, and store the result in q3

[0114] Similarly, for the second set of data, assuming that lookup_table_entry_group2 points to the memory address of the decoding information table entry corresponding to the second set of data, q4 is used to store the comparison result between the second set of data and the decoding information table:

[0115] vld1.8 {q4}, [lookup_table_entry_group2]

[0116] vceqq.u8 q5, q1, q4 / / Compare the second set of data with the contents of the decoding information table, and store the result in q5

[0117] The vceqq.u8 instruction is used to compare multiple bytes of data at the same time, giving full play to the ability of NEON instructions to process multiple data elements in parallel, and quickly determining the instruction type and related information corresponding to each group of data. For multi-byte instruction matching, such as SUB ECX, 0x5678, a sliding window mechanism is used to gradually move the data window for comparison operations to ensure accurate matching. At the same time, an early termination strategy is applied. If a byte comparison does not match, the comparison of the subsequent bytes of the current instruction in the group of data is immediately stopped, and the comparison link of the next instruction is entered to reduce unnecessary calculations.

[0118] S2-2.4. Extraction of decoding results:

[0119] According to the comparison result registers, such as q3, q5, etc., use vgetq_lane.u8 and other instructions to extract the decoded information. For example, extract the first set of data from q3 and decode it to know that it is a MOV instruction, the target register is EAX, the immediate number is 0x1234, etc., and store it in the corresponding ordinary register or memory area for temporary storage of the decoding results. Assume that ordinary registers such as r0 to r3 are used to store the decoding results of different parts. Similarly, extract the decoding results of the two instructions in the second set of data from q5, such as the ADD instruction operand situation, the SUB instruction operand and immediate number, and store them for subsequent encoding. The sample code is as follows:

[0120] vgetq_lane.u8 r0, q3, #0 / / Extract the first set of data decoding result information to r0

[0121] vgetq_lane.u8 r1, q3, #1 / / Extract the first set of data decoding results and another part of the information to r1

[0122] vgetq_lane.u8 r2, q5, #0 / / Extract the instruction decoding result information in the second group of data to r2

[0123] vgetq_lane.u8 r3, q5, #1 / / Extract the instruction decoding result information in the second group of data to r3

[0124] S2-3. Intermediate data storage and organization.

[0125] The intermediate data after decoding each group of instructions is stored in memory according to a specific format. For example, for the first group of MOVEAX, 0x1234 decoding results, a structure array element is created to store it. The structure contains information such as the instruction type field (store MOV), the destination register field (store EAX), and the source operand field (store 0x1234). The decoding results of multiple instructions in other groups are also stored in this structure array in turn according to the rules, forming an orderly intermediate data storage structure that is easy to access quickly for subsequent encoding, as shown below:

[0126] struct DecodedInstruction {

[0127] char instruction_type

[10] / /

[0128] char target_register

[10] / /

[0129] unsigned int source_operand / /

[0130] }

[0131] struct DecodedInstruction intermediate_data

[10] / / / / Assume that at most 10 instruction decoding results are stored, adjust the size according to the actual situation

[0132] / / Store the first set of instruction decoding results example

[0133] strcpy(intermediate_data[0].instruction_type, "MOV") / /

[0134] strcpy(intermediate_data[0].target_register, "EAX") / /

[0135] intermediate_data[0].source_operand = 0x1234 / /

[0136] / / Store the second set of instruction decoding results (two instructions)

[0137] strcpy(intermediate_data[1].instruction_type, "ADD") / /

[0138] strcpy(intermediate_data[1].target_register, "EBX") / /

[0139] strcpy(intermediate_data[1].source_operand, "EAX") / /

[0140] strcpy(intermediate_data[2].instruction_type, "SUB") / /

[0141] strcpy(intermediate_data[2].target_register, "ECX") / /

[0142] intermediate_data[2].source_operand = 0x5678 / /

[0143] S2-4. Use NEON instruction set for parallel encoding.

[0144] S2-4.1. Load intermediate data.

[0145] Use NEON instructions to load intermediate data stored in memory into NEON registers. You can also load registers corresponding to multiple sets of intermediate data in parallel. For example:

[0146] vld1.8 {q6}, [intermediate_data_memory_group1]

[0147] vld1.8 {q7}, [intermediate_data_memory_group2]

[0148] Here, intermediate_data_memory_group1 is the address in the memory where the intermediate data after decoding the first set of instructions is stored, and the q6 register is used to load this set of data; intermediate_data_memory_group2 corresponds to the memory address of the second set of intermediate data, and q7 is used to load it, and so on to achieve parallel loading and speed up data preparation.

[0149] S2-4.2. Application of coding rules.

[0150] Operation code part:

[0151] For different types of instructions (such as MOV, ADD, etc.), according to the pre-defined ARM instruction encoding rules and mapping relationships, NEON instructions are used to generate opcodes for the intermediate data loaded into the register. For example, for the MOV instruction, there may be different encoding forms in ARM. According to the information such as the instruction type MOV and the target register in the intermediate data, the correct opcode field is generated using a combination of instructions such as vshlq_n.u8 and vorrq.u8. Assuming that the intermediate data is obtained from q6 to generate the opcode part, and assuming that q8 is used to store the generated opcode field, the sample code is as follows:

[0152] vshlq_n.u8 q8, q6, #4 / / The first step in generating opcodes for left shift etc.

[0153] vorrq.u8 q8, q8, q6 / / Logical OR operation completes the opcode part generation

[0154] At the same time, for the intermediate data loaded into the corresponding registers (such as q7, etc.) by other groups, the opcode generation operations corresponding to the respective instruction types are performed in parallel to give full play to the parallel capability of NEON.

[0155] Register number section:

[0156] According to the register information corresponding to the source operand and the target operand recorded in the intermediate data (such as converting from x86 registers such as EAX to the corresponding registers of ARM), a specific NEON instruction is used to perform bit operations to extract and convert the register number format required by the ARM instruction. For example, if the EAX of x86 is to be converted to the R0 register of ARM (here is a simple illustration of a possible mapping situation), the corresponding bit operation instructions such as displacement and mask are used for conversion, and the register information corresponding to each set of intermediate data is processed in parallel, speeding up the overall encoding process.

[0157] Immediate part:

[0158] For the case where the intermediate data contains immediate numbers (such as 0x1234 in MOV EAX, 0x1234), according to the representation and size requirements of immediate numbers in ARM instructions, use instructions such as vqmovn_s16 to perform corresponding arithmetic operations, sign extension, or other bit operations. For example, for the immediate number 0xFFFF in the intermediate data after decoding the instruction AND ESI, 0xFFFF, when encoded as an ARM instruction, it is adjusted through NEON instructions to make it conform to the ARM instruction immediate number encoding rules, and multiple groups of intermediate data containing immediate numbers are operated in parallel to improve efficiency.

[0159] Use pre-calculated decoding information tables to process some common encoding operation combinations. For example, for the encoding of common MOV instruction opcodes and specific register combinations, pre-calculate the corresponding encoding results and store them in the decoding information table. When encoding, directly obtain part of the encoding results from the decoding information table based on the instruction type and register information in the intermediate data to reduce repeated calculations. At the same time, this decoding information table mechanism is used in parallel for multiple groups of data to speed up the encoding process.

[0160] S2-4.3. Storing the encoding results.

[0161] Store the encoded ARM instruction data in the specified memory area, using instructions such as vst1.8 {q9}, [arm_instruction_memory_group1] to store it, where q9 is the register that stores the encoded ARM instruction data, and arm_instruction_memory_group1 is the memory address that stores the corresponding ARM instruction. Similarly, store multiple sets of encoding results in parallel, for example:

[0162] vst1.8 {q9}, [arm_instruction_memory_group1]

[0163] vst1.8 {q10}, [arm_instruction_memory_group2]

[0164] Assume that after encoding, the generated ARM assembly instruction sequence is as follows:

[0165] MOV R0, #0x1234

[0166] ADD R1, R0

[0167] SUB R2, #0x5678

[0168] LDR R3, [R0]

[0169] CMP R0, R1

[0170] BNE label1_arm

[0171] AND R4, #0xFFFF

[0172] OR R5, #0x8888

[0173] EOR R6, R4

[0174] ADD R0, #1

[0175] SUB R1, #1

[0176] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for optimizing instruction encoding and decoding performance based on SIMD instruction acceleration, characterized in that: The specific steps include: Step 1: establish an opcode frequency table and a decoding information table for x86 instructions with a high usage frequency, wherein the key of the decoding information table is the x86 instruction feature group and the value is the instruction conversion relationship, and the instruction conversion relationship includes multiple conversion relationship pairs; load and execute the executable file in the ARM system by dynamic instruction conversion; Step 2, obtain the instruction stream, and the opcodes belonging to the opcode frequency table constitute the first opcode set; calculate the opcode-related instruction length of the first opcode set according to the opcode frequency table, and the byte sequence starting from the opcode and having a length equal to the instruction length is the x86 instruction group, forming the first instruction group set, and executing step 3; convert other instructions in the instruction stream into ARM instructions and execute step 5; Step 3: Obtain the instruction conversion relationship of the x86 instruction group in the first instruction group set from the decoding information table, load the operand type into the NEON register named x86 instruction register, and load the instruction conversion relationship into the NEON register named ARM instruction register; Step 4: Use NEON instructions to compare data in the x86 instruction register and the ARM instruction register in parallel, save conversion relationship pairs with the same operand type, use NEON instructions to decode the x86 instruction group in parallel according to the conversion relationship to form intermediate data, and use NEON instructions to encode the intermediate data into ARM instructions; Step 5: If the executable file has completed the conversion and execution, then end this process; otherwise, proceed to step 2.

2. The instruction encoding and decoding performance optimization method according to claim 1, characterized in that: The method for obtaining the usage frequency of x86 instructions is as follows: counting the occurrence frequencies of different opcodes in a set number of x86 programs, and using the occurrence frequencies as the usage frequencies corresponding to the opcodes.

3. The instruction encoding and decoding performance optimization method according to claim 1, characterized in that: The operation code frequency table includes instruction name, operation code and instruction encoding format.

4. The instruction encoding and decoding performance optimization method according to claim 1, characterized in that: The decoding information table is a hash table.

5. The instruction encoding and decoding performance optimization method according to claim 1, characterized in that: The conversion relationship pair is formed by the operand type and the ARM instruction or the ARM instruction combination and the decoding rule.

6. The instruction encoding and decoding performance optimization method according to claim 1, characterized in that: The x86 instruction feature group includes an operation code feature value, an addressing mode feature value, and an instruction prefix feature value.

7. The instruction encoding and decoding performance optimization method according to claim 6, characterized in that: The method of obtaining the instruction conversion relationship of the x86 instruction group in the first instruction group set from the decoding information table in step 3 is: extract the opcode feature value of the x86 instruction group, if there is a unique x86 instruction feature group matching the opcode feature value in the decoding information table, then obtain the instruction conversion relationship corresponding to the x86 instruction feature group; otherwise, extract the addressing mode feature value of the x86 instruction group, search for the x86 instruction feature group with the same feature value in the matched x86 instruction feature groups, if the result is unique, then obtain the instruction conversion relationship corresponding to the x86 instruction feature group, otherwise obtain the instruction conversion relationships corresponding to all matched x86 instruction feature groups.

8. The instruction encoding and decoding performance optimization method according to claim 1, characterized in that: The method of using NEON instructions in step 4 to decode the x86 instruction group in parallel according to the conversion relationship to form intermediate data is: extract the ARM instructions or ARM instruction combinations and decoding rules in the conversion relationship pair, decode the x86 instructions in the x86 instruction group into an ARM instruction set containing ARM instructions or ARM instruction combinations, decode the operands therein into a data segment set marked with the operand type corresponding to the ARM instruction field, and store them in the memory to form intermediate data.

9. The instruction encoding and decoding performance optimization method according to claim 1, characterized in that: The method of using NEON instructions to encode intermediate data into ARM instructions in step 4 is: using NEON instructions to load intermediate data into NEON registers, and then using NEON instructions to encode data in the ARM instruction set into ARM instruction opcodes according to the encoding rules of ARM instructions, and encoding data in the data segment set into ARM instruction format operands.

10. The instruction encoding and decoding performance optimization method according to claim 6, characterized in that: The operation code characteristic value is obtained by extracting the upper 4 bits and the lower 4 bits of the operation code, and the addressing mode characteristic value is extracted according to the position of the addressing mode in the instruction by using a data interception algorithm.

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