Instruction execution method, device, system and equipment and storage medium

Abstract

The invention relates to an instruction execution method, device and system, equipment and a storage medium. The instruction execution method comprises the steps of obtaining current instruction information and branch historical information of a current branch instruction; calculating a jump probability value of the branch instruction based on the current instruction information and the branch historical information through a pre-trained reasoning model deployed on a hardware accelerator; determining a branch prediction result according to the jump probability value and a set branch prediction decision; wherein the branch prediction result comprises a prediction execution result and target instruction information; and based on the prediction execution result, executing a target instruction determined according to the target instruction information. According to the method provided by the invention, the accuracy of branch prediction is improved, the performance loss of the processor caused by misprediction is reduced, and the accuracy of instruction execution is also ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to an instruction execution method, device, system, equipment and storage medium. Background Art

[0002] With the increasing complexity of processor architecture and the improvement of performance requirements, branch prediction technology has become one of the key factors determining processor performance. At present, the length and depth of processor pipelines are increasing, and the frequent appearance of conditional branch instructions will lead to interruptions of instruction flow and conflicts in pipelines, seriously affecting the throughput and execution efficiency of processors. Therefore, how to accurately predict the direction of branches and reduce the performance loss caused by misprediction to ensure the accuracy of instruction execution has become an important issue in modern processor design. Summary of the invention

[0003] In order to solve the above technical problems, the embodiments of the present disclosure provide an instruction execution method, apparatus, system, device and storage medium.

[0004] In a first aspect, an embodiment of the present disclosure provides an instruction execution method, the method comprising:

[0005] Get the current instruction information and branch history information of the current branch instruction;

[0006] The pre-trained inference model deployed on the hardware accelerator calculates the jump probability value of the previous branch instruction based on the current instruction information and branch history information;

[0007] Determine a branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes a predicted execution result and target instruction information;

[0008] Based on the predicted execution result, the target instruction determined according to the target instruction information is executed.

[0009] Optionally, based on the predicted execution result, executing a target instruction determined according to the target instruction information includes:

[0010] If the predicted execution result is a jump, before the current branch instruction is executed, the target instruction determined according to the target instruction information is executed through other processing stages, and execution data is generated; wherein the execution data is data required by at least one unexecuted instruction in the target processing stage where the current branch instruction is located, and the other processing stages are different from the target processing stage; or,

[0011] If the predicted execution result is no jump, then after the current branch instruction is executed, the target instruction determined according to the target instruction information is continued to be executed through the target processing stage, and execution data is generated; wherein at least one unexecuted instruction includes the target instruction.

[0012] Optionally, based on the predicted execution result, after executing the target instruction determined according to the target instruction information, the method further includes:

[0013] Get the actual execution result generated after the current branch instruction is executed;

[0014] Compare the actual execution result with the branch prediction result, generate error information, and update the branch history information according to the actual execution result;

[0015] The model parameters of the inference model are adjusted according to the error information to obtain an adjusted inference model; wherein the adjusted inference model is used for predicting the next branch instruction.

[0016] Optionally, executing a target instruction determined according to the target instruction information includes:

[0017] Determine a target instruction according to the target instruction information, and load the target instruction into an instruction register to decode the target instruction;

[0018] Execute corresponding operations according to the decoded execution information.

[0019] Among them, the current instruction information includes the branch instruction address and the branch instruction type, the branch history information includes the execution information of multiple branches in the program where the current branch instruction is located within a preset time period, and the branch history information reflects the branch behavior pattern when the program is running.

[0020] Optionally, the jump probability value of the aforementioned branch instruction is calculated based on the current instruction information and the branch history information, including:

[0021] Mapping the branch history information, the current branch instruction address and the current branch instruction type to a first vector of a set length through a hash function; the first vector refers to a numerical form suitable for an inference model;

[0022] Based on the first vector, capturing the time dependency in program execution, and generating a second vector;

[0023] The Sigmoid activation function is used to calculate the jump probability value of the aforementioned branch instruction based on the second vector.

[0024] Optionally, before obtaining the current instruction information and branch history information of the current branch instruction, the method further includes:

[0025] Design inference models in RISC-V cores to build hardware accelerators;

[0026] Integrating a hardware accelerator into a processor core; wherein the processor is used to execute a current branch instruction and a target instruction;

[0027] A dedicated interface unit is set for the hardware accelerator; wherein the dedicated interface unit is used to obtain current instruction information and branch history information.

[0028] In a second aspect, an embodiment of the present disclosure provides an instruction execution device, the device comprising:

[0029] An acquisition unit, used to acquire current instruction information and branch history information of a current branch instruction;

[0030] An inference unit, used to calculate the jump probability value of the previous branch instruction based on the current instruction information and branch history information through a pre-trained inference model deployed on the hardware accelerator;

[0031] A decision unit, used to determine a branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes a predicted execution result and target instruction information;

[0032] The execution unit is used to execute the target instruction determined according to the target instruction information based on the predicted execution result.

[0033] In a third aspect, an embodiment of the present disclosure provides an instruction execution system, the system comprising a feature extraction and preprocessing module, a hardware accelerator, a branch prediction decision module, an instruction acquisition module, an instruction execution module and a history record module, wherein:

[0034] The instruction acquisition module is used to acquire current instruction information of the current branch instruction; wherein the current instruction information includes the branch instruction address and the branch instruction type;

[0035] The history module is used to store the branch history information of the current branch instruction;

[0036] The feature extraction and preprocessing module is used to map the branch history information, the current branch instruction address and the current branch instruction type to a first vector of a set length through a hash function;

[0037] The hardware accelerator is used to calculate the jump probability value of the previous branch instruction based on the current instruction information and branch history information through a pre-trained inference model;

[0038] The branch prediction decision module is used to determine the branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes the predicted execution result and the target instruction information;

[0039] The instruction execution module is used to execute the target instruction determined according to the target instruction information based on the predicted execution result.

[0040] In a fourth aspect, an embodiment of the present disclosure provides an electronic device, including:

[0041] Memory;

[0042] Processor; and

[0043] Computer programs;

[0044] The computer program is stored in the memory and is configured to be executed by the processor to implement the method of the first aspect as described above.

[0045] In a fifth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the method in the first aspect are implemented.

[0046] The instruction execution method provided by the present disclosure includes: obtaining the current instruction information and branch history information of the current branch instruction; calculating the jump probability value of the aforementioned branch instruction based on the current instruction information and branch history information through a pre-trained inference model deployed on a hardware accelerator; determining the branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes the predicted execution result and the target instruction information; based on the predicted execution result, executing the target instruction determined according to the target instruction information. The method provided by the present application improves the accuracy of branch prediction, reduces the processor performance loss caused by misprediction, and ensures the accuracy of instruction execution. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0048] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0049] Figure 1 A flowchart of an instruction execution method provided by an embodiment of the present disclosure;

[0050] Figure 2 A schematic diagram of the structure of an instruction execution system provided by an embodiment of the present disclosure;

[0051] Figure 3 A schematic diagram of the structure of an instruction execution device provided by an embodiment of the present disclosure;

[0052] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0053] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0054] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0055] Before explaining the present disclosure in detail, the following terms are explained:

[0056] The branch predictor is a hardware mechanism used in modern processors to improve the efficiency of the instruction pipeline. It attempts to guess the results of each branch instruction in the program (i.e., whether a jump will occur) so as to load the next instruction that may be executed into the pipeline in advance. This method of processing instructions in advance can reduce pipeline stalls caused by waiting for branch results, thereby improving processor performance.

[0057] Instruction Pipeline is a technology in computer architecture that improves processor efficiency and throughput by breaking down the execution process of instructions into multiple stages and allowing these stages to process different instructions in parallel. This technology allows different parts of multiple instructions to be in different stages of execution at any given time, thereby making full use of hardware resources.

[0058] Specifically, the accuracy of traditional branch predictors is low when processing complex branch behaviors. Pipeline refresh caused by misprediction will reduce processor performance. Specifically, branch prediction technologies include:

[0059] Static branch prediction: It is based on static rules. For example, the processor simply assumes that all backward jump branches (usually loops) will occur, while all forward jump branches will not. Although this method is simple to implement, it has low accuracy in practical applications and cannot adapt to the operation of complex programs.

[0060] Dynamic branch prediction: To address the limitations of static prediction, modern processors have introduced dynamic branch prediction, which makes predictions based on the historical behavior of the program when it is running. For example, dynamic prediction usually uses information such as branch history and program counter (PC) for learning to improve prediction accuracy. Common dynamic branch predictors include: 1) single-bit or double-bit saturated counter predictor: by recording the historical jump situation of each branch, a state machine is used to determine the possible direction of the next branch; 2) Global History Register (GHR) and Global Pattern Predictor (Gshare): combining multiple branch history information to capture cross-instruction branch patterns and improve the prediction accuracy in complex scenarios. Specifically, the local branch predictor records the local historical behavior of each branch instruction. Each branch has its own independent history record and prediction table. Although it can give a higher prediction accuracy for frequently repeated branch instructions, it has a weaker ability to capture cross-instruction branch patterns; the global branch predictor combines the global history information of all branch instructions to process complex branch patterns with cross-instruction correlations. Although the global predictor can identify global correlations, it performs poorly in branch patterns with strong locality; the Gshare predictor combines global history information with the program counter, which can capture certain global correlations while retaining some local information.

[0061] In summary, traditional dynamic branch predictors (such as predictors based on local or global history information) rely on simple history tables, usually using limited bits to make state judgments. In addition, since this method can only handle short-term dependencies, it has low prediction accuracy when facing complex branch patterns, especially when there are long-term branch dependencies in the program. The global history predictor (such as Gshare) also has limitations. Although it combines the information of the global branch history with the program counter, it is still not effective in handling branch behaviors with long-term dependencies. In addition, the global predictor can only capture patterns within a shorter time range and cannot effectively deal with situations where branch behaviors are complex and span multiple instructions. This makes existing predictors prone to mispredictions when running complex programs, thereby affecting the performance of the processor.

[0062] In view of the above technical problems, the present disclosure provides an instruction execution method, which is described in detail through one or more of the following embodiments.

[0063] The instruction execution method provided in the embodiment of the present disclosure can be applied to the branch prediction execution scenario. The method can be executed by an instruction execution device, which can be implemented by software and / or hardware, and the device can be integrated in an electronic device. Among them, the electronic device can include but is not limited to mobile terminals such as smart phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (Tablet Personal Computers, Tablet PCs), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), wearable devices, etc., and fixed terminals such as digital televisions, desktop computers, smart home devices, etc.

[0064] Figure 1 A flowchart of an instruction execution method provided in an embodiment of the present disclosure specifically includes the following steps: Figure 1 The following steps are shown:

[0065] S101. Obtain current instruction information and branch history information of a current branch instruction.

[0066] It can be understood that the current branch instruction refers to a branch instruction being processed at the current stage of the pipeline. The current instruction address and current instruction type of the current branch instruction are obtained from the instruction memory or cache, and the current instruction information is obtained through the instruction acquisition module. The branch history information is obtained from the history record module. The branch history information refers to the execution information of N branch instructions of the program where the current branch instruction is located. The program includes multiple instructions. The types of multiple instructions include branch instructions, data transfer instructions, and arithmetic logic instructions. The types of branch instructions include conditional jumps, unconditional jumps, and loops. Jumping refers to jumping from the current processing stage to the processing stage of other instructions, such as sequentially executing instructions A, B, and C at a certain stage, where instruction A is the current branch instruction, one branch is instruction B, and the other branch is instruction D. One jump situation refers to jumping from instruction A to instruction D, and then returning from instruction D to instruction C to continue sequential execution. Instruction D and instruction A belong to different processing stages; a non-jump situation refers to sequentially executing instruction B from instruction A, and then sequentially executing instruction C.

[0067] Among them, the current instruction information includes the branch instruction address and the branch instruction type, the branch history information includes the execution information of multiple branches in the program where the current branch instruction is located within a preset time period, and the branch history information reflects the branch behavior pattern when the program is running.

[0068] It is understandable that the branch instruction address can be the program counter address (hereinafter referred to as the PC address). The PC address can help the model identify specific branch locations. For example, in the above example, the PC address of instruction A is 0x400000, and the PC address of instruction B is 0x400004. The branch instruction type refers to the type information of the branch instruction, such as the conditional branch and unconditional branch mentioned above. Different types of branch instructions have different branch behavior characteristics, so that the neural network can perform exclusive optimization for different branch instruction types. For example, the behavior of an unconditional branch is to determine whether to jump based on specific conditions. It can be described as jumping to the specified target address if the two values ​​are equal. The branch history information records the execution results of the last N branch instructions. The execution result refers to jumping or not jumping. The branch history information reflects the branch behavior of each branch instruction when the program is running.

[0069] Optionally, before obtaining the current instruction information and branch history information of the current branch instruction, the method further includes:

[0070] An inference model is designed in a RISC-V core to build a hardware accelerator; the hardware accelerator is integrated in a processor core; wherein the processor is used to execute a current branch instruction and a target instruction; a dedicated interface unit is set for the hardware accelerator; wherein the dedicated interface unit is used to obtain current instruction information and branch history information.

[0071] Understandably, before obtaining instruction information and branch history information, or before performing branch instruction prediction, a hardware accelerator needs to be designed. The purpose of the hardware accelerator is to accelerate the reasoning process of the reasoning model and meet the real-time requirements of the processor. The processor is used to execute the above information acquisition and process the data stream of each instruction. Specifically, a reasoning model is designed in the RISC-V kernel to build a hardware accelerator. The reasoning model can be understood as a neural network model, wherein RISC-V is an open source instruction set architecture based on the principle of reduced instruction set computing (RISC, Reduced Instruction Set Computing). Based on RISC-V, efficient and low-power neural network computing can be achieved. Subsequently, the hardware accelerator is directly integrated into the processor core and tightly coupled with the pipeline to reduce data transmission delay. In addition, a dedicated interface unit is also required for the hardware accelerator, which can be a dedicated bus or interface to ensure high-speed transmission of data between branch history information, instruction information and hardware accelerator.

[0072] It is understandable that deploying the inference model on the hardware accelerator can control energy consumption. Specifically, choosing a lightweight model of appropriate size balances the prediction accuracy and computational complexity; dynamically adjusting the operating frequency of the hardware accelerator according to the workload can reduce power consumption.

[0073] S102, using a pre-trained inference model deployed on a hardware accelerator, calculating a jump probability value of the aforementioned branch instruction based on current instruction information and branch history information.

[0074] It is understandable that, based on the above S101, the inference model is deployed on the hardware accelerator, and the parallel computing capability of the hardware accelerator can be utilized to reduce the inference time of calculating the jump probability value based on the current instruction information and branch history information. In addition, the calculation process of the inference model is pipelined, which effectively improves the throughput and further speeds up the calculation speed of the jump probability value.

[0075] Optionally, the above calculation of the jump probability value of the aforementioned branch instruction based on the current instruction information and the branch history information can be specifically implemented through the following steps:

[0076] The branch history information, the current branch instruction address and the current branch instruction type are mapped to a first vector of a set length through a hash function; the first vector refers to a numerical form suitable for an inference model; based on the first vector, the time dependency in program execution is captured to generate a second vector; and the Sigmoid activation function is used to calculate the jump probability value of the aforementioned branch instruction based on the second vector.

[0077] It is understandable that before the current instruction information and branch history information are input into the inference model, the input information needs to be properly preprocessed, such as encoding and normalization. Specifically: the branch history information, PC address and branch instruction type are converted into a numerical form acceptable to the neural network, such as mapping the above information to a vector of fixed length through a hash function to obtain a first vector; the first vector is normalized to prevent the large difference in data range from affecting the calculation accuracy of the model. Subsequently, the temporal dependency during program execution is captured from the first vector to generate a second vector, where the temporal dependency includes short-term dependency and long-term dependency. Finally, the second vector is mapped to the output space, and the Sigmoid activation function is used to output the jump probability value of the current branch instruction for branch jump, where the jump probability value is between 0 and 1.

[0078] Optionally, the inference model is trained as follows:

[0079] Determine the input information; preprocess the input information; design the neural network architecture and build a neural network model; output the probability value of branch jump based on the input information through the neural network model; train and optimize the neural network model to obtain the final inference model.

[0080] It can be understood that the input information includes the branch instruction address, PC address and branch instruction type. Preprocessing includes encoding and normalization. Normalization can prevent the data range from being too different and affect the model training during the model training stage.

[0081] Understandably, the long short-term memory network (LSTM) can be used as the main architecture of the neural network, in which LSTM can effectively process long sequence data, capture long-term dependencies in branch history information, and solve the gradient vanishing and explosion problems of traditional networks through the gating mechanism. Among them, the network structure includes an input layer, an LSTM layer, a fully connected layer, and an output layer. The input layer is used to receive the preprocessed input vector; the LSTM layer is used to process the input vector and learn time dependencies; the fully connected layer is used to map the output of the LSTM layer to the output space; the output layer is used to use the Sigmoid activation function to output the probability value of the branch jump. Subsequently, the model will output the probability value to the branch prediction decision module, which is used to convert the probability value into a binary classification result according to the set threshold. For example, if the probability value (such as 1) is greater than the set threshold (such as 0.5), it is predicted to jump, and if the probability value (such as 0) is less than the set threshold (such as 0.5), it is predicted not to jump. Other possible threshold settings are not limited and can be set according to needs.

[0082] It is understandable that for model training and optimization, when collecting training data, a large number of collection programs can be used to collect branch execution related data on simulators or actual hardware, where the collection program can be a SPEC CPU benchmark test set and common applications. The training data set includes input information (branch history information, instruction type and PC address) and the corresponding actual execution result (jump or no jump). A training data is: instruction A, conditional branch, 0x400080 and jump. The loss function for model training can select the cross entropy loss function, which is used to measure the difference between the model prediction value and the actual value, as shown in the following formula (1).

[0083]

[0084] In the formula, y i is the actual label, that is, the jump or no jump in the actual execution result, p i is the predicted label, that is, the predicted result output by the model based on the input data.

[0085] Understandably, the optimization algorithm of the model can use the Adam optimizer: an adaptive learning rate optimization algorithm that combines the advantages of momentum and RMSProp (Root Mean Square Propagation) to accelerate model convergence. RMSProp is an adaptive learning rate optimization algorithm for training deep learning models. During the training process, the model parameters are iteratively updated to minimize the loss function until the model performance meets the requirements.

[0086] S103 : Determine a branch prediction result according to the jump probability value and the set branch prediction decision.

[0087] The branch prediction result includes the predicted execution result and the target instruction information.

[0088] It is understandable that, based on the above S102, the set branch prediction decision refers to the judgment logic determined based on the jump probability value, such as the judgment logic in the branch prediction decision is to jump if the jump probability value is greater than the set threshold, and not to jump if the jump probability value is less than the set threshold. Among them, jumping and not jumping refer to the predicted execution results, and the target instruction information includes the relevant information of the next instruction to be executed (target instruction) of the current branch instruction. In the case of not jumping, the target instruction is an instruction to be executed that is in the same processing stage as the current branch instruction, that is, there is no need to add the target instruction to the pipeline, and the current branch instruction can be executed sequentially. In the case of jumping, the target instruction is an instruction to be executed that is in a different processing stage from the current branch instruction, that is, the target instruction needs to be added to the pipeline and executed in advance to reduce the program execution time.

[0089] S104. Execute the target instruction determined according to the target instruction information based on the predicted execution result.

[0090] It is understandable that, based on the above S103, the target instruction is executed before or after the current branch instruction is executed based on the predicted execution result.

[0091] Optionally, executing the target instruction determined according to the target instruction information based on the predicted execution result in S104 may be specifically implemented through the following steps:

[0092] If the predicted execution result is a jump, then before the current branch instruction is executed, the target instruction determined according to the target instruction information is executed through other processing stages, and execution data is generated; wherein the execution data is data required for at least one unexecuted instruction in the target processing stage where the current branch instruction is located, and the other processing stages are different from the target processing stage; or, if the predicted execution result is not a jump, then after the current branch instruction is executed, the target instruction determined according to the target instruction information is continued to be executed through the target processing stage, and execution data is generated; wherein at least one unexecuted instruction includes the target instruction; wherein the data flow includes the target processing stage and other processing stages.

[0093] It is understandable that if the predicted execution result is a jump, the target instruction is pre-loaded into the data stream before the current branch instruction is executed, or before the current branch instruction has not yet determined the actual execution result. For the entire program, the data stream is divided into multiple stages, and each stage can process different instructions, such as executing the current branch instruction through the target processing stage, and executing the target instruction through other processing stages. The target processing stage and other processing stages can process different instructions in parallel, that is, multi-stage parallel processing instructions. That is to say, based on the above example, when it is predicted that instruction A (current branch instruction) is to jump, the instruction D (target instruction) to be jumped is loaded and executed in advance, that is, instruction D and instruction A are processed in parallel. When instruction A is executed and instruction C (unexecuted instruction) is to be executed, the execution data after instruction D is executed can be directly obtained to improve the processing speed. If the execution result is not to jump, after the current branch instruction is executed, the target instruction can be continued to be executed in the target processing stage. Based on the above example, after instruction A is executed, instruction B is executed, and instruction B is the target instruction at this time.

[0094] Optionally, based on the predicted execution result, after executing the target instruction determined according to the target instruction information, the method further includes:

[0095] Obtain the actual execution result generated after the current branch instruction is executed; compare the actual execution result with the branch prediction result to generate error information, and update the branch history information according to the actual execution result; adjust the model parameters of the inference model according to the error information to obtain the adjusted inference model; wherein the adjusted inference model is used to predict the next branch instruction.

[0096] It can be understood that the actual execution result refers to whether the current branch instruction actually jumps or not after execution. In one possible case, the predicted execution result is a jump, while the actual execution result is no jump, that is, there may be an error in the prediction of the execution result. In this case, the actual execution result is compared with the branch prediction result, the branch history information is updated, and the error information is fed back to the inference model to optimize the model performance, that is, the inference model can be optimized in real time during program execution. The specific implementation method of adjusting the inference model parameters according to the error information is not described in detail. The optimized inference model can predict the next branch instruction to improve the prediction accuracy.

[0097] Optionally, executing the target instruction determined according to the target instruction information may be specifically implemented through the following steps:

[0098] The target instruction is determined according to the target instruction information, and the target instruction is loaded into the instruction register to decode the target instruction; and a corresponding operation is performed according to the decoded execution information.

[0099] It is understandable that the target instruction information includes information such as the identifier of the target instruction or the PC address that can directly determine the target instruction. After determining the target instruction, the target instruction is loaded into the instruction register and decoded. Decoding means that the processor parses the instruction and determines the operation type, operand source, and target register of the instruction. The result of instruction decoding will guide the subsequent execution stage to ensure that the processor can correctly interpret and execute each instruction. After completing the instruction decoding and obtaining the decoded execution information, the corresponding operation is performed to generate the execution data of the target instruction.

[0100] It is understandable that the current branch instruction will also be decoded during execution. After executing corresponding operations according to the decoded execution information, the actual execution result is generated, and the specific execution process will not be described in detail.

[0101] An instruction execution method provided by the embodiment of the present disclosure can effectively handle the complexity of branch jumps through a neural network model, and use branch history information, PC address and instruction type as input data, which can significantly improve the prediction accuracy. Secondly, according to the branch prediction results and the actual execution results, the weight of the inference model is dynamically adjusted, and the model is optimized by continuously feeding back the real branch execution results, which effectively ensures the accuracy of branch prediction and maintains the adaptability of the branch predictor. In addition, in view of the computational overhead problem of the inference model, it is proposed to design a dedicated hardware accelerator in the RISC-V kernel to improve the speed of model reasoning and ensure the real-time nature of the prediction. The seamless integration of the hardware accelerator and the processor pipeline also ensures that the model can run with low latency. In order to further reduce the energy consumption of hardware implementation, a lightweight neural network model architecture is adopted, and the inference frequency is adjusted through branches of different complexities, which reduces the overall power consumption while ensuring the prediction accuracy.

[0102] Based on the above embodiments, Figure 2 This is a schematic diagram of the structure of an instruction execution system provided by an embodiment of the present disclosure. The system includes a feature extraction and preprocessing module, a hardware accelerator, a branch prediction decision module, an instruction acquisition module, an instruction execution module and a history record module, wherein:

[0103] The instruction acquisition module is used to acquire current instruction information of the current branch instruction; wherein the current instruction information includes the branch instruction address and the branch instruction type;

[0104] The history module is used to store the branch history information of the current branch instruction;

[0105] The feature extraction and preprocessing module is used to map the branch history information, the current branch instruction address and the current branch instruction type to a first vector of a set length through a hash function;

[0106] The hardware accelerator is used to calculate the jump probability value of the previous branch instruction based on the current instruction information and branch history information through a pre-trained inference model;

[0107] The branch prediction decision module is used to determine the branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes the predicted execution result and the target instruction information;

[0108] The instruction execution module is used to execute the target instruction determined according to the target instruction information based on the predicted execution result.

[0109] Optionally, the system also includes an instruction decoding module, a branch result feedback module and a model update module, wherein the instruction decoding module is used to decode the instruction information to obtain the decoded execution information; the instruction execution module is used to perform corresponding operations according to the decoded execution information to generate an actual execution result; the branch result feedback module is used to compare the actual execution result with the branch prediction result, update the history record module, and generate error information; the model update module is used to optimize the inference model according to the error information.

[0110] It is understandable that the specific implementation description of each module included in the system can be found in the above embodiments and will not be repeated here.

[0111] based on Figure 2 In one implementation scenario shown, the instruction acquisition module obtains the current instruction address and the current instruction type from the instruction memory or cache and generates instruction information. The feature extraction module and the preprocessing module generate an input vector based on the instruction information generated by the instruction acquisition module and the global branch history information stored by the history record module. The neural network reasoning module deployed on the hardware accelerator calculates the branch jump probability based on the input vector. The branch prediction decision module determines the prediction result based on the branch jump probability. The instruction acquisition module obtains the prediction result for guiding the pre-fetch instruction, and pre-loads the instruction into the data stream and executes it in parallel with the current instruction. The instruction decoding module decodes the instruction information of the current instruction to obtain the decoded execution information. The instruction execution module performs corresponding operations according to the decoded execution information to generate an actual execution result. The branch result feedback module compares the prediction result with the actual execution result, stores the branch history information in the history record module, and generates error information. The model update module adjusts the parameters of the neural network model based on the error information, and feeds back the adjusted neural network model parameters to the hardware accelerator.

[0112] The instruction execution system provided by this application has the following advantages:

[0113] 1) Improve branch prediction accuracy

[0114] Traditional branch prediction methods, such as local predictors or global history predictors, usually rely on fixed-pattern branch history information, while neural networks can capture more complex branch patterns. When branch behavior is difficult to predict with simple rules, neural networks can provide more accurate prediction results by learning deep patterns in branch history information. This high-precision prediction helps reduce pipeline stalls caused by incorrect branch predictions.

[0115] 2) Adapting to complex branching behaviors

[0116] Neural networks, especially LSTM, can handle long-term dependencies in branch history information (i.e. branch behavior depends on more distant history). This makes it perform better for complex and unpredictable branch behaviors, significantly improving its adaptability to complex program branches.

[0117] 3) Reduce pipeline pauses and performance loss

[0118] Each incorrect branch prediction will cause the processor's pipeline to refresh, increasing performance loss. By improving the accuracy of the prediction, it is possible to reduce the number of mispredictions, thereby reducing the number of pipeline stalls. Fewer pipeline stalls means that the processor can execute instructions more efficiently, improving overall performance.

[0119] 4) Hardware acceleration improves real-time performance

[0120] In order to deal with the high computational complexity of neural networks, a dedicated hardware accelerator is introduced into the RISCV core to achieve fast reasoning of neural networks. Through the low-latency calculation of dedicated hardware, the real-time branch prediction can be guaranteed even in an environment where the processor runs at high speed, without slowing down the pipeline speed.

[0121] 5) Reduce energy consumption

[0122] For problems with high computational requirements of neural networks, power consumption is optimized through lightweight network architecture and dynamic adjustment of inference frequency. Compared with other complex models, LSTM can significantly reduce energy consumption while ensuring high accuracy, making it efficient for use in embedded or mobile devices.

[0123] 6) Adaptability and dynamic optimization

[0124] The constructed neural network branch predictor dynamically adjusts its internal weights by continuously receiving feedback (i.e., the actual branch execution results), forming an adaptive system. This capability ensures that the predictor can be optimized in real time as the application runs, so that it always maintains a high prediction accuracy when facing different programs or running scenarios.

[0125] Based on the above embodiments, Figure 3The structure diagram of an instruction execution device provided by the embodiment of the present disclosure is as follows. The instruction execution device provided by the embodiment of the present disclosure can execute the processing stages provided by the instruction execution method embodiment, such as Figure 3 As shown, the instruction execution device 300 includes an acquisition unit 301, an inference unit 302, a decision unit 303 and an execution unit 304, wherein:

[0126] The acquisition unit 301 is used to acquire the current instruction information and branch history information of the current branch instruction;

[0127] The reasoning unit 302 is used to calculate the jump probability value of the aforementioned branch instruction based on the current instruction information and the branch history information through a pre-trained reasoning model deployed on the hardware accelerator;

[0128] A decision unit 303, used to determine a branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes a predicted execution result and target instruction information;

[0129] The execution unit 304 is used to execute the target instruction determined according to the target instruction information based on the predicted execution result.

[0130] Optionally, the execution unit 304 is used to:

[0131] If the predicted execution result is a jump, before the current branch instruction is executed, the target instruction determined according to the target instruction information is executed through other processing stages, and execution data is generated; wherein the execution data is data required by at least one unexecuted instruction in the target processing stage where the current branch instruction is located, and the other processing stages are different from the target processing stage; or,

[0132] If the predicted execution result is no jump, then after the current branch instruction is executed, the target instruction determined according to the target instruction information is continued to be executed through the target processing stage, and execution data is generated; wherein at least one unexecuted instruction includes the target instruction.

[0133] Optionally, the instruction execution device 300 is used to:

[0134] Get the actual execution result generated after the current branch instruction is executed;

[0135] Compare the actual execution result with the branch prediction result, generate error information, and update the branch history information according to the actual execution result;

[0136] The model parameters of the inference model are adjusted according to the error information to obtain an adjusted inference model; wherein the adjusted inference model is used for predicting the next branch instruction.

[0137] Optionally, the execution unit 304 is used to:

[0138] Determine a target instruction according to the target instruction information, and load the target instruction into an instruction register to decode the target instruction;

[0139] Execute corresponding operations according to the decoded execution information.

[0140] Among them, the current instruction information includes the branch instruction address and the branch instruction type, the branch history information includes the execution information of multiple branches in the program where the current branch instruction is located within a preset time period, and the branch history information reflects the branch behavior pattern when the program is running.

[0141] Optionally, the reasoning unit 303 is used to:

[0142] Mapping the branch history information, the current branch instruction address and the current branch instruction type to a first vector of a set length through a hash function; the first vector refers to a numerical form suitable for an inference model;

[0143] Based on the first vector, capturing the time dependency in program execution, and generating a second vector;

[0144] The Sigmoid activation function is used to calculate the jump probability value of the aforementioned branch instruction based on the second vector.

[0145] Optionally, the instruction execution device 300 is further configured to:

[0146] Design inference models in RISC-V cores to build hardware accelerators;

[0147] Integrating a hardware accelerator into a processor core; wherein the processor is used to execute a current branch instruction and a target instruction;

[0148] A dedicated interface unit is set for the hardware accelerator; wherein the dedicated interface unit is used to obtain current instruction information and branch history information.

[0149] Figure 3 The instruction execution device of the illustrated embodiment can be used to execute the technical solution of the above-mentioned method embodiment. Its implementation principle and technical effect are similar and will not be repeated here.

[0150] Figure 4 This is a schematic diagram of the structure of an electronic device provided by an embodiment of the present disclosure. Figure 4, which shows a schematic diagram of the structure of an electronic device 400 suitable for implementing the embodiment of the present disclosure. The electronic device 400 in the embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle terminals (such as vehicle navigation terminals), wearable electronic devices, etc., and fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 4 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0151] like Figure 4 As shown, the electronic device 400 may include a processing device 401 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 402 or a program loaded from a storage device 408 to a random access memory (RAM) 403 to implement the instruction execution method of the embodiment described in the present disclosure. In the RAM 403, various programs and data required for the operation of the electronic device 400 are also stored. The processing device 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0152] Typically, the following devices may be connected to the I / O interface 405: an input device 406 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 407 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 408 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 409. The communication device 409 may allow the electronic device 400 to communicate with other devices wirelessly or by wire to exchange data. Although Figure 4 The electronic device 400 is shown with various devices, but it should be understood that it is not required to implement or possess all the devices shown. More or fewer devices may be implemented or possessed instead.

[0153] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a non-transitory computer-readable medium, and the computer program contains a program code for executing the method shown in the flowchart, thereby implementing the instruction execution method as described above. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 409, or installed from the storage device 408, or installed from the ROM 402. When the computer program is executed by the processing device 401, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0154] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0155] In some embodiments, the client and the server may communicate using any currently known or future developed network protocol such as HTTP (HyperText Transfer Protocol), and may be interconnected with any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network ("LAN"), a wide area network ("WAN"), an internet (e.g., the Internet), and a peer-to-peer network (e.g., an ad hoc peer-to-peer network), as well as any currently known or future developed network.

[0156] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0157] Optionally, when the above one or more programs are executed by the electronic device, the electronic device may also execute other steps described in the above embodiments.

[0158] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages ​​or a combination thereof, including, but not limited to, object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0159] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0160] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware, wherein the name of a unit does not, in some cases, limit the unit itself.

[0161] The functions described above herein may be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), and the like.

[0162] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0163] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or gateway that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or gateway. In the absence of further restrictions, the elements defined by the sentence "comprise one..." do not exclude the presence of other identical elements in the process, method, article or gateway that includes the elements.

[0164] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for executing an instruction, characterized in that: The method comprises: Get the current instruction information and branch history information of the current branch instruction; Calculate the jump probability value of the aforementioned branch instruction based on the current instruction information and the branch history information through a pre-trained inference model deployed on the hardware accelerator; Determining a branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes a predicted execution result and target instruction information; Based on the predicted execution result, a target instruction determined according to the target instruction information is executed.

2. The method according to claim 1, characterized in that The executing, based on the predicted execution result, a target instruction determined according to the target instruction information, comprises: If the predicted execution result is a jump, before the current branch instruction is executed, the target instruction determined according to the target instruction information is executed through other processing stages, and execution data is generated; wherein the execution data is data required by at least one unexecuted instruction in the target processing stage where the current branch instruction is located, and the other processing stage is different from the target processing stage; or, If the predicted execution result is no jump, then after the current branch instruction is executed, the target instruction determined according to the target instruction information is continued to be executed through the target processing stage, and execution data is generated; wherein the at least one unexecuted instruction includes the target instruction.

3. The method according to claim 1, characterized in that After executing the target instruction determined according to the target instruction information based on the predicted execution result, the method further includes: Obtaining an actual execution result generated after the current branch instruction is executed; Compare the actual execution result with the branch prediction result to generate error information, and update the branch history information according to the actual execution result; The model parameters of the inference model are adjusted according to the error information to obtain an adjusted inference model; wherein the adjusted inference model is used for predicting the next branch instruction.

4. The method according to claim 1, characterized in that: The executing the target instruction determined according to the target instruction information includes: Determine a target instruction according to the target instruction information, and load the target instruction into an instruction register to decode the target instruction; Execute corresponding operations according to the decoded execution information.

5. The method according to claim 1, characterized in that The current instruction information includes a branch instruction address and a branch instruction type, the branch history information includes execution information of multiple branches in the program where the current branch instruction is located within a preset period of time, and the branch history information reflects the branch behavior pattern when the program is running; The calculating the jump probability value of the aforementioned branch instruction based on the current instruction information and the branch history information includes: Mapping the branch history information, the current branch instruction address and the current branch instruction type to a first vector of a set length through a hash function; the first vector refers to a numerical form suitable for the reasoning model; Based on the first vector, capturing the time dependency in the execution of the program to generate a second vector; A Sigmoid activation function is used to calculate a jump probability value of the aforementioned branch instruction based on the second vector.

6. The method according to claim 1, characterized in that Before obtaining the current instruction information and branch history information of the current branch instruction, the method further includes: Designing the inference model in a RISC-V kernel to build a hardware accelerator; Integrating the hardware accelerator into a processor core; wherein the processor is used to execute the current branch instruction and the target instruction; A dedicated interface unit is provided for the hardware accelerator; wherein the dedicated interface unit is used to obtain the current instruction information and the branch history information.

7. An instruction execution device, characterized in that: The device comprises: An acquisition unit, used to acquire current instruction information and branch history information of a current branch instruction; An inference unit, configured to calculate the jump probability value of the aforementioned branch instruction based on the current instruction information and the branch history information through a pre-trained inference model deployed on the hardware accelerator; A decision unit, configured to determine a branch prediction result according to the jump probability value and a set branch prediction decision; wherein the branch prediction result includes a predicted execution result and target instruction information; An execution unit is used to execute a target instruction determined according to the target instruction information based on the predicted execution result.

8. An instruction execution system, characterized in that: The system includes a feature extraction and preprocessing module, a hardware accelerator, a branch prediction decision module, an instruction acquisition module, an instruction execution module and a history record module, wherein: The instruction acquisition module is used to acquire current instruction information of the current branch instruction; wherein the current instruction information includes a branch instruction address and a branch instruction type; The history record module is used to store the branch history information of the current branch instruction; The feature extraction and preprocessing module is used to map the branch history information, the current branch instruction address and the current branch instruction type to a first vector of a set length through a hash function; The hardware accelerator is used to calculate the jump probability value of the aforementioned branch instruction based on the current instruction information and the branch history information through a pre-trained reasoning model; The branch prediction decision module is used to determine a branch prediction result according to the jump probability value and the set branch prediction decision; wherein the branch prediction result includes a predicted execution result and target instruction information; The instruction execution module is used to execute a target instruction determined according to the target instruction information based on the predicted execution result.

9. An electronic device, characterized in that: include: Memory; processor; as well as Computer programs; The computer program is stored in the memory and is configured to be executed by the processor to implement the instruction execution method as claimed in any one of claims 1 to 6.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the instruction execution method according to any one of claims 1 to 6 are implemented.

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