A memory alignment optimization method for instruction translation based on virtual address redirection

Abstract

The present invention discloses an instruction conversion memory alignment optimization method based on virtual address redirection. When an executable file is loaded and executed in a dynamic instruction conversion manner, the conversion of memory access instructions and function call instructions related to non-aligned memory access is realized through precise instruction analysis, flexible memory adjustment, optimized instruction conversion and perfect memory cleaning, which effectively solves the problem of non-aligned memory access in function call parameters and provides a feasible and efficient solution for cross-architecture assembly code conversion.

Description

Technical Field

[0001] The invention belongs to the technical field of computer software development, and in particular relates to an instruction conversion memory alignment optimization method based on virtual address redirection. Background Art

[0002] In computer architecture, the x86 architecture and the ARM architecture have significant differences in the alignment requirements for memory access. The x86 architecture has looser requirements and allows a certain degree of non-aligned memory access, but this results in a certain degree of performance loss. When using certain instructions such as load or store instructions in the ARM architecture, the memory address accessed is required to be word-aligned. Due to the differences in the x86 architecture and the ARM architecture's requirements for memory access alignment, when a program is executed across architectures from the x86 architecture to the ARM architecture in a dynamic instruction conversion manner, an exception may occur when the function call parameter involves non-aligned memory access, which in turn prevents the program from running correctly and efficiently on the ARM architecture. Summary of the invention

[0003] In view of this, the present invention provides an instruction conversion memory alignment optimization method based on virtual address redirection, which realizes efficient and accurate execution of x86 instruction programs in ARM systems by efficiently converting memory access instructions and function call instructions related to non-aligned memory access.

[0004] The present invention provides an instruction conversion memory alignment optimization method based on virtual address redirection, which specifically includes the following steps:

[0005] Step 1: Load and execute the executable file in the ARM system through dynamic instruction conversion;

[0006] Step 2, obtain the current instruction to be converted. If it is a function call instruction of the x86 architecture, the first code set is formed by the relevant codes of the function parameters, and step 3 is executed; otherwise, the current instruction to be converted is converted into an ARM instruction and step 7 is executed;

[0007] Step 3: If there is a first target code in the first code set that includes a memory access instruction whose operand is a non-aligned memory address, then execute step 4; otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 7;

[0008] Step 4, the non-aligned memory address in the ARM system is the first temporary memory, and the pointer is the first ARM base address; after alignment, the first target data is read from the aligned memory address, and a first ARM instruction combination of allocating the first temporary memory and copying the first target data to the first temporary memory is constructed;

[0009] Step 5, converting the first target code into an instruction sequence consisting of a first ARM instruction combination and a second ARM instruction; the operands of the second ARM instruction are the first ARM register and the first temporary memory, and the function is the same as that of the first target code;

[0010] Step 6: Convert the current instruction to be converted into an instruction sequence consisting of a third ARM instruction, a fourth ARM instruction and a second ARM instruction combination, wherein the third ARM instruction reads data from the first temporary memory to the second ARM register, the second ARM instruction combination writes the data of the first temporary memory back to the original memory space and then releases it, and the fourth ARM instruction has the same function as the current instruction to be converted and uses the second ARM register as a function parameter;

[0011] Step 7: If the executable file is executed and the conversion is completed, then the process ends; otherwise, proceed to step 2.

[0012] Furthermore, the memory space size of the first temporary memory is calculated as follows: rounding the unaligned memory address down to the nearest aligned memory address, the address offset between the unaligned memory address and the aligned memory address is the first offset, obtaining the data length of the data to be read from the unaligned memory address, and setting the memory space size of the first temporary memory to be able to save the data of the data length and the value of the first offset.

[0013] Furthermore, the memory space size of the first temporary memory is: the sum of the data length required to read data from the non-aligned memory address and the first offset.

[0014] Furthermore, the method for obtaining the data length required to read data from the non-aligned memory address is: if the number of operands in the first target code is greater than 1, the size of the operand of the non-memory address is used as the data length; otherwise, the data length is the number of general register bits of the x86 system.

[0015] Furthermore, the first temporary memory is a memory space allocated in the stack space or heap space of the ARM system.

[0016] Furthermore, the construction method of the first ARM instruction combination includes: determining whether the first target data is cross-memory page data, if it is cross-memory page data, the constructed loading instruction includes a loading instruction for reading data from an aligned memory address and a loading instruction for reading data from the next page, otherwise the loading instruction is a loading instruction for reading data from an aligned memory address.

[0017] Furthermore, when the first temporary memory is a memory space allocated in the stack space of the ARM system, the second ARM instruction combination includes: calculating the starting address and the ending address of the original memory space according to the unaligned memory address, the aligned memory address and the first target data, the starting address is the aligned memory address, and the ending address is the sum of the aligned memory address and the data length of the first target data; when the first target data is non-cross-memory page data, a stack load instruction is used to load the data read from the first temporary memory into the original memory space composed of the starting address and the ending address; when the first target data is cross-memory page data, a stack load instruction is used to load the data read from the first temporary memory into the original memory space composed of the starting address to the end position of the page where it is located and from the starting position of the next page to the end address.

[0018] Furthermore, when the first temporary memory is a memory space allocated in the heap space of the ARM system, the second ARM instruction combination includes: calculating the starting address and the ending address of the original memory space according to the unaligned memory address and the data length of the data required to be read from the unaligned memory address; when the first target data is non-cross-memory page data, using the heap loading instruction to load the data read from the first temporary memory into the original memory space composed of the starting address and the ending address; when the first target data is cross-memory page data, using the heap loading instruction to load the data read from the first temporary memory into the original memory space composed of the starting address to the ending position of the page and from the starting position of the next page to the ending address.

[0019] Furthermore, when the first temporary memory is a memory space allocated in the heap space of the ARM system, the first temporary memory is released by calling a heap release function to complete the release.

[0020] Furthermore, the first code set is formed by codes related to the parameters in the first parameter set within a set range, and the set range is an instruction set of a set number of bars backward from the function call instruction. Beneficial Effects

[0021] When the executable file is loaded and executed in a dynamic instruction conversion manner, the present invention realizes the conversion of memory access instructions and function call instructions related to non-aligned memory access through precise instruction analysis, flexible memory adjustment, optimized instruction conversion and perfect memory cleaning, effectively solves the problem of non-aligned memory access in function call parameters, and provides a feasible and efficient solution for cross-architecture assembly code conversion. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A flowchart of a method for optimizing instruction conversion memory alignment based on virtual address redirection is provided by the present invention. DETAILED DESCRIPTION

[0023] The present invention is described in detail below with reference to the accompanying drawings and with reference to the embodiments.

[0024] The invention provides an instruction conversion memory alignment optimization method based on virtual address redirection, the core idea of ​​which is: when an executable file is loaded and executed in a dynamic instruction conversion mode, a function call instruction under an x86 architecture is extracted to obtain a memory access instruction related to its parameter; for a memory access instruction whose operand memory address is non-aligned, a temporary memory is allocated for data corresponding to the memory address in an ARM system; the memory access instruction is converted into an instruction sequence consisting of a first ARM instruction combination for allocating temporary memory and copying data and a second ARM instruction; the function call instruction is converted into an instruction sequence consisting of a third ARM instruction, a fourth ARM instruction and a second ARM instruction combination for writing data in the temporary memory back to the original memory space and releasing the temporary memory, thereby completing the cross-architecture execution of the executable file.

[0025] The present invention provides an instruction conversion memory alignment optimization method based on virtual address redirection, the process is as follows: Figure 1 As shown, the specific steps include:

[0026] Step 1: Load and execute the executable file in the ARM system through dynamic instruction conversion.

[0027] Step 2, obtain the current instruction to be converted. If the current instruction to be converted is a function call instruction under the x86 architecture, obtain the parameters of the function in the function call instruction to form a first parameter set, obtain the code related to the parameters in the first parameter set within a set range to form a first code set, and execute step 3; otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 7. The set range is the instruction set of the number of bars set backward from the function call instruction.

[0028] Specifically, the function call instructions in the x86 architecture are such as CALL instructions or RET instructions. The commonly used parameter passing methods in the x86 architecture include register passing, stack passing and memory passing. Among them, register passing refers to the use of registers to complete the parameter passing. For example, registers such as eax, ebx, ecx and edx are often used to pass parameters. Especially in 32-bit mode, the first few parameters are generally passed by registers such as ecx and edx. Stack passing is another important parameter passing method. When a function is called, the parameters will be pushed into the stack in a certain order, and the called function will obtain these parameters from the stack. Memory passing is a method in which the parameters are stored in a specific location in the memory, and the function obtains the parameters by accessing the specific location. The data segment (.data) or heap memory is usually used to store these parameters.

[0029] The memory access instructions involved in the above parameter transfer method generally include MOV, PUSH, LODSB, STOSB and other instructions.

[0030] Step 3. If there is code containing memory access instructions in the first code set, a second code set is formed by the code containing memory access instructions in the first code set, the operands of the instructions in each code in the second code set are parsed, and the operands of the memory address type are extracted. If the memory address corresponding to the operand is unaligned, the code containing the operand is used as the first target code, and the instructions, instruction addresses and operands of the first target code are recorded, and step 4 is executed; otherwise, the current instruction to be converted is converted into an ARM instruction and step 7 is executed.

[0031] Step 4: round the non-aligned memory address down to the nearest aligned memory address, record the data to be read from the aligned memory address as the first target data, record the temporary memory corresponding to the non-aligned memory address in the ARM system as the first temporary memory, construct a first ARM instruction combination for allocating the first temporary memory and copying the first target data to the first temporary memory, record the pointer corresponding to the first temporary memory as the first ARM base address, and the first ARM instruction combination includes memory allocation, loading and storage instructions.

[0032] Specifically, the memory space size of the first temporary memory is calculated as follows: rounding down the non-aligned memory address to the nearest aligned memory address, recording the address offset between the non-aligned memory address and the aligned memory address as the first offset, obtaining the data length of the data to be read from the non-aligned memory address, and setting the memory space size of the first temporary memory to be able to store the data of the data length and the value of the first offset. The first temporary memory is the memory space allocated in the stack space or heap space of the ARM system.

[0033] Among them, when the first temporary memory is the memory space allocated in the stack space of the ARM system, the memory allocation instruction is, for example: sub sp, sp, #size, where sp is the stack pointer pointing to the starting position of the first temporary memory; when the first temporary memory is the memory space allocated in the heap space of the ARM system, the heap management function is called to allocate the required memory space, and the memory allocation instruction is, for example:

[0034] bl allocate_heap_memory / / allocate_heap_memory is a heap management function

[0035] mov r0, #size / / pass the required memory size to the heap allocation function

[0036] Store the returned stack pointer in a specific register.

[0037] In order to further improve the memory space utilization, the memory space size of the first temporary memory in the present invention is the sum of the data length to be read and the first offset. The method of obtaining the data length of the data read from the non-aligned memory address is: if the number of operands in the first target code is greater than 1, the size of the operand of the non-memory address is used as the data length; otherwise, the data length is the number of general register bits of the x86 system.

[0038] For example, the stack space in the ARM system is used as the first temporary memory, the number of general registers in the x86 system is 64 bits, and the unaligned memory address is 0x1003, then:

[0039] ldr r0, =0x1000 / / load the aligned start address to r0

[0040] ldm r0, {r1, r2} / / Load 64-bit data from the original memory space to the r1 and r2 registers

[0041] add sp, sp, #-8 / / Adjust the stack pointer to make room for storing data

[0042] stm sp, {r1, r2} / / Store data in temporary memory on the stack

[0043] In order to further improve reliability, the present invention executes when constructing a first ARM instruction combination for copying the first target data to the first temporary memory: first determine whether the first target data is cross-memory page data; if it is cross-memory page data, the load instructions in the constructed first ARM instruction combination include load instructions that read data from an aligned memory address and load instructions that read data from the next page; otherwise, the load instructions are load instructions that read data from an aligned memory address.

[0044] Step 5: record the ARM instruction with the same instruction function as the first target code as the second ARM instruction, select an ARM register with the same size as the first target data, and use the ARM register and the first temporary memory represented by the first ARM base address as operands of the second ARM instruction; convert the first target code into an instruction sequence consisting of the first ARM instruction combination and the second ARM instruction.

[0045] Step 6. Construct a second ARM instruction combination that writes the data in the first temporary memory back to the original memory space and releases the first temporary memory, use the ARM instruction that reads data from the first temporary memory to a specific ARM register as the third ARM instruction, record the ARM instruction with the same function as the current instruction to be converted as the fourth ARM instruction, and use the specific ARM register as a parameter of the function in the fourth ARM instruction; convert the current instruction to be converted into an instruction sequence consisting of the third ARM instruction, the fourth ARM instruction and the second ARM instruction combination.

[0046] Among them, when the first temporary memory is the memory space allocated in the stack space of the ARM system, the second ARM instruction combination includes: according to the unaligned memory address, the aligned memory address and the first target data, the starting address and the ending address of the original memory space are calculated, the starting address is the aligned memory address, and the ending address is the sum of the aligned memory address and the data length of the first target data; when the first target data is non-cross-memory page data, the stack loading instruction is used to load the data read from the first temporary memory into the original memory space composed of the starting address and the ending address; when the first target data is cross-memory page data, the stack loading instruction is used to load the data read from the first temporary memory into the original memory space composed of the starting address to the end position of the page and the starting position of the next page to the end address.

[0047] At this time, the first temporary memory is released by using the add sp, sp, #size instruction.

[0048] When the first temporary memory is the memory space allocated in the heap space of the ARM system, the second ARM instruction combination includes: calculating the starting address and the ending address of the original memory space according to the non-aligned memory address and the data length of the data required to be read from the non-aligned memory address; when the first target data is non-cross-memory page data, using the heap loading instruction to load the data read from the first temporary memory into the original memory space composed of the starting address and the ending address; when the first target data is cross-memory page data, using the heap loading instruction to load the data read from the first temporary memory into the original memory space composed of the starting address to the ending position of the page and the starting position to the ending address of the next page.

[0049] At this time, the first temporary memory is released by calling a heap release function to complete the release.

[0050] In order to ensure the correctness of the first temporary memory release and prevent memory leakage, the present invention sets an exception handler at the function entry position of the ARM instruction obtained by conversion where the current instruction to be converted is located, and records the address related to the first temporary memory release on the stack or in a special register. When an exception occurs in the execution process, the exception handler is started to jump to the recorded address to complete the release of the first temporary memory.

[0051] Step 7: If the executable file is executed to complete the conversion, then the process ends; otherwise, execute step 2. Example

[0052] In this embodiment, an instruction conversion memory alignment optimization method based on virtual address redirection provided by the present invention is adopted to realize efficient and accurate execution of x86 instruction programs in an ARM system, including the following steps:

[0053] S1. Parse x86 instructions when executing dynamic instruction conversion from x86 architecture to ARM architecture, reversely analyze function-related parameter passing instructions when encountering function call instructions, and extract relevant information when the parameter passing instruction is a memory access instruction.

[0054] For example, for the instruction mov eax, [ebx + ecx], where [ebx + ecx] is a memory access related operation, the analysis process includes:

[0055] S1.1. Calculate the address of the memory access operation. If the value of ebx is 0x1000 and the value of ecx is 3, then the access address of ecx is 0x1003.

[0056] S1.2, determine whether the address is word-aligned. For 32-bit word alignment, perform a logical AND operation on the address and 0x3, such as 0x1003 & 0x3. If the result is not zero, the memory access is unaligned. This embodiment uses logical operations to quickly determine whether it is unaligned.

[0057] S1.3. For memory access operations determined to be unaligned, record detailed information of the operation, including instruction address, operand, operand size, and current unaligned memory address.

[0058] S2. For each unaligned memory access operation, temporary memory is allocated in the ARM stack space or heap space according to the operand size and the memory alignment requirements of the ARM architecture.

[0059] S2.1. Determine the size of the temporary memory space required based on the size of the operand. If it is a 32-bit word operand, 4 bytes of space need to be allocated; if it is a 64-bit double-word operand, 8 bytes of space need to be allocated. Taking stack space allocation as an example, use the ARM architecture's sub sp, sp, #size instruction, where size is the required space size. For example, for a 64-bit double-word operand, use the sub sp, sp, #8 instruction to create space on the stack.

[0060] S2.2. To ensure the integrity and correctness of the data, the unaligned memory address needs to be adjusted to find its aligned start address. The calculation method is to round down the unaligned memory address to the nearest aligned memory address. For example, for the unaligned memory address 0x1003, its nearest 32-bit word aligned memory address is 0x1000, which can be calculated by (unalignedAddress & ~0x3).

[0061] S2.3. Determine the length of data to be copied from the original memory space based on the operand size and the offset of the non-aligned memory address relative to the aligned start address. Assuming the operand is a 64-bit double word and the non-aligned memory address is 0x1003, then 11 bytes of data need to be copied starting from 0x1000, specifically 4 bytes from 0x1000 to 0x1003 plus the subsequent 7 bytes to fully store 64 bits of data.

[0062] S2.4. Determine the size of the temporary memory based on the calculated data length, and allocate a piece of temporary memory in the ARM stack space or heap space.

[0063] S2.5. Use a combination of ARM load and store instructions to copy the data in the original memory to the temporary memory. Assume that the stack is used as temporary storage and the operand is a 64-bit double word, and the non-aligned memory address is 0x1003, as shown in the following sample code:

[0064] ldr r0, =0x1000 / / load the aligned start address to r0

[0065] ldm r0, {r1, r2} / / Load 64-bit data from the original memory space into the r1 and r2 registers

[0066] add sp, sp, #-8 / / Adjust the stack pointer to make room for storing data

[0067] stm sp, {r1, r2} / / Store data in temporary memory on the stack

[0068] S2.6. For non-aligned memory accesses that cross memory page boundaries, first check whether it crosses the page boundary. This can be determined by comparing whether the original address and the result of the original address plus the operand size are in the same page. If it crosses the page boundary, data needs to be read from the page where the original address is located and the next page respectively. For example, assuming the page size is 0x1000, the original address is 0xFFF0, and the operand size is 16 bytes, then the page boundary will be crossed. Use the following code:

[0069] ldr r0, =0xFFF0 / / Read data from the page where the original address is located

[0070] ldm r0, {r1, r2, r3, r4} / / Assume that four registers are used to store 16 bytes of data

[0071] ldr r5, =0x10000 / / Read the remaining data from the next page

[0072] ldm r5, {r6, r7} / / store data into temporary memory

[0073] add sp, sp, #-16

[0074] stm sp, {r1, r2, r3, r4, r5, r6, r7}

[0075] Through precise address calculation and memory copy strategy, not only the non-aligned memory address processing under normal circumstances is taken into account, but also special processing is performed for complex situations crossing page boundaries, ensuring the integrity and accuracy of the data and avoiding data loss or inconsistency problems caused by traditional methods. At the same time, the ARM load and store instruction sets are flexibly used to improve the versatility and reliability of memory adjustment.

[0076] S3, instruction conversion stage. Replace the unaligned memory access instructions in the original x86 function call parameters with temporary memory access instructions. For the previously identified unaligned memory access instructions, perform the following instruction conversion steps:

[0077] S3.1. Determine the temporary memory storage location and size. According to the operation in the memory adjustment phase, temporary memory has been allocated in the ARM stack space or heap space for the unaligned memory access operation:

[0078] For stack space allocation, use the sub sp, sp, #size instruction, where size is the required space size determined by the operand size. For example, if the operand is 32 bits (4 bytes), use sub sp, sp, #4; if it is 64 bits (8 bytes), use sub sp, sp, #8. This implements allocating a space on the stack that is large enough to store the data copied from the original aligned memory address.

[0079] For heap space allocation, you need to call a heap management function, similar to the ARM implementation of the malloc function in C language, to allocate the required memory space. For example, the custom ARM heap management function allocate_heap_memory, assuming that the returned heap pointer is stored in r1, uses the following instructions:

[0080] bl allocate_heap_memory / / Call heap allocation function

[0081] mov r0, #size / / pass the required memory size to the heap allocation function

[0082] Temporary memory is dynamically allocated according to the size of the operand, avoiding space waste or shortage caused by fixed-size allocation. Both stack and heap storage methods are supported, providing greater flexibility.

[0083] S3.2, the address is relocated to the temporary memory address, which realizes the accurate relocation of the address and ensures that the subsequent instruction operations can correctly access the temporarily stored data. The specific steps are as follows:

[0084] After copying data from the original aligned memory address to the temporary memory, it is necessary to relocate the access to the original memory space to the temporary memory address. For temporary memory stored on the stack, use the stack pointer sp as the base address of the temporary memory. For example, if 4 bytes of temporary memory are allocated using sub sp, sp, #4, then sp now points to the starting position of this temporary memory.

[0085] For temporary memory stored on the heap, the heap pointer stored in a register (such as r1) is used as the base address of the temporary memory. In instruction conversion, subsequent accesses to the original memory will be replaced by accesses to the address pointed to by the heap pointer.

[0086] S3.3. Replace the original memory access instructions. For the non-aligned memory access instructions in the original x86 function call parameters, replace them with access instructions to temporary memory addresses. The following are some specific examples:

[0087] Depending on the size and storage location of the operand, choose the appropriate ARM register to store the data read from the temporary memory. For 32-bit operands, you can usually use registers r0 to r3; for 64-bit operands, you need to use a pair of registers, such as r0 and r1, or r2 and r3. For example, if the original x86 instruction is mov eax, [ebx + ecx] and the operand is 32 bits, where [ebx + ecx] is an unaligned memory access, it is converted into an access to temporary memory. If the temporary memory is stored on the stack, and assuming that the data has been copied to the stack, the corresponding ARM instruction is:

[0088] ldr r0, [sp] / / Read data from temporary memory on the stack to register r0

[0089] If heap storage is used, assuming the heap pointer is stored in r1, the converted instructions are:

[0090] ldr r0, [r1] / / Read data from temporary memory on the heap to register r0

[0091] For complex addressing modes, such as mov eax, [ebx + ecx * 2 + 4], when converting in ARM, first convert the complex addressing calculation to ARM's addressing mode, and then use the temporary memory address. Assuming ebx corresponds to r2, ecx corresponds to r3, and the temporary memory is on the stack, the conversion steps are as follows:

[0092] lsl r3, r3, #1 / / ecx left shift 1 bit

[0093] add r3, r3, r2 / / add ebx

[0094] add r3, r3, #4 / / add offset 4

[0095] ldr r0, [sp, r3] / / Read data from the temporary memory on the stack according to the calculated offset

[0096] The above process not only simply replaces the address, but also completely converts the complex addressing mode, ensuring that the converted instructions are functionally equivalent to the original x86 instructions, while using ARM's addressing mode to improve the accuracy and efficiency of the conversion.

[0097] S4, memory cleaning phase. After the function call is completed, the data in the temporary memory needs to be written back to the original memory space. The specific steps are as follows:

[0098] S4.1. Calculate the starting address and ending address of the original memory based on the previously recorded operand size and non-aligned memory address. For example, for non-aligned memory address 0x1003 and 64-bit operand, the starting address is 0x1000 and the ending address is 0x1007.

[0099] S4.2. Read data from temporary memory using ARM's load instruction. As shown in the following example, assuming that the stack is used as temporary storage, it is:

[0100] ldm sp, {r1, r2} / / Read data from temporary memory on the stack into registers r1 and r2

[0101] For situations that do not cross page boundaries, use the storage instruction directly:

[0102] ldr r0, =0x1000

[0103] stm r0, {r1, r2} / / store the data back to the original memory space

[0104] In the case of crossing page boundaries, the data needs to be written back to the original memory page and the next page respectively:

[0105] ldr r0, =0xFFF0

[0106] stm r0, {r1, r2, r3, r4} / / Write back the data of the page where the original memory space is located

[0107] ldr r5, =0x10000

[0108] stm r5, {r6, r7} / / Write back the data of the next page

[0109] S4.3. Release the allocated temporary memory. For temporary memory allocated on the stack, use the add sp, sp, #size instruction to restore the stack pointer to its previous position and release the stack space. For temporary memory allocated on the heap, more complex heap management operations are required. Assuming that heap storage is used, the heap management function free_heap_memory receives a pointer as a parameter, which is used in the following way in ARM:

[0110] ldr r0, =heap_pointer / / Load heap pointer

[0111] bl free_heap_memory / / Call heap release function

[0112] S4.4. When exception handling or function call ends prematurely, ensure that temporary memory can be released correctly to prevent memory leaks. You can set an exception handler at the function entry, store the address of the cleanup operation on the stack or in a special register, and once an exception occurs, jump to the address to perform the cleanup operation. The following is an exception handling example:

[0113] push {lr} / / Save the return address

[0114] sub sp, sp, #exception_handler_size / / Make room for exception handlers

[0115] str lr, [sp] / / Store the return address in the exception handler space

[0116] / / Function body ...

[0117] / / Exception handling part

[0118] b handle_exception / / Jump to the exception handler when an exception occurs

[0119] / / Exception handler

[0120] handle_exception:

[0121] / / Call the memory cleanup function

[0122] bl cleanUpMemory

[0123] / / Restore stack and register states

[0124] ldr lr, [sp]

[0125] add sp, sp, #exception_handler_size

[0126] pop {pc} / / Return to the caller or other appropriate location

[0127] A variety of mechanisms are used to ensure the safe release of temporary memory, including the handling of different memory boundary conditions and memory cleanup in abnormal situations, avoiding memory leaks caused by function execution exceptions. At the same time, a feasible ARM implementation method for heap memory release is provided, improving the stability and robustness of the system.

[0128] In summary, the above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory alignment optimization method for instruction conversion based on virtual address redirection, characterized in that: The specific steps include: Step 1: Load and execute the executable file in the ARM system through dynamic instruction conversion; Step 2, obtain the current instruction to be converted. If it is a function call instruction of the x86 architecture, the first code set is formed by the relevant codes of the function parameters, and step 3 is executed; otherwise, the current instruction to be converted is converted into an ARM instruction and step 7 is executed; Step 3: If there is a first target code in the first code set that includes a memory access instruction whose operand is a non-aligned memory address, execute step 4; Otherwise, convert the current instruction to be converted into an ARM instruction and then execute step 7; Step 4, the non-aligned memory address in the ARM system is the first temporary memory, and the pointer is the first ARM base address; After alignment, read the first target data from the aligned memory address, and construct a first ARM instruction combination for allocating a first temporary memory and copying the first target data to the first temporary memory; Step 5, converting the first target code into an instruction sequence consisting of a first ARM instruction combination and a second ARM instruction; the operands of the second ARM instruction are the first ARM register and the first temporary memory, and the function is the same as that of the first target code; The first ARM register is an ARM register having the same size as the first target data; Step 6: Convert the current instruction to be converted into an instruction sequence consisting of a third ARM instruction, a fourth ARM instruction and a second ARM instruction combination, wherein the third ARM instruction reads data from the first temporary memory to the second ARM register, the second ARM instruction combination writes the data of the first temporary memory back to the original memory space and then releases it, and the fourth ARM instruction has the same function as the current instruction to be converted and uses the second ARM register as a function parameter; Step 7: If the executable file is executed and the conversion is completed, then the process ends; otherwise, go to step 2; The memory space size of the first temporary memory is calculated as follows: round the unaligned memory address down to the nearest aligned memory address, the address offset between the unaligned memory address and the aligned memory address is the first offset, the data length of the data to be read from the unaligned memory address is obtained, and the memory space size of the first temporary memory is set to be able to save the data of the data length and the value of the first offset.

2. The instruction conversion memory alignment optimization method according to claim 1, characterized in that: The memory space size of the first temporary memory is: the sum of the data length required to read data from the non-aligned memory address and the first offset.

3. The instruction conversion memory alignment optimization method according to claim 1, characterized in that: The method for obtaining the data length required to read data from the non-aligned memory address is: if the number of operands in the first target code is greater than 1, the size of the operand of the non-memory address is used as the data length; otherwise, the data length is the number of general register bits of the x86 system.

4. The instruction conversion memory alignment optimization method according to claim 1, characterized in that: The first temporary memory is a memory space allocated in the stack space or heap space of the ARM system.

5. The instruction conversion memory alignment optimization method according to claim 1, characterized in that: The construction method of the first ARM instruction combination includes: determining whether the first target data is cross-memory page data, if it is cross-memory page data, the constructed load instruction includes a load instruction to read data from an aligned memory address and a load instruction to read data from the next page, otherwise the load instruction is a load instruction to read data from an aligned memory address.

6. The instruction conversion memory alignment optimization method according to claim 4, characterized in that: When the first temporary memory is a memory space allocated in the stack space of the ARM system, the second ARM instruction combination includes: calculating the starting address and the ending address of the original memory space according to the unaligned memory address, the aligned memory address and the first target data, the starting address is the aligned memory address, and the ending address is the sum of the aligned memory address and the data length of the first target data; when the first target data is non-cross-memory page data, a stack loading instruction is used to load the data read from the first temporary memory into the original memory space composed of the starting address and the ending address; when the first target data is cross-memory page data, a stack loading instruction is used to load the data read from the first temporary memory into the original memory space composed of the starting address to the ending position of the page where it is located and the starting position of the next page to the ending address.

7. The instruction conversion memory alignment optimization method according to claim 4, characterized in that: When the first temporary memory is a memory space allocated in the heap space of the ARM system, the second ARM instruction combination includes: calculating the starting address and the ending address of the original memory space according to the unaligned memory address and the data length of the data required to be read from the unaligned memory address; when the first target data is non-cross-memory page data, using a heap loading instruction to load the data read from the first temporary memory into the original memory space composed of the starting address and the ending address; when the first target data is cross-memory page data, using a heap loading instruction to load the data read from the first temporary memory into the original memory space composed of the starting address to the ending position of the page and the starting position of the next page to the ending address.

8. The instruction conversion memory alignment optimization method according to claim 4, characterized in that: When the first temporary memory is a memory space allocated in the heap space of the ARM system, the first temporary memory is released by calling a heap release function to complete the release.

9. The instruction conversion memory alignment optimization method according to claim 1, characterized in that: The first code set is formed by codes related to parameters in the first parameter set within a set range, and the set range is an instruction set of a set number of instructions backward from the function call instruction.

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