A prefetch-based processor-accelerated instruction fetching method and apparatus

Abstract

This invention discloses a prefetch-based processor accelerated instruction fetching method and apparatus, relating to the field of computer processor technology. The method includes: fetching instructions; pre-decoding the instructions to obtain a first category of instructions; classifying a portion of the instructions in the first category according to execution type to obtain a second category of instructions; and performing jumps between the instructions in the first and second categories according to a preset processing method to update the target address of the instructions, thereby realizing the instruction fetching process. This invention can quickly fetch the required instructions, enabling high-performance, low-power, small-area, and simple-structure processing devices, thus giving the processor good engineering practicality.

Description

Technical Field

[0001] This invention belongs to the field of computer processor technology, specifically relating to a prefetch-based processor accelerated instruction fetching method and apparatus. Background Technology

[0002] In the operation of modern computer processors, pipelining is an essential technique. Instruction pipelining divides the instruction execution process into multiple stages through parallelization, such as fetch, decode, and execute, thereby improving processor throughput. Instruction fetch is located at the beginning of the modern processor pipeline, and its main function is to fetch instructions from the instruction cache to the instruction register of the fetch stage.

[0003] In the operation of modern computer processors, the instruction fetch stage has a crucial impact on the overall processor performance. Traditional processor instruction fetch methods, when faced with branch jump instructions, often need to wait for the conditional judgment results of the execution stage to determine the address of the next instruction. This leads to fetch bouncy, reducing fetch efficiency and consequently affecting the overall processor speed. Therefore, how to effectively reduce fetch bouncy and improve fetch efficiency has become a problem that needs to be solved in processor design. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a prefetch-based processor accelerated instruction fetch method and apparatus. The technical problem to be solved by this invention is achieved through the following technical solution:

[0005] In a first aspect, the present invention provides a processor-accelerated instruction fetching method based on prefetching, comprising:

[0006] Get instructions;

[0007] The instructions are pre-decoded to obtain the first category of instructions; according to the execution type, some instructions in the first category are classified to obtain the second category of instructions; according to the preset processing method, jumps are performed on the instructions in the first category and the instructions in the second category to update the target address of the instructions, thus realizing the instruction fetching process.

[0008] In a second aspect, the present invention also provides a processor-accelerated instruction fetching device based on prefetching, comprising:

[0009] The instruction fetch unit is used to fetch instructions. The instruction fetch unit includes a pre-decode module, which pre-decodes the instructions to obtain a first category of instructions; classifies some of the instructions in the first category according to the execution type to obtain a second category of instructions; and performs jumps on the instructions in the first category and the instructions in the second category according to a preset processing method to update the target address of the instructions, thereby realizing the instruction fetching process.

[0010] The beneficial effects of this invention are:

[0011] This invention provides a prefetch-based processor instruction fetching acceleration method and apparatus, which pre-decodes instructions to obtain a first category of instructions; classifies some instructions in the first category according to execution type to obtain a second category of instructions; and performs jumps between instructions in the first and second categories according to a preset processing method to update the target address of the instructions, thereby realizing the instruction fetching process. It can quickly obtain the required instructions, realize a high-performance, low-power, small-area, and simple-structure processing device, and make the processor have good engineering practicality.

[0012] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0013] Figure 1 This is a flowchart of a processor-accelerated instruction fetching method based on prefetching provided in an embodiment of the present invention;

[0014] Figure 2 This is a schematic diagram of an instruction fetching method provided in an embodiment of the present invention;

[0015] Figure 3 This is a schematic diagram of a prefetch-based processor accelerated instruction fetching device provided in an embodiment of the present invention;

[0016] Figure 4 This is a schematic diagram of the branch jump instruction type and instruction format provided in an embodiment of the present invention;

[0017] Figure 5 This is a schematic diagram of pre-decoding and branch prediction provided in an embodiment of the present invention;

[0018] Figure 6 This is a schematic diagram of a microarchitecture module for the instruction fetching method provided in an embodiment of the present invention. Detailed Implementation

[0019] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0020] To overcome the shortcomings of traditional processors, such as slow instruction fetch speed and waiting time due to instruction fetch idling during branch jump instruction judgment, the instruction fetch method proposed in this invention has higher instruction fetch efficiency and lower power consumption.

[0021] Please see Figure 1 , Figure 1 This is a flowchart of a prefetch-based processor accelerated instruction fetch method provided by an embodiment of the present invention. The prefetch-based processor accelerated instruction fetch method provided by the present invention includes:

[0022] S101, Obtain the instruction.

[0023] Specifically, in this embodiment, please refer to Figure 2 , Figure 2 This is a schematic diagram of an instruction fetching method provided in an embodiment of the present invention, which includes obtaining instructions, including:

[0024] Fetch instructions from instruction-closely coupled memory;

[0025] Alternatively, instructions can be fetched from external memory via a bus.

[0026] In this embodiment, instructions are fetched from two paths: one is from the on-chip Instruction Tightly Coupled Memory (ITCM), and the other is from external memory via the system bus. In this embodiment, the vast majority of instruction fetching occurs in the ITCM. The proposed processor is a small-area processor designed for embedded, ultra-low-power scenarios, and does not use an instruction cache, primarily relying on the ITCM for storage to meet real-time requirements. However, for certain special cases where instructions need to be read from external memory (for example, the bootloader after system power-on may need to be read from external flash memory), no acceleration optimization design is implemented for these few use cases.

[0027] In this embodiment, the instruction tightly coupled memory uses a customer-configurable, small-capacity SRAM to store instructions. It is physically close to the processor core and dedicated to the processor core, which can achieve lower access latency and speed up the instruction fetch process.

[0028] S102. Pre-decode the instructions to obtain the first category of instructions; classify some of the instructions in the first category according to the execution type to obtain the second category of instructions; according to the preset processing method, jump to the instructions in the first category and the instructions in the second category to update the target address of the instructions and realize the instruction fetching process.

[0029] Specifically, in this embodiment, please refer to Figure 3 , Figure 3 This is a schematic diagram of a prefetch-based processor-accelerated instruction fetching device provided in an embodiment of the present invention. The scheme in this embodiment is designed based on the RV32IM subset of the RISC-V instruction set architecture. This embodiment adds a pre-decoding module to the instruction fetch unit. To facilitate maintenance and reduce the logic synthesis of other unrelated circuits, the pre-decoding module pre-decodes the fetched instruction to obtain partial instruction information. The pre-decoding module instantiates the complete decoder module of the decoding unit, sets its unrelated input signals to zero, leaves the output signals floating, and optimizes the unrelated circuits through logic synthesis.

[0030] In this embodiment, the first category includes ordinary instructions and branch jump instructions. Please refer to [link to documentation]. Figure 4 , Figure 4 This is a schematic diagram of the branch jump instruction types and instruction formats provided in the embodiments of the present invention. The second category includes conditional direct branch jump instructions, unconditional direct branch jump instructions, and unconditional indirect branch jump instructions.

[0031] In this embodiment, the preset processing methods include processing methods for ordinary instructions, processing methods for conditional direct branch jump instructions, processing methods for unconditional direct branch jump instructions, and processing methods for unconditional indirect branch jump instructions.

[0032] It should be noted that instruction decoding can be performed on the opcode segment according to the instruction encoding structure characteristics of the RISC-V instruction set architecture. In this embodiment, instruction decoding can determine whether the current instruction is a normal instruction or a branch jump instruction. Branch jump instructions are then classified according to their execution type, resulting in a conditional direct branch jump instruction (beq, bne, blt, bge, btu, bgeu instructions), an unconditional direct branch jump instruction (jal instruction), or an unconditional indirect branch jump instruction (jalr instruction). Different types of instructions are processed differently. For specific operations, please refer to the following content. Figure 5 , Figure 5 This is a schematic diagram of pre-decoding and branch prediction provided in an embodiment of the present invention.

[0033] Furthermore, the processing method for ordinary instructions includes: fetching the target address of the next instruction according to a preset fetch order, adding a threshold, and using this as the target address of the updated instruction for jump; wherein, the threshold is the number of instruction bits in the instruction set pre-implemented by the processor divided by 8; it should be noted that, since the instruction is 32-bit, for ordinary instructions, the target address of the updated instruction is directly generated by the target address generation module, that is, for ordinary instructions, the target address of the next instruction is fetched according to the preset fetch order, adding 4, and using this as the target address of the updated instruction;

[0034] The method for handling conditional direct branch jump instructions includes: performing branch prediction on the conditional direct branch jump instruction; if the prediction is that the jump will occur according to the first jump order, the target address of the current instruction plus an offset represented by an immediate value is used as the updated target address of the instruction for the jump; if the prediction is that the jump will occur according to the second jump order, no jump is performed; wherein, the first jump order includes the target address to which the instruction needs to jump being smaller than the current target address of the instruction, and the first jump order is the reverse of the second jump order; optionally, the first jump order is a backward jump, and the second jump order is a backward jump; it should be noted that this method is based on the fact that in actual assembly programs, backward jumps are more common than forward jumps, such as the assembly instructions generated by common for loops often using backward jump branch instructions. Using this method increases the prediction accuracy and speeds up the instruction fetching process;

[0035] The handling methods for unconditional direct branch jump instructions include: predicting that an unconditional direct branch jump instruction will definitely jump, without needing to predict the jump direction, adding an immediate offset to the current target address of the instruction, and using this as the target address of the updated instruction for the jump; it should be noted that the content executed by all types of jump instructions is the source target address (PC value) + offset, but the jalr instruction is different. Its base address is not the source PC value, but the operand indexed from the first source operand (rs1). The offset of each instruction is composed of an immediate value, as specified in the RISC-V manual. For example, the beq instruction executes if(x[rs1]==x[rs2]), pc+=sext(offset). Specifically, when the value of register x[rs1] is exactly equal to the value of x[rs2], the program counter pc is added to the offset after sign extension (sext), and this offset is the immediate value.

[0036] The processing method for unconditional indirect branch jump instructions includes: predicting that the unconditional indirect branch jump instruction is a certain jump, without the need to predict the jump direction; based on the base address read from the general-purpose register set, which may cause data conflicts with the instructions in the execution phase; the base address comes from the operand index of the first source operand; the processor uses different methods to optimize it according to different index values ​​of the first source operand to obtain the target address of the updated instruction for jump.

[0037] Furthermore, for unconditional indirect branch jump instructions, a certain jump is predicted. Based on the base address read from the general-purpose register set, the updated target address of the instruction is obtained, including:

[0038] If the index of the first source operand is the value of the first register, then... According to the RISC-V architecture definition, the value of the register is the constant 0, without needing to read the value from the register set. The offset represented by 0 plus an immediate value is used as the target address of the updated instruction for jumping.

[0039] If the index value of the first source operand is the value of the second bit register, then... The register values, according to the RISC-V instruction set architecture assembly language rules, Registers are used for function return jump instructions, therefore... The register is directly retrieved from the general-purpose register group in the decoding stage, without occupying the general-purpose register group read port. The value read from the second register is added to the offset represented by the immediate value, which is used as the target address of the updated instruction for jump.

[0040] If the index value of the first source operand is the first... The value of the bit register is not accelerated; it is necessary to check for data conflicts. If a conflict is found, it is read from the register group read port during the execution phase after resolving the data conflict. This value will then be retrieved from the bit register. The value read from the bit register plus the offset represented by the immediate value is used as the target address of the updated instruction for jump, meaning it is not accelerated; where, Indicates register, This refers to registers other than the first and second bits. For example, , ... ... There are a total of 32 registers, which are the names assigned to each register in the RISC-V instruction set architecture manual. It represents any number from 2 to 31, excluding 0 and 1.

[0041] Understandably, the data conflict mentioned above refers to two pieces of data: one is the data that jalr needs to read from register xn, which conflicts with the data in subsequent instructions that were not written back.

[0042] In summary, the present invention provides a prefetch-based processor instruction fetching acceleration method that fetches instructions, pre-decodes the instructions to obtain a first category of instructions, classifies some instructions in the first category according to the execution type to obtain a second category of instructions, and performs jumps between instructions in the first and second categories according to a preset processing method to update the target address of the instructions, thereby realizing the instruction fetching process. This method can quickly fetch the required instructions, realize a high-performance, low-power, small-area, and simple-structure processing device, and make the processor have good engineering practicality.

[0043] Based on the same inventive concept, please continue to see Figure 3The present invention also provides a prefetch-based processor accelerated instruction fetch device for implementing the prefetch-based processor accelerated instruction fetch method provided in the above embodiments of the present invention. Embodiments of the method are described above and will not be repeated here. The device includes:

[0044] The instruction fetch unit is used to fetch instructions. The instruction fetch unit includes a pre-decode module, which pre-decodes the instructions to obtain a first category of instructions; classifies some of the instructions in the first category according to the execution type to obtain a second category of instructions; and performs jumps on the instructions in the first category and the instructions in the second category according to a preset processing method to update the target address of the instructions, thereby realizing the instruction fetching process.

[0045] Specifically, in this embodiment, the instruction fetch unit (IFU) is the module in the CPU responsible for fetching instructions. The instruction fetch unit includes a pre-decode module. The pre-decode module instantiates the complete decoder module of the decoding unit, sets its irrelevant input signals to zero, leaves the output signals floating, and optimizes the irrelevant circuits through logic synthesis.

[0046] In this embodiment, a pre-decoding module is added to the processor's instruction fetch stage. This module pre-decodes the fetched instructions, using the RV32IM subset rules of the RISC-V instruction set architecture to perform partial decoding functions. These functions include determining whether the instruction is a normal instruction or a branch jump instruction, and if so, whether the branch jump instruction is a conditional direct jump instruction, a conditional indirect jump instruction, an unconditional direct jump instruction, or an unconditional indirect jump instruction. Further instruction fetching processing is then performed based on the different instruction types, thus achieving a fast instruction fetch process.

[0047] In an optional embodiment of the present invention, please continue to refer to... Figure 3 The instruction fetch unit also includes a branch prediction module, which is used to predict branch jumps for conditional direct branch jump instructions, predict that unconditional direct branch jump instructions will definitely jump, and predict that unconditional indirect branch jump instructions will definitely jump.

[0048] Specifically, in this embodiment, considering that branch instructions are an essential type of instruction in every instruction set architecture, and that branch instructions can lead to control hazards, potentially causing pipeline flushing when the processor executes them, and that branch instructions typically account for about 1 / 4 of the program code, this embodiment introduces a branch prediction module to perform special processing on branch instructions, thereby improving processor performance.

[0049] This embodiment uses the RISC-V instruction set. In the RISC-V instruction set, branch instructions are mainly divided into two categories: conditional branch instructions and unconditional branch instructions. For loop segments, in processors with long pipelines, the predictor typically needs to learn multiple times to accurately predict the loop segment, making precise prediction impossible. In this embodiment, a branch prediction unit is added to the instruction fetch stage to predict the branch jump direction and preload possible instructions to reduce waiting time. The branch prediction unit predicts whether the current branch instruction will jump and the target address based on historical data and the behavior patterns of branch instructions. Thus, the processor can continue loading the predicted instructions without pausing when encountering a branch instruction, thereby improving the execution efficiency of the instruction pipeline.

[0050] In an optional embodiment of the present invention, please continue to refer to... Figure 3 The branch prediction module is a static branch prediction module.

[0051] Specifically, considering that in a typical instruction fetch module, the pipeline cannot determine whether the condition of an instruction is met during the instruction fetch stage, and therefore cannot decide whether to jump to the next target address, the final jump result can only be resolved after the execution stage is completed. If the processor's instruction fetch is paused until the execution stage is finished, it will cause a large amount of pipeline idling, thus affecting performance. In this embodiment, a static branch prediction method is used in the instruction fetch stage to improve processor performance. Since backward jumps are more common than forward jumps in actual assembly programs, the branch prediction module (lite-bpu) in this embodiment uses a static branch prediction method, predicting backward jumps as jumps and forward jumps as no jumps. For predicting the jump address, this embodiment uses Return Address Stack (RAS), which refers to using a hardware stack with limited capacity to store the return address of a function call. In the RISC-V architecture, indirect jump / branch instructions can be used for function calls and returns. Function calls and returns often occur in pairs within a program. Therefore, when a function is called, the current PC value is incremented by 4, pushing the PC value of the next instruction to be executed sequentially into the RAS. When the function returns, the value in the RAS is popped, allowing for rapid prediction of the target address for the branch jump instruction returned by the function. The instruction fetching device described above in this embodiment is suitable for embedded products that do not require high clock speeds but require low power consumption and small area.

[0052] In an optional embodiment of the present invention, please continue to refer to... Figure 3 It also includes a target address generator module, which is used to generate the target addresses of updated instructions.

[0053] In an optional embodiment of the present invention, it is considered that in existing storage architectures, there is a bottleneck in the data transfer speed between the processor and the storage device. While main memory (such as DRAM) has a large capacity, its access speed is relatively slow. Although cache (such as traditional cache) can alleviate the speed difference to some extent, it still has some problems. For example, the storage content and management method of cache are based on hardware automatic control, and its data replacement strategy and hit rate have certain statistical characteristics. For some application scenarios with extremely high requirements for real-time performance and determinism, this uncertainty may lead to performance fluctuations.

[0054] Meanwhile, computer systems handling complex tasks, such as real-time control, encryption / decryption, and multimedia processing, require more precise and efficient storage solutions. These applications often demand fast and predictable access to specific code or data. In real-time control systems, interrupt handlers must execute at precise times; any delay or uncertainty in storage access can lead to system failure. For encryption algorithms, not only high performance is required, but also security vulnerabilities arising from the predictability of storage systems (such as cache analysis attacks potentially exploiting cache behavior to obtain encrypted information).

[0055] The instruction fetch unit's cache is a tightly coupled memory (TCM), comprising instruction tightly coupled memory (ITCM) and data tightly coupled memory (DTCM). TCM, as a special type of high-speed cache, addresses the aforementioned technical problems. TCM is tightly coupled to the processor, providing a high-speed storage mechanism between the processor registers and main memory. By allowing program code to precisely control which functions or code are stored in the TCM (located in specific areas of RAM), TCM achieves precise management of stored content. Unlike traditional caches, TCM is not easily replaced from main memory; its performance is preset by the user according to specific application requirements. This provides stable and predictable memory access for applications with high performance and deterministic requirements, meeting the special requirements of modern computer systems for storage systems in complex application scenarios.

[0056] This embodiment uses a TCM tightly coupled memory architecture, which is divided into instruction tightly coupled memory and data tightly coupled memory. SRAM is used as the instruction tightly coupled memory, and its physical distance from the processor core is set close to the processor core and dedicated to the processor core, which can achieve lower access latency.

[0057] In this embodiment, TCM has significant application value and is indispensable in various specific code scenarios. For foreseeable real-time processing situations, such as interrupt handling, TCM can ensure the timeliness and accuracy of processing, meeting real-time requirements. In scenarios with predictable time, such as during the execution of encryption algorithms, TCM can guarantee the predictability of algorithm execution in time. In situations where cache analysis needs to be avoided, especially for encryption algorithms, TCM can effectively prevent security risks that may be caused by cache characteristics. In addition, for code that only requires high performance, such as code related to encoding and decoding functions, TCM can provide a stable and high-performance operating environment, ensuring efficient code execution, thereby improving the performance and security of the entire system in these critical application scenarios.

[0058] In an optional embodiment of the present invention, please refer to Figure 6 , Figure 6 This is a schematic diagram of a microarchitecture module for an instruction fetching method provided in an embodiment of the present invention. The bus includes an AHB bus slave and an AHB bus master, used to fetch instructions from memory.

[0059] In an optional embodiment of the present invention, please continue to refer to... Figure 3 and Figure 6 The transfer registers include the PC register and the IR register, which are used to register and transfer instructions after fetching.

[0060] In an optional embodiment of the present invention, please continue to refer to... Figure 6 The decoding unit includes a general-purpose register group module, a decoder module, and a lag instruction tracer FIFO module. The decoding unit is used to decode the fetched instructions.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0063] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A processor-accelerated instruction fetching method based on prefetching, characterized in that, include: Fetch instructions from instruction-closely coupled memory; The instructions are pre-decoded to obtain a first category of instructions, which includes ordinary instructions and branch jump instructions. Based on the execution type, some instructions in the first category are further classified to obtain a second category of instructions, which includes conditional direct branch jump instructions, unconditional direct branch jump instructions, and unconditional indirect branch jump instructions. According to a preset processing method, jumps are performed on the instructions in the first and second categories to update the target address of the instructions, thus implementing the instruction fetching process. The preset processing method includes processing methods for ordinary instructions, processing methods for conditional direct branch jump instructions, processing methods for unconditional direct branch jump instructions, and processing methods for unconditional indirect branch jump instructions. The processing method for ordinary instructions includes: fetching the target address of the next instruction according to a preset fetch order, adding a threshold as the updated target address of the instruction, and then performing the jump. The threshold is the number of instruction bits in the processor's pre-implemented instruction set divided by 8. The method for processing conditional direct branch jump instructions includes: performing branch prediction on the conditional direct branch jump instruction; if the prediction is to jump according to a first jump order, adding an offset represented by an immediate value to the target address of the current instruction to obtain the updated target address of the instruction, and then performing the jump; if the prediction is to jump according to a second jump order, no jump is performed; wherein, the first jump order includes the target address to which the instruction needs to jump being smaller than the current target address of the instruction, and the first jump order is the reverse of the second jump order; The method for processing unconditional direct branch jump instructions includes: predicting that an unconditional direct branch jump instruction will definitely jump, adding an offset represented by an immediate value to the current target address of the instruction, and using this as the updated target address of the instruction to perform the jump; The method for processing unconditional indirect branch jump instructions includes: predicting that the unconditional indirect branch jump instruction is a certain jump, obtaining the updated target address of the instruction based on the base address read from the general-purpose register group, wherein the base address comes from the operand of the first source operand index, and performing the jump.

2. The processor-accelerated instruction fetching method based on prefetching according to claim 1, characterized in that, The prediction of an unconditional indirect branch jump instruction as a certain jump, and the acquisition of the updated target address of the instruction based on the base address read from the general-purpose register set, includes: If the index value of the first source operand is the value of the first register, the offset represented by the immediate value is used as the target address of the updated instruction for the jump; If the index value of the first source operand is the value of the second register, the value read from the second register plus the offset represented by the immediate value is used as the target address of the updated instruction for jump. If the index value of the first source operand is the first... The value of the bit register is used to determine if a data conflict exists. If a conflict is found, the data will be read from the bit register. The value read from the bit register plus the offset represented by the immediate value is used as the target address of the updated instruction for jump; where, Indicates register, .

3. A processor-accelerated instruction fetching device based on prefetching, characterized in that, include: An instruction fetch unit is used to fetch instructions from instruction tightly coupled memory. The instruction fetch unit includes a pre-decoding module for pre-decoding the instructions to obtain a first category of instructions, which includes ordinary instructions and branch jump instructions. Based on the execution type, some instructions in the first category are further classified to obtain a second category of instructions, which includes conditional direct branch jump instructions, unconditional direct branch jump instructions, and unconditional indirect branch jump instructions. According to a preset processing method, jumps are performed on the instructions in the first and second categories to update the target address of the instructions, thus implementing the instruction fetch process. The preset processing method includes processing methods for ordinary instructions, processing methods for conditional direct branch jump instructions, processing methods for unconditional direct branch jump instructions, and processing methods for unconditional indirect branch jump instructions. The processing method for ordinary instructions includes: fetching the target address of the next instruction according to a preset fetch order, adding a threshold as the updated target address of the instruction, and then performing a jump. The threshold is the number of instruction bits in the processor's pre-implemented instruction set divided by 8. The method for processing conditional direct branch jump instructions includes: performing branch prediction on the conditional direct branch jump instruction; if the prediction is to jump according to a first jump order, adding an offset represented by an immediate value to the target address of the current instruction to obtain the updated target address of the instruction, and then performing the jump; if the prediction is to jump according to a second jump order, no jump is performed; wherein, the first jump order includes the target address to which the instruction needs to jump being smaller than the current target address of the instruction, and the first jump order is the reverse of the second jump order; The method for processing unconditional direct branch jump instructions includes: predicting that an unconditional direct branch jump instruction will definitely jump, adding an offset represented by an immediate value to the current target address of the instruction, and using this as the updated target address of the instruction to perform the jump; The method for processing unconditional indirect branch jump instructions includes: predicting that the unconditional indirect branch jump instruction is a certain jump, obtaining the updated target address of the instruction based on the base address read from the general-purpose register group, wherein the base address comes from the operand of the first source operand index, and performing the jump.

4. The processor-accelerated instruction fetching device based on prefetching according to claim 3, characterized in that, The instruction fetching unit also includes a branch prediction module, which is used to predict branch jumps for conditional direct branch jump instructions, predict that unconditional direct branch jump instructions will definitely jump, and predict that unconditional indirect branch jump instructions will definitely jump.

5. The processor-accelerated instruction fetching device based on prefetching according to claim 4, characterized in that, The branch prediction module is a static branch prediction module.

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