SPI (Serial Peripheral Interface) and I2C multiplexing digital isolator

Abstract

The invention discloses an SPI and I2C multiplexing digital isolator, which comprises a switching module and an isolation chip, the isolation chip at least comprises a first mode and a second mode, in the first mode, a fourth channel and a fifth channel are respectively used for isolating an SPI interface MOSI signal and an SPI interface MISO signal, and in the second mode, the fourth channel and the fifth channel are respectively used for isolating the SPI interface MOSI signal and the SPI interface MISO signal. The fourth channel and the fifth channel are used for bidirectional isolation of SDA signals of the I2C interface, and the switching module is connected with the fourth channel and the fifth channel and used for switching the fourth channel and the fifth channel between the first mode and the second mode. The isolation chip is configured to have the two working modes, the switching mode capable of switching the two working modes is set, the isolation chip works in the two working modes according to needs, in the first mode, isolation of the SPI interface can be achieved, in the second mode, isolation of the I2C can be achieved, and the isolation efficiency of the SPI interface can be improved. Therefore, a multiplexing function which can be realized by a plurality of traditional isolators can be realized by one isolation chip.

Description

Technical Field

[0001] The invention relates to a digital isolator, in particular to a digital isolator capable of realizing SPI and I2C multiplexing. Background Art

[0002] In embedded systems, SPI and I2C are two widely used serial peripheral interfaces, which play a big role in data transmission between devices. Both SPI and I2C are simple and efficient, and are used in consumer electronics products for communication between the host computer and various peripherals (such as touch chips, cameras, power supplies, flash chips, etc.). SPI, with its advantages of high-speed transmission and full-duplex communication, is particularly suitable for application scenarios that require fast data exchange, such as high-speed application scenarios such as image data transmission. I2C has great flexibility through a flexible master-slave address mechanism, and can connect multiple devices on the same bus, which is suitable for more complex system designs. When designing and implementing these communication protocols, it is necessary to pay attention to their stability to ensure the efficiency and reliability of the system.

[0003] Digital isolators play an important role in SPI and I2C communications, mainly in terms of electrical isolation. Digital isolators can effectively isolate signals between different voltage domains. This is crucial in many applications, especially in environments where the host computer and various peripherals communicate in different voltage domains. Isolation can enable the microcontroller or host computer to obtain more stable communication data that is not affected by different voltage domains.

[0004] The most widely used digital isolator is the general-purpose digital isolator. For the SPI bus interface, the general-purpose digital isolator can be used directly for circuit design, while the I2C bus interface requires a dedicated I2C digital isolator, or the general-purpose digital isolator can be used with peripheral circuits to complete the I2C digital isolation. In traditional applications, in order to meet the requirements of SPI and I2C communication, two or even more digital isolators are often required. In addition, in the scenario where SPI and I2C are flexibly used, different isolation circuits need to be designed for different communications, which causes great trouble in switching. Summary of the invention

[0005] In view of the above problems, the present invention provides an isolated communication capable of implementing SPI and I2C multiplexing through a single digital isolator.

[0006] The present invention provides a digital isolator for SPI and I2C multiplexing, comprising: a switching module and an isolation chip, wherein the isolation chip comprises at least a first mode and a second mode, wherein in the first mode, the fourth channel and the fifth channel are respectively used for isolating an SPI interface MOSI signal and an SPI interface MISO signal, and in the second mode, the fourth channel and the fifth channel are used for bidirectional isolation of an I2C interface SDA signal, and the switching module is connected to the fourth channel and the fifth channel, and is used for switching the fourth channel and the fifth channel between the first mode and the second mode.

[0007] In some embodiments, the switching module is a key switch, and the key state includes a first state and a second state. When the key switch is in the first state, the isolation chip is in a first mode, and when the key switch is in the second state, the isolation chip switches from the first mode to the second mode.

[0008] In some embodiments, the input end of the fourth channel and the output end of the fifth channel are on one side of the isolation chip, and the output end of the fourth channel and the input end of the fifth channel are on the other side of the isolation chip. The input end of the fourth channel is connected to the first MOS transistor q3, and the output end of the fifth channel is connected to the second MOS transistor q2. The electrode of the first MOS transistor q3 is connected to the gate of the second MOS transistor q2 and is connected to a key switch. The output end of the fourth channel is connected to the third MOS transistor q4, and the input end of the fifth channel is connected to the fourth MOS transistor q5. The electrode of the third MOS transistor q4 is connected to the gate of the fourth MOS transistor q5 and is connected to the key switch. When the key switch is in the first state, the first MOS transistor q3, the second MOS transistor q2, the third MOS transistor q4 and the fourth MOS transistor q5 are in the cut-off state. When the key switch is in the second state, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are in the on state.

[0009] In some embodiments, a fifth MOS transistor Q1 is further included. The fifth MOS transistor Q1 is connected to the drain of the first MOS transistor q3 and to the base of the second MOS transistor q2. The gate of the fifth MOS transistor Q1 and the I2C interface MASTER_SDA signal are connected to the analog voltage VDDA. The third MOS transistor q4, the fourth MOS transistor q5 and the I2C interface SLAVE_SDA signal are connected to the analog voltage VDDB. The first MOS transistor q3 is connected to the SPI interface MOSI signal. The second MOS transistor q2 is connected to the I2C interface MASTER_SDA signal and the SPI interface MISO signal. The third MOS transistor q4 is connected to the SPI interface MOSI signal. The fourth MOS transistor q5 is connected to the I2C interface SLAVE_SDA signal and the SPI interface MISO signal.

[0010] In some embodiments, a resistor and a first diode D3 are connected between the drain of the fifth MOS transistor Q1 and the drain of the second MOS transistor Q2 , and a second diode D4 is connected between the third MOS transistor Q4 and the fourth MOS transistor Q5 .

[0011] In some embodiments, the isolation chip also includes a third channel, and the third channel is a multiplexing interface of the SPI interface CSN signal and the I2C interface SCL signal. The I2C interface MASTER_SCL signal connected to the input end of the third channel is connected to the analog voltage VDDA, and the I2C interface SLAVE_SCL signal connected to the output end of the third channel is connected to the analog voltage VDDB.

[0012] In some embodiments, the isolation chip also includes a first channel and a sixth channel, the input end of the first channel and the output end of the sixth channel are located on one side of the isolation chip, the output end of the first channel and the input end of the sixth channel are located on the other side of the isolation chip, and the first channel and the second channel are used to isolate other functions except the SPI interface and the I2C interface.

[0013] In some embodiments, the first channel is used for reset RST, and the sixth channel is used for interrupt INT.

[0014] In some embodiments, the isolation chip further includes a second channel, and the second channel is used for the SCK signal of the SPI interface.

[0015] In some embodiments, the isolation chip is a 6-channel 4-input 2-output digital isolator.

[0016] In the technical solution of the embodiment of the present invention, the isolation chip is configured with two working modes, and a switching mode that can switch between the two working modes is set, so that the isolation chip works in the two working modes as needed, wherein in the first mode, the isolation of the SPI interface can be achieved, and in the second mode, the isolation of the I2C can be achieved, thereby achieving a multiplexing function that can only be achieved by multiple isolators in the traditional way with one isolation chip.

[0017] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference numerals are used throughout the drawings to represent the same components. In the drawings:

[0019] Figure 1 The figure is a schematic diagram of the structure of a digital isolator for multiplexing SPI and I2C in some embodiments of the present invention. DETAILED DESCRIPTION

[0020] The following embodiments of the technical solution of the present invention are described in detail in conjunction with the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and are therefore only used as examples, and cannot be used to limit the protection scope of the present invention.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by technicians in the technical field to which the present invention belongs; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present invention; the terms "including" and "having" in the specification and claims of the present invention and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions.

[0022] In the description of the embodiments of the present invention, the technical terms "first", "second", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present invention, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0023] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive of other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments. In the description of the embodiments of the present invention, the term "multiple" refers to more than two (including two)

[0024] This application provides a method for solving the above problems. Figure 1 As shown, a digital isolator for SPI and I2C multiplexing is provided, including: a switching module 10 and an isolation chip 20, wherein the isolation chip 20 includes at least a first mode and a second mode. In the first mode, the fourth channel (such as Figure 1 IN4 / OUT4) and the fifth channel (as Figure 1 IN5 / OUT5 in the SPI interface are used to isolate the SPI interface MOSI signal and the SPI interface MISO signal respectively. In the second mode, the fourth channel and the fifth channel are used for bidirectional isolation of the I2C interface SDA signal, and the switching module 10 is connected to the fourth channel and the fifth channel, and is used to switch the fourth channel and the fifth channel between the first mode and the second mode.

[0025] Specifically, the input terminal IN4 of the fourth channel and the output terminal OUT5 of the fifth channel are on one side of the isolation chip 20, such as Figure 1 The output terminal OUT4 of the fourth channel and the input terminal IN5 of the fifth channel are on the other side of the isolation chip 20, as shown in FIG. Figure 1 On the right side of the isolation chip, the input IN4 and output OUT4 of the fourth channel can be connected to the SPI interface MOSI signal, the input N5 and output OUT5 of the fifth channel can be connected to the SPI interface MISO, and the input IN4 and output OUT4 of the fourth channel as well as the input IN5 and output OUT5 of the fifth channel can be connected to the I2C interface SDA signal.

[0026] In some embodiments, the switching module 10 is a key switch, and the key state includes a first state and a second state. When the key switch is in the first state, the isolation chip 20 is in the first mode, and when the key switch is in the second state, the isolation chip 20 switches from the first mode to the second mode. Through the selection function of the switching module 10 for the first mode and the second mode of the isolation chip, the fourth channel and the fifth channel can isolate the SPI interface and the I2C interface as needed or in time-sharing.

[0027] In some embodiments, four MOS tubes are arranged between the key switch and the fourth channel and the second channel, and the mode switching of the fourth channel and the fifth channel is realized by the cooperation between the key switch and the MOS tubes. Specifically, the input end IN4 of the fourth channel is connected to the first MOS tube Q3, the output end OUT5 of the fifth channel is connected to the second MOS tube Q2, the electrode of the first MOS tube Q3 is connected to the gate of the second MOS tube Q2 and connected to the key switch, the input end OUT4 of the fourth channel is connected to the third MOS tube Q4, the input end IN5 of the fifth channel is connected to the fourth MOS tube Q5, the electrode of the third MOS tube Q4 is connected to the gate of the fourth MOS tube Q5 and connected to the key switch.

[0028] When the key switch is in the first state, the first MOS transistor Q3, the second MOS transistor Q2, the third MOS transistor Q4 and the fourth MOS transistor Q5 are in the cut-off state. When the key switch is in the second state, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are in the on state. Figure 1 By default, the middle button switch SW1 will pull down the bases of the four MOS tubes, which will cut off the MOS tubes. At this time, it is in the SPI isolation state. When the button is pressed, the four bases will be pulled high. At this time, the MOS tubes are in the on state and the circuit is in the I2C isolation state.

[0029] In some embodiments, a fifth MOS transistor Q1 is further included. The fifth MOS transistor Q1 is connected to the drain of the first MOS transistor Q3 and to the base of the second MOS transistor Q2. The gate of the fifth MOS transistor Q1 and the I2C interface MASTER_SDA signal are connected to the analog voltage VDDA. The third MOS transistor Q4, the fourth MOS transistor Q5 and the I2C interface SLAVE_SDA signal are connected to the analog voltage VDDB. The first MOS transistor Q3 is connected to the SPI interface MOSI signal. The second MOS transistor Q2 is connected to the I2C interface MASTER_SDA signal and the SPI interface MISO signal. The third MOS transistor Q4 is connected to the SPI interface MOSI signal. The fourth MOS transistor Q5 is connected to the I2C interface SLAVE_SDA signal and the SPI interface MISO signal.

[0030] In some embodiments, a resistor R7 and a first diode D3 are connected between the drain of the fifth MOS transistor Q1 and the drain of the second MOS transistor Q2, and a second diode D4 is connected between the third MOS transistor Q4 and the fourth MOS transistor Q5.

[0031] Regarding the principle of the I2C isolation circuit, when the left I2C_MASTER_SDA level is pulled low, the Q1 drain level is lower than the base level, Q1 is turned on, IN4 is also pulled low, OUT4 and IN4 are both low, and the right Schottky diode D4 is turned on, pulling down the right I2C_SLAVE_SDA. The I2C_MASTER_SDA low level signal is transmitted to the right I2C_SLAVE_SDA along the IN4 / OUT4 path.

[0032] When the level of I2C_SLAVE_SDA on the right is pulled low, the voltage of OUT5 will also be pulled low. After passing through Schottky diode D3 and resistor R7, this level will be recognized as a low level by the left host. At the same time, it will be higher than the base voltage of q1, making q1 cut off. q1 plays the role of a comparator here, and its base voltage is determined by resistors R4, R5 and diode D2. After q1 is cut off, the voltage of OUT4 and IN4 is the same, and D4 is cut off, which does not affect the release of I2C_SLAVE_SDA on the right to a high level. The low-level signal of I2C_SLAVE_SDA is transmitted to the right I2C_MASTER_SDA along the IN5 / OUT5 path.

[0033] In some embodiments, the isolation chip 20 further includes a third channel, and the third channel IN3 / OUT3 is a multiplexing interface of the SPI interface CSN signal and the I2C interface SCL signal, the I2C interface MASTER_SCL signal connected to the third channel input terminal IN3 is connected to the analog voltage VDDA, and the I2C interface SLAVE_SCL signal connected to the third channel output terminal is connected to the analog voltage VDDB. IN 3 / OUT3 is a multiplexing interface of SPI_CSN and I2C_SCL, because CSN is low level effective, and I2C needs to be pulled up, so the interface is pulled up through VDDA / VDDB.

[0034] In some embodiments, the isolation chip 20 further includes a first channel IN1 / OUT1 and a sixth channel 1N6 / OUT6, the input end of the first channel 1N1 / OUT1 and the output end of the sixth channel 1N6 / OUT6 are located on one side of the isolation chip 20, the output end of the first channel and the input end of the sixth channel are located on the other side of the isolation chip 20, and the first channel and the second channel are used to isolate other functions except the SPI interface and the I2C interface. That is, Figure 1As shown, the isolation chip includes 6 channels, the input ends of 4 channels and the output ends of 2 channels of the 6 channels are on one side of the isolation chip 20, and correspondingly, the output ends of 4 channels and the input ends of 2 channels are on the other side of the isolation chip 20, wherein the first channel is used to reset RST, the sixth channel is used to interrupt INT, IN2 / OUT2 is used as SPI_SCK, and plays an isolation role for the SCK signal, IN3 / OUT3 is a multiplexed interface of SPI_CSN and I2C_SCL, because CSN is valid at a low level, and I2C needs to be pulled up, so the interface is pulled up through VDDANDDB. IN14 / OUT4 and IN 5 / OUT5 are used as SPI_MOSI and SPI_MISO channels, and these two groups of channels can be combined as bidirectional isolation channels of I2C_SDA, as described above, and will not be repeated here.

[0035] The isolation circuit of the present application can freely switch SPI isolation or I2C isolation through a button, solving the problem that SPI and I2C digital isolation circuits cannot be reused and need to be switched in actual application. In addition, the circuit reduces the number of digital isolator components used, and only one isolator can be used to achieve the multiplexing function that can only be achieved by multiple isolators, saving costs. In addition, the circuit can reserve two paths for isolation of other functions (such as isolation of reset, interrupt and other functions), which better meets the actual engineering application needs.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be included in the scope of the claims and specification of the present invention. In particular, as long as there is no structural conflict, the various technical features mentioned in each embodiment can be combined in any way. The present invention is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A digital isolator for SPI and I2C multiplexing, characterized in that: include: A switching module and an isolation chip, the isolation chip includes at least a first mode and a second mode. In the first mode, the fourth channel and the fifth channel are respectively used to isolate the SPI interface MOSI signal and the SPI interface MISO signal. In the second mode, the fourth channel and the fifth channel are used for bidirectional isolation of the I2C interface SDA signal. The switching module is connected to the fourth channel and the fifth channel, and is used to switch the fourth channel and the fifth channel between the first mode and the second mode.

2. The digital isolator according to claim 1, characterized in that: The switching module is a key switch, and the key state includes a first state and a second state. When the key switch is in the first state, the isolation chip is in a first mode, and when the key switch is in the second state, the isolation chip switches from the first mode to the second mode.

3. The digital isolator according to claim 2, characterized in that: The input end of the fourth channel and the output end of the fifth channel are on one side of the isolation chip, and the output end of the fourth channel and the input end of the fifth channel are on the other side of the isolation chip. The input end of the fourth channel is connected to the first MOS transistor Q3, and the output end of the fifth channel is connected to the second MOS transistor Q2. The electrode of the first MOS transistor Q3 is connected to the gate of the second MOS transistor Q2 and is connected to a key switch. The output end of the fourth channel is connected to the third MOS transistor Q4, and the input end of the fifth channel is connected to the fourth MOS transistor Q5. The electrode of the third MOS transistor Q4 is connected to the gate of the fourth MOS transistor Q5 and is connected to the key switch. When the key switch is in the first state, the first MOS transistor Q3, the second MOS transistor Q2, the third MOS transistor Q4 and the fourth MOS transistor Q5 are in the cut-off state; when the key switch is in the second state, the first MOS transistor, the second MOS transistor, the third MOS transistor and the fourth MOS transistor are in the on state.

4. The digital isolator according to claim 3, characterized in that: The device further includes a fifth MOS transistor Q1, which is connected to the drain of the first MOS transistor Q3 and to the base of the second MOS transistor Q2. The gate of the fifth MOS transistor Q1 and the I2C interface MASTER_SDA signal are connected to the analog voltage VDDA. The third MOS transistor Q4, the fourth MOS transistor Q5 and the I2C interface SLAVE_SDA signal are connected to the analog voltage VDDB. The first MOS transistor Q3 is connected to the SPI interface MOSI signal. The second MOS transistor Q2 is connected to the I2C interface MASTER_SDA signal and the SPI interface MISO signal. The third MOS transistor Q4 is connected to the SPI interface MOSI signal. The fourth MOS transistor Q5 is connected to the I2C interface SLAVE_SDA signal and the SPI interface MISO signal.

5. The digital isolator according to claim 4, characterized in that: A resistor and a first diode D3 are connected between the drain of the fifth MOS transistor Q1 and the drain of the second MOS transistor Q2 , and a second diode D4 is connected between the third MOS transistor Q4 and the fourth MOS transistor Q5 .

6. The digital isolator according to claim 1, characterized in that: The isolation chip also includes a third channel, which is a multiplexing interface of the SPI interface CSN signal and the I2C interface SCL signal. The I2C interface MASTER_SCL signal connected to the input end of the third channel is connected to the analog voltage VDDA, and the I2C interface SLAVE_SCL signal connected to the output end of the third channel is connected to the analog voltage VDDB.

7. The digital isolator according to claim 6, characterized in that: The isolation chip also includes a first channel and a sixth channel, the input end of the first channel and the output end of the sixth channel are located on one side of the isolation chip, the output end of the first channel and the input end of the sixth channel are located on the other side of the isolation chip, and the first channel and the second channel are used to isolate other functions except the SPI interface and the I2C interface.

8. The digital isolator according to claim 7, characterized in that: The first channel is used for resetting RST, and the sixth channel is used for interrupting INT.

9. The digital isolator according to claim 7, characterized in that: The isolation chip also includes a second channel, and the second channel is used for the SCK signal of the SPI interface.

10. The digital isolator according to any one of claims 1 to 9, characterized in that: The isolation chip is a 6-channel 4-input 2-output digital isolator.

Images