A bit stream parsing and dynamic editing method for LUT resources in Xilinx FPGA

Abstract

The application discloses a bit stream analysis and dynamic editing method for LUT resources in Xilinx FPGA, comprising the following steps: S1, intercepting bit stream data, combining the structure information of FPGA, and extracting the content of all LUT resources; S2, according to the mapping relationship between the pin and the bit stream, generating a bit stream storage value search item list according to all possible bit stream arrangement modes of the truth table content of any target LUT; S3, traversing the search item list in the content extracted in S1, and locating the target LUT to calculate the target frame address and the in-frame offset involved in the configuration of the LUT according to the physical address of the target LUT; S4, calling the ICAP interface, inputting a read command sequence, reading the frame data containing the target LUT information and storing it in the BRAM; S5, calling the ICAP interface, inputting a write command sequence, and writing back the frame data in the BRAM after modification to the corresponding frame. The application solves the problems of the prior art, such as the insufficient completeness of the analysis of the arrangement mode of LUT in the bit stream, and the low efficiency and precision of the dynamic reconfiguration of the resources in the FPGA.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of FPGA dynamic reconfiguration, and particularly relates to a bitstream analysis and dynamic editing method for LUT resources in Xilinx FPGA. BACKGROUND

[0002] Thanks to its high parallelism and user programmable characteristics, FPGA has been more and more widely used in various high-performance computing implementations. With the further improvement of design complexity, how to accurately and effectively configure and manage the logic resources therein has important research significance. Xilinx provides an internal configuration access port (ICAP) for SRAM-based FPGA to perform dynamic partial reconfiguration (DPR), which can access the configuration memory and modify specific parts thereof at runtime after the interface is activated, while the remaining parts can remain normal operation without being affected by these specific modifications.

[0003] Dynamic partial reconfiguration can be used at different granularity levels, including partial bitstream, IP core, and LUT (Look up table), BRAM, and other basic logic components. Since FPGA manufacturers do not disclose the proprietary format and mapping information of the bitstream, in the case of only being able to obtain the bitstream file, to further reconfigure the LUT and other logic elements therein, it is necessary to first analyze and restore the distribution and arrangement of the LUT in the bitstream to a certain extent. In recent years, domestic and foreign researchers have designed high-performance ICAP controllers to implement the reading and writing of partial bitstreams or configuration frames for fault detection and correction in the configuration memory; some research has also implemented runtime reconfiguration at the LUT level, but the specific storage and distribution of LUT configuration bits are not described in detail, or only applicable to older FPGA devices, and there are few corresponding researches on 7 series and more advanced devices.

[0004] The existing technology has the following problems:

[0005] (1) The existing literature and tools have less research on the addressing and configuration method of LUT and its mapping rules in the bitstream, and lack an effective method to extract the storage location of LUT resources from the bitstream with high precision and speed and correspond the logic information of LUT resources to the bitstream content.

[0006] (2) Due to the inability to accurately locate the LUT resources in the bitstream, especially the LUT of a specified logic function, the existing technology mainly focuses on dynamic reconfiguration of partial bitstream, and the operation range stays in a larger dimension, and there is less research on targeted dynamic modification of more fine-grained logic resources, lacking accuracy and flexibility. SUMMARY

[0007] To address the aforementioned shortcomings of the existing technology, the present invention provides a precise and efficient method for bitstream parsing and dynamic editing of LUT resources within Xilinx FPGAs. This method rapidly extracts and searches the location and logic information of LUT resources within the bitstream, then modifies the truth table content of a specified LUT at runtime via the ICAP interface, thereby changing its functionality. Unlike bitstream-level reconfiguration, this method directly and dynamically edits the logic functions of fine-grained LUT resources within the device. This method can be performed while the device is running, improving the accuracy and flexibility of FPGA configuration and management of internal logic resources.

[0008] The technical solution adopted by the present invention to solve the technical problem is:

[0009] A method for bitstream parsing and dynamic editing of LUT resources in Xilinx FPGA includes the following steps:

[0010] S1: intercepts the bitstream data, combines it with the FPGA structure information, and extracts the contents of all LUT resources;

[0011] S2: Based on the mapping relationship between pins and bitstreams, the contents of any target LUT truth table are arranged according to all possible bitstream arrangements to generate a list of bitstream storage value items to be searched;

[0012] S3: traverse the list of items to be searched in the content extracted by S1, and after locating them, calculate the target frame address and the offset within the frame involved in configuring the LUT according to the physical address of the target LUT;

[0013] S4: Call the ICAP interface, input the read command sequence, read the frame data containing the target LUT information and store it in BRAM;

[0014] S5: Call the ICAP interface, input the write command sequence, modify the frame data in the BRAM and write it back to the corresponding frame.

[0015] Furthermore, in step S1, the extraction of the LUT content at each physical address includes the following steps:

[0016] S1-1: Create a blank project, do not instantiate any logic unit or I / O interface, and generate a blank bitstream comparison file;

[0017] S1-2: Select a reference CLB, initialize each bit value of all LUTs in it to all 1s, and generate a bitstream. The position range of the configuration bit set of the current LUT in the complete bitstream is obtained by the difference between the bits and the blank bitstream.

[0018] S1-3: Select another CLB to be tested, instantiate the LUTs in the reference CLB and the CLB to be tested to the same initial values, generate a bitstream, and calculate the offset between the LUT configuration bit set addresses corresponding to the reference CLB and the CLB to be tested;

[0019] S1-4: In combination with the underlying structure of the FPGA, the mapping information and offset information of each LUT configuration bit in the reference CLB in the bitstream are used to traverse all CLBs at physical addresses in the chip and obtain the specific storage locations of the configuration bits of all LUTs in the bitstream;

[0020] S1-5: intercept the complete bitstream that has been loaded into the device for operation, extract the contents of all LUT resources in the bitstream according to the location information of the LUT resources obtained in S1-4, and correspond them to the physical addresses in the device.

[0021] Furthermore, in step S2, the LUT truth table content corresponds to the generation of the stored value in the bitstream, including the following steps:

[0022] S2-1: IA mapping relationship extraction: Match the LUT input pins instantiated in the code with the actual LUT pins optimized by the FPGA synthesis tool, and restore the N possible pin arrangements of the N-input LUT;

[0023] S2-2: INIT-BIT mapping relationship extraction: By separately instantiating each configuration bit of different types of LUTs and comparing them with blank bit streams, the 2-bit mapping relationship of each type of N-input LUT is restored. N The INIT value of the bit truth table is the same as the 2 N The corresponding relationship between the storage order of bit BIT values;

[0024] S2-3: Generate items to be searched: Convert the original truth table content of the target LUT according to all possible pin arrangement combinations and bit value storage mapping relationships, and generate a list of items to be searched whose truth table content corresponds to the actual storage values ​​in the bit stream.

[0025] Furthermore, in step S3, the list of items to be searched obtained in S2-3 is traversed in the partial bitstream containing all LUT contents extracted in S1-5 to filter out the specific storage value and storage location of the target LUT in the bitstream, thereby determining the physical address of the target LUT.

[0026] The frame address set of all frames involved in configuring the LUT is derived from the physical coordinates of the CLB column and slice where it is located, so as to prepare for subsequent reading and writing of data at these specific frame addresses;

[0027] The offset of the 32-bit word in which the LUT configuration bit is located in the frame is derived from the ordinate of the slice in which the LUT configuration bit is located, so as to locate the specific address in the BRAM for the purpose of modifying the frame data stored therein.

[0028] The actual pin mapping relationship under the current search result is recorded, so that when the original value is covered by using the new truth table content, the mapping relationship determined can be converted, and then new frame data can be obtained through bit stream mapping.

[0029] Further, in step S4, the frame data is read by using the ICAP interface, including the following steps:

[0030] S4-1: initialization: enable csib and rdwrb control signals, set the interface direction to write mode, and perform synchronization, CRC reset and other operations on the ICAP interface;

[0031] S4-2. Input related parameters: activate RCFG, input the start frame address and the total number of frames to be read according to the target frame address set obtained in step 3;

[0032] S4-3: execute read-back: switch the interface direction to read mode, save the frame data read back through the ICAP interface in the BRAM after waiting for several cycles, and switch to write mode again to complete the desynchronization operation after receiving all the read-back data.

[0033] Further, in step S5, the modified frame data is written back by using the ICAP interface, including the following steps:

[0034] S5-1: initialization: enable csib and rdwrb control signals, set the interface direction to write mode, and perform synchronization, CRC reset and other operations on the ICAP interface;

[0035] S5-2. Input related parameters: after inputting the device IDCODE for verification, input the same write-back start frame address and the number of frames to be written back as in step 4;

[0036] S5-3. Execute modified write-back: for all frame data read back, modify the frame data according to the offset information of the target LUT configuration bit in the frame, and input the modified write-back data in sequence through the ICAP interface;

[0037] S5-4: second read-back verification: all data on the target frame address are executed again read-back process, compared with the original data read to the BRAM in S4-3, to determine whether the rewriting operation is successful.

[0038] The beneficial effects of the present application are:

[0039] (1) The application provides a method for quickly and flexibly reconfiguring a logic function of any LUT, and can realize dynamic reconfiguration of a specific content LUT by calling an ICAP interface during device operation, which has lower hardware structure complexity and faster speed compared with the way of modifying the content of a bit stream file and then reprogramming through an external interface such as JTAG.

[0040] (2) The application can find the storage location of the LUT configuration value of any truth table content in the bit stream, and obtain the frame address corresponding to the configuration memory, so as to perform targeted fine-grained modification on the corresponding data in the memory online, thereby solving the problems of insufficient LUT information restoration completeness, low efficiency and low reconfiguration precision of FPGA resources in the prior art.

[0041] (3) The logic function of the LUT is modified during operation, the internal data of the FPGA is accessed and manipulated in real time, and the FPGA implemented function and algorithm can be further modified, thereby providing an effective means for content tampering, fault injection and other attacks at the configuration memory level. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A bit stream parsing and dynamic editing method flow chart for LUT resources in Xilinx FPGA;

[0043] Figure 2 A state transition diagram for implementation of an ICAP interface read-write module state machine. DETAILED DESCRIPTION

[0044] The specific embodiments of the application are described below.

[0045] A bit stream parsing and dynamic editing method for LUT resources in Xilinx FPGA, as shown in Figure 1 , includes the following steps:

[0046] S1: Intercepting FPGA bit stream data, combining the structure information of the FPGA, extracting the content of all LUT resources therein and corresponding to the physical addresses thereof respectively.

[0047] At present, the mainstream SRAM-based FPGA bit stream is stored in a flash memory or an EEPROM or other external non-volatile memory, which can be directly read out or obtained by eavesdropping the configuration bus of the FPGA during power-on.

[0048] The structure information of the specified FPGA can be obtained by the -report command in xdl.exe of the EDA tool ISE of Xilinx, and an xdlrc file including the number, location and all possible configuration states of each type of resource inside is generated.

[0049] The extraction of the LUT content at each physical address includes the following steps:

[0050] S1-1: Establish a blank project without instantiating any logic unit or I / O interface, generate a blank bitstream comparison file, and turn off the DRC design rule check throughout the test process;

[0051] S1-2. Select a reference CLB, instantiate one LUT in it with all 1s and generate a bitstream, and obtain the location range of all configuration bits of the LUT in the complete bitstream from the difference bits between the blank bitstream and the bitstream. Perform the same operation on other LUTs in the CLB and store the location information of these bitstream configuration bits accordingly;

[0052] S1-3: Select another CLB to be tested, instantiate the LUTs in the reference CLB and the CLB to be tested with the same initial value, generate bitstreams respectively and calculate the offset between the configuration bit addresses of each LUT in the reference CLB and the CLB to be tested;

[0053] S1-4: Based on the underlying structure and resource arrangement rules of the FPGA, use the mapping information and offset information of the LUT configuration bits in the reference CLB in the bitstream to traverse all CLBs at physical addresses on the chip and obtain the specific storage locations of all LUT configuration bits in the bitstream;

[0054] S1-5: Extract the content of all LUT resources in the complete bitstream file loaded into the device for running according to the storage location information of the LUT resources in the bitstream obtained in S1-4, and correspond the physical addresses in the device.

[0055] S2: According to the pin-to-bitstream mapping relationship of the LUT resource, convert the content of any selected target LUT truth table according to all possible pin arrangement modes and bitstream storage rules to generate a bitstream storage value search item list.

[0056] The extraction of the LUT storage mapping rules in the bitstream and the generation of the search items include the following steps:

[0057] S2-1: I-A mapping relationship extraction: map the N input pins (I0-I N-1 ) of the instantiated LUT in the code to the on-chip pins (A0-A N-1) corresponding, reducing N input LUT theoretically N! possible pin arrangement;

[0058] S2-2: INIT-BIT mapping relationship extraction: by instantiating each configuration bit of N input LUT alone and comparing with blank bit stream, restoring its 2 N bit truth table INIT value and bit file 2 N bit BIT value storage order corresponding relationship, as shown in Table 1. Different types of LUTs in SLICEM and SLICEL in CLB are mapped according to this operation to restore the mapping rule;

[0059] The following table is the storage arrangement of LUT truth table content in bit stream in all SLICEL in a certain CLB column, which involves the content of bit stream file 2648-2673, a total of 26 rows. The storage format of each row in the bit stream is 4 32bit words.

[0060] Table 1. LUT resource mapping rule in the corresponding configuration frame of SLICEL in a certain CLB column

[0061]

[0062] The row offset value listed in the table is from the start bit of the header file of the bit stream. Due to the different lengths of the header file, the row offset value will be different. SX in the table represents the vertical coordinate position of a Slice, and AX-DX represents the specific bit number in the 64bit truth table configuration bit of LUTA-LUTD contained in a Slice. For example, S50 in the table represents Slice_X0Y50, S51 represents Slice_X0Y51, and so on; B63 represents the 63rd bit of the initial value of the 64bit truth table in LUTB, and so on.

[0063] S2-3: generate search items: convert the original truth table content of any selected target LUT according to all possible pin arrangement combinations and bit value storage mapping relationship, and automatically generate a list of search items corresponding to the actual storage values in the bit stream.

[0064] S3: traverse the search item list in the extracted bit stream content containing all LUT resources, locate and calculate the frame address and frame offset involved in configuring the LUT according to the physical address of the target LUT.

[0065] After finding the storage location of the LUT content in the bit stream, first deduce the frame address set of all frames involved in configuring the LUT according to the physical coordinates of the CLB column and Slice corresponding to the LUT.

[0066] For example, a CLB configuration frame containing 101 32-bit words, whose configuration range involves 50 slices in a column, will include the content of 4 LUTs belonging to a slice, so it can only configure 2 bytes of a LUT, and a complete LUT needs 4 consecutive frames. The starting frame address can be calculated from the coordinates of the LUT's CLB and slice, as shown in Table 2.

[0067] The frame address contains five parts. The block type 000 represents a CLB, the selection bits of the upper / lower part and the row address part are determined by the position of the Clock Region, the column address is determined by the X coordinate of the CLB, and the specific frame number address is determined by the X coordinate of the slice.

[0068] Table 2. Frame address representation of a LUT on a certain physical address

[0069]

[0070] After determining the frame address range, the offset of the 32-bit word where the LUT configuration bits are located in the frame is derived from the Y coordinate of the slice where the LUT is located, so as to locate the specific address in the BRAM when modifying and perform targeted partial rewriting on the frame data stored therein.

[0071] In addition, the actual pin mapping relationship under the current lookup result needs to be recorded for subsequent use of new truth table content to cover the original value, which can be converted by the determined mapping relationship and then mapped by the bit stream to obtain new frame data.

[0072] S4: Call the ICAP interface, input the read command sequence, read the frame data on all target frame addresses containing the target LUT configuration information, and store it in the BRAM for subsequent use.

[0073] Reading frame data using the ICAP interface includes the following steps:

[0074] S4-1: Initialization: enable csib and rdwrb control signals, set the interface direction to write mode, perform synchronization, CRC reset and other operations on the ICAP interface;

[0075] S4-2: Input relevant parameters: activate RCFG, input the starting frame address for reading back and the total number of words to be read according to the target frame address set obtained in step 3;

[0076] S4-3: Perform read back: switch the interface direction to read mode, wait for a few cycles, and then save the frame data read back through the ICAP interface in the BRAM. After receiving all the read back data, switch to write mode again to complete the desynchronization operation.

[0077] The entire process of reading through the ICAP interface can be done by Figure 2 After activating the read function of the ICAP interface, you need to enter the relevant parameters, including the start frame address and the total number of words to read back (Nwords). Since the first frame of the data read back is an additional padding frame, for the 7 series FPGA, which contains 101 32-bit words per frame, the number of consecutive N words starting from the start frame address is 101. f When the content on the frame is read, the number of words N that need to be read back words The calculation formula is: N words =101×(N f +1).

[0078] It can be seen that when reading back the contents of four adjacent frames involved in a LUT, N f =4, then N words =505.

[0079] S5: Call the ICAP interface, input the write command sequence, modify the frame data in the BRAM and write it to the same frame address as step S4, and read it back again to verify whether the operation is successful.

[0080] Using the ICAP interface to write back the modified frame data includes the following steps:

[0081] S5-1: Initialization: Enable csib and rdwrb control signals, set the interface direction to write mode, synchronize the ICAP interface, reset CRC, etc.

[0082] S5-2: Enter relevant parameters: After entering the device IDCODE for verification, enter the same write-back start frame address and the number of frames to be written back as when performing the read operation in step 4;

[0083] S5-3: Execute modified write-back: For all frame data read back, modify them in a targeted manner according to the offset information of the target LUT configuration bit in the frame, and input the modified write-back data in sequence through the ICAP interface;

[0084] S5-4: Secondary read-back verification: The read-back process is performed again on all data at the target frame address, and compared with the original data stored in the BRAM in S4-3 to determine whether the rewrite operation is successful.

[0085] like Figure 2 As shown in the figure, the write command sequence is similar to the read command sequence process. The difference is that the device IDCODE needs to be given to establish communication with the chip, and the input start frame address and readback word count are consistent with the read operation.

[0086] After reading the frame data in the BRAM in order, according to the specific offset and pin mapping relationship of the target LUT configuration content, the new truth table content is converted and overwritten to the specific position in the frame data, and the remaining part remains unchanged. After the effective frame data after partial modification is attached to the padding frame, it is input into the ICAP interface in order to complete the targeted modification of the LUT content in the configuration memory. Embodiments:

[0088] In the embodiments of the application, the standard test set ISCAS85 circuit and the two practical applications of AES and DES are selected as test codes, Xilinx Artix-7 XC7A35T is selected as the target chip, and Vivado is used to compile these test codes to generate bit streams. In combination with the bit stream and the known target LUT truth table information, the LUT resources used can be searched and modified by the method described in the application, such as the LUTs for implementing XOR gates, AND gates, full adders or other arbitrary specified logic functions in ISCAS85; and the LUTs for implementing S-box functions in DES, AES and other encryption algorithms.

[0089] As shown in Table 3, the substitution calculation function performed by one DES S-box converts 6-bit input into 4-bit output, which can be implemented by 4 six-input LUTs, each LUT contains a column of output results, and a complete DES design usually includes 8 S-boxes, a total of 32 LUTs.

[0090] Table 3. LUT implementation of 6-bit-to-4-bit DES S-box

[0091]

[0092] As a standard algorithm, the content of each S-box, that is, the truth table content of the four six-input LUTs, is fixed. With the decrypted pin and bit stream mapping relationship, 6! = 720 possible storage bit values in the bit stream can be obtained for each type of LUT. For the bit stream content containing all LUT resources, the storage location of the four LUTs configuring a single S-box in the bit stream and the frame address set involved are determined by sequentially searching the 720 permutation modes of each type of LUT, and the remaining seven S-boxes are the same. In practical applications, the search times can be reduced and the efficiency of searching and positioning can be improved by certain combination and deduplication.

[0093] Taking the first S-box Sbox1 as an example, the fixed truth table configuration content of the four LUTs required to perform the substitution function is as follows:

[0094] LUT1 = (a64,..., a1) = 64'b1000011010011101010010010111101010000110111001100111011000011001;

[0095] LUT2 = (b64,..., b1) = 64'b1011000011000111100001110001101101001001011110000010011010111101;

[0096] LUT3 = (c64,..., c1) = 64'b0010011111101001110101001001001001100000100111110001111100101001;

[0097] LUT4 = (d64,..., d1) = 64'b1001000101111011111010010000011001101111100000011011010001111000.

[0098] In the bit stream of all LUT information extracted, the corresponding content of the above LUT configuration value after pin and bit stream mapping is searched respectively, and the arrangement mode actually stored in the configuration memory is obtained as follows:

[0099] LUT1 = (a64,..., a1) = 0xc3722dc9e3295e92;

[0100] LUT2 = (b64,..., b1) = 0xe52976c2a995cba4;

[0101] LUT3 = (c64,..., c1) = 0x8ee16ba4971c497a;

[0102] LUT4 = (d64,..., d1) = 0x586b615e8e712d9c.

[0103] After identifying and locating the four target LUTs performing the S-box function, obtaining the corresponding physical address and calculating the target frame address, the ICAP interface can be activated, the frame address and the number of words are input, and the data is accessed and manipulated in real time online, such as setting the content to zero to completely disable it; or set to be identical to the input to destroy the nonlinear characteristics, thereby weakening the encryption algorithm, providing an effective attack means for analyzing and cracking the key.

[0104] Observe the output port of ICAP, and the reading result of frame data is as follows:

[0105] Frame address 0000121A on data: xxxxxxxx...xxxx 8ee1586b c372e529 xxxxxxxx...xxxx;

[0106] Frame address 0000121B on data: xxxxxxxx...xxxx 6ba4615e 2dc976c2 xxxxxxxx...xxxx;

[0107] Frame address 0000121C on data: xxxxxxxx...xxxx 971c8e71 e329a995 xxxxxxxx...xxxx;

[0108] Frame address 0000121D on data: xxxxxxxx...xxxx 497a2d9c 5e92cba4 xxxxxxxx...xxxx.

[0109] After keeping the rest of the frame unchanged, the content of the target LUT is cleared and written back to the same frame address, and the result of re-reading is as follows, the operation is successful.

[0110] Frame address 0000121A on data: xxxxxxxx...xxxx 00000000 00000000 xxxxxxxx...xxxx;

[0111] Frame address 0000121B on data: xxxxxxxx...xxxx 00000000 00000000 xxxxxxxx...xxxx;

[0112] Frame address 0000121C on data: xxxxxxxx...xxxx 00000000 00000000 xxxxxxxx...xxxx;

[0113] Frame address 0000121D on data: xxxxxxxx...xxxx 00000000 00000000 xxxxxxxx...xxxx.

[0114] The identification and dynamic reconfiguration results of the LUT of the specified truth table content in each type of circuit described above in the bit stream are shown in Table 4, which can accurately and quickly extract and locate any LUT content in the bit stream, and further modify the whole process.

[0115] Table 4. Bit stream analysis and dynamic editing results of LUT resources

[0116]

[0117] The bit stream analysis and dynamic editing method for the LUT resource in the Xilinx FPGA provided by the application restores the accurate bit stream mapping and position information of any LUT resource, and through the designed ICAP read-write state machine, the LUT resource is dynamically reconfigured, which is helpful for fine-grained management and deployment of the internal resources of the FPGA, and further real-time, flexible and efficient control and adjustment of the functions or output results realized by the FPGA.

[0118] As described above, although the application has been indicated and expressed with reference to specific embodiments, it should not be interpreted as a limitation of the application itself. Various changes can be made to the form and details thereof without departing from the spirit and scope of the application defined in the appended claims.

Claims

1. A method for bitstream parsing and dynamic editing of LUT resources in Xilinx FPGA, characterized in that: The steps include: S1, intercept the bitstream data, combine it with the FPGA structure information, and extract the content of all LUT resources; S2. Based on the mapping relationship between pins and bitstreams, the contents of any target LUT truth table are arranged according to all possible bitstream arrangements to generate a list of bitstream storage value items to be searched. S3, traversing the list of items to be searched in the content extracted in S1, and after locating the items, calculating the target frame address and the offset within the frame involved in configuring the LUT according to the physical address of the target LUT; S4, call the ICAP interface, input the read command sequence, read the frame data containing the target LUT information and store it in BRAM; S5. Call the ICAP interface, input the write command sequence, modify the frame data in the BRAM and write it back to the corresponding frame; In step S1, the extraction of the LUT content at each physical address includes the following steps: S1-1: Create a blank project, do not instantiate any logic unit or I / O interface, and generate a blank bitstream comparison file; S1-2: Select a reference CLB, instantiate all LUT initial values ​​in it to all 1s, and generate a bitstream. Obtain the position range of the configuration bit set of the current LUT in the complete bitstream through the difference bits with the blank bitstream; S1-3: Select another CLB to be tested, instantiate the LUTs in the reference CLB and the CLB to be tested to the same initial values, generate a bitstream, and calculate the offset between the LUT configuration bit set addresses corresponding to the reference CLB and the CLB to be tested; S1-4: In combination with the underlying structure of the FPGA, the mapping information and offset information of each LUT configuration bit in the reference CLB in the bitstream are used to traverse all CLBs at physical addresses in the chip and obtain the specific storage locations of the configuration bits of all LUTs in the bitstream; S1-5: intercept the complete bitstream that has been loaded into the device for operation, extract the contents of all LUT resources in the bitstream according to the location information of the LUT resources obtained in S1-4, and correspond them to the physical addresses in the device; In step S2, the LUT truth table content corresponds to the generation of the stored value in the bitstream, including the following steps: S2-1: IA mapping relationship extraction: Match the LUT input pin I instantiated in the code with the actual LUT pin A optimized by the FPGA synthesis tool, and restore the N possible pin arrangements of the N-input LUT; S2-2: INIT-BIT mapping relationship extraction: By separately instantiating each configuration bit of different types of LUTs and comparing them with blank bit streams, the 2-bit mapping relationship of each type of N-input LUT is restored. N The INIT value of the bit truth table is the same as the 2 N The corresponding relationship between the storage order of bit BIT values; S2-3: Generate items to be searched: Convert the original truth table content of the target LUT according to all possible pin arrangement combinations and bit value storage mapping relationships, and generate a list of items to be searched whose truth table content corresponds to the actual storage values ​​in the bit stream.

2. The method for parsing and dynamically editing specific LUT resources in Xilinx FPGA according to claim 1, wherein: The target LUT includes LUT resources at any physical address, with any number of input pins, and implementing any logic function.

3. The method for parsing and dynamically editing specific LUT resources in Xilinx FPGA according to claim 1, wherein: When dynamically editing the LUT content, an ICAP state machine is designed and implemented to directly control the read and write enable signals of the ICAP primitive and input command sequences to implement the complete process of read back, modify, and write back on the FPGA hardware.

4. The method for parsing and dynamically editing specific LUT resources in Xilinx FPGA according to claim 1, wherein: The read and write operations of the configuration memory using the ICAP interface are performed in frames; the process of modifying the target LUT content according to its configuration bit offset is further refined to each 32-bit word within the frame.

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