A design method and packaging device for a multi-layer HTCC ceramic RF SIP package shell

Abstract

The present invention provides a design method and packaging device for a multi-layer HTCC ceramic RF SIP packaging tube shell, which relates to the field of RF SIP packaging technology. The present invention optimizes the packaging design comprehensively from multiple objectives such as signal integrity, heat dissipation performance and mechanical reliability by dynamically optimizing the number of layers and thickness of the multi-layer stacking structure, thereby avoiding conflicts caused by single performance optimization. At the same time, based on the gradient microstrip line design, the impedance matching performance of the radio frequency signal is significantly improved, the signal reflection and transmission loss are reduced, and it is suitable for high-frequency signal transmission requirements. Sensitivity analysis and correction factors are introduced through trial assembly feedback, and the deviation between simulation modeling and actual performance is gradually reduced, thereby achieving efficient and accurate multiple update optimization. The final packaging tube shell design ensures excellent signal integrity, heat dissipation capability and structural reliability, and provides a systematic solution for modern high-frequency and miniaturized packaging.

Description

Technical Field

[0001] The invention relates to the technical field of RF SIP packaging, in particular to a design method of a multi-layer HTCC ceramic RF SIP packaging tube shell and a packaging device. Background Art

[0002] With the rapid development of 5G communications, high-frequency radars, and high-speed signal transmission, higher requirements are being placed on multi-layer HTCC (high-temperature co-fired ceramic) packaging technology. Traditional multi-layer ceramic packaging usually adopts a fixed number of layers and structural design, lacks dynamic optimization capabilities, and is difficult to balance signal transmission loss, heat dissipation requirements, and mechanical strength. In addition, the fixed thickness design method limits the flexible matching of the target impedance of the RF signal, which can easily lead to signal reflection and distortion problems, reducing signal integrity.

[0003] At the same time, the RF ports and microstrip line structures designed by existing technologies in high-frequency applications often cause parasitic capacitance and inductance effects due to impedance discontinuity, exacerbating the problem of electrical performance degradation. In the optimization process, traditional methods rely on static simulation modeling adjustments and fail to combine actual trial assembly data feedback for multiple iterative optimizations, resulting in a large deviation between the simulation results and the actual performance, limiting the accuracy and reliability of the package design. These problems make it difficult for traditional package designs to meet the modern high-frequency, miniaturized, and multifunctional system-in-package (SIP) requirements.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute the prior art that is already known to one of ordinary skill in the art. Summary of the invention

[0005] The object of the present invention is to provide a design method of a multi-layer HTCC ceramic RF SIP package tube shell and a packaged device to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A design method for a multi-layer HTCC ceramic RF SIP package tube shell, the specific steps comprising:

[0008] S1: Determine the substrate material and corresponding dimensions of the package shell based on design requirements, use a multi-layer stacking structure to construct the package shell, and perform preliminary simulation modeling;

[0009] S2: Based on the design requirements, the electrical components are laid out in the simulation model with the best electrical performance and the smallest occupied space as the goal, a gradient microstrip line is set at the RF port, and the simulation model is updated;

[0010] S3: performing trial assembly according to the simulation modeling after the primary update, collecting electrical parameters of the package shell after the trial assembly, and performing secondary update on the simulation modeling based on the collected electrical parameters and electrical parameters obtained by simulation analysis;

[0011] S4: Generate correction factors based on the electrical parameters obtained in the simulation analysis and the electrical parameters collected in the trial assembly of the simulation modeling after the second update, update the simulation modeling three times based on the correction factors, and use the simulation modeling after the three updates as the final solution for the formal operation.

[0012] Preferably, the packaging shell adopts The HTCC substrate material of the system has a sintering temperature of 1600°C, a sintering time of 2h, and a sintering pressure of 5MPa.

[0013] Preferably, when performing simulation modeling, the design method of the multi-layer stacking structure is:

[0014] Based on the design requirements, the total number of layers of the multi-layer stacking structure is determined. The total number of layers is expressed as:

[0015] ;

[0016] in , , , , Respectively represent the total number of layers, signal line layers, power layers, ground layers, and shielding layers;

[0017] Simulate and analyze the multi-layer stacking structure, calculate the signal transmission loss, and optimize the number of ground layers and the total number of layers based on the calculation results;

[0018] The thickness and total thickness of each layer in the multilayer stacked structure are calculated according to the target impedance of the microstrip line, and it is determined whether the total thickness meets the heat dissipation and mechanical strength requirements of the chip. The thickness and total thickness of each layer are optimized according to the heat dissipation and mechanical strength requirements of the chip.

[0019] Preferably, the signal transmission loss is calculated as follows:

[0020] ;

[0021] In the formula Indicates the transmission loss of the signal. represents the signal frequency, represents the magnetic permeability of the conductor, represents the conductor resistivity, represents the dielectric constant of the substrate, represents the substrate dielectric loss angle, represents the scale factor, and ;

[0022] When the signal transmission loss , it is considered that the transmission loss exceeds the design requirement, and the number of grounding layers is increased by one, that is, ,in Indicates the preset loss threshold.

[0023] Preferably, the calculation method of the thickness of each layer and the total thickness in the multi-layer stacked structure is:

[0024] Substitute the preset width and thickness of the microstrip line on the multi-layer stacked structure into the impedance calculation equation, and solve for the thickness of each layer of the substrate in the multi-layer stacked structure. The impedance calculation equation is:

[0025] ;

[0026] In the formula represents the target impedance of the microstrip line, , represent the preset width and preset thickness of the microstrip line respectively, Indicates the thickness of each substrate in a multi-layer stacked structure;

[0027] The total thickness of the multilayer stacked structure is expressed as:

[0028] ;

[0029] In the formula Represents the total thickness of a multi-layer stacked structure.

[0030] Preferably, the method for determining whether the total thickness meets the chip heat dissipation requirements and mechanical strength requirements is:

[0031] Determine the heat dissipation power and operating temperature of the chip based on the design requirements, and calculate the minimum heat dissipation thickness. The calculation method is:

[0032] ;

[0033] In the formula Indicates the minimum heat dissipation thickness, represents the thermal conductivity of the substrate, Indicates the contact area between the chip and the substrate. , Respectively represent the preset working temperature and reference temperature, Indicates the heat dissipation power of the chip;

[0034] Then, based on the design requirements, determine the overall bearing pressure of the package shell and calculate the minimum bearing thickness. The calculation method is:

[0035] ;

[0036] In the formula Indicates the minimum load-bearing thickness, , represent the substrate width and substrate length respectively, Indicates the bending strength of the substrate, Indicates bearing pressure;

[0037] When the total thickness of the multilayer stacked structure satisfies:

[0038] ;

[0039] When the total thickness meets the chip heat dissipation and mechanical strength requirements, otherwise the thickness of each layer and the total thickness are adjusted by changing the width and thickness of the microstrip line on the multi-layer stacked structure until the total thickness of the multi-layer stacked structure meets the chip heat dissipation and mechanical strength requirements.

[0040] Preferably, when setting a gradient microstrip line to update the simulation modeling, the width of the gradient microstrip line is determined by a variation function, and the variation function is as follows:

[0041] ;

[0042] In the formula Indicates the distance from the RF port is The microstrip line width at , Respectively represent the maximum width and minimum width of the gradient microstrip line, Represents the total length of the tapered microstrip line.

[0043] Preferably, when the simulation modeling is updated for the second time, the optimization order is determined based on the sensitivity of different electrical parameters, and the electrical parameter sensitivity is calculated as follows:

[0044] ;

[0045] In the formula Indicates The sensitivity of the electrical parameters, Indicates the index of electrical parameters, , Respectively represent the first The electrical parameters and the Electrical parameters, The first Electrical parameters, Indicates the preset first Electrical parameters.

[0046] Preferably, the logic of generating the correction factor and updating the simulation modeling three times based on the correction factor is:

[0047] The simulation modeling after the second update generates correction factors based on the electrical parameters obtained in the simulation analysis and the electrical parameters collected in the trial assembly. The calculation method is:

[0048] ;

[0049] In the formula represents the correction factor, Indicates the second update setting. Electrical parameters;

[0050] The simulation modeling was updated three times. The electrical parameter adjustment method is expressed as:

[0051] ;

[0052] In the formula Indicates the first setting after three updates. Electrical parameters.

[0053] A packaged device includes a SIP package shell, and the SIP package shell is designed using the above-mentioned design method.

[0054] Compared with the prior art, the present invention has the following beneficial effects:

[0055] The present invention optimizes the packaging design comprehensively from multiple objectives such as signal integrity, heat dissipation performance and mechanical reliability by dynamically optimizing the number and thickness of multi-layer stacked structures, thereby avoiding conflicts caused by single performance optimization. At the same time, based on the gradient microstrip line design, the impedance matching performance of the RF signal is significantly improved, and the signal reflection and transmission loss are reduced, which is suitable for high-frequency signal transmission requirements. By introducing sensitivity analysis and correction factors through trial assembly feedback, the deviation between simulation modeling and actual performance is gradually reduced, and efficient and accurate multiple update optimizations are achieved. The final packaging shell design ensures excellent signal integrity, heat dissipation capability and structural reliability, and provides a systematic solution for modern high-frequency and miniaturized packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 It is a schematic diagram of the overall method flow of the present invention. DETAILED DESCRIPTION

[0057] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments.

[0058] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the present invention should be understood by people with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0059] Example:

[0060] See also Figure 1 , the present invention provides a technical solution:

[0061] A design method for a multi-layer HTCC ceramic RF SIP package tube shell, the specific steps comprising:

[0062] S1: Determine the substrate material and corresponding dimensions of the package shell based on design requirements, use a multi-layer stacking structure to construct the package shell, and perform preliminary simulation modeling.

[0063] Package shell adopts The HTCC substrate material of the system has a sintering temperature of 1600°C, a sintering time of 2h, and a sintering pressure of 5MPa. Laser cutting technology can also be used for precise size control, and surface chemical polishing technology can also be used to improve the surface flatness of the substrate material.

[0064] use The HTCC substrate material of the system is considered to have excellent mechanical strength, high temperature resistance and high thermal conductivity. After the introduction of TiC (titanium carbide), the conductivity and thermal shock resistance of the substrate can be significantly enhanced. At the same time, the dielectric properties of the material are optimized, so that the material has lower dielectric loss and higher dielectric constant, which can meet the needs of high-frequency signal transmission, and can maintain excellent signal integrity and low signal loss in RF radio frequency applications and SIP system-level packaging.

[0065] When performing simulation modeling, the design method of the multi-layer stacked structure is:

[0066] Based on the design requirements, the total number of layers of the multi-layer stacking structure is determined. The total number of layers is expressed as:

[0067] ;

[0068] in , , , , Respectively represent the total number of layers, signal line layers, power layers, ground layers, and shielding layers;

[0069] Simulate and analyze the multi-layer stacking structure, calculate the signal transmission loss, and optimize the number of ground layers and the total number of layers based on the calculation results;

[0070] The thickness and total thickness of each layer in the multilayer stacked structure are calculated according to the target impedance of the microstrip line, and it is determined whether the total thickness meets the heat dissipation and mechanical strength requirements of the chip. The thickness and total thickness of each layer are optimized according to the heat dissipation and mechanical strength requirements of the chip.

[0071] Traditional multilayer ceramic packaging usually only relies on a fixed number of layers and structural design, and cannot be dynamically optimized according to actual electrical performance (such as transmission loss), heat dissipation requirements, mechanical strength, etc., which can easily lead to insufficient signal integrity or electromagnetic interference problems. The invention clearly defines the composition of the total number of layers, including signal layer, power layer, ground layer and shielding. This layered design can make the function of each layer of the structure clear, reduce signal interference and optimize electrical performance. Furthermore, the design method is to first optimize the signal transmission loss, then calculate the impedance and thickness, and finally adjust according to the heat dissipation requirements and mechanical strength. This multi-objective phased optimization method can avoid design failures due to target conflicts.

[0072] The signal transmission loss is calculated as:

[0073] ;

[0074] In the formula Indicates the transmission loss of the signal. represents the signal frequency, represents the magnetic permeability of the conductor, represents the conductor resistivity, represents the dielectric constant of the substrate, represents the substrate dielectric loss angle, represents the scale factor, and ;

[0075] When the signal transmission loss , it is considered that the transmission loss exceeds the design requirement, and the number of grounding layers is increased by one, that is, ,in It represents a preset loss threshold, the specific value of which can be determined according to expert experience or simulation results. In this embodiment, it can be set to 0.2dB.

[0076] The calculation method for the thickness of each layer and the total thickness in a multilayer stacked structure is:

[0077] Substitute the preset width and thickness of the microstrip line on the multi-layer stacked structure into the impedance calculation equation, and solve for the thickness of each layer of the substrate in the multi-layer stacked structure. The impedance calculation equation is:

[0078] ;

[0079] In the formula represents the target impedance of the microstrip line, , represent the preset width and preset thickness of the microstrip line respectively, Indicates the thickness of each substrate layer in a multi-layer stack structure.

[0080] Here, the width and thickness of the microstrip line are precisely associated with the thickness of each layer of the substrate, so that the design of the multi-layer stacked structure directly meets the target impedance matching requirements of the RF signal, which can effectively reduce reflections and distortions in signal transmission and optimize signal integrity. Moreover, according to the calculation results of the target impedance, the thickness of each layer of the substrate can be refined. At the same time, by adjusting the width and thickness of the microstrip line, the thickness of each layer of the substrate and the total thickness can be further optimized. This adjustment method provides flexibility for the optimization of the multi-layer stacked structure and avoids the performance defects that may be caused by the fixed thickness design.

[0081] The total thickness of the multilayer stacked structure is expressed as:

[0082] ;

[0083] In the formula Represents the total thickness of a multi-layer stacked structure.

[0084] The method to determine whether the total thickness meets the chip heat dissipation requirements and mechanical strength requirements is:

[0085] Determine the heat dissipation power and operating temperature of the chip based on the design requirements, and calculate the minimum heat dissipation thickness. The calculation method is:

[0086] ;

[0087] In the formula Indicates the minimum heat dissipation thickness, represents the thermal conductivity of the substrate, Indicates the contact area between the chip and the substrate. , Respectively represent the preset working temperature and reference temperature, Indicates the heat dissipation power of the chip. When the substrate material is too thin, its thermal resistance will be greatly increased, resulting in reduced heat dissipation effect. Therefore, the substrate material needs to meet a certain thickness for heat dissipation. This method can ensure that the multi-layer stacking structure has sufficient thermal conductivity to prevent the performance degradation or failure of the chip due to insufficient heat dissipation under high-power working conditions.

[0088] Then, based on the design requirements, determine the overall bearing pressure of the package shell and calculate the minimum bearing thickness. The calculation method is:

[0089] ;

[0090] In the formula Indicates the minimum load-bearing thickness, , represent the substrate width and substrate length respectively, Indicates the bending strength of the substrate, Indicates the bearing pressure. This method can prevent the mechanical failure of the multi-layer stacked structure under thermal cycling or external stress and improve the structural reliability of the package.

[0091] When the total thickness of the multilayer stacked structure satisfies:

[0092] ;

[0093] When the total thickness meets the chip heat dissipation and mechanical strength requirements, otherwise the thickness of each layer and the total thickness are adjusted by changing the width and thickness of the microstrip line on the multi-layer stacked structure until the total thickness of the multi-layer stacked structure meets the chip heat dissipation and mechanical strength requirements. This step dynamically adjusts the width and thickness of the microstrip line and the thickness of each layer of the substrate instead of simply increasing the overall thickness. This method can avoid ineffective thickness increase and maintain the efficiency and economy of the design.

[0094] In this step, the present invention comprehensively considers electrical performance (target impedance matching), thermal performance (heat dissipation requirements) and mechanical performance (load-bearing capacity) to perform multi-objective optimization design, avoiding the problem that single performance optimization may cause other performance failures. Comprehensively considering these performance requirements in the early stage of design can reduce subsequent design iterations and improve design efficiency and reliability.

[0095] S2: Based on design requirements, electrical components are jointly laid out with the best electrical performance and minimum occupied space as the goal in simulation modeling, gradient microstrip lines are set at the RF port, and the simulation modeling is updated once. It can be understood that an update refers to the update of hardware in simulation modeling, that is, electrical component layout and gradient microstrip line setting are performed on the preliminary simulation modeling. Specific electrical parameters, such as impedance, width, thickness, transmission loss of microstrip lines, dielectric constant and dielectric loss tangent of substrate materials, and reflection coefficient and insertion loss of RF ports, are not adjusted or updated.

[0096] By jointly optimizing the layout of electrical components and the design of microstrip lines, the best electrical performance is achieved in the smallest package space. This layout optimization method provides support for multifunctional and miniaturized package design and meets the needs of modern electronic products for compact space. By setting a gradient microstrip line, the linear change of its width optimizes the propagation path of the signal on the microstrip line, significantly reduces the reflection coefficient, improves the impedance matching performance, and can alleviate the parasitic capacitance and inductance problems caused by impedance mutation, making it more suitable for high-frequency and high-speed signal transmission.

[0097] When setting a gradient microstrip line to update the simulation model, the width of the gradient microstrip line is determined by the variation function, which is as follows:

[0098] ;

[0099] In the formula Indicates the distance from the RF port is The microstrip line width at , Respectively represent the maximum width and minimum width of the gradient microstrip line, Represents the total length of the tapered microstrip line.

[0100] Ensure that the width of the microstrip line changes linearly with position, so that the RF signal gradually transitions from the port, reducing the electrical loss caused by electromagnetic wave reflection and discontinuity. The gradient design realizes a smooth transition between different impedance areas, avoiding the impedance mismatch problem that may be caused by fixed-width microstrip lines and optimizing signal integrity.

[0101] S3: Perform trial assembly based on the simulation modeling after the first update, collect the electrical parameters of the package shell after the trial assembly, and perform a second update on the simulation modeling based on the collected electrical parameters and the electrical parameters obtained by simulation analysis. It can be understood that, unlike the first update, the second update is to modify each electrical parameter in the simulation modeling to achieve the update effect, thereby achieving accurate and efficient model optimization.

[0102] When the simulation model is updated for the second time, the optimization order is determined based on the sensitivity of different electrical parameters. The electrical parameter sensitivity is calculated as follows:

[0103] ;

[0104] In the formula Indicates The sensitivity of the electrical parameters, Indicates the index of electrical parameters, , Respectively represent the first The electrical parameters and the Electrical parameters, The first Electrical parameters, Indicates the preset first Electrical parameters.

[0105] The sensitivity formula comprehensively considers the deviation between the trial assembly parameters and the simulation parameters, as well as the relationship between the current parameter values ​​and the target parameter values. Through sensitivity sorting, electrical parameters with higher sensitivity can be optimized first, thereby quickly improving the overall system performance, avoiding blind adjustment of various parameters, reducing unnecessary tests and simulation iterations, and giving priority to optimizing the parameters that have the greatest impact on system performance, so that performance indicators can be achieved quickly.

[0106] Through the two-way feedback of trial assembly and simulation analysis, the simulation modeling is gradually corrected and improved to make it more accurate. Compared with the traditional method that only relies on simulation modeling, this method can more efficiently approach the design goal. It not only avoids the unnecessary work of adjusting each parameter by the same amount in the traditional optimization process, greatly improving the optimization efficiency, but also avoids the problem that a single performance optimization may lead to the degradation of other performances, thus achieving a balance of overall performance.

[0107] S4: Generate correction factors based on the electrical parameters obtained in the simulation analysis and the electrical parameters collected in the trial assembly after the second update of the simulation modeling, update the simulation modeling three times based on the correction factors, and use the simulation modeling after the three updates as the final solution for the formal operation. The three updates also modify the various electrical parameters in the simulation modeling to achieve the update effect, thereby achieving accurate and efficient model optimization.

[0108] Generate correction factors and update the simulation model three times based on the correction factors:

[0109] The simulation modeling after the second update generates correction factors based on the electrical parameters obtained in the simulation analysis and the electrical parameters collected in the trial assembly. The calculation method is:

[0110] ;

[0111] In the formula represents the correction factor, Indicates the second update setting. The correction factor reflects the relative deviation between the electrical parameters of the simulation analysis and the actual electrical parameters collected by the trial assembly after the secondary update. The positive or negative value indicates the direction of the deviation, and the size indicates the magnitude of the deviation. It is based on actual measurement data and can accurately reflect the difference between the model and actual performance.

[0112] The simulation modeling was updated three times. The electrical parameter adjustment method is expressed as:

[0113] ;

[0114] In the formula Indicates the first setting after three updates. Electrical parameters.

[0115] The electrical parameters after the third update are obtained by adjusting the parameters based on the second update combined with the correction factors. By introducing the correction factors, the three updates can scientifically adjust the electrical parameters in the simulation model and gradually approach the actual performance, effectively solving the problem of theoretical and practical deviations that may occur in the process of relying solely on simulation optimization. The updated model is more reliable, can cover the deviation range in the manufacturing process, and adapt to environmental changes in actual applications.

[0116] In summary, the present invention optimizes the packaging design comprehensively from multiple objectives such as signal integrity, heat dissipation performance and mechanical reliability by dynamically optimizing the number of layers and thickness of the multi-layer stacking structure, thereby avoiding conflicts caused by single performance optimization. At the same time, based on the gradient microstrip line design, the impedance matching performance of the RF signal is significantly improved, and the signal reflection and transmission loss are reduced, which is suitable for high-frequency signal transmission requirements. By introducing sensitivity analysis and correction factors through trial assembly feedback, the deviation between simulation modeling and actual performance is gradually reduced, and efficient and accurate multiple update optimization is achieved. The final packaging shell design ensures excellent signal integrity, heat dissipation capability and structural reliability, and provides a systematic solution for modern high-frequency and miniaturized packaging.

[0117] The present invention also provides a packaged device, including a SIP package tube shell, and is designed by adopting the above-mentioned design method.

[0118] The above formulas are all dimensionless and numerical calculations. The formula is a formula for the most recent real situation obtained by collecting a large amount of data and performing software simulation. The preset parameters in the formula are set by technicians in this field according to actual conditions.

[0119] The above embodiments may be implemented in whole or in part by software, hardware, firmware or any other combination thereof. When implemented by software, the above embodiments may be implemented in whole or in part in the form of a computer program product. Those skilled in the art may appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein may be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed by hardware or software methods depends on the specific application and design constraints of the technical solution.

[0120] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0121] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A design method for a multi-layer HTCC ceramic RF SIP package shell, characterized in that: The specific steps include: S1: Determine the substrate material and corresponding dimensions of the package shell based on design requirements, use a multi-layer stacking structure to construct the package shell, and perform preliminary simulation modeling; S2: Based on the design requirements, the electrical components are laid out in the simulation model with the best electrical performance and the smallest occupied space as the goal, a gradient microstrip line is set at the RF port, and the simulation model is updated; S3: performing trial assembly according to the simulation modeling after the primary update, collecting electrical parameters of the package shell after the trial assembly, and performing secondary update on the simulation modeling based on the collected electrical parameters and electrical parameters obtained by simulation analysis; S4: Generate correction factors based on the electrical parameters obtained in the simulation analysis and the electrical parameters collected in the trial assembly of the simulation modeling after the second update, update the simulation modeling three times based on the correction factors, and use the simulation modeling after the three updates as the final solution for the formal operation.

2. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 1, characterized in that: The package shell adopts The HTCC substrate material of the system has a sintering temperature of 1600°C, a sintering time of 2h, and a sintering pressure of 5MPa.

3. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 1, characterized in that: When performing simulation modeling, the design method of the multi-layer stacked structure is: Based on the design requirements, the total number of layers of the multi-layer stacking structure is determined. The total number of layers is expressed as: ； in , , , , Respectively represent the total number of layers, signal line layers, power layers, ground layers, and shielding layers; Simulate and analyze the multi-layer stacking structure, calculate the signal transmission loss, and optimize the number of ground layers and the total number of layers based on the calculation results; The thickness and total thickness of each layer in the multilayer stacked structure are calculated according to the target impedance of the microstrip line, and it is determined whether the total thickness meets the heat dissipation and mechanical strength requirements of the chip. The thickness and total thickness of each layer are optimized according to the heat dissipation and mechanical strength requirements of the chip.

4. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 3, characterized in that: The signal transmission loss is calculated as: ； In the formula Indicates the transmission loss of the signal. represents the signal frequency, represents the magnetic permeability of the conductor, represents the conductor resistivity, represents the dielectric constant of the substrate, represents the substrate dielectric loss angle, represents the scale factor, and ; When the signal transmission loss , it is considered that the transmission loss exceeds the design requirement, and the number of grounding layers is increased by one, that is, ,in Indicates the preset loss threshold.

5. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 3, characterized in that: The calculation method for the thickness of each layer and the total thickness in a multilayer stacked structure is: Substitute the preset width and thickness of the microstrip line on the multi-layer stacked structure into the impedance calculation equation, and solve for the thickness of each layer of the substrate in the multi-layer stacked structure. The impedance calculation equation is: ； In the formula represents the target impedance of the microstrip line, , represent the preset width and preset thickness of the microstrip line, respectively. Indicates the thickness of each substrate in a multi-layer stacked structure; The total thickness of the multilayer stacked structure is expressed as: ； In the formula Represents the total thickness of a multi-layer stacked structure.

6. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 3, characterized in that: The method to determine whether the total thickness meets the chip heat dissipation requirements and mechanical strength requirements is: Determine the heat dissipation power and operating temperature of the chip based on the design requirements, and calculate the minimum heat dissipation thickness. The calculation method is: ； In the formula Indicates the minimum heat dissipation thickness, represents the thermal conductivity of the substrate, Indicates the contact area between the chip and the substrate. , Respectively represent the preset working temperature and reference temperature, Indicates the heat dissipation power of the chip; Then, based on the design requirements, determine the overall bearing pressure of the package shell and calculate the minimum bearing thickness. The calculation method is: ； In the formula Indicates the minimum load-bearing thickness, , represent the substrate width and substrate length respectively, Indicates the bending strength of the substrate, Indicates bearing pressure; When the total thickness of the multilayer stacked structure satisfies: ； When the total thickness meets the chip heat dissipation and mechanical strength requirements, otherwise the thickness of each layer and the total thickness are adjusted by changing the width and thickness of the microstrip line on the multi-layer stacked structure until the total thickness of the multi-layer stacked structure meets the chip heat dissipation and mechanical strength requirements.

7. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 1, characterized in that: When setting a gradient microstrip line to update the simulation model, the width of the gradient microstrip line is determined by the variation function, which is as follows: ； In the formula Indicates the distance from the RF port is The microstrip line width at , Respectively represent the maximum width and minimum width of the gradient microstrip line, Represents the total length of the tapered microstrip line.

8. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 1, characterized in that: When the simulation model is updated for the second time, the optimization order is determined based on the sensitivity of different electrical parameters. The electrical parameter sensitivity is calculated as follows: ； In the formula Indicates The sensitivity of the electrical parameters, Indicates the index of electrical parameters, , Respectively represent the first The electrical parameters and the Electrical parameters, The first Electrical parameters, Indicates the preset first Electrical parameters.

9. The design method of a multi-layer HTCC ceramic RF SIP package tube shell according to claim 1, characterized in that: Generate correction factors and update the simulation model three times based on the correction factors: The simulation modeling after the second update generates correction factors based on the electrical parameters obtained in the simulation analysis and the electrical parameters collected in the trial assembly. The calculation method is: ； In the formula represents the correction factor, Indicates the second update setting. Electrical parameters; The simulation modeling was updated three times. The electrical parameter adjustment method is expressed as: ； In the formula Indicates the first setting after three updates. Electrical parameters.

10. A packaging device, characterized in that: The packaged device comprises a SIP package shell, and the SIP package shell is designed using the design method according to any one of claims 1 to 9.

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